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Pull requests: llvm/llvm-project
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[MLIR][XeGPU] Allow create mem desc from 2d memref mlir:gpu mlir
#167767 opened Nov 12, 2025 by Jianhui-Li Loading…
Support folding of higher dimensional memeref subviews in XeGPUFoldAliasOps mlir:gpu mlir
#99593 opened Jul 19, 2024 by charithaintc Loading…
6 tasks
[TableGen] Split *GenRegisterInfo.inc. backend:AMDGPU mlir:core MLIR Core Infrastructure mlir tablegen
#167700 opened Nov 12, 2025 by kosarev Loading…
[offload-arch] Fix amdgpu-arch crash on Windows with ROCm 7.1 backend:AMDGPU clang Clang issues not falling into any other category
#167695 opened Nov 12, 2025 by yxsamliu Loading…
[RISCV] Enable TLSDESC by default backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
[SYCL] Add platform enumeration and info query using liboffload
#166927 opened Nov 7, 2025 by KseniyaTikhomirova Loading…
[llvm][AddressSanitizer] option for applying AddressSanitizer to specific address spaces compiler-rt:sanitizer llvm:transforms
#167770 opened Nov 12, 2025 by etsal Loading…
Refactoring llvm-ir2vec.cpp into separate components for handling IR2Vec, MIR2Vec calls mlgo
#167656 opened Nov 12, 2025 by nishant-sachdeva • Draft
[llvm][AddressSanitizer] option for specifying the address space of the shadow map compiler-rt:sanitizer llvm:transforms
#167772 opened Nov 12, 2025 by etsal Loading…
[llvm] Improve IR dump to files llvm:analysis Includes value tracking, cost tables and constant folding llvm:codegen llvm:ir
#165712 opened Oct 30, 2025 by macurtis-amd Loading…
[Sample Profile] make page size configurable for ProfiledBinary PGO Profile Guided Optimizations
#164773 opened Oct 23, 2025 by wjx951753 Loading…
[TableGen] correctly escape dependency filenames tablegen
#160834 opened Sep 26, 2025 by ZhongRuoyu Loading…
[flang][cuf] Add to cuf.alloc/cuf.allocate mem alloc effect flang:fir-hlfir flang Flang issues not falling into any other category
#167414 opened Nov 10, 2025 by SusanTan Loading…
[X86] Delete Profile Guided Prefetch Passes backend:X86
#167317 opened Nov 10, 2025 by boomanaiden154 Loading…
[AArch64] Allow forcing unrolling of small loops backend:AArch64 llvm:transforms
#167488 opened Nov 11, 2025 by VladiKrapp-Arm Loading…
[LoongArch] Add option for disable MI scheduling backend:loongarch
#163150 opened Oct 13, 2025 by wangleiat Loading…
[lldb-dap] Migrating 'evaluate' to structured types. lldb lldb-dap
#167720 opened Nov 12, 2025 by ashgti Loading…
[LoopVectorize] Support vectorization of compressing patterns in VPlan llvm:analysis Includes value tracking, cost tables and constant folding llvm:transforms vectorizers
#140723 opened May 20, 2025 by skachkov-sc Loading…
[MLIR][OpenMP] Introduce overlapped record type map support flang:fir-hlfir flang:openmp flang Flang issues not falling into any other category mlir:llvm mlir:openmp mlir offload
#119588 opened Dec 11, 2024 by agozillon Loading…
[RISCV] Add an option to enable CFIInstrInserter. backend:RISC-V
#164477 opened Oct 21, 2025 by mgudim Loading…
[LoongArch] Make the code generation of the trap pattern configurable backend:loongarch
#166913 opened Nov 7, 2025 by heiher Loading…
[SelectionDAG] Verify SDTCisVT and SDTCVecEltisVT constraints backend:AArch64 backend:m68k backend:RISC-V backend:Sparc llvm:SelectionDAG SelectionDAGISel as well tablegen
#150125 opened Jul 22, 2025 by s-barannikov Loading…
[MLIR] Move the MLIR Core Infrastructure mlir
mlir-generate-reproducer option to be a PassManager option instead of mlir-opt mlir:core #159004 opened Sep 16, 2025 by joker-eph Loading…
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