Search results

[RISCV] Remove Match_InvalidXSfmmVType. NFC

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 168465

#168465 In llvm/llvm-project;

· topperc opened on Nov 18, 2025

[RISCV] Legalize misaligned unmasked vp.load/vp.store to vle8/vse8.

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 167745

#167745 In llvm/llvm-project;

· topperc opened on Nov 12, 2025

[ExpandVectorPredication] Expand vp.load.ff.

llvm:codegen

llvm:transforms

Status: Open (in progress).

llvm/llvm-projectnumber 154440

#154440 In llvm/llvm-project;

· topperc opened on Aug 19, 2025

[ScalarEvolutionExpander] Use IRBuilder::CreateBinOp in SCEVExpander::InsertBinop.

backend:AArch64

backend:X86

llvm:transforms

Status: Open (in progress).

llvm/llvm-projectnumber 146443

#146443 In llvm/llvm-project;

· topperc opened on Jul 1, 2025

[RISCV] Move vendor extensions after standard extensions in RISCVDisassembler::getInstruction16.

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 130821

#130821 In llvm/llvm-project;

· topperc opened on Mar 11, 2025

[RISCV][GISel][WIP] Support s64 G_PHI on RV32 when D extension is enabled.

backend:RISC-V

llvm:globalisel

Status: Draft (not ready).

llvm/llvm-projectnumber 119026

#119026 In llvm/llvm-project;

· topperc opened on Dec 6, 2024

[SelectionDAG] Use size_t for ResNo in SDValue.

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 104660

#104660 In llvm/llvm-project;

· topperc opened on Aug 17, 2024

[IR] Add CallBr to Instruction::isFenceLike.

Status: Open (in progress).

llvm/llvm-projectnumber 101128

#101128 In llvm/llvm-project;

· topperc opened on Jul 30, 2024

[LegalizeDAG][X86][AArch64][LoongArch] Freeze index when converting extract_elt/extract_subvector to load/store on stack.

backend:AArch64

backend:loongarch

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 88985

#88985 In llvm/llvm-project;

· topperc opened on Apr 16, 2024

[DAGCombiner][X86][WIP] Combine (build_vector (load X))->(vecty (load X))

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 88753

#88753 In llvm/llvm-project;

· topperc opened on Apr 15, 2024

[RISCV] Add CodeGen only version of conditional branch instructions t…

backend:RISC-V

llvm:globalisel

Status: Draft (not ready).

llvm/llvm-projectnumber 87834

#87834 In llvm/llvm-project;

· topperc opened on Apr 5, 2024

[LegalizeTypes][X86][PowerPC] Use shift by 1 instead of adding a value to itself to double.

backend:PowerPC

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 86857

#86857 In llvm/llvm-project;

· topperc opened on Mar 27, 2024