[RISCV] Collapse fast unaligned access into a single feature [nfc-ish] (#73971)

When we'd originally added unaligned-scalar-mem and unaligned-vector-mem, they were separated into two parts under the theory that some processor might implement one, but not the other. At the moment, we don't have evidence of such a processor. The C/C++ level interface, and the clang driver command lines have settled on a single unaligned flag which indicates both scalar and vector support unaligned. Given that, let's remove the test matrix complexity for a set of configurations which don't appear useful. Given these are internal feature names, I don't think we need to provide any forward compatibility. Anyone disagree? Note: The immediate trigger for this patch was finding another case where the unaligned-vector-mem wasn't being properly serialized to IR from clang which resulted in problems reproducing assembly from clang's -emit-llvm feature. Instead of fixing this, I decided getting rid of the complexity was the better approach.

Author: preames

clang/lib/Basic/Targets/RISCV.cpp

@@ -376,7 +376,7 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
  if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
  HasLegalHalfType = true;
 
- FastUnalignedAccess = llvm::is_contained(Features, "+unaligned-scalar-mem");
+ FastUnalignedAccess = llvm::is_contained(Features, "+fast-unaligned-access");
 
  return true;
 }

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

@@ -65,7 +65,7 @@ static void getRISCFeaturesFromMcpu(const Driver &D, const Arg *A,
  }
 
  if (llvm::RISCV::hasFastUnalignedAccess(Mcpu))
- Features.push_back("+unaligned-scalar-mem");
+ Features.push_back("+fast-unaligned-access");
 }
 
 void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
@@ -171,18 +171,12 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
  Features.push_back("-save-restore");
 
  // -mno-unaligned-access is default, unless -munaligned-access is specified.
- bool HasV = llvm::is_contained(Features, "+zve32x");
  if (const Arg *A = Args.getLastArg(options::OPT_munaligned_access,
  options::OPT_mno_unaligned_access)) {
- if (A->getOption().matches(options::OPT_munaligned_access)) {
- Features.push_back("+unaligned-scalar-mem");
- if (HasV)
- Features.push_back("+unaligned-vector-mem");
- } else {
- Features.push_back("-unaligned-scalar-mem");
- if (HasV)
- Features.push_back("-unaligned-vector-mem");
- }
+ if (A->getOption().matches(options::OPT_munaligned_access))
+ Features.push_back("+fast-unaligned-access");
+ else
+ Features.push_back("-fast-unaligned-access");
  }
 
  // Now add any that the user explicitly requested on the command line,

clang/test/Driver/riscv-features.c

@@ -27,19 +27,13 @@
 // DEFAULT: "-target-feature" "-save-restore"
 // DEFAULT-NOT: "-target-feature" "+save-restore"
 
-// RUN: %clang --target=riscv32-unknown-elf -### %s -munaligned-access 2>&1 | FileCheck %s -check-prefix=UNALIGNED-SCALAR-MEM
-// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-unaligned-access 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-SCALAR-MEM
-// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-strict-align 2>&1 | FileCheck %s -check-prefix=UNALIGNED-SCALAR-MEM
-// RUN: %clang --target=riscv32-unknown-elf -### %s -mstrict-align 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-SCALAR-MEM
-// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv -munaligned-access 2>&1 | FileCheck %s -check-prefix=UNALIGNED-VECTOR-MEM
-// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv -mno-unaligned-access 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-VECTOR-MEM
-// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv -mno-strict-align 2>&1 | FileCheck %s -check-prefix=UNALIGNED-VECTOR-MEM
-// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv -mstrict-align 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-VECTOR-MEM
-
-// UNALIGNED-SCALAR-MEM: "-target-feature" "+unaligned-scalar-mem"
-// NO-UNALIGNED-SCALAR-MEM: "-target-feature" "-unaligned-scalar-mem"
-// UNALIGNED-VECTOR-MEM: "-target-feature" "+unaligned-vector-mem"
-// NO-UNALIGNED-VECTOR-MEM: "-target-feature" "-unaligned-vector-mem"
+// RUN: %clang --target=riscv32-unknown-elf -### %s -munaligned-access 2>&1 | FileCheck %s -check-prefix=FAST-UNALIGNED-ACCESS
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-unaligned-access 2>&1 | FileCheck %s -check-prefix=NO-FAST-UNALIGNED-ACCESS
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-strict-align 2>&1 | FileCheck %s -check-prefix=FAST-UNALIGNED-ACCESS
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mstrict-align 2>&1 | FileCheck %s -check-prefix=NO-FAST-UNALIGNED-ACCESS
+
+// FAST-UNALIGNED-ACCESS: "-target-feature" "+fast-unaligned-access"
+// NO-FAST-UNALIGNED-ACCESS: "-target-feature" "-fast-unaligned-access"
 
 // RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
 // RUN: | FileCheck %s -check-prefix=DEFAULT-LINUX

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

@@ -309,8 +309,8 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
  .addReg(MBBI->getOperand(1).getReg())
  .add(MBBI->getOperand(2));
  if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
- // FIXME: Zdinx RV32 can not work on unaligned scalar memory.
- assert(!STI->enableUnalignedScalarMem());
+ // FIXME: Zdinx RV32 can not work on unaligned memory.
+ assert(!STI->hasFastUnalignedAccess());
 
  assert(MBBI->getOperand(2).getOffset() % 8 == 0);
  MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -946,15 +946,10 @@ def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence",
  "true",
  "Enable trailing fence for seq-cst store.">;
 
-def FeatureUnalignedScalarMem
- : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
- "true", "Has reasonably performant unaligned scalar "
- "loads and stores">;
-
-def FeatureUnalignedVectorMem
- : SubtargetFeature<"unaligned-vector-mem", "EnableUnalignedVectorMem",
- "true", "Has reasonably performant unaligned vector "
- "loads and stores">;
+def FeatureFastUnalignedAccess
+ : SubtargetFeature<"fast-unaligned-access", "HasFastUnalignedAccess",
+ "true", "Has reasonably performant unaligned "
+ "loads and stores (both scalar and vector)">;
 
 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
  "UsePostRAScheduler", "true", "Schedule again after register allocation">;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -1874,7 +1874,7 @@ bool RISCVTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
  // replace. If we don't support unaligned scalar mem, prefer the constant
  // pool.
  // TODO: Can the caller pass down the alignment?
- if (!Subtarget.enableUnalignedScalarMem())
+ if (!Subtarget.hasFastUnalignedAccess())
  return true;
 
  // Prefer to keep the load if it would require many instructions.
@@ -14689,7 +14689,7 @@ static bool matchIndexAsWiderOp(EVT VT, SDValue Index, SDValue Mask,
  if (WiderElementSize > ST.getELen()/8)
  return false;
 
- if (!ST.enableUnalignedVectorMem() && BaseAlign < WiderElementSize)
+ if (!ST.hasFastUnalignedAccess() && BaseAlign < WiderElementSize)
  return false;
 
  for (unsigned i = 0; i < Index->getNumOperands(); i++) {
@@ -19288,8 +19288,8 @@ bool RISCVTargetLowering::allowsMisalignedMemoryAccesses(
  unsigned *Fast) const {
  if (!VT.isVector()) {
  if (Fast)
- *Fast = Subtarget.enableUnalignedScalarMem();
- return Subtarget.enableUnalignedScalarMem();
+ *Fast = Subtarget.hasFastUnalignedAccess();
+ return Subtarget.hasFastUnalignedAccess();
  }
 
  // All vector implementations must support element alignment
@@ -19305,8 +19305,8 @@ bool RISCVTargetLowering::allowsMisalignedMemoryAccesses(
  // misaligned accesses. TODO: Work through the codegen implications of
  // allowing such accesses to be formed, and considered fast.
  if (Fast)
- *Fast = Subtarget.enableUnalignedVectorMem();
- return Subtarget.enableUnalignedVectorMem();
+ *Fast = Subtarget.hasFastUnalignedAccess();
+ return Subtarget.hasFastUnalignedAccess();
 }
 
 
@@ -19341,7 +19341,7 @@ EVT RISCVTargetLowering::getOptimalMemOpType(const MemOp &Op,
 
  // Do we have sufficient alignment for our preferred VT? If not, revert
  // to largest size allowed by our alignment criteria.
- if (PreferredVT != MVT::i8 && !Subtarget.enableUnalignedVectorMem()) {
+ if (PreferredVT != MVT::i8 && !Subtarget.hasFastUnalignedAccess()) {
  Align RequiredAlign(PreferredVT.getStoreSize());
  if (Op.isFixedDstAlign())
  RequiredAlign = std::min(RequiredAlign, Op.getDstAlign());
@@ -19533,7 +19533,7 @@ bool RISCVTargetLowering::isLegalStridedLoadStore(EVT DataType,
  if (!isLegalElementTypeForRVV(ScalarType))
  return false;
 
- if (!Subtarget.enableUnalignedVectorMem() &&
+ if (!Subtarget.hasFastUnalignedAccess() &&
  Alignment < ScalarType.getStoreSize())
  return false;
 

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

@@ -199,7 +199,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
  return false;
 
  EVT ElemType = DataTypeVT.getScalarType();
- if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
+ if (!ST->hasFastUnalignedAccess() && Alignment < ElemType.getStoreSize())
  return false;
 
  return TLI->isLegalElementTypeForRVV(ElemType);
@@ -224,7 +224,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
  return false;
 
  EVT ElemType = DataTypeVT.getScalarType();
- if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
+ if (!ST->hasFastUnalignedAccess() && Alignment < ElemType.getStoreSize())
  return false;
 
  return TLI->isLegalElementTypeForRVV(ElemType);

llvm/test/CodeGen/RISCV/memcpy-inline.ll

@@ -3,9 +3,9 @@
 ; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
 ; RUN: llc < %s -mtriple=riscv64 \
 ; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
-; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem \
+; RUN: llc < %s -mtriple=riscv32 -mattr=+fast-unaligned-access \
 ; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
-; RUN: llc < %s -mtriple=riscv64 -mattr=+unaligned-scalar-mem \
+; RUN: llc < %s -mtriple=riscv64 -mattr=+fast-unaligned-access \
 ; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
 
 ; ----------------------------------------------------------------------

llvm/test/CodeGen/RISCV/memcpy.ll

@@ -3,9 +3,9 @@
 ; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
 ; RUN: llc < %s -mtriple=riscv64 \
 ; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
-; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem \
+; RUN: llc < %s -mtriple=riscv32 -mattr=+fast-unaligned-access \
 ; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
-; RUN: llc < %s -mtriple=riscv64 -mattr=+unaligned-scalar-mem \
+; RUN: llc < %s -mtriple=riscv64 -mattr=+fast-unaligned-access \
 ; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
 %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
 

llvm/test/CodeGen/RISCV/memset-inline.ll

@@ -3,9 +3,9 @@
 ; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m \
 ; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
-; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+unaligned-scalar-mem \
+; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+fast-unaligned-access \
 ; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
-; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+unaligned-scalar-mem \
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+fast-unaligned-access \
 ; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
 %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }