[DAG] Fix shift amount limit in SimplifyDemandedBits trunc(shift(x,c)) to truncated bitwidth

We lost this in D56387/rG69bc0990a9181e6eb86228276d2f59435a7fae67 - where I got the src/dst bitwidths mixed up and assumed getValidShiftAmountConstant would catch it. Patch by @craig.topper - confirmed by @carrot that it fixes PR49162 (cherry picked from commit 7ad0c57)

Author: RKSimon

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -2012,7 +2012,7 @@ bool TargetLowering::SimplifyDemandedBits(
 
  const APInt *ShAmtC =
  TLO.DAG.getValidShiftAmountConstant(Src, DemandedElts);
- if (!ShAmtC)
+ if (!ShAmtC || ShAmtC->uge(BitWidth))
  break;
  uint64_t ShVal = ShAmtC->getZExtValue();
 

llvm/test/CodeGen/X86/pr49162.ll

@@ -17,7 +17,11 @@ define i32* @PR49162(i32* %base, i160* %ptr160) {
 ;
 ; X64-LABEL: PR49162:
 ; X64: # %bb.0:
-; X64-NEXT: leaq -4(%rdi), %rax
+; X64-NEXT: movl 8(%rsi), %eax
+; X64-NEXT: shll $16, %eax
+; X64-NEXT: cltq
+; X64-NEXT: sarq $16, %rax
+; X64-NEXT: leaq (%rdi,%rax,4), %rax
 ; X64-NEXT: retq
  %load160 = load i160, i160* %ptr160, align 4
  %shl = shl i160 %load160, 80