@@ -149,19 +149,12 @@ define <32 x i16> @illegal_no_extract_mul(<32 x i16> %i) nounwind {
149149
150150; Result would undershift 
151151define  <4  x i64 > @no_extract_shl (<4  x i64 > %i ) nounwind  {
152- ; X86-LABEL: no_extract_shl: 
153- ; X86: # %bb.0: 
154- ; X86-NEXT: vpsllq $24, %ymm0, %ymm1 
155- ; X86-NEXT: vpsrlq $39, %ymm0, %ymm0 
156- ; X86-NEXT: vpternlogq $236, {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %ymm1, %ymm0 
157- ; X86-NEXT: retl 
158- ; 
159- ; X64-LABEL: no_extract_shl: 
160- ; X64: # %bb.0: 
161- ; X64-NEXT: vpsllq $24, %ymm0, %ymm1 
162- ; X64-NEXT: vpsrlq $39, %ymm0, %ymm0 
163- ; X64-NEXT: vpternlogq $236, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm1, %ymm0 
164- ; X64-NEXT: retq 
152+ ; CHECK-LABEL: no_extract_shl: 
153+ ; CHECK: # %bb.0: 
154+ ; CHECK-NEXT: vpsllq $24, %ymm0, %ymm1 
155+ ; CHECK-NEXT: vpsrlq $39, %ymm0, %ymm0 
156+ ; CHECK-NEXT: vpternlogq {{.*#+}} ymm0 = (ymm0 & m64bcst) | ymm1 
157+ ; CHECK-NEXT: ret{{[l|q]}} 
165158 %lhs_mul  = shl  <4  x i64 > %i , <i64  11 , i64  11 , i64  11 , i64  11 >
166159 %rhs_mul  = shl  <4  x i64 > %i , <i64  24 , i64  24 , i64  24 , i64  24 >
167160 %lhs_shift  = lshr  <4  x i64 > %lhs_mul , <i64  50 , i64  50 , i64  50 , i64  50 >
@@ -171,19 +164,12 @@ define <4 x i64> @no_extract_shl(<4 x i64> %i) nounwind {
171164
172165; Result would overshift 
173166define  <4  x i32 > @no_extract_shrl (<4  x i32 > %i ) nounwind  {
174- ; X86-LABEL: no_extract_shrl: 
175- ; X86: # %bb.0: 
176- ; X86-NEXT: vpsrld $9, %xmm0, %xmm1 
177- ; X86-NEXT: vpslld $25, %xmm0, %xmm0 
178- ; X86-NEXT: vpternlogd $236, {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm1, %xmm0 
179- ; X86-NEXT: retl 
180- ; 
181- ; X64-LABEL: no_extract_shrl: 
182- ; X64: # %bb.0: 
183- ; X64-NEXT: vpsrld $9, %xmm0, %xmm1 
184- ; X64-NEXT: vpslld $25, %xmm0, %xmm0 
185- ; X64-NEXT: vpternlogd $236, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0 
186- ; X64-NEXT: retq 
167+ ; CHECK-LABEL: no_extract_shrl: 
168+ ; CHECK: # %bb.0: 
169+ ; CHECK-NEXT: vpsrld $9, %xmm0, %xmm1 
170+ ; CHECK-NEXT: vpslld $25, %xmm0, %xmm0 
171+ ; CHECK-NEXT: vpternlogd {{.*#+}} xmm0 = (xmm0 & m32bcst) | xmm1 
172+ ; CHECK-NEXT: ret{{[l|q]}} 
187173 %lhs_div  = lshr  <4  x i32 > %i , <i32  3 , i32  3 , i32  3 , i32  3 >
188174 %rhs_div  = lshr  <4  x i32 > %i , <i32  9 , i32  9 , i32  9 , i32  9 >
189175 %lhs_shift  = shl  <4  x i32 > %lhs_div , <i32  28 , i32  28 , i32  28 , i32  28 >
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