[Thumb2] carry.ll - regenerate test checks (#163173)

Author: RKSimon

llvm/test/CodeGen/Thumb2/carry.ll

@@ -1,35 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
 
 define i64 @f1(i64 %a, i64 %b) {
-entry:
 ; CHECK-LABEL: f1:
-; CHECK: subs r0, r0, r2
-; CHECK: sbcs r1, r3
-%tmp = sub i64 %a, %b
-ret i64 %tmp
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: subs r0, r0, r2
+; CHECK-NEXT: sbcs r1, r3
+; CHECK-NEXT: bx lr
+entry:
+ %tmp = sub i64 %a, %b
+ ret i64 %tmp
 }
 
 define i64 @f2(i64 %a, i64 %b) {
-entry:
 ; CHECK-LABEL: f2:
-; CHECK: lsls r1, r1, #1
-; CHECK: orr.w r1, r1, r0, lsr #31
-; CHECK: rsbs r0, r2, r0, lsl #1
-; CHECK: sbcs r1, r3
- %tmp1 = shl i64 %a, 1
-%tmp2 = sub i64 %tmp1, %b
-ret i64 %tmp2
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: lsls r1, r1, #1
+; CHECK-NEXT: orr.w r1, r1, r0, lsr #31
+; CHECK-NEXT: rsbs r0, r2, r0, lsl #1
+; CHECK-NEXT: sbcs r1, r3
+; CHECK-NEXT: bx lr
+entry:
+ %tmp1 = shl i64 %a, 1
+ %tmp2 = sub i64 %tmp1, %b
+ ret i64 %tmp2
 }
 
 ; rdar://12559385
 define i64 @f3(i32 %vi) {
-entry:
 ; CHECK-LABEL: f3:
-; CHECK: movw [[REG:r[0-9]+]], #36102
-; CHECK: sbcs r{{[0-9]+}}, [[REG]]
- %v0 = zext i32 %vi to i64
- %v1 = xor i64 %v0, -155057456198619
- %v4 = add i64 %v1, 155057456198619
- %v5 = add i64 %v4, %v1
- ret i64 %v5
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: movw r1, #19493
+; CHECK-NEXT: movt r1, #57191
+; CHECK-NEXT: eors r0, r1
+; CHECK-NEXT: movw r2, #29433
+; CHECK-NEXT: movw r3, #46043
+; CHECK-NEXT: movw r1, #36102
+; CHECK-NEXT: movt r2, #65535
+; CHECK-NEXT: adds r0, r0, r0
+; CHECK-NEXT: movt r3, #8344
+; CHECK-NEXT: sbcs r2, r1
+; CHECK-NEXT: adds r0, r0, r3
+; CHECK-NEXT: adcs r1, r2
+; CHECK-NEXT: bx lr
+entry:
+ %v0 = zext i32 %vi to i64
+ %v1 = xor i64 %v0, -155057456198619
+ %v4 = add i64 %v1, 155057456198619
+ %v5 = add i64 %v4, %v1
+ ret i64 %v5
 }