[VPlan] Implement printing VPIRMetadata.

Implement and use debug printing for VPIRMetadata.

Author: fhahn

llvm/lib/Transforms/Vectorize/VPlan.h

@@ -968,6 +968,9 @@ class VPIRMetadata {
  /// Intersect this VPIRMetada object with \p MD, keeping only metadata
  /// nodes that are common to both.
  void intersect(const VPIRMetadata &MD);
+
+ /// Print metadata with node IDs.
+ void print(raw_ostream &O, const Module &M) const;
 };
 
 /// This is a concrete Recipe that models a single VPlan-level instruction.
@@ -4282,6 +4285,11 @@ class VPlan {
  /// Return the VPIRBasicBlock wrapping the header of the scalar loop.
  VPIRBasicBlock *getScalarHeader() const { return ScalarHeader; }
 
+ /// Return the Module from the scalar header.
+ const Module &getModule() const {
+ return *ScalarHeader->getIRBasicBlock()->getModule();
+ }
+
  /// Return an ArrayRef containing VPIRBasicBlocks wrapping the exit blocks of
  /// the original scalar loop.
  ArrayRef<VPIRBasicBlock *> getExitBlocks() const { return ExitBlocks; }

llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

@@ -1443,6 +1443,7 @@ void VPInstruction::print(raw_ostream &O, const Twine &Indent,
 
  printFlags(O);
  printOperands(O, SlotTracker);
+ VPIRMetadata::print(O, getParent()->getPlan()->getModule());
 
  if (auto DL = getDebugLoc()) {
  O << ", !dbg ";
@@ -1669,6 +1670,25 @@ void VPIRMetadata::intersect(const VPIRMetadata &Other) {
  Metadata = std::move(MetadataIntersection);
 }
 
+void VPIRMetadata::print(raw_ostream &O, const Module &M) const {
+ if (Metadata.empty())
+ return;
+
+ SmallVector<StringRef, 8> MDNames;
+ M.getContext().getMDKindNames(MDNames);
+
+ O << " (";
+ interleaveComma(Metadata, O, [&](const auto &KindNodePair) {
+ auto [Kind, Node] = KindNodePair;
+ assert(Kind != 0 && "Debug metadata should not be managed by VPIRMetadata");
+ assert(Kind < MDNames.size() && !MDNames[Kind].empty() &&
+ "Unexpected unnamed metadata kind");
+ O << "!" << MDNames[Kind] << " ";
+ Node->printAsOperand(O, &M);
+ });
+ O << ")";
+}
+
 void VPWidenCallRecipe::execute(VPTransformState &State) {
  assert(State.VF.isVector() && "not widening");
  assert(Variant != nullptr && "Can't create vector function.");
@@ -1729,6 +1749,7 @@ void VPWidenCallRecipe::print(raw_ostream &O, const Twine &Indent,
  Op->printAsOperand(O, SlotTracker);
  });
  O << ")";
+ VPIRMetadata::print(O, getParent()->getPlan()->getModule());
 
  O << " (using library function";
  if (Variant->hasName())
@@ -1863,6 +1884,7 @@ void VPWidenIntrinsicRecipe::print(raw_ostream &O, const Twine &Indent,
  Op->printAsOperand(O, SlotTracker);
  });
  O << ")";
+ VPIRMetadata::print(O, getParent()->getPlan()->getModule());
 }
 #endif
 
@@ -2255,6 +2277,7 @@ void VPWidenRecipe::print(raw_ostream &O, const Twine &Indent,
  O << " = " << Instruction::getOpcodeName(Opcode);
  printFlags(O);
  printOperands(O, SlotTracker);
+ VPIRMetadata::print(O, getParent()->getPlan()->getModule());
 }
 #endif
 
@@ -2336,6 +2359,7 @@ void VPWidenCastRecipe::print(raw_ostream &O, const Twine &Indent,
  printFlags(O);
  printOperands(O, SlotTracker);
  O << " to " << *getResultType();
+ VPIRMetadata::print(O, getParent()->getPlan()->getModule());
 }
 #endif
 
@@ -3617,6 +3641,7 @@ void VPWidenLoadRecipe::print(raw_ostream &O, const Twine &Indent,
  printAsOperand(O, SlotTracker);
  O << " = load ";
  printOperands(O, SlotTracker);
+ VPIRMetadata::print(O, getParent()->getPlan()->getModule());
 }
 #endif
 
@@ -3738,6 +3763,7 @@ void VPWidenStoreRecipe::print(raw_ostream &O, const Twine &Indent,
  VPSlotTracker &SlotTracker) const {
  O << Indent << "WIDEN store ";
  printOperands(O, SlotTracker);
+ VPIRMetadata::print(O, getParent()->getPlan()->getModule());
 }
 #endif
 

llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll

@@ -7,11 +7,11 @@ define void @test_widen_metadata(ptr noalias %A, ptr noalias %B, i32 %n) {
 ; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
 ; CHECK: <x1> vector loop: {
 ; CHECK: vector.body:
-; CHECK: WIDEN ir<%lv> = load vp<{{.*}}>
-; CHECK: WIDEN-CAST ir<%conv> = sitofp ir<%lv> to float
-; CHECK: WIDEN ir<%mul> = fmul ir<%conv>, ir<2.000000e+00>
+; CHECK: WIDEN ir<%lv> = load vp<{{.*}}> (!tbaa !{{[0-9]+}})
+; CHECK: WIDEN-CAST ir<%conv> = sitofp ir<%lv> to float (!fpmath !{{[0-9]+}})
+; CHECK: WIDEN ir<%mul> = fmul ir<%conv>, ir<2.000000e+00> (!fpmath !{{[0-9]+}})
 ; CHECK: WIDEN-CAST ir<%conv.back> = fptosi ir<%mul> to i32
-; CHECK: WIDEN store vp<{{.*}}>, ir<%conv.back>
+; CHECK: WIDEN store vp<{{.*}}>, ir<%conv.back> (!tbaa !{{[0-9]+}})
 ;
 entry:
  br label %loop
@@ -40,9 +40,9 @@ define void @test_intrinsic_with_metadata(ptr noalias %A, ptr noalias %B, i32 %n
 ; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
 ; CHECK: <x1> vector loop: {
 ; CHECK: vector.body:
-; CHECK: WIDEN ir<%lv> = load vp<{{.*}}>
-; CHECK: WIDEN-INTRINSIC ir<%sqrt> = call llvm.sqrt(ir<%lv>)
-; CHECK: WIDEN store vp<{{.*}}>, ir<%sqrt>
+; CHECK: WIDEN ir<%lv> = load vp<{{.*}}> (!tbaa !{{[0-9]+}})
+; CHECK: WIDEN-INTRINSIC ir<%sqrt> = call llvm.sqrt(ir<%lv>) (!fpmath !{{[0-9]+}})
+; CHECK: WIDEN store vp<{{.*}}>, ir<%sqrt> (!tbaa !{{[0-9]+}})
 ;
 entry:
  br label %loop
@@ -67,11 +67,11 @@ define void @test_widen_with_multiple_metadata(ptr noalias %A, ptr noalias %B, i
 ; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
 ; CHECK: <x1> vector loop: {
 ; CHECK: vector.body:
-; CHECK: WIDEN ir<%lv> = load vp<{{.*}}>
+; CHECK: WIDEN ir<%lv> = load vp<{{.*}}> (!tbaa !{{[0-9]+}})
 ; CHECK: WIDEN-CAST ir<%conv> = sitofp ir<%lv> to float
 ; CHECK: WIDEN ir<%mul> = fmul ir<%conv>, ir<2.000000e+00>
 ; CHECK: WIDEN-CAST ir<%conv.back> = fptosi ir<%mul> to i32
-; CHECK: WIDEN store vp<{{.*}}>, ir<%conv.back>
+; CHECK: WIDEN store vp<{{.*}}>, ir<%conv.back> (!tbaa !{{[0-9]+}})
 ;
 entry:
  br label %loop