[LV] Return getPredBlockCostDivisor in uint64_t

When the probability of a block is extremely low, HeaderFreq / BBFreq may be larger than 32 bits. Previously this got truncated to uint32_t which could cause division by zero exceptions on x86. Widen the return type to uint64_t which should fit the entire range of BlockFrequency values. It's also worth noting that a frequency can never be zero according to BlockFrequency.h, so we shouldn't need to worry about divide by zero in getPredBlockCostDivisor itself.

Author: lukel97

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

@@ -1240,7 +1240,7 @@ class LoopVectorizationCostModel {
  /// Note that if a block wasn't originally predicated but was predicated due
  /// to tail folding, the divisor will still be 1 because it will execute for
  /// every iteration of the loop header.
- inline unsigned
+ inline uint64_t
  getPredBlockCostDivisor(TargetTransformInfo::TargetCostKind CostKind,
  const BasicBlock *BB);
 
@@ -2893,7 +2893,7 @@ bool LoopVectorizationCostModel::isPredicatedInst(Instruction *I) const {
  }
 }
 
-unsigned LoopVectorizationCostModel::getPredBlockCostDivisor(
+uint64_t LoopVectorizationCostModel::getPredBlockCostDivisor(
  TargetTransformInfo::TargetCostKind CostKind, const BasicBlock *BB) {
  if (CostKind == TTI::TCK_CodeSize)
  return 1;

llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll

@@ -438,6 +438,55 @@ exit:
  ret void
 }
 
+; BFI computes the relative frequency of if.2 to the loop header to be extremely
+; low, so the discount in getPredBlockCostDivisor is high enough to not fit in
+; uint32_t. Make sure we return uint64_t which fits all possible BlockFrequency
+; values.
+define void @getPredBlockCostDivisor_truncate(i32 %0) {
+; CHECK-LABEL: define void @getPredBlockCostDivisor_truncate(
+; CHECK-SAME: i32 [[TMP0:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[TMP0]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; CHECK-NEXT: [[ISNAN_1:%.*]] = fcmp uno double 0.000000e+00, 0.000000e+00
+; CHECK-NEXT: br i1 [[ISNAN_1]], label %[[IF_1:.*]], label %[[LATCH]]
+; CHECK: [[IF_1]]:
+; CHECK-NEXT: [[ISNAN_2:%.*]] = fcmp uno double 0.000000e+00, 0.000000e+00
+; CHECK-NEXT: br i1 [[ISNAN_2]], label %[[IF_2:.*]], label %[[LATCH]]
+; CHECK: [[IF_2]]:
+; CHECK-NEXT: br label %[[LATCH]]
+; CHECK: [[LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV]], 0
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [ %0, %entry ], [ %iv.next, %latch ]
+ %isnan.1 = fcmp uno double 0.000000e+00, 0.000000e+00
+ br i1 %isnan.1, label %if.1, label %latch
+
+if.1:
+ %isnan.2 = fcmp uno double 0.000000e+00, 0.000000e+00
+ br i1 %isnan.2, label %if.2, label %latch
+
+if.2:
+ br label %latch
+
+latch:
+ %iv.next = add i32 %iv, 1
+ %ec = icmp eq i32 %iv, 0
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
 ;.
 ; CHECK: [[META0]] = !{[[META1:![0-9]+]]}
 ; CHECK: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]}