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Author: HolyMolyCowMan

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp

@@ -137,22 +137,37 @@ bool isZeroExtended(Register R, MachineRegisterInfo &MRI) {
  return MRI.getVRegDef(R)->getOpcode() == TargetOpcode::G_ZEXT;
 }
 
+// This patten aims to match the following shape to avoid extra mov instructions
+// G_BUILD_VECTOR(
+// G_UNMERGE_VALUES(src, 0)
+// G_UNMERGE_VALUES(src, 1)
+// G_IMPLICIT_DEF
+// G_IMPLICIT_DEF
+// )
+// ->
+// G_CONCAT_VECTORS(
+// G_BUILD_VECTOR(
+// G_IMPLICIT_DEF
+// G_IMPLICIT_DEF
+// )
+// src
+// )
 bool matchCombineBuildUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
- SmallVectorImpl<Register> &unmergeSrc,
- SmallVectorImpl<Register> &undefinedValues) {
+ SmallVectorImpl<Register> &UnmergeSrc,
+ SmallVectorImpl<Register> &UndefinedValues) {
  assert(MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
 
- undefinedValues.clear();
- unmergeSrc.clear();
+ UndefinedValues.clear();
+ UnmergeSrc.clear();
 
- std::set<int> knownRegs;
+ std::set<int> KnownRegs;
 
  for (auto Use : MI.all_uses()) {
  auto *Def = getDefIgnoringCopies(Use.getReg(), MRI);
 
  if (!Def) {
- undefinedValues.clear();
- unmergeSrc.clear();
+ UndefinedValues.clear();
+ UnmergeSrc.clear();
  return false;
  }
 
@@ -162,33 +177,33 @@ bool matchCombineBuildUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
  default:
  return false;
  case TargetOpcode::G_IMPLICIT_DEF:
- undefinedValues.push_back(Use.getReg());
+ UndefinedValues.push_back(Use.getReg());
  break;
  case TargetOpcode::G_UNMERGE_VALUES:
  // We only want to match G_UNMERGE_VALUES <2 x Ty>
  // s16 is troublesome as <2 x s16> is generally not legal
  if (Def->getNumDefs() != 2 ||
  MRI.getType(Use.getReg()) == LLT::scalar(16)) {
- undefinedValues.clear();
- unmergeSrc.clear();
+ UndefinedValues.clear();
+ UnmergeSrc.clear();
  return false;
  }
 
  // Only track unique sources for the G_UNMERGE_VALUES
- if (knownRegs.find(Def->getOperand(2).getReg().id()) != knownRegs.end())
- continue; 
+ if (KnownRegs.find(Def->getOperand(2).getReg().id()) != KnownRegs.end())
+ continue;
+
+ KnownRegs.insert(Def->getOperand(2).getReg().id());
+ UnmergeSrc.push_back(Def->getOperand(2).getReg());
 
- knownRegs.insert(Def->getOperand(2).getReg().id());
- unmergeSrc.push_back(Def->getOperand(2).getReg());
- 
  break;
  }
  }
 
  // Only want to match patterns that pad two values with two undefined values
- if (!(undefinedValues.size() == 2 && unmergeSrc.size() == 1)) {
- undefinedValues.clear();
- unmergeSrc.clear();
+ if (!(UndefinedValues.size() == 2 && UnmergeSrc.size() == 1)) {
+ UndefinedValues.clear();
+ UnmergeSrc.clear();
  return false;
  }
 
@@ -197,19 +212,18 @@ bool matchCombineBuildUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
 
 void applyCombineBuildUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
  MachineIRBuilder &B,
- SmallVectorImpl<Register> &unmergeSrc,
- SmallVectorImpl<Register> &undefinedValues) {
- assert(unmergeSrc.size() == 1 && "Expected there to be one G_UNMERGE_VALUES");
+ SmallVectorImpl<Register> &UnmergeSrc,
+ SmallVectorImpl<Register> &UndefinedValues) {
+ assert(UnmergeSrc.size() == 1 && "Expected there to be one G_UNMERGE_VALUES");
  B.setInstrAndDebugLoc(MI);
 
- auto llt = LLT::fixed_vector(
- undefinedValues.size(),
- LLT::scalar(MRI.getType(unmergeSrc[0]).getScalarSizeInBits()));
-
- Register DefVec = MRI.createGenericVirtualRegister(llt);
+ auto UndefVecLLT = LLT::fixed_vector(
+ UndefinedValues.size(),
+ LLT::scalar(MRI.getType(UnmergeSrc[0]).getScalarSizeInBits()));
+ Register UndefVec = MRI.createGenericVirtualRegister(UndefVecLLT);
 
-  B.buildBuildVector(DefVec, undefinedValues);
-  B.buildConcatVectors(MI.getOperand(0), {unmergeSrc[0], DefVec});
+ B.buildBuildVector(UndefVec, UndefinedValues);
+ B.buildConcatVectors(MI.getOperand(0), {UnmergeSrc[0], UndefVec});
 
  MI.eraseFromParent();
 }

llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir

@@ -556,6 +556,9 @@
 # DEBUG-NEXT: G_FPTRUNC (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. the first uncovered type index: 2, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: G_FPTRUNC_ODD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_FPTOSI (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. the first uncovered type index: 2, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK