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Yogaraj-Alamendashikundi
Yogaraj-Alamenda
and
shikundi
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Add support for QAT HW & QAT SW Coexistence.
- Provide provision to enable build that links QAT HW & QAT SW libraries together and take decision at run time. - Add QAT device check for 1.7 device and enable QAT_HW when QAT Hardware is available - Removed dependancy with disable flags for enabling other algo and give preference to algorithm enable flag when both --with-qat_hw_dir & --enable-qat_sw is provided. Co-authored-by: Shikun Ding <shikun.ding@intel.com> Signed-off-by: Yogaraj Alamenda <yogarajx.alamenda@intel.com>
1 parent 639d94d commit c34ac30

25 files changed

+581
-524
lines changed

‎Makefile.am‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -80,17 +80,14 @@ AM_CFLAGS = $(cflags) $(cflags_cc_opt) $(cflags_qat_debug_file) \
8080
$(cflags_mem_driver) $(cflags_openssl_3) \
8181
$(cflags_qat_engine_id) $(cflags_qat_hw_intree) \
8282
$(cflags_qat_hw) $(cflags_qat_sw) $(cflags_qat_sw_ipsec) \
83-
$(enable_qat_hw_rsa) $(enable_qat_hw_ciphers) \
84-
$(enable_qat_hw_gcm) $(enable_qat_hw_dh) \
85-
$(enable_qat_hw_ecdsa) $(enable_qat_hw_dsa) \
86-
$(enable_qat_hw_ecdh) $(enable_qat_hw_prf) \
87-
$(enable_qat_hw_hkdf) $(enable_qat_hw_ecx) \
83+
$(cflags_qat_rsa) $(cflags_qat_ecx) $(cflags_qat_ecdsa) \
84+
$(cflags_qat_ecdh) $(cflags_qat_gcm) $(enable_qat_hw_dh) \
85+
$(enable_qat_hw_dsa) $(enable_qat_hw_ciphers) \
86+
$(enable_qat_hw_prf) $(enable_qat_hw_hkdf) \
8887
$(enable_qat_hw_small_pkt_offload) \
8988
$(enable_qat_hw_lenstra_protection) \
9089
$(enable_qat_hw_lenstra_verify_hw) \
91-
$(enable_qat_sw_gcm) $(enable_qat_sw_rsa) \
92-
$(enable_qat_sw_ecx) $(enable_qat_sw_ecdsa) \
93-
$(enable_qat_sw_ecdh) $(enable_qat_sw_heuristic_timeout) \
90+
$(enable_qat_sw_heuristic_timeout) \
9491
$(enable_qat_auto_engine_init_on_fork) \
9592
$(enable_qat_debug) $(enable_qat_warnings) \
9693
$(enable_qat_mem_debug) $(enable_qat_mem_warnings) \

‎configure.ac‎

Lines changed: 165 additions & 116 deletions
Large diffs are not rendered by default.

‎docs/features.md‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,5 +33,7 @@
3333
* NIST Prime Curves: P-256/P-384
3434
* AES128-GCM, AES192-GCM and AES256-GCM
3535

36+
[QAT_HW & QAT_SW Co-existence Feature](qat_hw.md#qat-hw-and-qat-sw-co-existence-feature)
37+
3638
Note: RSA Padding schemes are handled by OpenSSL\* rather than accelerated, so the
3739
engine supports the same padding schemes as OpenSSL does natively.

‎docs/qat_hw.md‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,3 +76,26 @@ This document can be found on the 01.org website at the following hyperlink:
7676
* [Intel&reg; QuickAssist Technology Programmer's Guide][2]
7777

7878
[2]:https://01.org/sites/default/files/downloads/336210qatswpg-013.pdf
79+
80+
### QAT_HW and QAT_SW Co-existence Feature
81+
82+
Intel&reg; QAT OpenSSL\* Engine supports QAT_HW and QAT_SW Co-existence build
83+
with both QAT_HW and QAT_SW dependant libraries(QAT Driver, cryptom_mb and
84+
ipsec_mb) linked in the qatengine.so library. This support can be enabled at
85+
build time when both QAT_HW flag `--with-qat_hw_dir=/path/to/QAT_Driver`
86+
and QAT_SW flag `--enable-qat_sw` configured together in the build configure
87+
option.
88+
89+
If the platform has support for both QAT_HW and QAT_SW, the default
90+
behaviour is to accelerate asymmetric algorithms and Symmetric chained ciphers
91+
using QAT Hardware and Symmetric GCM Ciphers using QAT Software. If the platform
92+
doesn't have QAT Hardware support then it will use QAT_SW Acceleration for
93+
QAT_SW asymmetric algorithms that are supported in the qatengine.
94+
95+
The default behaviour can be changed using corresponding algorithm's enable
96+
flags (eg:--enable-qat_sw_rsa) in which case the individual algorithms enabled
97+
(eiher qat_hw or qat_sw) in the build configure will get accelerated.
98+
99+
Note: ECDH & ECDSA can be accelerated together via QAT_HW or QAT_SW and
100+
cannot be seperated to use different acceleration due to limitation in
101+
the qatengine registration.

‎e_qat.c‎

Lines changed: 75 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -54,10 +54,11 @@
5454

5555
/* Defines */
5656
#ifdef QAT_HW
57+
# define QAT_DEV "/dev/qat_dev_processes"
5758
# if defined(USE_QAT_CONTIG_MEM) && !defined(USE_USDM_MEM)
58-
# define QAT_DEV "/dev/qat_contig_mem"
59+
# define QAT_MEM_DEV "/dev/qat_contig_mem"
5960
# elif defined(USE_USDM_MEM) && !defined(USE_QAT_CONTIG_MEM)
60-
# define QAT_DEV "/dev/usdm_drv"
61+
# define QAT_MEM_DEV "/dev/usdm_drv"
6162
# elif defined(USE_USDM_MEM) && defined(USE_QAT_CONFIG_MEM)
6263
# error "USE_QAT_CONTIG_MEM and USE_USDM_MEM both defined"
6364
# else
@@ -157,7 +158,11 @@ const char *engine_qat_name =
157158
#endif
158159
unsigned int engine_inited = 0;
159160

160-
int qat_offload = 0;
161+
int qat_hw_offload = 0;
162+
int qat_sw_offload = 0;
163+
int qat_hw_rsa_offload = 0;
164+
int qat_hw_ecx_offload = 0;
165+
int qat_hw_ec_offload = 0;
161166
int qat_keep_polling = 1;
162167
int multibuff_keep_polling = 1;
163168
int enable_external_polling = 0;
@@ -391,12 +396,13 @@ static int qat_engine_destroy(ENGINE *e)
391396
#endif
392397

393398
#ifdef QAT_SW_IPSEC
394-
# ifndef DISABLE_QAT_SW_GCM
399+
# ifdef ENABLE_QAT_SW_GCM
395400
vaesgcm_free_ipsec_mb_mgr();
396401
# endif
397402
#endif
398403

399-
qat_offload = 0;
404+
qat_hw_offload = 0;
405+
qat_sw_offload = 0;
400406
QAT_DEBUG_LOG_CLOSE();
401407
ERR_unload_QAT_strings();
402408
return 1;
@@ -474,11 +480,11 @@ int qat_engine_init(ENGINE *e)
474480
return 1;
475481
}
476482

477-
DEBUG("QAT Engine initialization:\n");
478483
CRYPTO_INIT_QAT_LOG();
484+
DEBUG("QAT Engine initialization:\n");
479485

480486
#ifdef QAT_HW
481-
if (qat_offload) {
487+
if (qat_hw_offload) {
482488
if (!qat_init(e)) {
483489
WARN("QAT initialization Failed\n");
484490
return 0;
@@ -487,7 +493,7 @@ int qat_engine_init(ENGINE *e)
487493
#endif
488494

489495
#ifdef QAT_SW
490-
if (!qat_offload) {
496+
if (qat_sw_offload) {
491497
if (!multibuff_init(e)) {
492498
WARN("Multibuff initialization Failed\n");
493499
return 0;
@@ -509,13 +515,13 @@ int qat_engine_finish_int(ENGINE *e, int reset_globals)
509515
qat_pthread_mutex_lock();
510516

511517
#ifdef QAT_HW
512-
if (qat_offload) {
518+
if (qat_hw_offload) {
513519
ret = qat_finish_int(e, reset_globals);
514520
}
515521
#endif
516522

517523
#ifdef QAT_SW
518-
if (!qat_offload) {
524+
if (qat_sw_offload) {
519525
ret = multibuff_finish_int(e, reset_globals);
520526
}
521527
#endif
@@ -862,11 +868,23 @@ static int bind_qat(ENGINE *e, const char *id)
862868
DEBUG("QAT Debug enabled.\n");
863869
WARN("%s - %s \n", id, engine_qat_name);
864870

865-
#if defined(QAT_HW) && !defined(QAT_HW_INTREE)
866-
if (access(QAT_DEV, F_OK) != 0) {
867-
WARN("Qat memory driver not present\n");
868-
goto end;
871+
#ifdef QAT_HW
872+
#ifdef QAT_HW_INTREE
873+
if (icp_sal_userIsQatAvailable() == CPA_TRUE) {
874+
qat_hw_offload = 1;
875+
} else {
876+
WARN("Qat Intree device not available\n");
877+
#else
878+
if (access(QAT_DEV, F_OK) == 0) {
879+
qat_hw_offload = 1;
880+
if (access(QAT_MEM_DEV, F_OK) != 0) {
881+
WARN("Qat memory driver not present\n");
882+
goto end;
883+
}
884+
} else {
885+
WARN("Qat device not available\n");
869886
}
887+
#endif
870888
#endif
871889

872890
if (id && (strcmp(id, engine_qat_id) != 0)) {
@@ -887,86 +905,80 @@ static int bind_qat(ENGINE *e, const char *id)
887905
/* Ensure the QAT error handling is set up */
888906
ERR_load_QAT_strings();
889907

908+
if (qat_hw_offload) {
890909
#ifdef QAT_HW
891-
892-
# ifdef QAT_INTREE
893-
if (icp_sal_userIsQatAvailable() == CPA_TRUE) {
894-
# endif
895-
DEBUG("Registering QAT supported algorithms\n");
896-
qat_offload = 1;
910+
DEBUG("Registering QAT HW supported algorithms\n");
897911

898912
/* Create static structures for ciphers now
899913
* as this function will be called by a single thread. */
900914
qat_create_ciphers();
901915

916+
# ifdef ENABLE_QAT_HW_RSA
902917
if (!ENGINE_set_RSA(e, qat_get_RSA_methods())) {
903-
WARN("ENGINE_set_RSA failed\n");
918+
WARN("ENGINE_set_RSA QAT HW failed\n");
904919
goto end;
905920
}
921+
# endif
906922

923+
# ifdef ENABLE_QAT_HW_DSA
907924
if (!ENGINE_set_DSA(e, qat_get_DSA_methods())) {
908-
WARN("ENGINE_set_DSA failed\n");
925+
WARN("ENGINE_set_DSA QAT HW failed\n");
909926
goto end;
910927
}
928+
# endif
911929

930+
# ifdef ENABLE_QAT_HW_DH
912931
if (!ENGINE_set_DH(e, qat_get_DH_methods())) {
913-
WARN("ENGINE_set_DH failed\n");
932+
WARN("ENGINE_set_DH QAT HW failed\n");
914933
goto end;
915934
}
935+
# endif
916936

937+
# if defined(ENABLE_QAT_HW_ECDH) || defined(ENABLE_QAT_HW_ECDSA)
917938
if (!ENGINE_set_EC(e, qat_get_EC_methods())) {
918-
WARN("ENGINE_set_EC failed\n");
939+
WARN("ENGINE_set_EC QAT HW failed\n");
919940
goto end;
920941
}
921-
922-
#ifndef QAT_OPENSSL_3
923-
if (!ENGINE_set_pkey_meths(e, qat_pkey_methods)) {
924-
WARN("ENGINE_set_pkey_meths failed\n");
925-
goto end;
926-
}
927-
#endif
928-
# ifdef QAT_INTREE
929-
}
930942
# endif
931943
#endif
944+
}
932945

933946
#ifdef QAT_SW
934-
if (!qat_offload) {
935-
if (mbx_get_algo_info(MBX_ALGO_RSA_2K) &&
947+
DEBUG("Registering QAT SW supported algorithms\n");
948+
949+
# ifdef ENABLE_QAT_SW_RSA
950+
if (!qat_hw_rsa_offload &&
951+
mbx_get_algo_info(MBX_ALGO_RSA_2K) &&
936952
mbx_get_algo_info(MBX_ALGO_RSA_3K) &&
937953
mbx_get_algo_info(MBX_ALGO_RSA_4K)) {
938-
DEBUG("Multibuffer RSA Supported\n");
954+
DEBUG("QAT SW RSA Supported\n");
955+
qat_sw_offload = 1;
939956
if (!ENGINE_set_RSA(e, multibuff_get_RSA_methods())) {
940-
WARN("ENGINE_set_RSA failed\n");
941-
goto end;
942-
}
943-
}
944-
# ifndef QAT_OPENSSL_3
945-
if (mbx_get_algo_info(MBX_ALGO_X25519)) {
946-
DEBUG("Multibuffer ECDH X25519 Supported\n");
947-
if (!ENGINE_set_pkey_meths(e, multibuff_x25519_pkey_methods)) {
948-
WARN("ENGINE_set_pkey_meths failed\n");
957+
WARN("ENGINE_set_RSA QAT SW failed\n");
949958
goto end;
950959
}
951960
}
952961
# endif
953962

954-
if (mbx_get_algo_info(MBX_ALGO_ECDHE_NIST_P256) &&
963+
# if defined(ENABLE_QAT_SW_ECDH) || defined(ENABLE_QAT_SW_ECDSA)
964+
if (!qat_hw_ec_offload &&
965+
mbx_get_algo_info(MBX_ALGO_ECDHE_NIST_P256) &&
955966
mbx_get_algo_info(MBX_ALGO_ECDHE_NIST_P384) &&
956967
mbx_get_algo_info(MBX_ALGO_ECDSA_NIST_P256) &&
957968
mbx_get_algo_info(MBX_ALGO_ECDSA_NIST_P384)) {
958-
DEBUG("Multibuffer ECDSA p256/p384 & ECDH p256/p384 Supported\n");
969+
DEBUG("QAT SW ECDSA p256/p384 & ECDH p256/p384 Supported\n");
970+
qat_sw_offload = 1;
959971
if (!ENGINE_set_EC(e, mb_get_EC_methods())) {
960-
WARN("ENGINE_set_EC failed\n");
972+
WARN("ENGINE_set_EC QAT SW failed\n");
961973
goto end;
962974
}
963975
}
964-
}
976+
# endif
965977
#endif
966978

967979
#ifdef QAT_SW_IPSEC
968980
if (hw_support()) {
969-
# ifndef DISABLE_QAT_SW_GCM
981+
# ifdef ENABLE_QAT_SW_GCM
970982
if (!vaesgcm_init_ipsec_mb_mgr()) {
971983
WARN("IPSec Multi-Buffer Manager Initialization failed\n");
972984
goto end;
@@ -975,6 +987,19 @@ static int bind_qat(ENGINE *e, const char *id)
975987
}
976988
#endif
977989

990+
#if defined(QAT_HW) || defined(QAT_SW)
991+
# ifndef QAT_OPENSSL_3
992+
if (!ENGINE_set_pkey_meths(e, qat_pkey_methods)) {
993+
WARN("ENGINE_set_pkey_meths failed\n");
994+
goto end;
995+
}
996+
# if ENABLE_QAT_SW_ECX
997+
if (mbx_get_algo_info(MBX_ALGO_X25519))
998+
qat_sw_offload = 1;
999+
# endif
1000+
# endif
1001+
#endif
1002+
9781003
#if defined(QAT_HW) || defined(QAT_SW_IPSEC)
9791004
if (!ENGINE_set_ciphers(e, qat_ciphers)) {
9801005
WARN("ENGINE_set_ciphers failed\n");

‎e_qat.h‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -298,7 +298,11 @@ extern const char *engine_qat_id;
298298
extern const char *engine_qat_name;
299299
extern unsigned int engine_inited;
300300

301-
extern int qat_offload;
301+
extern int qat_hw_offload;
302+
extern int qat_sw_offload;
303+
extern int qat_hw_rsa_offload;
304+
extern int qat_hw_ecx_offload;
305+
extern int qat_hw_ec_offload;
302306
extern int qat_keep_polling;
303307
extern int multibuff_keep_polling;
304308
extern int enable_external_polling;

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