Background

During program execution, polling is often used to wait for certain values to be written to memory (e.g., waiting for a lock release or producer data). Such polling wastes energy.

To address this inefficiency, the WRS (Wait for Reservation Set) instruction is introduced. Instead of actively polling a memory location, software can:

1. Register a reservation set (covering all bytes of the target memory location) using the LR (Load-Reserved) instruction.
2. Execute a subsequent WRS.NTO instruction, which stalls the hardware thread (hart) in a low-power state until either:

• A store operation modifies the reserved memory location.
• An interrupt occurs.

Instructions

• WRS.NTO (No Timeout):
  Enters low-power mode, waiting indefinitely for the reserved memory location to be written.
• WRS.STO (Short Timeout):
  Enters low-power mode but bounds the wait duration to a hardware-defined short timeout (stall ends if no write/interrupt occurs).

Usage

The Zawrs extension instructions require the LR instruction (provided by the A extension’s Zalrsc component). Steps:

1. Use LR to register the memory location.
2. Use Zawrs instructions (WRS.NTO/WRS.STO) to wait.

Implementation

The riscv-opcode tool generates the following instruction templates:

case AWRSNTO: return &inst{0x73, 0x0, 0x0, 0xd, 13, 0x0}// WRS.NTO encoding case AWRSSTO: return &inst{0x73, 0x0, 0x0, 0x1d, 29, 0x0} // WRS.STO encoding

In the RISC-V manual, the encoding format of these instructions are as follows:

• Encoding: Follows the I-type format.
• ins.imm is set based on the instruction type.
• rs1 and rd are set to 0.