Merge branch 'bugfix/fix_voip_pop_voice' into 'master'

bugfix(example): Fixed voip example pop voice in mini board See merge request adf/esp-adf-internal!1436

Author: jason-mao

components/audio_hal/driver/es7210/es7210.c

@@ -600,6 +600,6 @@ void es7210_read_all(void)
 {
  for (int i = 0; i <= 0x4E; i++) {
  uint8_t reg = es7210_read_reg(i);
- ESP_LOGI(TAG, "REG:%02x, %02x", reg, i);
+ ESP_LOGI(TAG, "REG:%02x, %02x", i, reg);
  }
 }

components/audio_hal/driver/es8311/es8311.c

@@ -301,68 +301,15 @@ esp_err_t es8311_pa_power(bool enable)
  return ret;
 }
 
-esp_err_t es8311_codec_init(audio_hal_codec_config_t *codec_cfg)
+esp_err_t es8311_config_sample(int sample_rate)
 {
- uint8_t datmp, regv;
- int coeff;
  esp_err_t ret = ESP_OK;
- i2c_init(); // ESP32 in master mode
-
- /* Enhance ES8311 I2C noise immunity */
- ret |= es8311_write_reg(ES8311_GPIO_REG44, 0x08);
- /* Due to occasional failures during the first I2C write with the ES8311 chip, a second write is performed to ensure reliability */
- ret |= es8311_write_reg(ES8311_GPIO_REG44, 0x08);
-
- ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG01, 0x30);
- ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG02, 0x00);
- ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG03, 0x10);
- ret |= es8311_write_reg(ES8311_ADC_REG16, 0x24);
- ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG04, 0x10);
- ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG05, 0x00);
- ret |= es8311_write_reg(ES8311_SYSTEM_REG0B, 0x00);
- ret |= es8311_write_reg(ES8311_SYSTEM_REG0C, 0x00);
- ret |= es8311_write_reg(ES8311_SYSTEM_REG10, 0x1F);
- ret |= es8311_write_reg(ES8311_SYSTEM_REG11, 0x7F);
- ret |= es8311_write_reg(ES8311_RESET_REG00, 0x80);
- /* Set Codec into Master or Slave mode */
- regv = es8311_read_reg(ES8311_RESET_REG00);
- /* Set master/slave audio interface */
- audio_hal_codec_i2s_iface_t *i2s_cfg = &(codec_cfg->i2s_iface);
- switch (i2s_cfg->mode) {
- case AUDIO_HAL_MODE_MASTER: /* MASTER MODE */
- ESP_LOGI(TAG, "ES8311 in Master mode");
- regv |= 0x40;
- break;
- case AUDIO_HAL_MODE_SLAVE: /* SLAVE MODE */
- ESP_LOGI(TAG, "ES8311 in Slave mode");
- regv &= 0xBF;
- break;
- default:
- regv &= 0xBF;
- }
- ret |= es8311_write_reg(ES8311_RESET_REG00, regv);
- ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG01, 0x3F);
- /* Select clock source for internal mclk */
- switch (get_es8311_mclk_src()) {
- case FROM_MCLK_PIN:
- regv = es8311_read_reg(ES8311_CLK_MANAGER_REG01);
- regv &= 0x7F;
- ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG01, regv);
- break;
- case FROM_SCLK_PIN:
- regv = es8311_read_reg(ES8311_CLK_MANAGER_REG01);
- regv |= 0x80;
- ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG01, regv);
- break;
- default:
- regv = es8311_read_reg(ES8311_CLK_MANAGER_REG01);
- regv &= 0x7F;
- ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG01, regv);
- break;
- }
+ uint8_t datmp, regv;
  int sample_fre = 0;
  int mclk_fre = 0;
- switch (i2s_cfg->samples) {
+ int coeff;
+
+ switch (sample_rate) {
  case AUDIO_HAL_08K_SAMPLES:
  sample_fre = 8000;
  break;
@@ -391,6 +338,7 @@ esp_err_t es8311_codec_init(audio_hal_codec_config_t *codec_cfg)
  ESP_LOGE(TAG, "Unable to configure sample rate %dHz", sample_fre);
  break;
  }
+
  mclk_fre = sample_fre * MCLK_DIV_FRE;
  coeff = get_coeff(mclk_fre, sample_fre);
  if (coeff < 0) {
@@ -421,7 +369,13 @@ esp_err_t es8311_codec_init(audio_hal_codec_config_t *codec_cfg)
 
  if (get_es8311_mclk_src() == FROM_SCLK_PIN) {
  datmp = 3; /* DIG_MCLK = LRCK * 256 = BCLK * 8 */
+ if (sample_fre == 8000) { 
+ /* When the sample rate is 8kHz, BCLK requires at least 512K (slot bit needs to be configured to 32bit).
+ DIG_MCLK = LRCK * 256 = BCLK * 4 */
+ datmp = 2;
+ }
  }
+
  regv |= (datmp) << 3;
  ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG02, regv);
 
@@ -456,6 +410,70 @@ esp_err_t es8311_codec_init(audio_hal_codec_config_t *codec_cfg)
  ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG06, regv);
  }
 
+ return ESP_OK;
+}
+
+esp_err_t es8311_codec_init(audio_hal_codec_config_t *codec_cfg)
+{
+ uint8_t regv;
+ esp_err_t ret = ESP_OK;
+ i2c_init(); // ESP32 in master mode
+
+ /* Enhance ES8311 I2C noise immunity */
+ ret |= es8311_write_reg(ES8311_GPIO_REG44, 0x08);
+ /* Due to occasional failures during the first I2C write with the ES8311 chip, a second write is performed to ensure reliability */
+ ret |= es8311_write_reg(ES8311_GPIO_REG44, 0x08);
+
+ ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG01, 0x30);
+ ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG02, 0x00);
+ ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG03, 0x10);
+ ret |= es8311_write_reg(ES8311_ADC_REG16, 0x24);
+ ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG04, 0x10);
+ ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG05, 0x00);
+ ret |= es8311_write_reg(ES8311_SYSTEM_REG0B, 0x00);
+ ret |= es8311_write_reg(ES8311_SYSTEM_REG0C, 0x00);
+ ret |= es8311_write_reg(ES8311_SYSTEM_REG10, 0x1F);
+ ret |= es8311_write_reg(ES8311_SYSTEM_REG11, 0x7F);
+ ret |= es8311_write_reg(ES8311_RESET_REG00, 0x80);
+ /* Set Codec into Master or Slave mode */
+ regv = es8311_read_reg(ES8311_RESET_REG00);
+ /* Set master/slave audio interface */
+ audio_hal_codec_i2s_iface_t *i2s_cfg = &(codec_cfg->i2s_iface);
+ switch (i2s_cfg->mode) {
+ case AUDIO_HAL_MODE_MASTER: /* MASTER MODE */
+ ESP_LOGI(TAG, "ES8311 in Master mode");
+ regv |= 0x40;
+ break;
+ case AUDIO_HAL_MODE_SLAVE: /* SLAVE MODE */
+ ESP_LOGI(TAG, "ES8311 in Slave mode");
+ regv &= 0xBF;
+ break;
+ default:
+ regv &= 0xBF;
+ }
+ ret |= es8311_write_reg(ES8311_RESET_REG00, regv);
+ ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG01, 0x3F);
+ /* Select clock source for internal mclk */
+ switch (get_es8311_mclk_src()) {
+ case FROM_MCLK_PIN:
+ regv = es8311_read_reg(ES8311_CLK_MANAGER_REG01);
+ regv &= 0x7F;
+ ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG01, regv);
+ break;
+ case FROM_SCLK_PIN:
+ regv = es8311_read_reg(ES8311_CLK_MANAGER_REG01);
+ regv |= 0x80;
+ ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG01, regv);
+ break;
+ default:
+ regv = es8311_read_reg(ES8311_CLK_MANAGER_REG01);
+ regv &= 0x7F;
+ ret |= es8311_write_reg(ES8311_CLK_MANAGER_REG01, regv);
+ break;
+ }
+
+ es8311_config_sample(i2s_cfg->samples);
+
  /* mclk inverted or not */
  if (INVERT_MCLK) {
  regv = es8311_read_reg(ES8311_CLK_MANAGER_REG01);
@@ -577,7 +595,9 @@ esp_err_t es8311_set_bits_per_sample(audio_hal_iface_bits_t bits)
 esp_err_t es8311_codec_config_i2s(audio_hal_codec_mode_t mode, audio_hal_codec_i2s_iface_t *iface)
 {
  int ret = ESP_OK;
+ ESP_LOGI(TAG, "CFG I2S: mode = %d, bits = %d, fmt = %d, samples = %d", mode, iface->bits, iface->fmt, iface->samples);
  ret |= es8311_set_bits_per_sample(iface->bits);
+ ret |= es8311_config_sample(iface->samples);
  ret |= es8311_config_fmt(iface->fmt);
  return ret;
 }
@@ -750,6 +770,6 @@ void es8311_read_all()
 {
  for (int i = 0; i < 0x4A; i++) {
  uint8_t reg = es8311_read_reg(i);
- ESP_LOGI(TAG, "REG:%02x, %02x", reg, i);
+ ESP_LOGI(TAG, "REG:%02x, %02x", i, reg);
  }
 }

components/esp_codec_dev/CHANGELOG.md

@@ -1,5 +1,11 @@
 # Changelog
 
+## Un-Release
+
+### Bug Fixed
+
+- Fixed the register configuration for es8311 when playing 8kHz audio without using MCLK.
+
 ## v1.4.0
 
 ### Bug Fixed

components/esp_codec_dev/device/es8311/es8311.c

@@ -438,6 +438,11 @@ static int es8311_config_sample(audio_codec_es8311_t *codec, int sample_rate)
  }
  if (codec->cfg.use_mclk == false) {
  datmp = 3;
+ if (sample_rate == 8000) { 
+ /* When the sample rate is 8kHz, BCLK requires at least 512K (slot bit needs to be configured to 32bit).
+ DIG_MCLK = LRCK * 256 = BCLK * 4 */
+ datmp = 2;
+ }
  }
  regv |= (datmp) << 3;
  ret |= es8311_write_reg(codec, ES8311_CLK_MANAGER_REG02, regv);

examples/protocols/components/audio_flash_tone/CMakeLists.txt

@@ -1,6 +1,6 @@
 set(COMPONENT_SRCS "audio_tone_uri.c" "audio_player_int_tone.c")
 set(COMPONENT_ADD_INCLUDEDIRS .)
 
-set(COMPONENT_REQUIRES esp-adf-libs audio_stream)
+set(COMPONENT_REQUIRES esp-adf-libs audio_stream audio_board audio_hal)
 
-register_component()
+register_component()

examples/protocols/components/audio_flash_tone/audio_player_int_tone.c

@@ -32,6 +32,8 @@
 #include "i2s_stream.h"
 #include "algorithm_stream.h"
 #include "audio_player_int_tone.h"
+#include "audio_hal.h"
+#include "board_def.h"
 
 static const char *TAG = "PLAYER_INT_TONE";
 
@@ -51,7 +53,11 @@ static int i2s_write_cb(audio_element_handle_t el, char *buf, int len, TickType_
  size = len / 2;
 #endif
 #if CONFIG_IDF_TARGET_ESP32
- algorithm_mono_fix((uint8_t *)buf, size);
+ audio_element_info_t info;
+ audio_element_getinfo(el, &info);
+ if (info.bits == I2S_DATA_BIT_WIDTH_16BIT) {
+ algorithm_mono_fix((uint8_t *)buf, size);
+ }
 #endif
  int ret = i2s_write_func(el, buf, size, wait_time, ctx);
  if (ret < 0) {
@@ -88,6 +94,9 @@ audio_err_t audio_player_int_tone_init(int sample_rate, int channel_format, int
  i2s_writer_cfg.expand_src_bits = 16;
  i2s_stream_set_channel_type(&i2s_writer_cfg, channel_format);
  i2s_writer = i2s_stream_init(&i2s_writer_cfg);
+ if (ES8311_MCLK_SOURCE == 1 && sample_rate == 8000) {
+ i2s_stream_set_clk(i2s_writer, sample_rate, I2S_DATA_BIT_WIDTH_32BIT, I2S_SLOT_MODE_MONO);
+ }
  esp_audio_output_stream_add(player, i2s_writer);
  audio_element_set_write_cb(i2s_writer, i2s_write_cb, audio_element_get_write_cb(i2s_writer));
  audio_element_set_output_timeout(i2s_writer, portMAX_DELAY);

examples/protocols/components/av_stream/av_stream_hal/av_stream_hal_audio.c

@@ -86,7 +86,15 @@ static esp_err_t i2s_write_drv_init(int port, uint32_t sample_rate, i2s_channel_
 {
  i2s_stream_cfg_t i2s_cfg = I2S_STREAM_CFG_DEFAULT_WITH_PARA(port, sample_rate, I2S_DEFAULT_BITS, AUDIO_STREAM_WRITER);
  i2s_cfg.task_stack = -1;
- i2s_cfg.need_expand = (16 != I2S_DEFAULT_BITS);
+
+ if (ES8311_MCLK_SOURCE == 1 && sample_rate == 8000) { // For ES8311, when MCLK comes from BLCK, 8kHz audio requires 32-bit data width
+ i2s_cfg.need_expand = true;
+ i2s_cfg.std_cfg.slot_cfg.data_bit_width = I2S_DATA_BIT_WIDTH_32BIT;
+ i2s_cfg.std_cfg.slot_cfg.slot_bit_width = I2S_DATA_BIT_WIDTH_32BIT;
+ i2s_cfg.std_cfg.slot_cfg.ws_width = I2S_DATA_BIT_WIDTH_32BIT;
+ } else {
+ i2s_cfg.need_expand = (I2S_DEFAULT_BITS != I2S_DATA_BIT_WIDTH_16BIT);
+ }
  i2s_stream_set_channel_type(&i2s_cfg, channels);
  i2s_io_writer = i2s_stream_init(&i2s_cfg);
  if (i2s_io_writer == NULL) {
@@ -109,6 +117,12 @@ static audio_board_handle_t i2s_device_init(uint32_t sample_rate)
  audio_board_handle_t board_handle = audio_board_init();
  audio_hal_ctrl_codec(board_handle->audio_hal, AUDIO_HAL_CODEC_MODE_BOTH, AUDIO_HAL_CTRL_START);
  audio_hal_set_volume(board_handle->audio_hal, 75);
+ if(sample_rate == 8000) {
+ ESP_LOGW(TAG, "i2s_device_init: sample_rate = %ld", sample_rate);
+ audio_hal_codec_config_t audio_codec_cfg = AUDIO_CODEC_DEFAULT_CONFIG();
+ audio_codec_cfg.i2s_iface.samples = AUDIO_HAL_08K_SAMPLES;
+ audio_hal_codec_iface_config(board_handle->audio_hal, AUDIO_HAL_CODEC_MODE_BOTH, &audio_codec_cfg.i2s_iface);
+ }
  return board_handle;
 }
 
@@ -174,9 +188,12 @@ int av_stream_audio_write(char *buf, int len, TickType_t wait_time, bool uac_en)
  #endif
  } else {
  #if CONFIG_IDF_TARGET_ESP32
- algorithm_mono_fix((uint8_t *)buf, len);
+ audio_element_info_t info;
+ audio_element_getinfo(i2s_io_writer, &info);
+ if (info.bits == I2S_DATA_BIT_WIDTH_16BIT) {
+ algorithm_mono_fix((uint8_t *)buf, len);
+ }
  #endif
-
  int ret = audio_element_output(i2s_io_writer, buf, len);
  if (ret < 0) {
  ESP_LOGE(TAG, "i2s write failed");