****** START compiling Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool (MethodHash=c68acd7b) Generating code for Unix x64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false OPTIONS: optimized using profile data OPTIONS: Jit invoked for ngen IL to import: IL_0000 0f 02 ldarga.s 0x2 IL_0002 28 29 05 00 0a call 0xA000529 IL_0007 17 ldc.i4.1 IL_0008 0a stloc.0 IL_0009 17 ldc.i4.1 IL_000a 59 sub IL_000b 0b stloc.1 IL_000c 16 ldc.i4.0 IL_000d 0c stloc.2 IL_000e 2b 3b br.s 59 (IL_004b) IL_0010 0f 03 ldarga.s 0x3 IL_0012 08 ldloc.2 IL_0013 28 f3 04 00 0a call 0xA0004F3 IL_0018 0d stloc.3 IL_0019 0f 02 ldarga.s 0x2 IL_001b 08 ldloc.2 IL_001c 28 2a 05 00 0a call 0xA00052A IL_0021 13 04 stloc.s 0x4 IL_0023 14 ldnull IL_0024 13 05 stloc.s 0x5 IL_0026 02 ldarg.0 IL_0027 03 ldarg.1 IL_0028 11 04 ldloc.s 0x4 IL_002a 09 ldloc.3 IL_002b 0e 04 ldarg.s 0x4 IL_002d 12 05 ldloca.s 0x5 IL_002f 28 1a 17 00 06 call 0x600171A IL_0034 2d 02 brtrue.s 2 (IL_0038) IL_0036 16 ldc.i4.0 IL_0037 0a stloc.0 IL_0038 11 05 ldloc.s 0x5 IL_003a 11 04 ldloc.s 0x4 IL_003c 0e 05 ldarg.s 0x5 IL_003e 28 1b 17 00 06 call 0x600171B IL_0043 2c 02 brfalse.s 2 (IL_0047) IL_0045 16 ldc.i4.0 IL_0046 0a stloc.0 IL_0047 08 ldloc.2 IL_0048 17 ldc.i4.1 IL_0049 58 add IL_004a 0c stloc.2 IL_004b 08 ldloc.2 IL_004c 07 ldloc.1 IL_004d 31 c1 ble.s -63 (IL_0010) IL_004f 06 ldloc.0 IL_0050 2a ret lvaSetClass: setting class for V00 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.VisualBasic.Symbol Arg #0 passed in register(s) rdi lvaSetClass: setting class for V01 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution Arg #1 passed in register(s) rsi **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 1 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 1 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 Arg #2 passed in register(s) firstEightByte: rdx, secondEightByte: **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 1 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 1 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 Arg #3 passed in register(s) firstEightByte: rcx, secondEightByte: lvaSetClass: setting class for V04 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo] Arg #4 passed in register(s) r8 Arg #5 passed in register(s) r9 lvaSetClass: setting class for V09 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol lvaSetClass: setting class for V10 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol lvaSetClass: setting class for V11 to (00000000D1FFAB1E) System.Collections.Generic.HashSet`1[[Microsoft.CodeAnalysis.DiagnosticInfo, Microsoft.CodeAnalysis, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]] lvaGrabTemp returning 12 (V12 tmp0) (a long lifetime temp) called for OutgoingArgSpace. ; Initial local variable assignments ; ; V00 arg0 ref class-hnd ; V01 arg1 ref class-hnd ; V02 arg2 struct ; V03 arg3 struct ; V04 arg4 ref class-hnd ; V05 arg5 byref ; V06 loc0 bool ; V07 loc1 int ; V08 loc2 int ; V09 loc3 ref class-hnd ; V10 loc4 ref class-hnd ; V11 loc5 ref class-hnd ; V12 OutArgs lclBlk "OutgoingArgSpace" *************** In compInitDebuggingInfo() for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 12 VarNum LVNum Name Beg End 0: 00h 00h V00 arg0 000h 051h 1: 01h 01h V01 arg1 000h 051h 2: 02h 02h V02 arg2 000h 051h 3: 03h 03h V03 arg3 000h 051h 4: 04h 04h V04 arg4 000h 051h 5: 05h 05h V05 arg5 000h 051h 6: 06h 06h V06 loc0 000h 051h 7: 07h 07h V07 loc1 000h 051h 8: 08h 08h V08 loc2 000h 051h 9: 09h 09h V09 loc3 000h 051h 10: 0Ah 0Ah V10 loc4 000h 051h 11: 0Bh 0Bh V11 loc5 000h 051h info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool weight= 77 : state 16 [ ldarga.s ] weight= 79 : state 40 [ call ] weight= 28 : state 24 [ ldc.i4.1 ] weight= 6 : state 11 [ stloc.0 ] weight= 28 : state 24 [ ldc.i4.1 ] weight=-15 : state 77 [ sub ] weight= 34 : state 12 [ stloc.1 ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 4 : state 13 [ stloc.2 ] weight= 44 : state 43 [ br.s ] weight= 77 : state 16 [ ldarga.s ] weight= 22 : state 9 [ ldloc.2 ] weight= 79 : state 40 [ call ] weight= 49 : state 14 [ stloc.3 ] weight= 77 : state 16 [ ldarga.s ] weight= 22 : state 9 [ ldloc.2 ] weight= 79 : state 40 [ call ] weight=-45 : state 20 [ stloc.s ] weight= 7 : state 21 [ ldnull ] weight=-45 : state 20 [ stloc.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 32 : state 18 [ ldloc.s ] weight= 24 : state 10 [ ldloc.3 ] weight= 32 : state 15 [ ldarg.s ] weight= 61 : state 19 [ ldloca.s ] weight= 79 : state 40 [ call ] weight= 25 : state 45 [ brtrue.s ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 6 : state 11 [ stloc.0 ] weight= 32 : state 18 [ ldloc.s ] weight= 32 : state 18 [ ldloc.s ] weight= 32 : state 15 [ ldarg.s ] weight= 79 : state 40 [ call ] weight= 27 : state 44 [ brfalse.s ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 6 : state 11 [ stloc.0 ] weight= 22 : state 9 [ ldloc.2 ] weight= 28 : state 24 [ ldc.i4.1 ] weight=-12 : state 76 [ add ] weight=-10 : state 201 [ stloc.2 -> ldloc.2 ] weight= 9 : state 8 [ ldloc.1 ] weight= 53 : state 49 [ ble.s ] weight= 12 : state 7 [ ldloc.0 ] weight= 19 : state 42 [ ret ] Marked V07 as a single def local Marked V09 as a single def local Marked V10 as a single def local Jump targets: IL_0010 IL_0038 IL_0047 IL_004b New Basic Block BB01 [0000] created. BB01 [000..010) New Basic Block BB02 [0001] created. BB02 [010..036) New Basic Block BB03 [0002] created. BB03 [036..038) New Basic Block BB04 [0003] created. BB04 [038..045) New Basic Block BB05 [0004] created. BB05 [045..047) New Basic Block BB06 [0005] created. BB06 [047..04B) New Basic Block BB07 [0006] created. BB07 [04B..04F) New Basic Block BB08 [0007] created. BB08 [04F..051) Inline candidate has an arg that feeds a constant test. Multiplier increased to 1. Prejit root candidate has arg that feeds a conditional. Multiplier increased to 4. Inline candidate callsite is hot. Multiplier increased to 7. calleeNativeSizeEstimate=1266 callsiteNativeSizeEstimate=235 benefit multiplier=7 threshold=1645 Native estimate for function size is within threshold for inlining 126.6 <= 164.5 (multiplier = 7) IL Code Size,Instr 81, 46, Basic Block count 8, Local Variable Num,Ref count 13, 27 for method Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool OPTIONS: opts.MinOpts() == false Basic block list for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 19862. 19862 [000..010)-> BB07 (always) IBC BB02 [0001] 1 20988. 20988 [010..036)-> BB04 ( cond ) bwd bwd-target IBC BB03 [0002] 1 501 501 [036..038) bwd IBC BB04 [0003] 2 20988. 20988 [038..045)-> BB06 ( cond ) bwd IBC BB05 [0004] 1 0 0 [045..047) rare bwd IBC BB06 [0005] 2 20988. 20988 [047..04B) bwd IBC BB07 [0006] 2 40850. 40850 [04B..04F)-> BB02 ( cond ) bwd IBC BB08 [0007] 1 19862. 19862 [04F..051) (return) IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import *************** Starting PHASE Importation *************** In impImport() for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool impImportBlockPending for BB01 Importing BB01 (PC=000) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 0 (0x000) ldarga.s 2 [ 1] 2 (0x002) call 0A000529 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 STMT00000 (IL 0x000... ???) [000002] I-C-G------- * CALL r2r_ind int System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].get_Length (exactContextHnd=0x00000000D1FFAB1E) [000001] ------------ this in rdi +--* ADDR byref [000000] -------N---- | \--* LCL_VAR struct V02 arg2 [000004] n----------- arg1 \--* IND long [000003] ------------ \--* CNS_INT(h) long 0xd1ffab1e class [ 1] 7 (0x007) ldc.i4.1 1 [ 2] 8 (0x008) stloc.0 STMT00001 (IL ???... ???) [000008] -A---------- * ASG int [000007] D------N---- +--* LCL_VAR int V06 loc0 [000006] ------------ \--* CNS_INT int 1 [ 1] 9 (0x009) ldc.i4.1 1 [ 2] 10 (0x00a) sub [ 1] 11 (0x00b) stloc.1 STMT00002 (IL ???... ???) [000012] -AC--------- * ASG int [000011] D------N---- +--* LCL_VAR int V07 loc1 [000010] --C--------- \--* SUB int [000005] --C--------- +--* RET_EXPR int (inl return from call [000002]) [000009] ------------ \--* CNS_INT int 1 [ 0] 12 (0x00c) ldc.i4.0 0 [ 1] 13 (0x00d) stloc.2 STMT00003 (IL 0x00C... ???) [000015] -A---------- * ASG int [000014] D------N---- +--* LCL_VAR int V08 loc2 [000013] ------------ \--* CNS_INT int 0 [ 0] 14 (0x00e) br.s impImportBlockPending for BB07 Importing BB07 (PC=075) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 75 (0x04b) ldloc.2 [ 1] 76 (0x04c) ldloc.1 [ 2] 77 (0x04d) ble.s STMT00004 (IL 0x04B... ???) [000019] ------------ * JTRUE void [000018] ------------ \--* LE int [000016] ------------ +--* LCL_VAR int V08 loc2 [000017] ------------ \--* LCL_VAR int V07 loc1 impImportBlockPending for BB08 impImportBlockPending for BB02 Importing BB02 (PC=016) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 16 (0x010) ldarga.s 3 [ 1] 18 (0x012) ldloc.2 [ 2] 19 (0x013) call 0A0004F3 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 STMT00005 (IL 0x010... ???) [000023] I-C-G------- * CALL r2r_ind ref System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].get_Item (exactContextHnd=0x00000000D1FFAB1E) [000021] ------------ this in rdi +--* ADDR byref [000020] -------N---- | \--* LCL_VAR struct V03 arg3 [000025] n----------- arg1 +--* IND long [000024] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000022] ------------ arg2 \--* LCL_VAR int V08 loc2 [ 1] 24 (0x018) stloc.3 STMT00006 (IL ???... ???) [000028] -AC--------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V09 loc3 [000026] --C--------- \--* RET_EXPR ref (inl return from call [000023]) [ 0] 25 (0x019) ldarga.s 2 [ 1] 27 (0x01b) ldloc.2 [ 2] 28 (0x01c) call 0A00052A In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 STMT00007 (IL 0x019... ???) [000032] I-C-G------- * CALL r2r_ind ref System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].get_Item (exactContextHnd=0x00000000D1FFAB1E) [000030] ------------ this in rdi +--* ADDR byref [000029] -------N---- | \--* LCL_VAR struct V02 arg2 [000034] n----------- arg1 +--* IND long [000033] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000031] ------------ arg2 \--* LCL_VAR int V08 loc2 [ 1] 33 (0x021) stloc.s 4 STMT00008 (IL ???... ???) [000037] -AC--------- * ASG ref [000036] D------N---- +--* LCL_VAR ref V10 loc4 [000035] --C--------- \--* RET_EXPR ref (inl return from call [000032]) [ 0] 35 (0x023) ldnull [ 1] 36 (0x024) stloc.s 5 STMT00009 (IL 0x023... ???) [000040] -A---------- * ASG ref [000039] D------N---- +--* LCL_VAR ref V11 loc5 [000038] ------------ \--* CNS_INT ref null [ 0] 38 (0x026) ldarg.0 [ 1] 39 (0x027) ldarg.1 [ 2] 40 (0x028) ldloc.s 4 [ 3] 42 (0x02a) ldloc.3 [ 4] 43 (0x02b) ldarg.s 4 [ 5] 45 (0x02d) ldloca.s 5 [ 6] 47 (0x02f) call 0600171A In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' INLINER: Marking Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 52 (0x034) brtrue.s STMT00010 (IL 0x026... ???) [000052] --C-G------- * JTRUE void [000051] --C-G------- \--* NE int [000049] --C-G------- +--* CAST int <- bool <- int [000048] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000041] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000042] ------------ arg1 | +--* LCL_VAR ref V01 arg1 [000043] ------------ arg2 | +--* LCL_VAR ref V10 loc4 [000044] ------------ arg3 | +--* LCL_VAR ref V09 loc3 [000045] ------------ arg4 | +--* LCL_VAR ref V04 arg4 [000047] ------------ arg5 | \--* ADDR byref [000046] -------N---- | \--* LCL_VAR ref V11 loc5 [000050] ------------ \--* CNS_INT int 0 impImportBlockPending for BB03 impImportBlockPending for BB04 Importing BB04 (PC=056) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 56 (0x038) ldloc.s 5 [ 1] 58 (0x03a) ldloc.s 4 [ 2] 60 (0x03c) ldarg.s 5 [ 3] 62 (0x03e) call 0600171B In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'has exception handling' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:AppendUseSiteDiagnostics(System.Collections.Generic.HashSet`1[[Microsoft.CodeAnalysis.DiagnosticInfo, Microsoft.CodeAnalysis, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,byref):bool' INLINER: Marking Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:AppendUseSiteDiagnostics(System.Collections.Generic.HashSet`1[[Microsoft.CodeAnalysis.DiagnosticInfo, Microsoft.CodeAnalysis, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,byref):bool as NOINLINE because of has exception handling INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'has exception handling' [ 1] 67 (0x043) brfalse.s STMT00011 (IL 0x038... ???) [000060] --C-G------- * JTRUE void [000059] --C-G------- \--* EQ int [000057] --C-G------- +--* CAST int <- bool <- int [000056] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ------------ arg0 | +--* LCL_VAR ref V11 loc5 [000054] ------------ arg1 | +--* LCL_VAR ref V10 loc4 [000055] ------------ arg2 | \--* LCL_VAR byref V05 arg5 [000058] ------------ \--* CNS_INT int 0 impImportBlockPending for BB05 impImportBlockPending for BB06 Importing BB06 (PC=071) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 71 (0x047) ldloc.2 [ 1] 72 (0x048) ldc.i4.1 1 [ 2] 73 (0x049) add [ 1] 74 (0x04a) stloc.2 STMT00012 (IL 0x047... ???) [000065] -A---------- * ASG int [000064] D------N---- +--* LCL_VAR int V08 loc2 [000063] ------------ \--* ADD int [000061] ------------ +--* LCL_VAR int V08 loc2 [000062] ------------ \--* CNS_INT int 1 impImportBlockPending for BB07 Importing BB05 (PC=069) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 69 (0x045) ldc.i4.0 0 [ 1] 70 (0x046) stloc.0 STMT00013 (IL 0x045... ???) [000068] -A---------- * ASG int [000067] D------N---- +--* LCL_VAR int V06 loc0 [000066] ------------ \--* CNS_INT int 0 impImportBlockPending for BB06 Importing BB03 (PC=054) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 54 (0x036) ldc.i4.0 0 [ 1] 55 (0x037) stloc.0 STMT00014 (IL 0x036... ???) [000071] -A---------- * ASG int [000070] D------N---- +--* LCL_VAR int V06 loc0 [000069] ------------ \--* CNS_INT int 0 impImportBlockPending for BB04 Importing BB08 (PC=079) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 79 (0x04f) ldloc.0 [ 1] 80 (0x050) ret STMT00015 (IL 0x04F... ???) [000073] ------------ * RETURN int [000072] ------------ \--* LCL_VAR int V06 loc0 *************** Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 19862. 19862 [000..010)-> BB07 (always) i IBC BB02 [0001] 1 20988. 20988 [010..036)-> BB04 ( cond ) i bwd bwd-target IBC BB03 [0002] 1 501 501 [036..038) i bwd IBC BB04 [0003] 2 20988. 20988 [038..045)-> BB06 ( cond ) i bwd IBC BB05 [0004] 1 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 20988. 20988 [047..04B) i bwd IBC BB07 [0006] 2 40850. 40850 [04B..04F)-> BB02 ( cond ) i bwd IBC BB08 [0007] 1 19862. 19862 [04F..051) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB07 (always), preds={} succs={BB07} ***** BB01 STMT00000 (IL 0x000...0x008) [000002] I-C-G------- * CALL r2r_ind int System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].get_Length (exactContextHnd=0x00000000D1FFAB1E) [000001] ------------ this in rdi +--* ADDR byref [000000] -------N---- | \--* LCL_VAR struct V02 arg2 [000004] n----------- arg1 \--* IND long [000003] ------------ \--* CNS_INT(h) long 0xd1ffab1e class ***** BB01 STMT00001 (IL ???... ???) [000008] -A---------- * ASG int [000007] D------N---- +--* LCL_VAR int V06 loc0 [000006] ------------ \--* CNS_INT int 1 ***** BB01 STMT00002 (IL ???...0x00B) [000012] -AC--------- * ASG int [000011] D------N---- +--* LCL_VAR int V07 loc1 [000010] --C--------- \--* SUB int [000005] --C--------- +--* RET_EXPR int (inl return from call [000002]) [000009] ------------ \--* CNS_INT int 1 ***** BB01 STMT00003 (IL 0x00C...0x00D) [000015] -A---------- * ASG int [000014] D------N---- +--* LCL_VAR int V08 loc2 [000013] ------------ \--* CNS_INT int 0 ------------ BB02 [010..036) -> BB04 (cond), preds={} succs={BB03,BB04} ***** BB02 STMT00005 (IL 0x010...0x018) [000023] I-C-G------- * CALL r2r_ind ref System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].get_Item (exactContextHnd=0x00000000D1FFAB1E) [000021] ------------ this in rdi +--* ADDR byref [000020] -------N---- | \--* LCL_VAR struct V03 arg3 [000025] n----------- arg1 +--* IND long [000024] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000022] ------------ arg2 \--* LCL_VAR int V08 loc2 ***** BB02 STMT00006 (IL ???... ???) [000028] -AC--------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V09 loc3 [000026] --C--------- \--* RET_EXPR ref (inl return from call [000023]) ***** BB02 STMT00007 (IL 0x019...0x021) [000032] I-C-G------- * CALL r2r_ind ref System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].get_Item (exactContextHnd=0x00000000D1FFAB1E) [000030] ------------ this in rdi +--* ADDR byref [000029] -------N---- | \--* LCL_VAR struct V02 arg2 [000034] n----------- arg1 +--* IND long [000033] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000031] ------------ arg2 \--* LCL_VAR int V08 loc2 ***** BB02 STMT00008 (IL ???... ???) [000037] -AC--------- * ASG ref [000036] D------N---- +--* LCL_VAR ref V10 loc4 [000035] --C--------- \--* RET_EXPR ref (inl return from call [000032]) ***** BB02 STMT00009 (IL 0x023...0x024) [000040] -A---------- * ASG ref [000039] D------N---- +--* LCL_VAR ref V11 loc5 [000038] ------------ \--* CNS_INT ref null ***** BB02 STMT00010 (IL 0x026...0x034) [000052] --C-G------- * JTRUE void [000051] --C-G------- \--* NE int [000049] --C-G------- +--* CAST int <- bool <- int [000048] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000041] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000042] ------------ arg1 | +--* LCL_VAR ref V01 arg1 [000043] ------------ arg2 | +--* LCL_VAR ref V10 loc4 [000044] ------------ arg3 | +--* LCL_VAR ref V09 loc3 [000045] ------------ arg4 | +--* LCL_VAR ref V04 arg4 [000047] ------------ arg5 | \--* ADDR byref [000046] -------N---- | \--* LCL_VAR ref V11 loc5 [000050] ------------ \--* CNS_INT int 0 ------------ BB03 [036..038), preds={} succs={BB04} ***** BB03 STMT00014 (IL 0x036...0x037) [000071] -A---------- * ASG int [000070] D------N---- +--* LCL_VAR int V06 loc0 [000069] ------------ \--* CNS_INT int 0 ------------ BB04 [038..045) -> BB06 (cond), preds={} succs={BB05,BB06} ***** BB04 STMT00011 (IL 0x038...0x043) [000060] --C-G------- * JTRUE void [000059] --C-G------- \--* EQ int [000057] --C-G------- +--* CAST int <- bool <- int [000056] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ------------ arg0 | +--* LCL_VAR ref V11 loc5 [000054] ------------ arg1 | +--* LCL_VAR ref V10 loc4 [000055] ------------ arg2 | \--* LCL_VAR byref V05 arg5 [000058] ------------ \--* CNS_INT int 0 ------------ BB05 [045..047), preds={} succs={BB06} ***** BB05 STMT00013 (IL 0x045...0x046) [000068] -A---------- * ASG int [000067] D------N---- +--* LCL_VAR int V06 loc0 [000066] ------------ \--* CNS_INT int 0 ------------ BB06 [047..04B), preds={} succs={BB07} ***** BB06 STMT00012 (IL 0x047...0x04A) [000065] -A---------- * ASG int [000064] D------N---- +--* LCL_VAR int V08 loc2 [000063] ------------ \--* ADD int [000061] ------------ +--* LCL_VAR int V08 loc2 [000062] ------------ \--* CNS_INT int 1 ------------ BB07 [04B..04F) -> BB02 (cond), preds={} succs={BB08,BB02} ***** BB07 STMT00004 (IL 0x04B...0x04D) [000019] ------------ * JTRUE void [000018] ------------ \--* LE int [000016] ------------ +--* LCL_VAR int V08 loc2 [000017] ------------ \--* LCL_VAR int V07 loc1 ------------ BB08 [04F..051) (return), preds={} succs={} ***** BB08 STMT00015 (IL 0x04F...0x050) [000073] ------------ * RETURN int [000072] ------------ \--* LCL_VAR int V06 loc0 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 9, bitset array size: 1 (short) *************** In fgRemoveEmptyBlocks *************** Finishing PHASE Morph - Init *************** In fgDebugCheckBBlist *************** Starting PHASE Morph - Inlining Expanding INLINE_CANDIDATE in statement STMT00000 in BB01: STMT00000 (IL 0x000...0x008) [000002] I-C-G------- * CALL r2r_ind int System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].get_Length (exactContextHnd=0x00000000D1FFAB1E) [000001] ------------ this in rdi +--* ADDR byref [000000] -------N---- | \--* LCL_VAR struct V02 arg2 [000004] n----------- arg1 \--* IND long [000003] ------------ \--* CNS_INT(h) long 0xd1ffab1e class thisArg: is a constant is byref to a struct local [000001] ------------ * ADDR byref [000000] -------N---- \--* LCL_VAR struct V02 arg2 INLINER: inlineInfo.tokenLookupContextHandle for System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Length():int:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 4b 00 00 0a ldfld 0xA00004B IL_0006 8e ldlen IL_0007 69 conv.i4 IL_0008 2a ret INLINER impTokenLookupContextHandle for System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Length():int:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Length():int:this Jump targets: none New Basic Block BB09 [0008] created. BB09 [000..009) Basic block list for 'System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Length():int:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB09 [0008] 1 1 [000..009) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000002] Starting PHASE Pre-import *************** Inline @[000002] Finishing PHASE Pre-import *************** Inline @[000002] Starting PHASE Importation *************** In impImport() for System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Length():int:this impImportBlockPending for BB09 Importing BB09 (PC=000) of 'System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A00004B [ 1] 6 (0x006) ldlen [ 1] 7 (0x007) conv.i4 [ 1] 8 (0x008) ret Inlinee Return expression (before normalization) => [000077] ---XG------- * ARR_LENGTH int [000076] ----G------- \--* FIELD ref array [000074] ------------ \--* ADDR byref [000075] -------N---- \--* LCL_VAR struct V02 arg2 Inlinee Return expression (after normalization) => [000077] ---XG------- * ARR_LENGTH int [000076] ----G------- \--* FIELD ref array [000074] ------------ \--* ADDR byref [000075] -------N---- \--* LCL_VAR struct V02 arg2 ** Note: inlinee IL was partially imported -- imported 0 of 9 bytes of method IL *************** Inline @[000002] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB09 [0008] 1 1 [000..009) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB09 [000..009) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000002] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000002] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000002] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000002] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000002] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000002] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000002] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. INLINER: Updating optMethodFlags -- root:0 callee:4 new:4 Return expression for call at [000002] is [000077] ---XG------- * ARR_LENGTH int [000076] ----G------- \--* FIELD ref array [000074] ------------ \--* ADDR byref [000075] -------N---- \--* LCL_VAR struct V02 arg2 Successfully inlined System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Length():int:this (9 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000005] with [000077] [000005] --C--------- * RET_EXPR int (inl return from call [000077]) Inserting the inline return expression [000077] ---XG------- * ARR_LENGTH int [000076] ----G------- \--* FIELD ref array [000074] ------------ \--* ADDR byref [000075] -------N---- \--* LCL_VAR struct V02 arg2 Expanding INLINE_CANDIDATE in statement STMT00005 in BB02: STMT00005 (IL 0x010...0x018) [000023] I-C-G------- * CALL r2r_ind ref System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].get_Item (exactContextHnd=0x00000000D1FFAB1E) [000021] ------------ this in rdi +--* ADDR byref [000020] -------N---- | \--* LCL_VAR struct V03 arg3 [000025] n----------- arg1 +--* IND long [000024] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000022] ------------ arg2 \--* LCL_VAR int V08 loc2 thisArg: is a constant is byref to a struct local [000021] ------------ * ADDR byref [000020] -------N---- \--* LCL_VAR struct V03 arg3 Argument #1: is a local var [000022] ------------ * LCL_VAR int V08 loc2 INLINER: inlineInfo.tokenLookupContextHandle for System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 4b 00 00 0a ldfld 0xA00004B IL_0006 03 ldarg.1 IL_0007 a3 1d 00 00 1b ldelem 0x1B00001D IL_000c 2a ret INLINER impTokenLookupContextHandle for System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this Jump targets: none New Basic Block BB10 [0009] created. BB10 [000..00D) Basic block list for 'System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB10 [0009] 1 1 [000..00D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000023] Starting PHASE Pre-import *************** Inline @[000023] Finishing PHASE Pre-import *************** Inline @[000023] Starting PHASE Importation *************** In impImport() for System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this impImportBlockPending for BB10 Importing BB10 (PC=000) of 'System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A00004B [ 1] 6 (0x006) ldarg.1 [ 2] 7 (0x007) ldelem 1B00001D [ 1] 12 (0x00c) ret Inlinee Return expression (before normalization) => [000082] ---XG------- * INDEX ref [000081] ----G------- +--* FIELD ref array [000079] ------------ | \--* ADDR byref [000080] -------N---- | \--* LCL_VAR struct V03 arg3 [000022] ------------ \--* LCL_VAR int V08 loc2 Inlinee Return expression (after normalization) => [000082] ---XG------- * INDEX ref [000081] ----G------- +--* FIELD ref array [000079] ------------ | \--* ADDR byref [000080] -------N---- | \--* LCL_VAR struct V03 arg3 [000022] ------------ \--* LCL_VAR int V08 loc2 ** Note: inlinee IL was partially imported -- imported 0 of 13 bytes of method IL *************** Inline @[000023] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB10 [0009] 1 1 [000..00D) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB10 [000..00D) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000023] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000023] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000023] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000023] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000023] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000023] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000023] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000023] is [000082] ---XG------- * INDEX ref [000081] ----G------- +--* FIELD ref array [000079] ------------ | \--* ADDR byref [000080] -------N---- | \--* LCL_VAR struct V03 arg3 [000022] ------------ \--* LCL_VAR int V08 loc2 Successfully inlined System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this (13 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000026] with [000082] [000026] --C--------- * RET_EXPR ref (inl return from call [000082]) Inserting the inline return expression [000082] ---XG------- * INDEX ref [000081] ----G------- +--* FIELD ref array [000079] ------------ | \--* ADDR byref [000080] -------N---- | \--* LCL_VAR struct V03 arg3 [000022] ------------ \--* LCL_VAR int V08 loc2 Querying runtime about current class of field System.Collections.Immutable.ImmutableArray`1[System.__Canon].array (declared as System.__Canon[]) Field's current class not available lvaUpdateClass: NOT Updating class for V09 from (00000000D1FFAB1E) Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol to (00000000D1FFAB1E) System.__Canon Expanding INLINE_CANDIDATE in statement STMT00007 in BB02: STMT00007 (IL 0x019...0x021) [000032] I-C-G------- * CALL r2r_ind ref System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].get_Item (exactContextHnd=0x00000000D1FFAB1E) [000030] ------------ this in rdi +--* ADDR byref [000029] -------N---- | \--* LCL_VAR struct V02 arg2 [000034] n----------- arg1 +--* IND long [000033] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000031] ------------ arg2 \--* LCL_VAR int V08 loc2 thisArg: is a constant is byref to a struct local [000030] ------------ * ADDR byref [000029] -------N---- \--* LCL_VAR struct V02 arg2 Argument #1: is a local var [000031] ------------ * LCL_VAR int V08 loc2 INLINER: inlineInfo.tokenLookupContextHandle for System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 4b 00 00 0a ldfld 0xA00004B IL_0006 03 ldarg.1 IL_0007 a3 1d 00 00 1b ldelem 0x1B00001D IL_000c 2a ret INLINER impTokenLookupContextHandle for System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this Jump targets: none New Basic Block BB11 [0010] created. BB11 [000..00D) Basic block list for 'System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB11 [0010] 1 1 [000..00D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000032] Starting PHASE Pre-import *************** Inline @[000032] Finishing PHASE Pre-import *************** Inline @[000032] Starting PHASE Importation *************** In impImport() for System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this impImportBlockPending for BB11 Importing BB11 (PC=000) of 'System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A00004B [ 1] 6 (0x006) ldarg.1 [ 2] 7 (0x007) ldelem 1B00001D [ 1] 12 (0x00c) ret Inlinee Return expression (before normalization) => [000087] ---XG------- * INDEX ref [000086] ----G------- +--* FIELD ref array [000084] ------------ | \--* ADDR byref [000085] -------N---- | \--* LCL_VAR struct V02 arg2 [000031] ------------ \--* LCL_VAR int V08 loc2 Inlinee Return expression (after normalization) => [000087] ---XG------- * INDEX ref [000086] ----G------- +--* FIELD ref array [000084] ------------ | \--* ADDR byref [000085] -------N---- | \--* LCL_VAR struct V02 arg2 [000031] ------------ \--* LCL_VAR int V08 loc2 ** Note: inlinee IL was partially imported -- imported 0 of 13 bytes of method IL *************** Inline @[000032] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB11 [0010] 1 1 [000..00D) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB11 [000..00D) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000032] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000032] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000032] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000032] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000032] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000032] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000032] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000032] is [000087] ---XG------- * INDEX ref [000086] ----G------- +--* FIELD ref array [000084] ------------ | \--* ADDR byref [000085] -------N---- | \--* LCL_VAR struct V02 arg2 [000031] ------------ \--* LCL_VAR int V08 loc2 Successfully inlined System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this (13 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000035] with [000087] [000035] --C--------- * RET_EXPR ref (inl return from call [000087]) Inserting the inline return expression [000087] ---XG------- * INDEX ref [000086] ----G------- +--* FIELD ref array [000084] ------------ | \--* ADDR byref [000085] -------N---- | \--* LCL_VAR struct V02 arg2 [000031] ------------ \--* LCL_VAR int V08 loc2 Querying runtime about current class of field System.Collections.Immutable.ImmutableArray`1[System.__Canon].array (declared as System.__Canon[]) Field's current class not available lvaUpdateClass: NOT Updating class for V10 from (00000000D1FFAB1E) Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol to (00000000D1FFAB1E) System.__Canon **************** Inline Tree Inlines into 06001719 Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool [1 IL=0002 TR=000002 060001B1] [below ALWAYS_INLINE size] System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Length():int:this [2 IL=0019 TR=000023 060001AE] [below ALWAYS_INLINE size] System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this [3 IL=0028 TR=000032 060001AE] [below ALWAYS_INLINE size] System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this [0 IL=0047 TR=000048 0600171A] [FAILED: too many il bytes] Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool [0 IL=0062 TR=000056 0600171B] [FAILED: has exception handling] Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:AppendUseSiteDiagnostics(System.Collections.Generic.HashSet`1[[Microsoft.CodeAnalysis.DiagnosticInfo, Microsoft.CodeAnalysis, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,byref):bool Budget: initialTime=303, finalTime=261, initialBudget=3030, currentBudget=3030 Budget: initialSize=1978, finalSize=1978 *************** Finishing PHASE Morph - Inlining Trees after Morph - Inlining ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 19862. 19862 [000..010)-> BB07 (always) i idxlen IBC BB02 [0001] 1 20988. 20988 [010..036)-> BB04 ( cond ) i bwd bwd-target IBC BB03 [0002] 1 501 501 [036..038) i bwd IBC BB04 [0003] 2 20988. 20988 [038..045)-> BB06 ( cond ) i bwd IBC BB05 [0004] 1 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 20988. 20988 [047..04B) i bwd IBC BB07 [0006] 2 40850. 40850 [04B..04F)-> BB02 ( cond ) i bwd IBC BB08 [0007] 1 19862. 19862 [04F..051) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB07 (always), preds={} succs={BB07} ***** BB01 STMT00001 (IL ???... ???) [000008] -A---------- * ASG int [000007] D------N---- +--* LCL_VAR int V06 loc0 [000006] ------------ \--* CNS_INT int 1 ***** BB01 STMT00002 (IL ???...0x00B) [000012] -AC--------- * ASG int [000011] D------N---- +--* LCL_VAR int V07 loc1 [000010] --C--------- \--* SUB int [000077] ---XG------- +--* ARR_LENGTH int [000076] ----G------- | \--* FIELD ref array [000074] ------------ | \--* ADDR byref [000075] -------N---- | \--* LCL_VAR struct V02 arg2 [000009] ------------ \--* CNS_INT int 1 ***** BB01 STMT00003 (IL 0x00C...0x00D) [000015] -A---------- * ASG int [000014] D------N---- +--* LCL_VAR int V08 loc2 [000013] ------------ \--* CNS_INT int 0 ------------ BB02 [010..036) -> BB04 (cond), preds={} succs={BB03,BB04} ***** BB02 STMT00006 (IL ???... ???) [000028] -AC--------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V09 loc3 [000082] ---XG------- \--* INDEX ref [000081] ----G------- +--* FIELD ref array [000079] ------------ | \--* ADDR byref [000080] -------N---- | \--* LCL_VAR struct V03 arg3 [000022] ------------ \--* LCL_VAR int V08 loc2 ***** BB02 STMT00008 (IL ???... ???) [000037] -AC--------- * ASG ref [000036] D------N---- +--* LCL_VAR ref V10 loc4 [000087] ---XG------- \--* INDEX ref [000086] ----G------- +--* FIELD ref array [000084] ------------ | \--* ADDR byref [000085] -------N---- | \--* LCL_VAR struct V02 arg2 [000031] ------------ \--* LCL_VAR int V08 loc2 ***** BB02 STMT00009 (IL 0x023...0x024) [000040] -A---------- * ASG ref [000039] D------N---- +--* LCL_VAR ref V11 loc5 [000038] ------------ \--* CNS_INT ref null ***** BB02 STMT00010 (IL 0x026...0x034) [000052] --C-G------- * JTRUE void [000051] --C-G------- \--* NE int [000049] --C-G------- +--* CAST int <- bool <- int [000048] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000041] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000042] ------------ arg1 | +--* LCL_VAR ref V01 arg1 [000043] ------------ arg2 | +--* LCL_VAR ref V10 loc4 [000044] ------------ arg3 | +--* LCL_VAR ref V09 loc3 [000045] ------------ arg4 | +--* LCL_VAR ref V04 arg4 [000047] ------------ arg5 | \--* ADDR byref [000046] -------N---- | \--* LCL_VAR ref V11 loc5 [000050] ------------ \--* CNS_INT int 0 ------------ BB03 [036..038), preds={} succs={BB04} ***** BB03 STMT00014 (IL 0x036...0x037) [000071] -A---------- * ASG int [000070] D------N---- +--* LCL_VAR int V06 loc0 [000069] ------------ \--* CNS_INT int 0 ------------ BB04 [038..045) -> BB06 (cond), preds={} succs={BB05,BB06} ***** BB04 STMT00011 (IL 0x038...0x043) [000060] --C-G------- * JTRUE void [000059] --C-G------- \--* EQ int [000057] --C-G------- +--* CAST int <- bool <- int [000056] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ------------ arg0 | +--* LCL_VAR ref V11 loc5 [000054] ------------ arg1 | +--* LCL_VAR ref V10 loc4 [000055] ------------ arg2 | \--* LCL_VAR byref V05 arg5 [000058] ------------ \--* CNS_INT int 0 ------------ BB05 [045..047), preds={} succs={BB06} ***** BB05 STMT00013 (IL 0x045...0x046) [000068] -A---------- * ASG int [000067] D------N---- +--* LCL_VAR int V06 loc0 [000066] ------------ \--* CNS_INT int 0 ------------ BB06 [047..04B), preds={} succs={BB07} ***** BB06 STMT00012 (IL 0x047...0x04A) [000065] -A---------- * ASG int [000064] D------N---- +--* LCL_VAR int V08 loc2 [000063] ------------ \--* ADD int [000061] ------------ +--* LCL_VAR int V08 loc2 [000062] ------------ \--* CNS_INT int 1 ------------ BB07 [04B..04F) -> BB02 (cond), preds={} succs={BB08,BB02} ***** BB07 STMT00004 (IL 0x04B...0x04D) [000019] ------------ * JTRUE void [000018] ------------ \--* LE int [000016] ------------ +--* LCL_VAR int V08 loc2 [000017] ------------ \--* LCL_VAR int V07 loc1 ------------ BB08 [04F..051) (return), preds={} succs={} ***** BB08 STMT00015 (IL 0x04F...0x050) [000073] ------------ * RETURN int [000072] ------------ \--* LCL_VAR int V06 loc0 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Allocate Objects no newobjs in this method; punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 19862. 19862 [000..010)-> BB07 (always) i idxlen IBC BB02 [0001] 1 20988. 20988 [010..036)-> BB04 ( cond ) i bwd bwd-target IBC BB03 [0002] 1 501 501 [036..038) i bwd IBC BB04 [0003] 2 20988. 20988 [038..045)-> BB06 ( cond ) i bwd IBC BB05 [0004] 1 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 20988. 20988 [047..04B) i bwd IBC BB07 [0006] 2 40850. 40850 [04B..04F)-> BB02 ( cond ) i bwd IBC BB08 [0007] 1 19862. 19862 [04F..051) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Compute preds Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 19862. 19862 [000..010)-> BB07 (always) i idxlen IBC BB02 [0001] 1 20988. 20988 [010..036)-> BB04 ( cond ) i bwd bwd-target IBC BB03 [0002] 1 501 501 [036..038) i bwd IBC BB04 [0003] 2 20988. 20988 [038..045)-> BB06 ( cond ) i bwd IBC BB05 [0004] 1 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 20988. 20988 [047..04B) i bwd IBC BB07 [0006] 2 40850. 40850 [04B..04F)-> BB02 ( cond ) i bwd IBC BB08 [0007] 1 19862. 19862 [04F..051) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! New BlockSet epoch 2, # of blocks (including unused BB00): 9, bitset array size: 1 (short) *************** In fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 19862. 19862 [000..010)-> BB07 (always) i idxlen IBC BB02 [0001] 1 20988. 20988 [010..036)-> BB04 ( cond ) i bwd bwd-target IBC BB03 [0002] 1 501 501 [036..038) i bwd IBC BB04 [0003] 2 20988. 20988 [038..045)-> BB06 ( cond ) i bwd IBC BB05 [0004] 1 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 20988. 20988 [047..04B) i bwd IBC BB07 [0006] 2 40850. 40850 [04B..04F)-> BB02 ( cond ) i bwd IBC BB08 [0007] 1 19862. 19862 [04F..051) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 19862. 19862 [000..010)-> BB07 (always) i label target idxlen IBC BB02 [0001] 1 BB07 20988. 20988 [010..036)-> BB04 ( cond ) i label target bwd bwd-target IBC BB03 [0002] 1 BB02 501 501 [036..038) i bwd IBC BB04 [0003] 2 BB02,BB03 20988. 20988 [038..045)-> BB06 ( cond ) i label target bwd IBC BB05 [0004] 1 BB04 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 BB04,BB05 20988. 20988 [047..04B) i label target bwd IBC BB07 [0006] 2 BB01,BB06 40850. 40850 [04B..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 1 BB07 19862. 19862 [04F..051) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Compute preds *************** Starting PHASE Merge throw blocks *************** In fgTailMergeThrows Method does not have multiple noreturn calls. *************** Finishing PHASE Merge throw blocks [no changes] *************** Starting PHASE Update flow graph early pass *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 19862. 19862 [000..010)-> BB07 (always) i label target idxlen IBC BB02 [0001] 1 BB07 20988. 20988 [010..036)-> BB04 ( cond ) i label target bwd bwd-target IBC BB03 [0002] 1 BB02 501 501 [036..038) i bwd IBC BB04 [0003] 2 BB02,BB03 20988. 20988 [038..045)-> BB06 ( cond ) i label target bwd IBC BB05 [0004] 1 BB04 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 BB04,BB05 20988. 20988 [047..04B) i label target bwd IBC BB07 [0006] 2 BB01,BB06 40850. 40850 [04B..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 1 BB07 19862. 19862 [04F..051) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Update flow graph early pass *************** Starting PHASE Morph - Promote Structs *************** In fgPromoteStructs() lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 ref class-hnd ; V01 arg1 ref class-hnd ; V02 arg2 struct ld-addr-op ; V03 arg3 struct ld-addr-op ; V04 arg4 ref class-hnd ; V05 arg5 byref ; V06 loc0 bool ; V07 loc1 int ; V08 loc2 int ; V09 loc3 ref class-hnd ; V10 loc4 ref class-hnd ; V11 loc5 ref ld-addr-op class-hnd ; V12 OutArgs lclBlk "OutgoingArgSpace" Promoting struct local V02 (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]): lvaGrabTemp returning 13 (V13 tmp1) (a long lifetime temp) called for field V02.array (fldOffset=0x0). Promoting struct local V03 (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]): lvaGrabTemp returning 14 (V14 tmp2) (a long lifetime temp) called for field V03.array (fldOffset=0x0). lvaTable after fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 ref class-hnd ; V01 arg1 ref class-hnd ; V02 arg2 struct ld-addr-op ; V03 arg3 struct ld-addr-op ; V04 arg4 ref class-hnd ; V05 arg5 byref ; V06 loc0 bool ; V07 loc1 int ; V08 loc2 int ; V09 loc3 ref class-hnd ; V10 loc4 ref class-hnd ; V11 loc5 ref ld-addr-op class-hnd ; V12 OutArgs lclBlk "OutgoingArgSpace" ; V13 tmp1 ref V02.array(offs=0x00) P-INDEP "field V02.array (fldOffset=0x0)" ; V14 tmp2 ref V03.array(offs=0x00) P-INDEP "field V03.array (fldOffset=0x0)" *************** Finishing PHASE Morph - Promote Structs *************** Starting PHASE Morph - Structs/AddrExp *************** In fgMarkAddressExposedLocals() LocalAddressVisitor visiting statement: STMT00001 (IL ???... ???) [000008] -A---------- * ASG int [000007] D------N---- +--* LCL_VAR int V06 loc0 [000006] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00002 (IL ???...0x00B) [000012] -AC--------- * ASG int [000011] D------N---- +--* LCL_VAR int V07 loc1 [000010] --C--------- \--* SUB int [000077] ---XG------- +--* ARR_LENGTH int [000076] ----G------- | \--* FIELD ref array [000074] ------------ | \--* ADDR byref [000075] -------N---- | \--* LCL_VAR struct(P) V02 arg2 | \--* ref V02.array (offs=0x00) -> V13 tmp1 [000009] ------------ \--* CNS_INT int 1 Replacing the field in promoted struct with local var V13 LocalAddressVisitor modified statement: STMT00002 (IL ???...0x00B) [000012] -AC--------- * ASG int [000011] D------N---- +--* LCL_VAR int V07 loc1 [000010] --C--------- \--* SUB int [000077] ---XG------- +--* ARR_LENGTH int [000076] ------------ | \--* LCL_VAR ref V13 tmp1 [000009] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00003 (IL 0x00C...0x00D) [000015] -A---------- * ASG int [000014] D------N---- +--* LCL_VAR int V08 loc2 [000013] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00006 (IL ???... ???) [000028] -AC--------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V09 loc3 [000082] ---XG------- \--* INDEX ref [000081] ----G------- +--* FIELD ref array [000079] ------------ | \--* ADDR byref [000080] -------N---- | \--* LCL_VAR struct(P) V03 arg3 | \--* ref V03.array (offs=0x00) -> V14 tmp2 [000022] ------------ \--* LCL_VAR int V08 loc2 Replacing the field in promoted struct with local var V14 LocalAddressVisitor modified statement: STMT00006 (IL ???... ???) [000028] -AC--------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V09 loc3 [000082] ---XG------- \--* INDEX ref [000081] ------------ +--* LCL_VAR ref V14 tmp2 [000022] ------------ \--* LCL_VAR int V08 loc2 LocalAddressVisitor visiting statement: STMT00008 (IL ???... ???) [000037] -AC--------- * ASG ref [000036] D------N---- +--* LCL_VAR ref V10 loc4 [000087] ---XG------- \--* INDEX ref [000086] ----G------- +--* FIELD ref array [000084] ------------ | \--* ADDR byref [000085] -------N---- | \--* LCL_VAR struct(P) V02 arg2 | \--* ref V02.array (offs=0x00) -> V13 tmp1 [000031] ------------ \--* LCL_VAR int V08 loc2 Replacing the field in promoted struct with local var V13 LocalAddressVisitor modified statement: STMT00008 (IL ???... ???) [000037] -AC--------- * ASG ref [000036] D------N---- +--* LCL_VAR ref V10 loc4 [000087] ---XG------- \--* INDEX ref [000086] ------------ +--* LCL_VAR ref V13 tmp1 [000031] ------------ \--* LCL_VAR int V08 loc2 LocalAddressVisitor visiting statement: STMT00009 (IL 0x023...0x024) [000040] -A---------- * ASG ref [000039] D------N---- +--* LCL_VAR ref V11 loc5 [000038] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00010 (IL 0x026...0x034) [000052] --C-G------- * JTRUE void [000051] --C-G------- \--* NE int [000049] --C-G------- +--* CAST int <- bool <- int [000048] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000041] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000042] ------------ arg1 | +--* LCL_VAR ref V01 arg1 [000043] ------------ arg2 | +--* LCL_VAR ref V10 loc4 [000044] ------------ arg3 | +--* LCL_VAR ref V09 loc3 [000045] ------------ arg4 | +--* LCL_VAR ref V04 arg4 [000047] ------------ arg5 | \--* ADDR byref [000046] -------N---- | \--* LCL_VAR ref V11 loc5 [000050] ------------ \--* CNS_INT int 0 Local V11 should not be enregistered because: it is address exposed LocalAddressVisitor modified statement: STMT00010 (IL 0x026...0x034) [000052] --C-G------- * JTRUE void [000051] --C-G------- \--* NE int [000049] --C-G------- +--* CAST int <- bool <- int [000048] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000041] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000042] ------------ arg1 | +--* LCL_VAR ref V01 arg1 [000043] ------------ arg2 | +--* LCL_VAR ref V10 loc4 [000044] ------------ arg3 | +--* LCL_VAR ref V09 loc3 [000045] ------------ arg4 | +--* LCL_VAR ref V04 arg4 [000047] ------------ arg5 | \--* LCL_VAR_ADDR byref V11 loc5 [000050] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00014 (IL 0x036...0x037) [000071] -A---------- * ASG int [000070] D------N---- +--* LCL_VAR int V06 loc0 [000069] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00011 (IL 0x038...0x043) [000060] --C-G------- * JTRUE void [000059] --C-G------- \--* EQ int [000057] --C-G------- +--* CAST int <- bool <- int [000056] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ------------ arg0 | +--* LCL_VAR ref (AX) V11 loc5 [000054] ------------ arg1 | +--* LCL_VAR ref V10 loc4 [000055] ------------ arg2 | \--* LCL_VAR byref V05 arg5 [000058] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00013 (IL 0x045...0x046) [000068] -A---------- * ASG int [000067] D------N---- +--* LCL_VAR int V06 loc0 [000066] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00012 (IL 0x047...0x04A) [000065] -A---------- * ASG int [000064] D------N---- +--* LCL_VAR int V08 loc2 [000063] ------------ \--* ADD int [000061] ------------ +--* LCL_VAR int V08 loc2 [000062] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00004 (IL 0x04B...0x04D) [000019] ------------ * JTRUE void [000018] ------------ \--* LE int [000016] ------------ +--* LCL_VAR int V08 loc2 [000017] ------------ \--* LCL_VAR int V07 loc1 LocalAddressVisitor visiting statement: STMT00015 (IL 0x04F...0x050) [000073] ------------ * RETURN int [000072] ------------ \--* LCL_VAR int V06 loc0 *************** Finishing PHASE Morph - Structs/AddrExp *************** Starting PHASE Morph - ByRefs *************** Finishing PHASE Morph - ByRefs *************** Starting PHASE Morph - Global *************** In fgMorphBlocks() Morphing BB01 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB01, STMT00001 (before) [000008] -A---------- * ASG int [000007] D------N---- +--* LCL_VAR int V06 loc0 [000006] ------------ \--* CNS_INT int 1 fgMorphTree (before 0): [000008] -A---------- * ASG int [000007] D------N---- +--* LCL_VAR int V06 loc0 [000006] ------------ \--* CNS_INT int 1 fgMorphTree (before 1): [000007] D------N---- * LCL_VAR int V06 loc0 fgMorphTree (after 1): [000007] D------N---- * LCL_VAR int V06 loc0 fgMorphTree (before 2): [000089] ------------ * CAST int <- bool <- int [000006] ------------ \--* CNS_INT int 1 fgMorphTree (before 3): [000006] ------------ * CNS_INT int 1 fgMorphTree (after 3): [000006] ------------ * CNS_INT int 1 fgMorphTree (after 2): [000006] -----+------ * CNS_INT int 1 fgMorphTree (after 0): [000008] -A---------- * ASG int [000007] D----+-N---- +--* LCL_VAR int V06 loc0 [000006] -----+------ \--* CNS_INT int 1 GenTreeNode creates assertion: [000008] -A---------- * ASG int In BB01 New Local Constant Assertion: V06 == 1 index=#01, mask=0000000000000001 fgMorphTree BB01, STMT00002 (before) [000012] -AC--------- * ASG int [000011] D------N---- +--* LCL_VAR int V07 loc1 [000010] --C--------- \--* SUB int [000077] ---XG------- +--* ARR_LENGTH int [000076] ------------ | \--* LCL_VAR ref V13 tmp1 [000009] ------------ \--* CNS_INT int 1 fgMorphTree (before 4): [000012] -AC--------- * ASG int [000011] D------N---- +--* LCL_VAR int V07 loc1 [000010] --C--------- \--* SUB int [000077] ---XG------- +--* ARR_LENGTH int [000076] ------------ | \--* LCL_VAR ref V13 tmp1 [000009] ------------ \--* CNS_INT int 1 fgMorphTree (before 5): [000011] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (after 5): [000011] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (before 6): [000010] --C--------- * SUB int [000077] ---XG------- +--* ARR_LENGTH int [000076] ------------ | \--* LCL_VAR ref V13 tmp1 [000009] ------------ \--* CNS_INT int 1 fgMorphTree (before 7): [000077] ---XG------- * ARR_LENGTH int [000076] ------------ \--* LCL_VAR ref V13 tmp1 fgMorphTree (before 8): [000076] ------------ * LCL_VAR ref V13 tmp1 fgMorphTree (after 8): [000076] ------------ * LCL_VAR ref V13 tmp1 fgMorphTree (after 7): [000077] ---XG------- * ARR_LENGTH int [000076] -----+------ \--* LCL_VAR ref V13 tmp1 GenTreeNode creates assertion: [000077] ---XG------- * ARR_LENGTH int In BB01 New Local Constant Assertion: V13 != null index=#02, mask=0000000000000002 fgMorphTree (before 9): [000009] ------------ * CNS_INT int 1 fgMorphTree (after 9): [000009] ------------ * CNS_INT int 1 fgMorphTree (after 6): [000010] ---XG------- * ADD int [000077] ---XG+------ +--* ARR_LENGTH int [000076] -----+------ | \--* LCL_VAR ref V13 tmp1 [000009] -----+------ \--* CNS_INT int -1 fgMorphTree (after 4): [000012] -A-XG------- * ASG int [000011] D----+-N---- +--* LCL_VAR int V07 loc1 [000010] ---XG+------ \--* ADD int [000077] ---XG+------ +--* ARR_LENGTH int [000076] -----+------ | \--* LCL_VAR ref V13 tmp1 [000009] -----+------ \--* CNS_INT int -1 fgMorphTree BB01, STMT00002 (after) [000012] -A-XG+------ * ASG int [000011] D----+-N---- +--* LCL_VAR int V07 loc1 [000010] ---XG+------ \--* ADD int [000077] ---XG+------ +--* ARR_LENGTH int [000076] -----+------ | \--* LCL_VAR ref V13 tmp1 [000009] -----+------ \--* CNS_INT int -1 fgMorphTree BB01, STMT00003 (before) [000015] -A---------- * ASG int [000014] D------N---- +--* LCL_VAR int V08 loc2 [000013] ------------ \--* CNS_INT int 0 fgMorphTree (before 10): [000015] -A---------- * ASG int [000014] D------N---- +--* LCL_VAR int V08 loc2 [000013] ------------ \--* CNS_INT int 0 fgMorphTree (before 11): [000014] D------N---- * LCL_VAR int V08 loc2 fgMorphTree (after 11): [000014] D------N---- * LCL_VAR int V08 loc2 fgMorphTree (before 12): [000013] ------------ * CNS_INT int 0 fgMorphTree (after 12): [000013] ------------ * CNS_INT int 0 fgMorphTree (after 10): [000015] -A---------- * ASG int [000014] D----+-N---- +--* LCL_VAR int V08 loc2 [000013] -----+------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000015] -A---------- * ASG int In BB01 New Local Constant Assertion: V08 == 0 index=#03, mask=0000000000000004 Morphing BB02 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB02, STMT00006 (before) [000028] -AC--------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V09 loc3 [000082] ---XG------- \--* INDEX ref [000081] ------------ +--* LCL_VAR ref V14 tmp2 [000022] ------------ \--* LCL_VAR int V08 loc2 fgMorphTree (before 13): [000028] -AC--------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V09 loc3 [000082] ---XG------- \--* INDEX ref [000081] ------------ +--* LCL_VAR ref V14 tmp2 [000022] ------------ \--* LCL_VAR int V08 loc2 fgMorphTree (before 14): [000027] D------N---- * LCL_VAR ref V09 loc3 fgMorphTree (after 14): [000027] D------N---- * LCL_VAR ref V09 loc3 fgMorphTree (before 15): [000082] ---XG------- * INDEX ref [000081] ------------ +--* LCL_VAR ref V14 tmp2 [000022] ------------ \--* LCL_VAR int V08 loc2 fgMorphTree (before 16): [000100] ---XG------- * COMMA ref [000093] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void [000022] ------------ | +--* LCL_VAR int V08 loc2 [000092] ---X-------- | \--* ARR_LENGTH int [000081] ------------ | \--* LCL_VAR ref V14 tmp2 [000082] a--XG------- \--* IND ref [000099] ------------ \--* ADD byref [000090] ------------ +--* LCL_VAR ref V14 tmp2 [000098] ------------ \--* ADD long [000096] ------------ +--* MUL long [000094] ------------ | +--* CAST long <- int [000091] ------------ | | \--* LCL_VAR int V08 loc2 [000095] -------N---- | \--* CNS_INT long 8 [000097] ------------ \--* CNS_INT long 16 fgMorphTree (before 17): [000093] ---X-------- * ARR_BOUNDS_CHECK_Rng void [000022] ------------ +--* LCL_VAR int V08 loc2 [000092] ---X-------- \--* ARR_LENGTH int [000081] ------------ \--* LCL_VAR ref V14 tmp2 fgMorphTree (before 18): [000022] ------------ * LCL_VAR int V08 loc2 fgMorphTree (after 18): [000022] ------------ * LCL_VAR int V08 loc2 fgMorphTree (before 19): [000092] ---X-------- * ARR_LENGTH int [000081] ------------ \--* LCL_VAR ref V14 tmp2 fgMorphTree (before 20): [000081] ------------ * LCL_VAR ref V14 tmp2 fgMorphTree (after 20): [000081] ------------ * LCL_VAR ref V14 tmp2 fgMorphTree (after 19): [000092] ---X-------- * ARR_LENGTH int [000081] -----+------ \--* LCL_VAR ref V14 tmp2 GenTreeNode creates assertion: [000092] ---X-------- * ARR_LENGTH int In BB02 New Local Constant Assertion: V14 != null index=#01, mask=0000000000000001 fgMorphTree (after 17): [000093] ---X-------- * ARR_BOUNDS_CHECK_Rng void [000022] -----+------ +--* LCL_VAR int V08 loc2 [000092] ---X-+------ \--* ARR_LENGTH int [000081] -----+------ \--* LCL_VAR ref V14 tmp2 fgMorphTree (before 21): [000082] a--XG------- * IND ref [000099] ------------ \--* ADD byref [000090] ------------ +--* LCL_VAR ref V14 tmp2 [000098] ------------ \--* ADD long [000096] ------------ +--* MUL long [000094] ------------ | +--* CAST long <- int [000091] ------------ | | \--* LCL_VAR int V08 loc2 [000095] -------N---- | \--* CNS_INT long 8 [000097] ------------ \--* CNS_INT long 16 fgMorphTree (before 22): [000099] ------------ * ADD byref [000090] ------------ +--* LCL_VAR ref V14 tmp2 [000098] ------------ \--* ADD long [000096] ------------ +--* MUL long [000094] ------------ | +--* CAST long <- int [000091] ------------ | | \--* LCL_VAR int V08 loc2 [000095] -------N---- | \--* CNS_INT long 8 [000097] ------------ \--* CNS_INT long 16 fgMorphTree (before 23): [000090] ------------ * LCL_VAR ref V14 tmp2 fgMorphTree (after 23): [000090] ------------ * LCL_VAR ref V14 tmp2 fgMorphTree (before 24): [000098] ------------ * ADD long [000096] ------------ +--* MUL long [000094] ------------ | +--* CAST long <- int [000091] ------------ | | \--* LCL_VAR int V08 loc2 [000095] -------N---- | \--* CNS_INT long 8 [000097] ------------ \--* CNS_INT long 16 fgMorphTree (before 25): [000096] ------------ * MUL long [000094] ------------ +--* CAST long <- int [000091] ------------ | \--* LCL_VAR int V08 loc2 [000095] -------N---- \--* CNS_INT long 8 fgMorphTree (before 26): [000094] ------------ * CAST long <- int [000091] ------------ \--* LCL_VAR int V08 loc2 fgMorphTree (before 27): [000091] ------------ * LCL_VAR int V08 loc2 fgMorphTree (after 27): [000091] ------------ * LCL_VAR int V08 loc2 fgMorphTree (after 26): [000094] ------------ * CAST long <- int [000091] -----+------ \--* LCL_VAR int V08 loc2 fgMorphTree (before 28): [000095] -------N---- * CNS_INT long 8 fgMorphTree (after 28): [000095] -------N---- * CNS_INT long 8 fgMorphTree (after 25): [000096] ------------ * LSH long [000094] -----+------ +--* CAST long <- int [000091] -----+------ | \--* LCL_VAR int V08 loc2 [000095] -----+-N---- \--* CNS_INT long 3 fgMorphTree (before 29): [000097] ------------ * CNS_INT long 16 fgMorphTree (after 29): [000097] ------------ * CNS_INT long 16 fgMorphTree (after 24): [000098] ------------ * ADD long [000096] -----+------ +--* LSH long [000094] -----+------ | +--* CAST long <- int [000091] -----+------ | | \--* LCL_VAR int V08 loc2 [000095] -----+-N---- | \--* CNS_INT long 3 [000097] -----+------ \--* CNS_INT long 16 fgMorphTree (after 22): [000099] ------------ * ADD byref [000090] -----+------ +--* LCL_VAR ref V14 tmp2 [000098] -----+------ \--* ADD long [000096] -----+------ +--* LSH long [000094] -----+------ | +--* CAST long <- int [000091] -----+------ | | \--* LCL_VAR int V08 loc2 [000095] -----+-N---- | \--* CNS_INT long 3 [000097] -----+------ \--* CNS_INT long 16 fgMorphTree (after 21): [000082] a---G------- * IND ref [000099] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V14 tmp2 [000098] -----+------ \--* ADD long [000096] -----+------ +--* LSH long [000094] -----+------ | +--* CAST long <- int [000091] -----+------ | | \--* LCL_VAR int V08 loc2 [000095] -----+-N---- | \--* CNS_INT long 3 [000097] -----+------ \--* CNS_INT long 16 fgMorphTree (after 16): [000100] ---XG------- * COMMA ref [000093] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000022] -----+------ | +--* LCL_VAR int V08 loc2 [000092] ---X-+------ | \--* ARR_LENGTH int [000081] -----+------ | \--* LCL_VAR ref V14 tmp2 [000082] a---G+------ \--* IND ref [000099] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V14 tmp2 [000098] -----+------ \--* ADD long [000096] -----+------ +--* LSH long [000094] -----+------ | +--* CAST long <- int [000091] -----+------ | | \--* LCL_VAR int V08 loc2 [000095] -----+-N---- | \--* CNS_INT long 3 [000097] -----+------ \--* CNS_INT long 16 fgMorphTree (after 15): [000100] ---XG+------ * COMMA ref [000093] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000022] -----+------ | +--* LCL_VAR int V08 loc2 [000092] ---X-+------ | \--* ARR_LENGTH int [000081] -----+------ | \--* LCL_VAR ref V14 tmp2 [000082] a---G+------ \--* IND ref [000099] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V14 tmp2 [000098] -----+------ \--* ADD long [000096] -----+------ +--* LSH long [000094] -----+------ | +--* CAST long <- int [000091] i----+------ | | \--* LCL_VAR int V08 loc2 [000095] -----+-N---- | \--* CNS_INT long 3 [000097] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree (after 13): [000028] -A-XG------- * ASG ref [000027] D----+-N---- +--* LCL_VAR ref V09 loc3 [000100] ---XG+------ \--* COMMA ref [000093] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000022] -----+------ | +--* LCL_VAR int V08 loc2 [000092] ---X-+------ | \--* ARR_LENGTH int [000081] -----+------ | \--* LCL_VAR ref V14 tmp2 [000082] a---G+------ \--* IND ref [000099] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V14 tmp2 [000098] -----+------ \--* ADD long [000096] -----+------ +--* LSH long [000094] -----+------ | +--* CAST long <- int [000091] i----+------ | | \--* LCL_VAR int V08 loc2 [000095] -----+-N---- | \--* CNS_INT long 3 [000097] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree BB02, STMT00006 (after) [000028] -A-XG+------ * ASG ref [000027] D----+-N---- +--* LCL_VAR ref V09 loc3 [000100] ---XG+------ \--* COMMA ref [000093] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000022] -----+------ | +--* LCL_VAR int V08 loc2 [000092] ---X-+------ | \--* ARR_LENGTH int [000081] -----+------ | \--* LCL_VAR ref V14 tmp2 [000082] a---G+------ \--* IND ref [000099] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V14 tmp2 [000098] -----+------ \--* ADD long [000096] -----+------ +--* LSH long [000094] -----+------ | +--* CAST long <- int [000091] i----+------ | | \--* LCL_VAR int V08 loc2 [000095] -----+-N---- | \--* CNS_INT long 3 [000097] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree BB02, STMT00008 (before) [000037] -AC--------- * ASG ref [000036] D------N---- +--* LCL_VAR ref V10 loc4 [000087] ---XG------- \--* INDEX ref [000086] ------------ +--* LCL_VAR ref V13 tmp1 [000031] ------------ \--* LCL_VAR int V08 loc2 fgMorphTree (before 30): [000037] -AC--------- * ASG ref [000036] D------N---- +--* LCL_VAR ref V10 loc4 [000087] ---XG------- \--* INDEX ref [000086] ------------ +--* LCL_VAR ref V13 tmp1 [000031] ------------ \--* LCL_VAR int V08 loc2 fgMorphTree (before 31): [000036] D------N---- * LCL_VAR ref V10 loc4 fgMorphTree (after 31): [000036] D------N---- * LCL_VAR ref V10 loc4 fgMorphTree (before 32): [000087] ---XG------- * INDEX ref [000086] ------------ +--* LCL_VAR ref V13 tmp1 [000031] ------------ \--* LCL_VAR int V08 loc2 fgMorphTree (before 33): [000111] ---XG------- * COMMA ref [000104] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void [000031] ------------ | +--* LCL_VAR int V08 loc2 [000103] ---X-------- | \--* ARR_LENGTH int [000086] ------------ | \--* LCL_VAR ref V13 tmp1 [000087] a--XG------- \--* IND ref [000110] ------------ \--* ADD byref [000101] ------------ +--* LCL_VAR ref V13 tmp1 [000109] ------------ \--* ADD long [000107] ------------ +--* MUL long [000105] ------------ | +--* CAST long <- int [000102] ------------ | | \--* LCL_VAR int V08 loc2 [000106] -------N---- | \--* CNS_INT long 8 [000108] ------------ \--* CNS_INT long 16 fgMorphTree (before 34): [000104] ---X-------- * ARR_BOUNDS_CHECK_Rng void [000031] ------------ +--* LCL_VAR int V08 loc2 [000103] ---X-------- \--* ARR_LENGTH int [000086] ------------ \--* LCL_VAR ref V13 tmp1 fgMorphTree (before 35): [000031] ------------ * LCL_VAR int V08 loc2 fgMorphTree (after 35): [000031] ------------ * LCL_VAR int V08 loc2 fgMorphTree (before 36): [000103] ---X-------- * ARR_LENGTH int [000086] ------------ \--* LCL_VAR ref V13 tmp1 fgMorphTree (before 37): [000086] ------------ * LCL_VAR ref V13 tmp1 fgMorphTree (after 37): [000086] ------------ * LCL_VAR ref V13 tmp1 fgMorphTree (after 36): [000103] ---X-------- * ARR_LENGTH int [000086] -----+------ \--* LCL_VAR ref V13 tmp1 GenTreeNode creates assertion: [000103] ---X-------- * ARR_LENGTH int In BB02 New Local Constant Assertion: V13 != null index=#02, mask=0000000000000002 fgMorphTree (after 34): [000104] ---X-------- * ARR_BOUNDS_CHECK_Rng void [000031] -----+------ +--* LCL_VAR int V08 loc2 [000103] ---X-+------ \--* ARR_LENGTH int [000086] -----+------ \--* LCL_VAR ref V13 tmp1 fgMorphTree (before 38): [000087] a--XG------- * IND ref [000110] ------------ \--* ADD byref [000101] ------------ +--* LCL_VAR ref V13 tmp1 [000109] ------------ \--* ADD long [000107] ------------ +--* MUL long [000105] ------------ | +--* CAST long <- int [000102] ------------ | | \--* LCL_VAR int V08 loc2 [000106] -------N---- | \--* CNS_INT long 8 [000108] ------------ \--* CNS_INT long 16 fgMorphTree (before 39): [000110] ------------ * ADD byref [000101] ------------ +--* LCL_VAR ref V13 tmp1 [000109] ------------ \--* ADD long [000107] ------------ +--* MUL long [000105] ------------ | +--* CAST long <- int [000102] ------------ | | \--* LCL_VAR int V08 loc2 [000106] -------N---- | \--* CNS_INT long 8 [000108] ------------ \--* CNS_INT long 16 fgMorphTree (before 40): [000101] ------------ * LCL_VAR ref V13 tmp1 fgMorphTree (after 40): [000101] ------------ * LCL_VAR ref V13 tmp1 fgMorphTree (before 41): [000109] ------------ * ADD long [000107] ------------ +--* MUL long [000105] ------------ | +--* CAST long <- int [000102] ------------ | | \--* LCL_VAR int V08 loc2 [000106] -------N---- | \--* CNS_INT long 8 [000108] ------------ \--* CNS_INT long 16 fgMorphTree (before 42): [000107] ------------ * MUL long [000105] ------------ +--* CAST long <- int [000102] ------------ | \--* LCL_VAR int V08 loc2 [000106] -------N---- \--* CNS_INT long 8 fgMorphTree (before 43): [000105] ------------ * CAST long <- int [000102] ------------ \--* LCL_VAR int V08 loc2 fgMorphTree (before 44): [000102] ------------ * LCL_VAR int V08 loc2 fgMorphTree (after 44): [000102] ------------ * LCL_VAR int V08 loc2 fgMorphTree (after 43): [000105] ------------ * CAST long <- int [000102] -----+------ \--* LCL_VAR int V08 loc2 fgMorphTree (before 45): [000106] -------N---- * CNS_INT long 8 fgMorphTree (after 45): [000106] -------N---- * CNS_INT long 8 fgMorphTree (after 42): [000107] ------------ * LSH long [000105] -----+------ +--* CAST long <- int [000102] -----+------ | \--* LCL_VAR int V08 loc2 [000106] -----+-N---- \--* CNS_INT long 3 fgMorphTree (before 46): [000108] ------------ * CNS_INT long 16 fgMorphTree (after 46): [000108] ------------ * CNS_INT long 16 fgMorphTree (after 41): [000109] ------------ * ADD long [000107] -----+------ +--* LSH long [000105] -----+------ | +--* CAST long <- int [000102] -----+------ | | \--* LCL_VAR int V08 loc2 [000106] -----+-N---- | \--* CNS_INT long 3 [000108] -----+------ \--* CNS_INT long 16 fgMorphTree (after 39): [000110] ------------ * ADD byref [000101] -----+------ +--* LCL_VAR ref V13 tmp1 [000109] -----+------ \--* ADD long [000107] -----+------ +--* LSH long [000105] -----+------ | +--* CAST long <- int [000102] -----+------ | | \--* LCL_VAR int V08 loc2 [000106] -----+-N---- | \--* CNS_INT long 3 [000108] -----+------ \--* CNS_INT long 16 fgMorphTree (after 38): [000087] a---G------- * IND ref [000110] -----+------ \--* ADD byref [000101] -----+------ +--* LCL_VAR ref V13 tmp1 [000109] -----+------ \--* ADD long [000107] -----+------ +--* LSH long [000105] -----+------ | +--* CAST long <- int [000102] -----+------ | | \--* LCL_VAR int V08 loc2 [000106] -----+-N---- | \--* CNS_INT long 3 [000108] -----+------ \--* CNS_INT long 16 fgMorphTree (after 33): [000111] ---XG------- * COMMA ref [000104] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000031] -----+------ | +--* LCL_VAR int V08 loc2 [000103] ---X-+------ | \--* ARR_LENGTH int [000086] -----+------ | \--* LCL_VAR ref V13 tmp1 [000087] a---G+------ \--* IND ref [000110] -----+------ \--* ADD byref [000101] -----+------ +--* LCL_VAR ref V13 tmp1 [000109] -----+------ \--* ADD long [000107] -----+------ +--* LSH long [000105] -----+------ | +--* CAST long <- int [000102] -----+------ | | \--* LCL_VAR int V08 loc2 [000106] -----+-N---- | \--* CNS_INT long 3 [000108] -----+------ \--* CNS_INT long 16 fgMorphTree (after 32): [000111] ---XG+------ * COMMA ref [000104] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000031] -----+------ | +--* LCL_VAR int V08 loc2 [000103] ---X-+------ | \--* ARR_LENGTH int [000086] -----+------ | \--* LCL_VAR ref V13 tmp1 [000087] a---G+------ \--* IND ref [000110] -----+------ \--* ADD byref [000101] -----+------ +--* LCL_VAR ref V13 tmp1 [000109] -----+------ \--* ADD long [000107] -----+------ +--* LSH long [000105] -----+------ | +--* CAST long <- int [000102] i----+------ | | \--* LCL_VAR int V08 loc2 [000106] -----+-N---- | \--* CNS_INT long 3 [000108] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree (after 30): [000037] -A-XG------- * ASG ref [000036] D----+-N---- +--* LCL_VAR ref V10 loc4 [000111] ---XG+------ \--* COMMA ref [000104] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000031] -----+------ | +--* LCL_VAR int V08 loc2 [000103] ---X-+------ | \--* ARR_LENGTH int [000086] -----+------ | \--* LCL_VAR ref V13 tmp1 [000087] a---G+------ \--* IND ref [000110] -----+------ \--* ADD byref [000101] -----+------ +--* LCL_VAR ref V13 tmp1 [000109] -----+------ \--* ADD long [000107] -----+------ +--* LSH long [000105] -----+------ | +--* CAST long <- int [000102] i----+------ | | \--* LCL_VAR int V08 loc2 [000106] -----+-N---- | \--* CNS_INT long 3 [000108] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree BB02, STMT00008 (after) [000037] -A-XG+------ * ASG ref [000036] D----+-N---- +--* LCL_VAR ref V10 loc4 [000111] ---XG+------ \--* COMMA ref [000104] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000031] -----+------ | +--* LCL_VAR int V08 loc2 [000103] ---X-+------ | \--* ARR_LENGTH int [000086] -----+------ | \--* LCL_VAR ref V13 tmp1 [000087] a---G+------ \--* IND ref [000110] -----+------ \--* ADD byref [000101] -----+------ +--* LCL_VAR ref V13 tmp1 [000109] -----+------ \--* ADD long [000107] -----+------ +--* LSH long [000105] -----+------ | +--* CAST long <- int [000102] i----+------ | | \--* LCL_VAR int V08 loc2 [000106] -----+-N---- | \--* CNS_INT long 3 [000108] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree BB02, STMT00009 (before) [000040] -A---------- * ASG ref [000039] D------N---- +--* LCL_VAR ref (AX) V11 loc5 [000038] ------------ \--* CNS_INT ref null fgMorphTree (before 47): [000040] -A---------- * ASG ref [000039] D------N---- +--* LCL_VAR ref (AX) V11 loc5 [000038] ------------ \--* CNS_INT ref null fgMorphTree (before 48): [000039] D------N---- * LCL_VAR ref (AX) V11 loc5 fgMorphTree (after 48): [000039] D---G--N---- * LCL_VAR ref (AX) V11 loc5 fgMorphTree (before 49): [000038] ------------ * CNS_INT ref null fgMorphTree (after 49): [000038] ------------ * CNS_INT ref null fgMorphTree (after 47): [000040] -A--G------- * ASG ref [000039] D---G+-N---- +--* LCL_VAR ref (AX) V11 loc5 [000038] -----+------ \--* CNS_INT ref null fgMorphTree BB02, STMT00010 (before) [000052] --C-G------- * JTRUE void [000051] --C-G------- \--* NE int [000049] --C-G------- +--* CAST int <- bool <- int [000048] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000041] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000042] ------------ arg1 | +--* LCL_VAR ref V01 arg1 [000043] ------------ arg2 | +--* LCL_VAR ref V10 loc4 [000044] ------------ arg3 | +--* LCL_VAR ref V09 loc3 [000045] ------------ arg4 | +--* LCL_VAR ref V04 arg4 [000047] ------------ arg5 | \--* LCL_VAR_ADDR byref V11 loc5 [000050] ------------ \--* CNS_INT int 0 fgMorphTree (before 50): [000052] --C-G------- * JTRUE void [000051] --C-G------- \--* NE int [000049] --C-G------- +--* CAST int <- bool <- int [000048] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000041] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000042] ------------ arg1 | +--* LCL_VAR ref V01 arg1 [000043] ------------ arg2 | +--* LCL_VAR ref V10 loc4 [000044] ------------ arg3 | +--* LCL_VAR ref V09 loc3 [000045] ------------ arg4 | +--* LCL_VAR ref V04 arg4 [000047] ------------ arg5 | \--* LCL_VAR_ADDR byref V11 loc5 [000050] ------------ \--* CNS_INT int 0 fgMorphTree (before 51): [000051] J-C-G--N---- * NE int [000049] --C-G------- +--* CAST int <- bool <- int [000048] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000041] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000042] ------------ arg1 | +--* LCL_VAR ref V01 arg1 [000043] ------------ arg2 | +--* LCL_VAR ref V10 loc4 [000044] ------------ arg3 | +--* LCL_VAR ref V09 loc3 [000045] ------------ arg4 | +--* LCL_VAR ref V04 arg4 [000047] ------------ arg5 | \--* LCL_VAR_ADDR byref V11 loc5 [000050] ------------ \--* CNS_INT int 0 fgMorphTree (before 52): [000049] --C-G------- * CAST int <- bool <- int [000048] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000041] ------------ arg0 +--* LCL_VAR ref V00 arg0 [000042] ------------ arg1 +--* LCL_VAR ref V01 arg1 [000043] ------------ arg2 +--* LCL_VAR ref V10 loc4 [000044] ------------ arg3 +--* LCL_VAR ref V09 loc3 [000045] ------------ arg4 +--* LCL_VAR ref V04 arg4 [000047] ------------ arg5 \--* LCL_VAR_ADDR byref V11 loc5 fgMorphTree (before 53): [000048] --C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000041] ------------ arg0 +--* LCL_VAR ref V00 arg0 [000042] ------------ arg1 +--* LCL_VAR ref V01 arg1 [000043] ------------ arg2 +--* LCL_VAR ref V10 loc4 [000044] ------------ arg3 +--* LCL_VAR ref V09 loc3 [000045] ------------ arg4 +--* LCL_VAR ref V04 arg4 [000047] ------------ arg5 \--* LCL_VAR_ADDR byref V11 loc5 Initializing arg info for 48.CALL: ArgTable for 48.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 41.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 42.LCL_VAR ref, 1 reg: rsi, align=1] fgArgTabEntry[arg 2 43.LCL_VAR ref, 1 reg: rdx, align=1] fgArgTabEntry[arg 3 44.LCL_VAR ref, 1 reg: rcx, align=1] fgArgTabEntry[arg 4 45.LCL_VAR ref, 1 reg: r8, align=1] fgArgTabEntry[arg 5 47.LCL_VAR_ADDR long, 1 reg: r9, align=1] Morphing args for 48.CALL: fgMorphTree (before 54): [000041] ------------ * LCL_VAR ref V00 arg0 fgMorphTree (after 54): [000041] ------------ * LCL_VAR ref V00 arg0 fgMorphTree (before 55): [000042] ------------ * LCL_VAR ref V01 arg1 fgMorphTree (after 55): [000042] ------------ * LCL_VAR ref V01 arg1 fgMorphTree (before 56): [000043] ------------ * LCL_VAR ref V10 loc4 fgMorphTree (after 56): [000043] ------------ * LCL_VAR ref V10 loc4 fgMorphTree (before 57): [000044] ------------ * LCL_VAR ref V09 loc3 fgMorphTree (after 57): [000044] ------------ * LCL_VAR ref V09 loc3 fgMorphTree (before 58): [000045] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (after 58): [000045] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (before 59): [000047] ------------ * LCL_VAR_ADDR long V11 loc5 fgMorphTree (after 59): [000047] ------------ * LCL_VAR_ADDR long V11 loc5 argSlots=6, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('r9'): [000047] -----+------ * LCL_VAR_ADDR long V11 loc5 Replaced with placeholder node: [000112] ----------L- * ARGPLACE long Deferred argument ('rdi'): [000041] -----+------ * LCL_VAR ref V00 arg0 Replaced with placeholder node: [000113] ----------L- * ARGPLACE ref Deferred argument ('rsi'): [000042] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000114] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000043] -----+------ * LCL_VAR ref V10 loc4 Replaced with placeholder node: [000115] ----------L- * ARGPLACE ref Deferred argument ('rcx'): [000044] -----+------ * LCL_VAR ref V09 loc3 Replaced with placeholder node: [000116] ----------L- * ARGPLACE ref Deferred argument ('r8'): [000045] -----+------ * LCL_VAR ref V04 arg4 Replaced with placeholder node: [000117] ----------L- * ARGPLACE ref Shuffled argument table: r9 rdi rsi rdx rcx r8 ArgTable for 48.CALL after fgMorphArgs: fgArgTabEntry[arg 5 47.LCL_VAR_ADDR long, 1 reg: r9, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 0 41.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 1 42.LCL_VAR ref, 1 reg: rsi, align=1, lateArgInx=2, processed] fgArgTabEntry[arg 2 43.LCL_VAR ref, 1 reg: rdx, align=1, lateArgInx=3, processed] fgArgTabEntry[arg 3 44.LCL_VAR ref, 1 reg: rcx, align=1, lateArgInx=4, processed] fgArgTabEntry[arg 4 45.LCL_VAR ref, 1 reg: r8, align=1, lateArgInx=5, processed] fgMorphTree (after 53): [000048] --CXG------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000047] -----+------ arg5 in r9 +--* LCL_VAR_ADDR long V11 loc5 [000041] -----+------ arg0 in rdi +--* LCL_VAR ref V00 arg0 [000042] -----+------ arg1 in rsi +--* LCL_VAR ref V01 arg1 [000043] -----+------ arg2 in rdx +--* LCL_VAR ref V10 loc4 [000044] -----+------ arg3 in rcx +--* LCL_VAR ref V09 loc3 [000045] -----+------ arg4 in r8 \--* LCL_VAR ref V04 arg4 fgMorphTree (after 52): [000049] --CXG------- * CAST int <- bool <- int [000048] --CXG+------ \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000047] -----+------ arg5 in r9 +--* LCL_VAR_ADDR long V11 loc5 [000041] -----+------ arg0 in rdi +--* LCL_VAR ref V00 arg0 [000042] -----+------ arg1 in rsi +--* LCL_VAR ref V01 arg1 [000043] -----+------ arg2 in rdx +--* LCL_VAR ref V10 loc4 [000044] -----+------ arg3 in rcx +--* LCL_VAR ref V09 loc3 [000045] -----+------ arg4 in r8 \--* LCL_VAR ref V04 arg4 fgMorphTree (before 60): [000050] ------------ * CNS_INT int 0 fgMorphTree (after 60): [000050] ------------ * CNS_INT int 0 fgMorphTree (after 51): [000051] J-CXG--N---- * NE int [000049] --CXG+------ +--* CAST int <- bool <- int [000048] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000047] -----+------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 [000041] -----+------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 [000042] -----+------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 [000043] -----+------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 [000044] -----+------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 [000045] -----+------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 [000050] -----+------ \--* CNS_INT int 0 fgMorphTree (after 50): [000052] --CXG------- * JTRUE void [000051] J-CXG+-N---- \--* NE int [000049] --CXG+------ +--* CAST int <- bool <- int [000048] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000047] -----+------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 [000041] -----+------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 [000042] -----+------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 [000043] -----+------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 [000044] -----+------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 [000045] -----+------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 [000050] -----+------ \--* CNS_INT int 0 fgMorphTree BB02, STMT00010 (after) [000052] --CXG+------ * JTRUE void [000051] J-CXG+-N---- \--* NE int [000049] --CXG+------ +--* CAST int <- bool <- int [000048] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000047] -----+------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 [000041] -----+------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 [000042] -----+------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 [000043] -----+------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 [000044] -----+------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 [000045] -----+------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 [000050] -----+------ \--* CNS_INT int 0 Morphing BB03 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB03, STMT00014 (before) [000071] -A---------- * ASG int [000070] D------N---- +--* LCL_VAR int V06 loc0 [000069] ------------ \--* CNS_INT int 0 fgMorphTree (before 61): [000071] -A---------- * ASG int [000070] D------N---- +--* LCL_VAR int V06 loc0 [000069] ------------ \--* CNS_INT int 0 fgMorphTree (before 62): [000070] D------N---- * LCL_VAR int V06 loc0 fgMorphTree (after 62): [000070] D------N---- * LCL_VAR int V06 loc0 fgMorphTree (before 63): [000118] ------------ * CAST int <- bool <- int [000069] ------------ \--* CNS_INT int 0 fgMorphTree (before 64): [000069] ------------ * CNS_INT int 0 fgMorphTree (after 64): [000069] ------------ * CNS_INT int 0 fgMorphTree (after 63): [000069] -----+------ * CNS_INT int 0 fgMorphTree (after 61): [000071] -A---------- * ASG int [000070] D----+-N---- +--* LCL_VAR int V06 loc0 [000069] -----+------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000071] -A---------- * ASG int In BB03 New Local Constant Assertion: V06 == 0 index=#01, mask=0000000000000001 Morphing BB04 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB04, STMT00011 (before) [000060] --C-G------- * JTRUE void [000059] --C-G------- \--* EQ int [000057] --C-G------- +--* CAST int <- bool <- int [000056] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ------------ arg0 | +--* LCL_VAR ref (AX) V11 loc5 [000054] ------------ arg1 | +--* LCL_VAR ref V10 loc4 [000055] ------------ arg2 | \--* LCL_VAR byref V05 arg5 [000058] ------------ \--* CNS_INT int 0 fgMorphTree (before 65): [000060] --C-G------- * JTRUE void [000059] --C-G------- \--* EQ int [000057] --C-G------- +--* CAST int <- bool <- int [000056] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ------------ arg0 | +--* LCL_VAR ref (AX) V11 loc5 [000054] ------------ arg1 | +--* LCL_VAR ref V10 loc4 [000055] ------------ arg2 | \--* LCL_VAR byref V05 arg5 [000058] ------------ \--* CNS_INT int 0 fgMorphTree (before 66): [000059] J-C-G--N---- * EQ int [000057] --C-G------- +--* CAST int <- bool <- int [000056] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ------------ arg0 | +--* LCL_VAR ref (AX) V11 loc5 [000054] ------------ arg1 | +--* LCL_VAR ref V10 loc4 [000055] ------------ arg2 | \--* LCL_VAR byref V05 arg5 [000058] ------------ \--* CNS_INT int 0 fgMorphTree (before 67): [000057] --C-G------- * CAST int <- bool <- int [000056] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ------------ arg0 +--* LCL_VAR ref (AX) V11 loc5 [000054] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000055] ------------ arg2 \--* LCL_VAR byref V05 arg5 fgMorphTree (before 68): [000056] --C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ------------ arg0 +--* LCL_VAR ref (AX) V11 loc5 [000054] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000055] ------------ arg2 \--* LCL_VAR byref V05 arg5 Initializing arg info for 56.CALL: ArgTable for 56.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 53.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 54.LCL_VAR ref, 1 reg: rsi, align=1] fgArgTabEntry[arg 2 55.LCL_VAR byref, 1 reg: rdx, align=1] Morphing args for 56.CALL: fgMorphTree (before 69): [000053] ------------ * LCL_VAR ref (AX) V11 loc5 fgMorphTree (after 69): [000053] ----G------- * LCL_VAR ref (AX) V11 loc5 fgMorphTree (before 70): [000054] ------------ * LCL_VAR ref V10 loc4 fgMorphTree (after 70): [000054] ------------ * LCL_VAR ref V10 loc4 fgMorphTree (before 71): [000055] ------------ * LCL_VAR byref V05 arg5 fgMorphTree (after 71): [000055] ------------ * LCL_VAR byref V05 arg5 argSlots=3, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000053] ----G+------ * LCL_VAR ref (AX) V11 loc5 Replaced with placeholder node: [000119] ----------L- * ARGPLACE ref Deferred argument ('rsi'): [000054] -----+------ * LCL_VAR ref V10 loc4 Replaced with placeholder node: [000120] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000055] -----+------ * LCL_VAR byref V05 arg5 Replaced with placeholder node: [000121] ----------L- * ARGPLACE byref Shuffled argument table: rdi rsi rdx ArgTable for 56.CALL after fgMorphArgs: fgArgTabEntry[arg 0 53.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 54.LCL_VAR ref, 1 reg: rsi, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 2 55.LCL_VAR byref, 1 reg: rdx, align=1, lateArgInx=2, processed] fgMorphTree (after 68): [000056] --CXG------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ----G+------ arg0 in rdi +--* LCL_VAR ref (AX) V11 loc5 [000054] -----+------ arg1 in rsi +--* LCL_VAR ref V10 loc4 [000055] -----+------ arg2 in rdx \--* LCL_VAR byref V05 arg5 fgMorphTree (after 67): [000057] --CXG------- * CAST int <- bool <- int [000056] --CXG+------ \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ----G+------ arg0 in rdi +--* LCL_VAR ref (AX) V11 loc5 [000054] -----+------ arg1 in rsi +--* LCL_VAR ref V10 loc4 [000055] -----+------ arg2 in rdx \--* LCL_VAR byref V05 arg5 fgMorphTree (before 72): [000058] ------------ * CNS_INT int 0 fgMorphTree (after 72): [000058] ------------ * CNS_INT int 0 fgMorphTree (after 66): [000059] J-CXG--N---- * EQ int [000057] --CXG+------ +--* CAST int <- bool <- int [000056] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ----G+------ arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 [000054] -----+------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 [000055] -----+------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 [000058] -----+------ \--* CNS_INT int 0 fgMorphTree (after 65): [000060] --CXG------- * JTRUE void [000059] J-CXG+-N---- \--* EQ int [000057] --CXG+------ +--* CAST int <- bool <- int [000056] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ----G+------ arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 [000054] -----+------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 [000055] -----+------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 [000058] -----+------ \--* CNS_INT int 0 fgMorphTree BB04, STMT00011 (after) [000060] --CXG+------ * JTRUE void [000059] J-CXG+-N---- \--* EQ int [000057] --CXG+------ +--* CAST int <- bool <- int [000056] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ----G+------ arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 [000054] -----+------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 [000055] -----+------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 [000058] -----+------ \--* CNS_INT int 0 Morphing BB05 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB05, STMT00013 (before) [000068] -A---------- * ASG int [000067] D------N---- +--* LCL_VAR int V06 loc0 [000066] ------------ \--* CNS_INT int 0 fgMorphTree (before 73): [000068] -A---------- * ASG int [000067] D------N---- +--* LCL_VAR int V06 loc0 [000066] ------------ \--* CNS_INT int 0 fgMorphTree (before 74): [000067] D------N---- * LCL_VAR int V06 loc0 fgMorphTree (after 74): [000067] D------N---- * LCL_VAR int V06 loc0 fgMorphTree (before 75): [000122] ------------ * CAST int <- bool <- int [000066] ------------ \--* CNS_INT int 0 fgMorphTree (before 76): [000066] ------------ * CNS_INT int 0 fgMorphTree (after 76): [000066] ------------ * CNS_INT int 0 fgMorphTree (after 75): [000066] -----+------ * CNS_INT int 0 fgMorphTree (after 73): [000068] -A---------- * ASG int [000067] D----+-N---- +--* LCL_VAR int V06 loc0 [000066] -----+------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000068] -A---------- * ASG int In BB05 New Local Constant Assertion: V06 == 0 index=#01, mask=0000000000000001 Morphing BB06 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB06, STMT00012 (before) [000065] -A---------- * ASG int [000064] D------N---- +--* LCL_VAR int V08 loc2 [000063] ------------ \--* ADD int [000061] ------------ +--* LCL_VAR int V08 loc2 [000062] ------------ \--* CNS_INT int 1 fgMorphTree (before 77): [000065] -A---------- * ASG int [000064] D------N---- +--* LCL_VAR int V08 loc2 [000063] ------------ \--* ADD int [000061] ------------ +--* LCL_VAR int V08 loc2 [000062] ------------ \--* CNS_INT int 1 fgMorphTree (before 78): [000064] D------N---- * LCL_VAR int V08 loc2 fgMorphTree (after 78): [000064] D------N---- * LCL_VAR int V08 loc2 fgMorphTree (before 79): [000063] ------------ * ADD int [000061] ------------ +--* LCL_VAR int V08 loc2 [000062] ------------ \--* CNS_INT int 1 fgMorphTree (before 80): [000061] ------------ * LCL_VAR int V08 loc2 fgMorphTree (after 80): [000061] ------------ * LCL_VAR int V08 loc2 fgMorphTree (before 81): [000062] ------------ * CNS_INT int 1 fgMorphTree (after 81): [000062] ------------ * CNS_INT int 1 fgMorphTree (after 79): [000063] ------------ * ADD int [000061] -----+------ +--* LCL_VAR int V08 loc2 [000062] -----+------ \--* CNS_INT int 1 fgMorphTree (after 77): [000065] -A---------- * ASG int [000064] D----+-N---- +--* LCL_VAR int V08 loc2 [000063] -----+------ \--* ADD int [000061] -----+------ +--* LCL_VAR int V08 loc2 [000062] -----+------ \--* CNS_INT int 1 Morphing BB07 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB07, STMT00004 (before) [000019] ------------ * JTRUE void [000018] ------------ \--* LE int [000016] ------------ +--* LCL_VAR int V08 loc2 [000017] ------------ \--* LCL_VAR int V07 loc1 fgMorphTree (before 82): [000019] ------------ * JTRUE void [000018] ------------ \--* LE int [000016] ------------ +--* LCL_VAR int V08 loc2 [000017] ------------ \--* LCL_VAR int V07 loc1 fgMorphTree (before 83): [000018] J------N---- * LE int [000016] ------------ +--* LCL_VAR int V08 loc2 [000017] ------------ \--* LCL_VAR int V07 loc1 fgMorphTree (before 84): [000016] ------------ * LCL_VAR int V08 loc2 fgMorphTree (after 84): [000016] ------------ * LCL_VAR int V08 loc2 fgMorphTree (before 85): [000017] ------------ * LCL_VAR int V07 loc1 fgMorphTree (after 85): [000017] ------------ * LCL_VAR int V07 loc1 fgMorphTree (after 83): [000018] J------N---- * LE int [000016] -----+------ +--* LCL_VAR int V08 loc2 [000017] -----+------ \--* LCL_VAR int V07 loc1 fgMorphTree (after 82): [000019] ------------ * JTRUE void [000018] J----+-N---- \--* LE int [000016] -----+------ +--* LCL_VAR int V08 loc2 [000017] -----+------ \--* LCL_VAR int V07 loc1 Morphing BB08 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB08, STMT00015 (before) [000073] ------------ * RETURN int [000072] ------------ \--* LCL_VAR int V06 loc0 fgMorphTree (before 86): [000073] ------------ * RETURN int [000072] ------------ \--* LCL_VAR int V06 loc0 fgMorphTree (before 87): [000072] ------------ * LCL_VAR int V06 loc0 fgMorphTree (after 87): [000072] ------------ * LCL_VAR int V06 loc0 fgMorphTree (after 86): [000073] ------------ * RETURN int [000072] -----+------ \--* LCL_VAR int V06 loc0 *************** Finishing PHASE Morph - Global Trees after Morph - Global ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 19862. 19862 [000..010)-> BB07 (always) i label target idxlen IBC BB02 [0001] 1 BB07 20988. 20988 [010..036)-> BB04 ( cond ) i label target gcsafe idxlen bwd bwd-target IBC BB03 [0002] 1 BB02 501 501 [036..038) i bwd IBC BB04 [0003] 2 BB02,BB03 20988. 20988 [038..045)-> BB06 ( cond ) i label target gcsafe bwd IBC BB05 [0004] 1 BB04 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 BB04,BB05 20988. 20988 [047..04B) i label target bwd IBC BB07 [0006] 2 BB01,BB06 40850. 40850 [04B..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 1 BB07 19862. 19862 [04F..051) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB07 (always), preds={} succs={BB07} ***** BB01 STMT00001 (IL ???... ???) [000008] -A---+------ * ASG int [000007] D----+-N---- +--* LCL_VAR int V06 loc0 [000006] -----+------ \--* CNS_INT int 1 ***** BB01 STMT00002 (IL ???...0x00B) [000012] -A-XG+------ * ASG int [000011] D----+-N---- +--* LCL_VAR int V07 loc1 [000010] ---XG+------ \--* ADD int [000077] ---XG+------ +--* ARR_LENGTH int [000076] -----+------ | \--* LCL_VAR ref V13 tmp1 [000009] -----+------ \--* CNS_INT int -1 ***** BB01 STMT00003 (IL 0x00C...0x00D) [000015] -A---+------ * ASG int [000014] D----+-N---- +--* LCL_VAR int V08 loc2 [000013] -----+------ \--* CNS_INT int 0 ------------ BB02 [010..036) -> BB04 (cond), preds={BB07} succs={BB03,BB04} ***** BB02 STMT00006 (IL ???... ???) [000028] -A-XG+------ * ASG ref [000027] D----+-N---- +--* LCL_VAR ref V09 loc3 [000100] ---XG+------ \--* COMMA ref [000093] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000022] -----+------ | +--* LCL_VAR int V08 loc2 [000092] ---X-+------ | \--* ARR_LENGTH int [000081] -----+------ | \--* LCL_VAR ref V14 tmp2 [000082] a---G+------ \--* IND ref [000099] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V14 tmp2 [000098] -----+------ \--* ADD long [000096] -----+------ +--* LSH long [000094] -----+------ | +--* CAST long <- int [000091] i----+------ | | \--* LCL_VAR int V08 loc2 [000095] -----+-N---- | \--* CNS_INT long 3 [000097] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB02 STMT00008 (IL ???... ???) [000037] -A-XG+------ * ASG ref [000036] D----+-N---- +--* LCL_VAR ref V10 loc4 [000111] ---XG+------ \--* COMMA ref [000104] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000031] -----+------ | +--* LCL_VAR int V08 loc2 [000103] ---X-+------ | \--* ARR_LENGTH int [000086] -----+------ | \--* LCL_VAR ref V13 tmp1 [000087] a---G+------ \--* IND ref [000110] -----+------ \--* ADD byref [000101] -----+------ +--* LCL_VAR ref V13 tmp1 [000109] -----+------ \--* ADD long [000107] -----+------ +--* LSH long [000105] -----+------ | +--* CAST long <- int [000102] i----+------ | | \--* LCL_VAR int V08 loc2 [000106] -----+-N---- | \--* CNS_INT long 3 [000108] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB02 STMT00009 (IL 0x023...0x024) [000040] -A--G+------ * ASG ref [000039] D---G+-N---- +--* LCL_VAR ref (AX) V11 loc5 [000038] -----+------ \--* CNS_INT ref null ***** BB02 STMT00010 (IL 0x026...0x034) [000052] --CXG+------ * JTRUE void [000051] J-CXG+-N---- \--* NE int [000049] --CXG+------ +--* CAST int <- bool <- int [000048] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000047] -----+------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 [000041] -----+------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 [000042] -----+------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 [000043] -----+------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 [000044] -----+------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 [000045] -----+------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 [000050] -----+------ \--* CNS_INT int 0 ------------ BB03 [036..038), preds={BB02} succs={BB04} ***** BB03 STMT00014 (IL 0x036...0x037) [000071] -A---+------ * ASG int [000070] D----+-N---- +--* LCL_VAR int V06 loc0 [000069] -----+------ \--* CNS_INT int 0 ------------ BB04 [038..045) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00011 (IL 0x038...0x043) [000060] --CXG+------ * JTRUE void [000059] J-CXG+-N---- \--* EQ int [000057] --CXG+------ +--* CAST int <- bool <- int [000056] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics [000053] ----G+------ arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 [000054] -----+------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 [000055] -----+------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 [000058] -----+------ \--* CNS_INT int 0 ------------ BB05 [045..047), preds={BB04} succs={BB06} ***** BB05 STMT00013 (IL 0x045...0x046) [000068] -A---+------ * ASG int [000067] D----+-N---- +--* LCL_VAR int V06 loc0 [000066] -----+------ \--* CNS_INT int 0 ------------ BB06 [047..04B), preds={BB04,BB05} succs={BB07} ***** BB06 STMT00012 (IL 0x047...0x04A) [000065] -A---+------ * ASG int [000064] D----+-N---- +--* LCL_VAR int V08 loc2 [000063] -----+------ \--* ADD int [000061] -----+------ +--* LCL_VAR int V08 loc2 [000062] -----+------ \--* CNS_INT int 1 ------------ BB07 [04B..04F) -> BB02 (cond), preds={BB01,BB06} succs={BB08,BB02} ***** BB07 STMT00004 (IL 0x04B...0x04D) [000019] -----+------ * JTRUE void [000018] J----+-N---- \--* LE int [000016] -----+------ +--* LCL_VAR int V08 loc2 [000017] -----+------ \--* LCL_VAR int V07 loc1 ------------ BB08 [04F..051) (return), preds={BB07} succs={} ***** BB08 STMT00015 (IL 0x04F...0x050) [000073] -----+------ * RETURN int [000072] -----+------ \--* LCL_VAR int V06 loc0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie *************** Starting PHASE Mark GC poll blocks *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 19862. 19862 [000..010)-> BB07 (always) i label target idxlen IBC BB02 [0001] 1 BB07 20988. 20988 [010..036)-> BB04 ( cond ) i label target gcsafe idxlen bwd bwd-target IBC BB03 [0002] 1 BB02 501 501 [036..038) i bwd IBC BB04 [0003] 2 BB02,BB03 20988. 20988 [038..045)-> BB06 ( cond ) i label target gcsafe bwd IBC BB05 [0004] 1 BB04 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 BB04,BB05 20988. 20988 [047..04B) i label target bwd IBC BB07 [0006] 2 BB01,BB06 40850. 40850 [04B..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 1 BB07 19862. 19862 [04F..051) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! *************** Finishing PHASE Mark GC poll blocks *************** Starting PHASE Compute edge weights (1, false) *************** In fgComputeBlockAndEdgeWeights() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 198.62 19862 [000..010)-> BB07 (always) i label target idxlen IBC BB02 [0001] 1 BB07 209.88 20988 [010..036)-> BB04 ( cond ) i label target gcsafe idxlen bwd bwd-target IBC BB03 [0002] 1 BB02 5.01 501 [036..038) i bwd IBC BB04 [0003] 2 BB02,BB03 209.88 20988 [038..045)-> BB06 ( cond ) i label target gcsafe bwd IBC BB05 [0004] 1 BB04 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 BB04,BB05 209.88 20988 [047..04B) i label target bwd IBC BB07 [0006] 2 BB01,BB06 408.50 40850 [04B..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 1 BB07 198.62 19862 [04F..051) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- We are using the Profile Weights and fgCalledCount is 19862. fgComputeEdgeWeights() was able to compute exact edge weights for all of the 10 edges, using 1 passes. Edge weights into BB02 :BB07 (20988) Edge weights into BB03 :BB02 (501) Edge weights into BB04 :BB02 (20487), BB03 (501) Edge weights into BB05 :BB04 (0) Edge weights into BB06 :BB04 (20988), BB05 (0) Edge weights into BB07 :BB01 (19862), BB06 (20988) Edge weights into BB08 :BB07 (19862) *************** Finishing PHASE Compute edge weights (1, false) *************** Starting PHASE Create EH funclets *************** In fgCreateFunclets() After fgCreateFunclets() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB07 (always) i label target idxlen IBC BB02 [0001] 1 BB07 1.06 20988 [010..036)-> BB04 ( cond ) i label target gcsafe idxlen bwd bwd-target IBC BB03 [0002] 1 BB02 0.03 501 [036..038) i bwd IBC BB04 [0003] 2 BB02,BB03 1.06 20988 [038..045)-> BB06 ( cond ) i label target gcsafe bwd IBC BB05 [0004] 1 BB04 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 BB04,BB05 1.06 20988 [047..04B) i label target bwd IBC BB07 [0006] 2 BB01,BB06 2.06 40850 [04B..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 1 BB07 1 19862 [04F..051) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Create EH funclets *************** Starting PHASE Optimize layout *************** In optOptimizeLayout() *************** Exception Handling table is empty *************** In fgDebugCheckBBlist Duplication of loop condition [000018] is performed, because the cost of duplication (5) is less or equal than 32, loopIterations = 1.057, countOfHelpers = 0, validProfileWeights = true Duplicating loop condition in BB01 for loop (BB02 - BB07) Estimated code size expansion is 5 STMT00016 (IL 0x04B... ???) [000127] ------------ * JTRUE void ( 7, 5) [000124] J------N---- \--* GT int ( 3, 2) [000125] ------------ +--* LCL_VAR int V08 loc2 ( 3, 2) [000126] ------------ \--* LCL_VAR int V07 loc1 fgComputeEdgeWeights() was able to compute exact edge weights for 7 of the 11 edges, using 2 passes. Edge weights into BB02 :BB01 (0..19862), BB07 (1126..20988) Edge weights into BB03 :BB02 (501) Edge weights into BB04 :BB02 (20487), BB03 (501) Edge weights into BB05 :BB04 (0) Edge weights into BB06 :BB04 (20988), BB05 (0) Edge weights into BB07 :BB06 (20988) Edge weights into BB08 :BB01 (0..19862), BB07 (0..19862) *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB08 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB07 1.06 20988 [010..036)-> BB04 ( cond ) i label target gcsafe idxlen bwd bwd-target IBC BB03 [0002] 1 BB02 0.03 501 [036..038) i bwd IBC BB04 [0003] 2 BB02,BB03 1.06 20988 [038..045)-> BB06 ( cond ) i label target gcsafe bwd IBC BB05 [0004] 1 BB04 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 BB04,BB05 1.06 20988 [047..04B) i label target bwd IBC BB07 [0006] 1 BB06 1.06 20988 [04B..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 2 BB01,BB07 1 19862 [04F..051) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB06 and BB07: *************** In fgDebugCheckBBlist After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB08 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB06 1.06 20988 [010..036)-> BB04 ( cond ) i label target gcsafe idxlen bwd bwd-target IBC BB03 [0002] 1 BB02 0.03 501 [036..038) i bwd IBC BB04 [0003] 2 BB02,BB03 1.06 20988 [038..045)-> BB06 ( cond ) i label target gcsafe bwd IBC BB05 [0004] 1 BB04 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 BB04,BB05 1.06 20988 [047..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 2 BB01,BB06 1 19862 [04F..051) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB08 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB06 1.06 20988 [010..036)-> BB04 ( cond ) i label target gcsafe idxlen bwd bwd-target IBC BB03 [0002] 1 BB02 0.03 501 [036..038) i bwd IBC BB04 [0003] 2 BB02,BB03 1.06 20988 [038..045)-> BB06 ( cond ) i label target gcsafe bwd IBC BB05 [0004] 1 BB04 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 BB04,BB05 1.06 20988 [047..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 2 BB01,BB06 1 19862 [04F..051) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB02 branch to BB04 because of IBC profile data fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB04, jumpBlk=BB00, runRarely=false) Relocated uncommon block BB03 by reversing conditional jump at BB02 Relocated block [BB03..BB03] inserted after BB08 at the end of method Block BB03 ended with a BBJ_NONE, Changed to an unconditional jump to BB04 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB08 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB06 1.06 20988 [010..036)-> BB03 ( cond ) i label target gcsafe idxlen bwd bwd-target IBC BB04 [0003] 2 BB02,BB03 1.06 20988 [038..045)-> BB06 ( cond ) i label target gcsafe bwd IBC BB05 [0004] 1 BB04 0 0 [045..047) i rare bwd IBC BB06 [0005] 2 BB04,BB05 1.06 20988 [047..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 2 BB01,BB06 1 19862 [04F..051) (return) i label target IBC BB03 [0002] 1 BB02 0.03 501 [036..038)-> BB04 (always) i label target bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB04 branch to BB06 because of IBC profile data Relocated rarely run block BB05 by reversing conditional jump at BB04 Relocated block [BB05..BB05] inserted after BB03 at the end of method Block BB05 ended with a BBJ_NONE, Changed to an unconditional jump to BB06 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB08 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB06 1.06 20988 [010..036)-> BB03 ( cond ) i label target gcsafe idxlen bwd bwd-target IBC BB04 [0003] 2 BB02,BB03 1.06 20988 [038..045)-> BB05 ( cond ) i label target gcsafe bwd IBC BB06 [0005] 2 BB04,BB05 1.06 20988 [047..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 2 BB01,BB06 1 19862 [04F..051) (return) i label target IBC BB03 [0002] 1 BB02 0.03 501 [036..038)-> BB04 (always) i label target bwd IBC BB05 [0004] 1 BB04 0 0 [045..047)-> BB06 (always) i rare label target bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- Duplication of the conditional block BB04 (always branch from BB03) not done, because the cost of duplication (20) is greater than 12, validProfileWeights = true *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB08 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB06 1.06 20988 [010..036)-> BB03 ( cond ) i label target gcsafe idxlen bwd bwd-target IBC BB04 [0003] 2 BB02,BB03 1.06 20988 [038..045)-> BB05 ( cond ) i label target gcsafe bwd IBC BB06 [0005] 2 BB04,BB05 1.06 20988 [047..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 2 BB01,BB06 1 19862 [04F..051) (return) i label target IBC BB03 [0002] 1 BB02 0.03 501 [036..038)-> BB04 (always) i label target bwd IBC BB05 [0004] 1 BB04 0 0 [045..047)-> BB06 (always) i rare label target bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize layout *************** Starting PHASE Compute blocks reachability *************** In fgComputeReachability *************** In fgDebugCheckBBlist Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB08 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB06 1.06 20988 [010..036)-> BB03 ( cond ) i label target gcsafe idxlen bwd bwd-target IBC BB04 [0003] 2 BB02,BB03 1.06 20988 [038..045)-> BB05 ( cond ) i label target gcsafe bwd IBC BB06 [0005] 2 BB04,BB05 1.06 20988 [047..04F)-> BB02 ( cond ) i label target bwd IBC BB08 [0007] 2 BB01,BB06 1 19862 [04F..051) (return) i label target IBC BB03 [0002] 1 BB02 0.03 501 [036..038)-> BB04 (always) i label target bwd IBC BB05 [0004] 1 BB04 0 0 [045..047)-> BB06 (always) i rare label target bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB04 to BB03 Renumber BB06 to BB04 Renumber BB08 to BB05 Renumber BB03 to BB06 Renumber BB05 to BB07 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i label target gcsafe idxlen bwd bwd-target IBC BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i label target gcsafe bwd IBC BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i label target bwd IBC BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target bwd IBC BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 3, # of blocks (including unused BB00): 8, bitset array size: 1 (short) Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 BB03 BB04 BB06 BB07 BB03 : BB01 BB02 BB03 BB04 BB06 BB07 BB04 : BB01 BB02 BB03 BB04 BB06 BB07 BB05 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB06 : BB01 BB02 BB03 BB04 BB06 BB07 BB07 : BB01 BB02 BB03 BB04 BB06 BB07 After computing reachability: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeDoms *************** In fgDebugCheckBBlist Dominator computation start blocks (those blocks with no incoming edges): BB01 ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB01: BB01 BB02: BB02 BB01 BB03: BB03 BB02 BB01 BB04: BB04 BB03 BB02 BB01 BB07: BB07 BB03 BB02 BB01 BB06: BB06 BB02 BB01 BB05: BB05 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB05 BB02 BB02 : BB06 BB03 BB03 : BB07 BB04 After numbering the dominator tree: BB01: pre=01, post=07 BB02: pre=03, post=06 BB03: pre=05, post=05 BB04: pre=07, post=04 BB05: pre=02, post=01 BB06: pre=04, post=02 BB07: pre=06, post=03 *************** Finishing PHASE Compute blocks reachability *************** Starting PHASE Optimize loops *************** In optOptimizeLoops() *************** In fgDebugCheckBBlist *************** In optFindNaturalLoops() Marking a loop from BB02 to BB04 BB02(wt=1.06) BB03(wt=1.06) BB04(wt=1.06) Marking a loop from BB03 to BB06 BB03(wt=1.06) BB04(wt=1.06) BB06(wt=0.03) Marking a loop from BB04 to BB07 BB04(wt=1.06) BB06(wt=0.03) Found a total of 3 loops. After loop weight marking: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Optimize loops *************** Starting PHASE Clone loops *************** In optCloneLoops() *************** Finishing PHASE Clone loops *************** Starting PHASE Unroll loops *************** Finishing PHASE Unroll loops *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** *** marking local variables in block BB01 (weight=1 ) STMT00001 (IL ???... ???) [000008] -A---+------ * ASG int [000007] D----+-N---- +--* LCL_VAR int V06 loc0 [000006] -----+------ \--* CNS_INT int 1 New refCnts for V06: refCnt = 1, refCntWtd = 1 STMT00002 (IL ???...0x00B) [000012] -A-XG+------ * ASG int [000011] D----+-N---- +--* LCL_VAR int V07 loc1 [000010] ---XG+------ \--* ADD int [000077] ---XG+------ +--* ARR_LENGTH int [000076] -----+------ | \--* LCL_VAR ref V13 tmp1 [000009] -----+------ \--* CNS_INT int -1 New refCnts for V07: refCnt = 1, refCntWtd = 1 New refCnts for V13: refCnt = 1, refCntWtd = 1 STMT00003 (IL 0x00C...0x00D) [000015] -A---+------ * ASG int [000014] D----+-N---- +--* LCL_VAR int V08 loc2 [000013] -----+------ \--* CNS_INT int 0 New refCnts for V08: refCnt = 1, refCntWtd = 1 STMT00016 (IL 0x04B... ???) [000127] ------------ * JTRUE void ( 7, 5) [000124] J------N---- \--* GT int ( 3, 2) [000125] ------------ +--* LCL_VAR int V08 loc2 ( 3, 2) [000126] ------------ \--* LCL_VAR int V07 loc1 New refCnts for V08: refCnt = 2, refCntWtd = 2 New refCnts for V07: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB02 (weight=1.06) STMT00006 (IL ???... ???) [000028] -A-XG+------ * ASG ref [000027] D----+-N---- +--* LCL_VAR ref V09 loc3 [000100] ---XG+------ \--* COMMA ref [000093] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000022] -----+------ | +--* LCL_VAR int V08 loc2 [000092] ---X-+------ | \--* ARR_LENGTH int [000081] -----+------ | \--* LCL_VAR ref V14 tmp2 [000082] a---G+------ \--* IND ref [000099] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V14 tmp2 [000098] -----+------ \--* ADD long [000096] -----+------ +--* LSH long [000094] -----+------ | +--* CAST long <- int [000091] i----+------ | | \--* LCL_VAR int V08 loc2 [000095] -----+-N---- | \--* CNS_INT long 3 [000097] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] New refCnts for V09: refCnt = 1, refCntWtd = 1.06 New refCnts for V08: refCnt = 3, refCntWtd = 3.06 New refCnts for V14: refCnt = 1, refCntWtd = 1.06 New refCnts for V14: refCnt = 2, refCntWtd = 2.12 New refCnts for V08: refCnt = 4, refCntWtd = 4.12 STMT00008 (IL ???... ???) [000037] -A-XG+------ * ASG ref [000036] D----+-N---- +--* LCL_VAR ref V10 loc4 [000111] ---XG+------ \--* COMMA ref [000104] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000031] -----+------ | +--* LCL_VAR int V08 loc2 [000103] ---X-+------ | \--* ARR_LENGTH int [000086] -----+------ | \--* LCL_VAR ref V13 tmp1 [000087] a---G+------ \--* IND ref [000110] -----+------ \--* ADD byref [000101] -----+------ +--* LCL_VAR ref V13 tmp1 [000109] -----+------ \--* ADD long [000107] -----+------ +--* LSH long [000105] -----+------ | +--* CAST long <- int [000102] i----+------ | | \--* LCL_VAR int V08 loc2 [000106] -----+-N---- | \--* CNS_INT long 3 [000108] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] New refCnts for V10: refCnt = 1, refCntWtd = 1.06 New refCnts for V08: refCnt = 5, refCntWtd = 5.18 New refCnts for V13: refCnt = 2, refCntWtd = 2.06 New refCnts for V13: refCnt = 3, refCntWtd = 3.12 New refCnts for V08: refCnt = 6, refCntWtd = 6.24 STMT00009 (IL 0x023...0x024) [000040] -A--G+------ * ASG ref [000039] D---G+-N---- +--* LCL_VAR ref (AX) V11 loc5 [000038] -----+------ \--* CNS_INT ref null New refCnts for V11: refCnt = 1, refCntWtd = 1.06 STMT00010 (IL 0x026...0x034) [000052] --CXG+------ * JTRUE void [000051] J-CXG+-N---- \--* EQ int [000049] --CXG+------ +--* CAST int <- bool <- int [000048] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints [000047] -----+------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 [000041] -----+------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 [000042] -----+------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 [000043] -----+------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 [000044] -----+------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 [000045] -----+------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 [000050] -----+------ \--* CNS_INT int 0 New refCnts for V11: refCnt = 2, refCntWtd = 2.12 New refCnts for V00: refCnt = 1, refCntWtd = 1.06 New refCnts for V01: refCnt = 1, refCntWtd = 1.06 New refCnts for V10: refCnt = 2, refCntWtd = 2.12 New refCnts for V09: refCnt = 2, refCntWtd = 2.12 New refCnts for V04: refCnt = 1, refCntWtd = 1.06 *** marking local variables in block BB03 (weight=1.06) STMT00011 (IL 0x038...0x043) ( 28, 20) [000060] --CXG------- * JTRUE void ( 26, 18) [000059] J-CXG--N---- \--* NE int ( 24, 16) [000057] --CXG------- +--* CAST int <- bool <- int ( 23, 14) [000056] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics ( 3, 2) [000053] ----G------- arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 ( 3, 2) [000054] ------------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 ( 3, 2) [000055] ------------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 ( 1, 1) [000058] ------------ \--* CNS_INT int 0 New refCnts for V11: refCnt = 3, refCntWtd = 3.18 New refCnts for V10: refCnt = 3, refCntWtd = 3.18 New refCnts for V05: refCnt = 1, refCntWtd = 1.06 *** marking local variables in block BB04 (weight=1.06) STMT00012 (IL 0x047...0x04A) [000065] -A---+------ * ASG int [000064] D----+-N---- +--* LCL_VAR int V08 loc2 [000063] -----+------ \--* ADD int [000061] -----+------ +--* LCL_VAR int V08 loc2 [000062] -----+------ \--* CNS_INT int 1 New refCnts for V08: refCnt = 7, refCntWtd = 7.30 New refCnts for V08: refCnt = 8, refCntWtd = 8.36 STMT00004 (IL 0x04B...0x04D) [000019] -----+------ * JTRUE void ( 7, 5) [000018] J------N---- \--* LE int ( 3, 2) [000016] ------------ +--* LCL_VAR int V08 loc2 ( 3, 2) [000017] ------------ \--* LCL_VAR int V07 loc1 New refCnts for V08: refCnt = 9, refCntWtd = 9.42 New refCnts for V07: refCnt = 3, refCntWtd = 3.06 *** marking local variables in block BB05 (weight=1 ) STMT00015 (IL 0x04F...0x050) [000073] -----+------ * RETURN int [000072] -----+------ \--* LCL_VAR int V06 loc0 New refCnts for V06: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB06 (weight=0.03) STMT00014 (IL 0x036...0x037) [000071] -A---+------ * ASG int [000070] D----+-N---- +--* LCL_VAR int V06 loc0 [000069] -----+------ \--* CNS_INT int 0 New refCnts for V06: refCnt = 3, refCntWtd = 2.03 *** marking local variables in block BB07 (weight=0 ) STMT00013 (IL 0x045...0x046) [000068] -A---+------ * ASG int [000067] D----+-N---- +--* LCL_VAR int V06 loc0 [000066] -----+------ \--* CNS_INT int 0 New refCnts for V06: refCnt = 4, refCntWtd = 2.03 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 2, refCntWtd = 2.06 New refCnts for V00: refCnt = 3, refCntWtd = 3.06 New refCnts for V01: refCnt = 2, refCntWtd = 2.06 New refCnts for V01: refCnt = 3, refCntWtd = 3.06 New refCnts for V04: refCnt = 2, refCntWtd = 2.06 New refCnts for V04: refCnt = 3, refCntWtd = 3.06 New refCnts for V05: refCnt = 2, refCntWtd = 2.06 New refCnts for V05: refCnt = 3, refCntWtd = 3.06 New refCnts for V13: refCnt = 4, refCntWtd = 4.12 New refCnts for V14: refCnt = 3, refCntWtd = 3.12 *************** In optAddCopies() *************** Finishing PHASE Mark local vars *************** Starting PHASE Optimize bools *************** In optOptimizeBools() *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize bools *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order *************** Starting PHASE Set block order *************** In fgSetBlockOrder() fgMarkLoopHead: Checking loop head block BB02: this block will execute a call fgMarkLoopHead: Checking loop head block BB03: this block will execute a call fgMarkLoopHead: Checking loop head block BB04: this block will execute a call The biggest BB has 17 tree nodes *************** Finishing PHASE Set block order Trees before Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00001 (IL ???... ???) N003 ( 5, 4) [000008] -A------R--- * ASG int N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR int V06 loc0 N001 ( 1, 1) [000006] ------------ \--* CNS_INT int 1 ***** BB01 STMT00002 (IL ???...0x00B) N006 ( 5, 5) [000012] -A-XG---R--- * ASG int N005 ( 1, 1) [000011] D------N---- +--* LCL_VAR int V07 loc1 N004 ( 5, 5) [000010] ---XG------- \--* ADD int N002 ( 3, 3) [000077] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR ref V13 tmp1 N003 ( 1, 1) [000009] ------------ \--* CNS_INT int -1 ***** BB01 STMT00003 (IL 0x00C...0x00D) N003 ( 1, 3) [000015] -A------R--- * ASG int N002 ( 1, 1) [000014] D------N---- +--* LCL_VAR int V08 loc2 N001 ( 1, 1) [000013] ------------ \--* CNS_INT int 0 ***** BB01 STMT00016 (IL 0x04B... ???) N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* GT int N001 ( 1, 1) [000125] ------------ +--* LCL_VAR int V08 loc2 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} ***** BB02 STMT00006 (IL ???... ???) N016 ( 18, 21) [000028] -A-XG---R--- * ASG ref N015 ( 3, 2) [000027] D------N---- +--* LCL_VAR ref V09 loc3 N014 ( 14, 18) [000100] ---XG------- \--* COMMA ref N004 ( 8, 11) [000093] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR int V08 loc2 N003 ( 3, 3) [000092] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000081] ------------ | \--* LCL_VAR ref V14 tmp2 N013 ( 6, 7) [000082] a---G------- \--* IND ref N012 ( 5, 6) [000099] -------N---- \--* ADD byref N005 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V14 tmp2 N011 ( 4, 5) [000098] -------N---- \--* ADD long N009 ( 3, 4) [000096] -------N---- +--* LSH long N007 ( 2, 3) [000094] ------------ | +--* CAST long <- int N006 ( 1, 1) [000091] i----------- | | \--* LCL_VAR int V08 loc2 N008 ( 1, 1) [000095] -------N---- | \--* CNS_INT long 3 N010 ( 1, 1) [000097] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB02 STMT00008 (IL ???... ???) N016 ( 14, 18) [000037] -A-XG---R--- * ASG ref N015 ( 1, 1) [000036] D------N---- +--* LCL_VAR ref V10 loc4 N014 ( 14, 18) [000111] ---XG------- \--* COMMA ref N004 ( 8, 11) [000104] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000031] ------------ | +--* LCL_VAR int V08 loc2 N003 ( 3, 3) [000103] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000086] ------------ | \--* LCL_VAR ref V13 tmp1 N013 ( 6, 7) [000087] a---G------- \--* IND ref N012 ( 5, 6) [000110] -------N---- \--* ADD byref N005 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 N011 ( 4, 5) [000109] -------N---- \--* ADD long N009 ( 3, 4) [000107] -------N---- +--* LSH long N007 ( 2, 3) [000105] ------------ | +--* CAST long <- int N006 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 N008 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 N010 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB02 STMT00009 (IL 0x023...0x024) N003 ( 5, 4) [000040] -A--G---R--- * ASG ref N002 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V11 loc5 N001 ( 1, 1) [000038] ------------ \--* CNS_INT ref null ***** BB02 STMT00010 (IL 0x026...0x034) N017 ( 29, 26) [000052] --CXG------- * JTRUE void N016 ( 27, 24) [000051] J-CXG--N---- \--* EQ int N014 ( 25, 22) [000049] --CXG------- +--* CAST int <- bool <- int N013 ( 24, 20) [000048] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints N007 ( 3, 3) [000047] ------------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 N008 ( 1, 1) [000041] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 N009 ( 1, 1) [000042] ------------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 N010 ( 1, 1) [000043] ------------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 N011 ( 3, 2) [000044] ------------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 N012 ( 1, 1) [000045] ------------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 N015 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} ***** BB03 STMT00011 (IL 0x038...0x043) N011 ( 24, 18) [000060] --CXG------- * JTRUE void N010 ( 22, 16) [000059] J-CXG--N---- \--* NE int N008 ( 20, 14) [000057] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000056] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics N004 ( 3, 2) [000053] ----G------- arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 N005 ( 1, 1) [000054] ------------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 N006 ( 1, 1) [000055] ------------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 N009 ( 1, 1) [000058] ------------ \--* CNS_INT int 0 ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} ***** BB04 STMT00012 (IL 0x047...0x04A) N005 ( 3, 3) [000065] -A------R--- * ASG int N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 N003 ( 3, 3) [000063] ------------ \--* ADD int N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 ***** BB04 STMT00004 (IL 0x04B...0x04D) N004 ( 5, 5) [000019] ------------ * JTRUE void N003 ( 3, 3) [000018] J------N---- \--* LE int N001 ( 1, 1) [000016] ------------ +--* LCL_VAR int V08 loc2 N002 ( 1, 1) [000017] ------------ \--* LCL_VAR int V07 loc1 ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} ***** BB05 STMT00015 (IL 0x04F...0x050) N002 ( 4, 3) [000073] ------------ * RETURN int N001 ( 3, 2) [000072] ------------ \--* LCL_VAR int V06 loc0 ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} ***** BB06 STMT00014 (IL 0x036...0x037) N003 ( 5, 4) [000071] -A------R--- * ASG int N002 ( 3, 2) [000070] D------N---- +--* LCL_VAR int V06 loc0 N001 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} ***** BB07 STMT00013 (IL 0x045...0x046) N003 ( 5, 4) [000068] -A------R--- * ASG int N002 ( 3, 2) [000067] D------N---- +--* LCL_VAR int V06 loc0 N001 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Build SSA representation *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 8. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB05 BB02 BB02 : BB06 BB03 BB03 : BB07 BB04 *************** In fgLocalVarLiveness() In fgLocalVarLivenessInit Tracked variable (11 out of 15) table: V08 loc2 [ int]: refCnt = 9, refCntWtd = 9.42 V13 tmp1 [ ref]: refCnt = 4, refCntWtd = 4.12 V14 tmp2 [ ref]: refCnt = 3, refCntWtd = 3.12 V00 arg0 [ ref]: refCnt = 3, refCntWtd = 3.06 V01 arg1 [ ref]: refCnt = 3, refCntWtd = 3.06 V04 arg4 [ ref]: refCnt = 3, refCntWtd = 3.06 V05 arg5 [ byref]: refCnt = 3, refCntWtd = 3.06 V10 loc4 [ ref]: refCnt = 3, refCntWtd = 3.18 V07 loc1 [ int]: refCnt = 3, refCntWtd = 3.06 V09 loc3 [ ref]: refCnt = 2, refCntWtd = 2.12 V06 loc0 [ bool]: refCnt = 4, refCntWtd = 2.03 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={ V13 } DEF(3)={V08 V07 V06} BB02 USE(6)={V08 V13 V14 V00 V01 V04 } + ByrefExposed + GcHeap DEF(2)={ V10 V09} + ByrefExposed* + GcHeap* BB03 USE(2)={V05 V10} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB04 USE(2)={V08 V07} DEF(1)={V08 } BB05 USE(1)={V06} DEF(0)={ } BB06 USE(0)={ } DEF(1)={V06} BB07 USE(0)={ } DEF(1)={V06} ** Memory liveness computed, GcHeap states and ByrefExposed states diverge *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (6)={ V13 V14 V00 V01 V04 V05 } + ByrefExposed + GcHeap OUT(9)={V08 V13 V14 V00 V01 V04 V05 V07 V06} + ByrefExposed + GcHeap BB02 IN (9)={V08 V13 V14 V00 V01 V04 V05 V07 V06} + ByrefExposed + GcHeap OUT(10)={V08 V13 V14 V00 V01 V04 V05 V10 V07 V06} + ByrefExposed + GcHeap BB03 IN (10)={V08 V13 V14 V00 V01 V04 V05 V10 V07 V06} + ByrefExposed + GcHeap OUT(9)={V08 V13 V14 V00 V01 V04 V05 V07 V06} + ByrefExposed + GcHeap BB04 IN (9)={V08 V13 V14 V00 V01 V04 V05 V07 V06} + ByrefExposed + GcHeap OUT(9)={V08 V13 V14 V00 V01 V04 V05 V07 V06} + ByrefExposed + GcHeap BB05 IN (1)={V06} OUT(0)={ } BB06 IN (9)={V08 V13 V14 V00 V01 V04 V05 V10 V07 } + ByrefExposed + GcHeap OUT(10)={V08 V13 V14 V00 V01 V04 V05 V10 V07 V06} + ByrefExposed + GcHeap BB07 IN (8)={V08 V13 V14 V00 V01 V04 V05 V07 } + ByrefExposed + GcHeap OUT(9)={V08 V13 V14 V00 V01 V04 V05 V07 V06} + ByrefExposed + GcHeap *************** In SsaBuilder::InsertPhiFunctions() Inserting phi functions: Added PHI definition for V08 at start of BB02. Added PHI definition for V06 at start of BB04. Added PHI definition for V06 at start of BB05. Added PHI definition for V06 at start of BB02. Inserting phi definition for ByrefExposed at start of BB02. Inserting phi definition for GcHeap at start of BB02. Added PHI definition for V06 at start of BB03. *************** In SsaBuilder::RenameVariables() After fgSsaBuild: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00001 (IL ???... ???) N003 ( 5, 4) [000008] -A------R--- * ASG int N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000006] ------------ \--* CNS_INT int 1 ***** BB01 STMT00002 (IL ???...0x00B) N006 ( 5, 5) [000012] -A-XG---R--- * ASG int N005 ( 1, 1) [000011] D------N---- +--* LCL_VAR int V07 loc1 d:2 N004 ( 5, 5) [000010] ---XG------- \--* ADD int N002 ( 3, 3) [000077] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 N003 ( 1, 1) [000009] ------------ \--* CNS_INT int -1 ***** BB01 STMT00003 (IL 0x00C...0x00D) N003 ( 1, 3) [000015] -A------R--- * ASG int N002 ( 1, 1) [000014] D------N---- +--* LCL_VAR int V08 loc2 d:2 N001 ( 1, 1) [000013] ------------ \--* CNS_INT int 0 ***** BB01 STMT00016 (IL 0x04B... ???) N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* GT int N001 ( 1, 1) [000125] ------------ +--* LCL_VAR int V08 loc2 u:2 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} ***** BB02 STMT00020 (IL ???... ???) N005 ( 0, 0) [000139] -A------R--- * ASG bool N004 ( 0, 0) [000137] D------N---- +--* LCL_VAR bool V06 loc0 d:4 N003 ( 0, 0) [000138] ------------ \--* PHI bool N001 ( 0, 0) [000151] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 ***** BB02 STMT00017 (IL ???... ???) N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 ***** BB02 STMT00006 (IL ???... ???) N016 ( 18, 21) [000028] -A-XG---R--- * ASG ref N015 ( 3, 2) [000027] D------N---- +--* LCL_VAR ref V09 loc3 d:2 N014 ( 14, 18) [000100] ---XG------- \--* COMMA ref N004 ( 8, 11) [000093] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR int V08 loc2 u:3 N003 ( 3, 3) [000092] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000081] ------------ | \--* LCL_VAR ref V14 tmp2 u:1 N013 ( 6, 7) [000082] a---G------- \--* IND ref N012 ( 5, 6) [000099] -------N---- \--* ADD byref N005 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V14 tmp2 u:1 N011 ( 4, 5) [000098] -------N---- \--* ADD long N009 ( 3, 4) [000096] -------N---- +--* LSH long N007 ( 2, 3) [000094] ------------ | +--* CAST long <- int N006 ( 1, 1) [000091] i----------- | | \--* LCL_VAR int V08 loc2 u:3 N008 ( 1, 1) [000095] -------N---- | \--* CNS_INT long 3 N010 ( 1, 1) [000097] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB02 STMT00008 (IL ???... ???) N016 ( 14, 18) [000037] -A-XG---R--- * ASG ref N015 ( 1, 1) [000036] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N014 ( 14, 18) [000111] ---XG------- \--* COMMA ref N004 ( 8, 11) [000104] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000031] ------------ | +--* LCL_VAR int V08 loc2 u:3 N003 ( 3, 3) [000103] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000086] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 N013 ( 6, 7) [000087] a---G------- \--* IND ref N012 ( 5, 6) [000110] -------N---- \--* ADD byref N005 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 u:1 N011 ( 4, 5) [000109] -------N---- \--* ADD long N009 ( 3, 4) [000107] -------N---- +--* LSH long N007 ( 2, 3) [000105] ------------ | +--* CAST long <- int N006 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 u:3 N008 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 N010 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB02 STMT00009 (IL 0x023...0x024) N003 ( 5, 4) [000040] -A--G---R--- * ASG ref N002 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V11 loc5 N001 ( 1, 1) [000038] ------------ \--* CNS_INT ref null ***** BB02 STMT00010 (IL 0x026...0x034) N017 ( 29, 26) [000052] --CXG------- * JTRUE void N016 ( 27, 24) [000051] J-CXG--N---- \--* EQ int N014 ( 25, 22) [000049] --CXG------- +--* CAST int <- bool <- int N013 ( 24, 20) [000048] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints N007 ( 3, 3) [000047] ------------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 N008 ( 1, 1) [000041] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 N009 ( 1, 1) [000042] ------------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 u:1 N010 ( 1, 1) [000043] ------------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 u:1 N015 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} ***** BB03 STMT00021 (IL ???... ???) N005 ( 0, 0) [000142] -A------R--- * ASG bool N004 ( 0, 0) [000140] D------N---- +--* LCL_VAR bool V06 loc0 d:6 N003 ( 0, 0) [000141] ------------ \--* PHI bool N001 ( 0, 0) [000147] ------------ pred BB06 +--* PHI_ARG bool V06 loc0 u:5 N002 ( 0, 0) [000146] ------------ pred BB02 \--* PHI_ARG bool V06 loc0 u:4 ***** BB03 STMT00011 (IL 0x038...0x043) N011 ( 24, 18) [000060] --CXG------- * JTRUE void N010 ( 22, 16) [000059] J-CXG--N---- \--* NE int N008 ( 20, 14) [000057] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000056] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics N004 ( 3, 2) [000053] ----G------- arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 N005 ( 1, 1) [000054] ------------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 u:1 N009 ( 1, 1) [000058] ------------ \--* CNS_INT int 0 ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} ***** BB04 STMT00018 (IL ???... ???) N005 ( 0, 0) [000133] -A------R--- * ASG bool N004 ( 0, 0) [000131] D------N---- +--* LCL_VAR bool V06 loc0 d:8 N003 ( 0, 0) [000132] ------------ \--* PHI bool N001 ( 0, 0) [000149] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:7 N002 ( 0, 0) [000148] ------------ pred BB03 \--* PHI_ARG bool V06 loc0 u:6 ***** BB04 STMT00012 (IL 0x047...0x04A) N005 ( 3, 3) [000065] -A------R--- * ASG int N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 N003 ( 3, 3) [000063] ------------ \--* ADD int N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 ***** BB04 STMT00004 (IL 0x04B...0x04D) N004 ( 5, 5) [000019] ------------ * JTRUE void N003 ( 3, 3) [000018] J------N---- \--* LE int N001 ( 1, 1) [000016] ------------ +--* LCL_VAR int V08 loc2 u:4 N002 ( 1, 1) [000017] ------------ \--* LCL_VAR int V07 loc1 u:2 ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} ***** BB05 STMT00019 (IL ???... ???) N005 ( 0, 0) [000136] -A------R--- * ASG bool N004 ( 0, 0) [000134] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000135] ------------ \--* PHI bool N001 ( 0, 0) [000150] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 ***** BB05 STMT00015 (IL 0x04F...0x050) N002 ( 4, 3) [000073] ------------ * RETURN int N001 ( 3, 2) [000072] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} ***** BB06 STMT00014 (IL 0x036...0x037) N003 ( 5, 4) [000071] -A------R--- * ASG int N002 ( 3, 2) [000070] D------N---- +--* LCL_VAR int V06 loc0 d:5 N001 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} ***** BB07 STMT00013 (IL 0x045...0x046) N003 ( 5, 4) [000068] -A------R--- * ASG int N002 ( 3, 2) [000067] D------N---- +--* LCL_VAR int V06 loc0 d:7 N001 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Build SSA representation Trees after Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00001 (IL ???... ???) N003 ( 5, 4) [000008] -A------R--- * ASG int N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000006] ------------ \--* CNS_INT int 1 ***** BB01 STMT00002 (IL ???...0x00B) N006 ( 5, 5) [000012] -A-XG---R--- * ASG int N005 ( 1, 1) [000011] D------N---- +--* LCL_VAR int V07 loc1 d:2 N004 ( 5, 5) [000010] ---XG------- \--* ADD int N002 ( 3, 3) [000077] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 N003 ( 1, 1) [000009] ------------ \--* CNS_INT int -1 ***** BB01 STMT00003 (IL 0x00C...0x00D) N003 ( 1, 3) [000015] -A------R--- * ASG int N002 ( 1, 1) [000014] D------N---- +--* LCL_VAR int V08 loc2 d:2 N001 ( 1, 1) [000013] ------------ \--* CNS_INT int 0 ***** BB01 STMT00016 (IL 0x04B... ???) N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* GT int N001 ( 1, 1) [000125] ------------ +--* LCL_VAR int V08 loc2 u:2 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} ***** BB02 STMT00020 (IL ???... ???) N005 ( 0, 0) [000139] -A------R--- * ASG bool N004 ( 0, 0) [000137] D------N---- +--* LCL_VAR bool V06 loc0 d:4 N003 ( 0, 0) [000138] ------------ \--* PHI bool N001 ( 0, 0) [000151] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 ***** BB02 STMT00017 (IL ???... ???) N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 ***** BB02 STMT00006 (IL ???... ???) N016 ( 18, 21) [000028] -A-XG---R--- * ASG ref N015 ( 3, 2) [000027] D------N---- +--* LCL_VAR ref V09 loc3 d:2 N014 ( 14, 18) [000100] ---XG------- \--* COMMA ref N004 ( 8, 11) [000093] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR int V08 loc2 u:3 N003 ( 3, 3) [000092] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000081] ------------ | \--* LCL_VAR ref V14 tmp2 u:1 N013 ( 6, 7) [000082] a---G------- \--* IND ref N012 ( 5, 6) [000099] -------N---- \--* ADD byref N005 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V14 tmp2 u:1 N011 ( 4, 5) [000098] -------N---- \--* ADD long N009 ( 3, 4) [000096] -------N---- +--* LSH long N007 ( 2, 3) [000094] ------------ | +--* CAST long <- int N006 ( 1, 1) [000091] i----------- | | \--* LCL_VAR int V08 loc2 u:3 N008 ( 1, 1) [000095] -------N---- | \--* CNS_INT long 3 N010 ( 1, 1) [000097] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB02 STMT00008 (IL ???... ???) N016 ( 14, 18) [000037] -A-XG---R--- * ASG ref N015 ( 1, 1) [000036] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N014 ( 14, 18) [000111] ---XG------- \--* COMMA ref N004 ( 8, 11) [000104] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000031] ------------ | +--* LCL_VAR int V08 loc2 u:3 N003 ( 3, 3) [000103] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000086] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 N013 ( 6, 7) [000087] a---G------- \--* IND ref N012 ( 5, 6) [000110] -------N---- \--* ADD byref N005 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 u:1 N011 ( 4, 5) [000109] -------N---- \--* ADD long N009 ( 3, 4) [000107] -------N---- +--* LSH long N007 ( 2, 3) [000105] ------------ | +--* CAST long <- int N006 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 u:3 N008 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 N010 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB02 STMT00009 (IL 0x023...0x024) N003 ( 5, 4) [000040] -A--G---R--- * ASG ref N002 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V11 loc5 N001 ( 1, 1) [000038] ------------ \--* CNS_INT ref null ***** BB02 STMT00010 (IL 0x026...0x034) N017 ( 29, 26) [000052] --CXG------- * JTRUE void N016 ( 27, 24) [000051] J-CXG--N---- \--* EQ int N014 ( 25, 22) [000049] --CXG------- +--* CAST int <- bool <- int N013 ( 24, 20) [000048] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints N007 ( 3, 3) [000047] ------------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 N008 ( 1, 1) [000041] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 N009 ( 1, 1) [000042] ------------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 u:1 N010 ( 1, 1) [000043] ------------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 u:1 N015 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} ***** BB03 STMT00021 (IL ???... ???) N005 ( 0, 0) [000142] -A------R--- * ASG bool N004 ( 0, 0) [000140] D------N---- +--* LCL_VAR bool V06 loc0 d:6 N003 ( 0, 0) [000141] ------------ \--* PHI bool N001 ( 0, 0) [000147] ------------ pred BB06 +--* PHI_ARG bool V06 loc0 u:5 N002 ( 0, 0) [000146] ------------ pred BB02 \--* PHI_ARG bool V06 loc0 u:4 ***** BB03 STMT00011 (IL 0x038...0x043) N011 ( 24, 18) [000060] --CXG------- * JTRUE void N010 ( 22, 16) [000059] J-CXG--N---- \--* NE int N008 ( 20, 14) [000057] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000056] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics N004 ( 3, 2) [000053] ----G------- arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 N005 ( 1, 1) [000054] ------------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 u:1 N009 ( 1, 1) [000058] ------------ \--* CNS_INT int 0 ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} ***** BB04 STMT00018 (IL ???... ???) N005 ( 0, 0) [000133] -A------R--- * ASG bool N004 ( 0, 0) [000131] D------N---- +--* LCL_VAR bool V06 loc0 d:8 N003 ( 0, 0) [000132] ------------ \--* PHI bool N001 ( 0, 0) [000149] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:7 N002 ( 0, 0) [000148] ------------ pred BB03 \--* PHI_ARG bool V06 loc0 u:6 ***** BB04 STMT00012 (IL 0x047...0x04A) N005 ( 3, 3) [000065] -A------R--- * ASG int N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 N003 ( 3, 3) [000063] ------------ \--* ADD int N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 ***** BB04 STMT00004 (IL 0x04B...0x04D) N004 ( 5, 5) [000019] ------------ * JTRUE void N003 ( 3, 3) [000018] J------N---- \--* LE int N001 ( 1, 1) [000016] ------------ +--* LCL_VAR int V08 loc2 u:4 N002 ( 1, 1) [000017] ------------ \--* LCL_VAR int V07 loc1 u:2 ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} ***** BB05 STMT00019 (IL ???... ???) N005 ( 0, 0) [000136] -A------R--- * ASG bool N004 ( 0, 0) [000134] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000135] ------------ \--* PHI bool N001 ( 0, 0) [000150] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 ***** BB05 STMT00015 (IL 0x04F...0x050) N002 ( 4, 3) [000073] ------------ * RETURN int N001 ( 3, 2) [000072] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} ***** BB06 STMT00014 (IL 0x036...0x037) N003 ( 5, 4) [000071] -A------R--- * ASG int N002 ( 3, 2) [000070] D------N---- +--* LCL_VAR int V06 loc0 d:5 N001 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} ***** BB07 STMT00013 (IL 0x045...0x046) N003 ( 5, 4) [000068] -A------R--- * ASG int N002 ( 3, 2) [000067] D------N---- +--* LCL_VAR int V06 loc0 d:7 N001 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Redundant zero Inits *************** In optRemoveRedundantZeroInits() *************** Finishing PHASE Redundant zero Inits *************** Starting PHASE Early Value Propagation *************** In optEarlyProp() After optEarlyProp: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00001 (IL ???... ???) N003 ( 5, 4) [000008] -A------R--- * ASG int N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000006] ------------ \--* CNS_INT int 1 ***** BB01 STMT00002 (IL ???...0x00B) N006 ( 5, 5) [000012] -A-XG---R--- * ASG int N005 ( 1, 1) [000011] D------N---- +--* LCL_VAR int V07 loc1 d:2 N004 ( 5, 5) [000010] ---XG------- \--* ADD int N002 ( 3, 3) [000077] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 N003 ( 1, 1) [000009] ------------ \--* CNS_INT int -1 ***** BB01 STMT00003 (IL 0x00C...0x00D) N003 ( 1, 3) [000015] -A------R--- * ASG int N002 ( 1, 1) [000014] D------N---- +--* LCL_VAR int V08 loc2 d:2 N001 ( 1, 1) [000013] ------------ \--* CNS_INT int 0 ***** BB01 STMT00016 (IL 0x04B... ???) N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* GT int N001 ( 1, 1) [000125] ------------ +--* LCL_VAR int V08 loc2 u:2 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} ***** BB02 STMT00020 (IL ???... ???) N005 ( 0, 0) [000139] -A------R--- * ASG bool N004 ( 0, 0) [000137] D------N---- +--* LCL_VAR bool V06 loc0 d:4 N003 ( 0, 0) [000138] ------------ \--* PHI bool N001 ( 0, 0) [000151] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 ***** BB02 STMT00017 (IL ???... ???) N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 ***** BB02 STMT00006 (IL ???... ???) N016 ( 18, 21) [000028] -A-XG---R--- * ASG ref N015 ( 3, 2) [000027] D------N---- +--* LCL_VAR ref V09 loc3 d:2 N014 ( 14, 18) [000100] ---XG------- \--* COMMA ref N004 ( 8, 11) [000093] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR int V08 loc2 u:3 N003 ( 3, 3) [000092] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000081] ------------ | \--* LCL_VAR ref V14 tmp2 u:1 N013 ( 6, 7) [000082] a---G------- \--* IND ref N012 ( 5, 6) [000099] -------N---- \--* ADD byref N005 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V14 tmp2 u:1 N011 ( 4, 5) [000098] -------N---- \--* ADD long N009 ( 3, 4) [000096] -------N---- +--* LSH long N007 ( 2, 3) [000094] ------------ | +--* CAST long <- int N006 ( 1, 1) [000091] i----------- | | \--* LCL_VAR int V08 loc2 u:3 N008 ( 1, 1) [000095] -------N---- | \--* CNS_INT long 3 N010 ( 1, 1) [000097] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB02 STMT00008 (IL ???... ???) N016 ( 14, 18) [000037] -A-XG---R--- * ASG ref N015 ( 1, 1) [000036] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N014 ( 14, 18) [000111] ---XG------- \--* COMMA ref N004 ( 8, 11) [000104] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000031] ------------ | +--* LCL_VAR int V08 loc2 u:3 N003 ( 3, 3) [000103] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000086] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 N013 ( 6, 7) [000087] a---G------- \--* IND ref N012 ( 5, 6) [000110] -------N---- \--* ADD byref N005 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 u:1 N011 ( 4, 5) [000109] -------N---- \--* ADD long N009 ( 3, 4) [000107] -------N---- +--* LSH long N007 ( 2, 3) [000105] ------------ | +--* CAST long <- int N006 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 u:3 N008 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 N010 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB02 STMT00009 (IL 0x023...0x024) N003 ( 5, 4) [000040] -A--G---R--- * ASG ref N002 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V11 loc5 N001 ( 1, 1) [000038] ------------ \--* CNS_INT ref null ***** BB02 STMT00010 (IL 0x026...0x034) N017 ( 29, 26) [000052] --CXG------- * JTRUE void N016 ( 27, 24) [000051] J-CXG--N---- \--* EQ int N014 ( 25, 22) [000049] --CXG------- +--* CAST int <- bool <- int N013 ( 24, 20) [000048] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints N007 ( 3, 3) [000047] ------------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 N008 ( 1, 1) [000041] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 N009 ( 1, 1) [000042] ------------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 u:1 N010 ( 1, 1) [000043] ------------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 u:1 N015 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} ***** BB03 STMT00021 (IL ???... ???) N005 ( 0, 0) [000142] -A------R--- * ASG bool N004 ( 0, 0) [000140] D------N---- +--* LCL_VAR bool V06 loc0 d:6 N003 ( 0, 0) [000141] ------------ \--* PHI bool N001 ( 0, 0) [000147] ------------ pred BB06 +--* PHI_ARG bool V06 loc0 u:5 N002 ( 0, 0) [000146] ------------ pred BB02 \--* PHI_ARG bool V06 loc0 u:4 ***** BB03 STMT00011 (IL 0x038...0x043) N011 ( 24, 18) [000060] --CXG------- * JTRUE void N010 ( 22, 16) [000059] J-CXG--N---- \--* NE int N008 ( 20, 14) [000057] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000056] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics N004 ( 3, 2) [000053] ----G------- arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 N005 ( 1, 1) [000054] ------------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 u:1 N009 ( 1, 1) [000058] ------------ \--* CNS_INT int 0 ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} ***** BB04 STMT00018 (IL ???... ???) N005 ( 0, 0) [000133] -A------R--- * ASG bool N004 ( 0, 0) [000131] D------N---- +--* LCL_VAR bool V06 loc0 d:8 N003 ( 0, 0) [000132] ------------ \--* PHI bool N001 ( 0, 0) [000149] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:7 N002 ( 0, 0) [000148] ------------ pred BB03 \--* PHI_ARG bool V06 loc0 u:6 ***** BB04 STMT00012 (IL 0x047...0x04A) N005 ( 3, 3) [000065] -A------R--- * ASG int N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 N003 ( 3, 3) [000063] ------------ \--* ADD int N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 ***** BB04 STMT00004 (IL 0x04B...0x04D) N004 ( 5, 5) [000019] ------------ * JTRUE void N003 ( 3, 3) [000018] J------N---- \--* LE int N001 ( 1, 1) [000016] ------------ +--* LCL_VAR int V08 loc2 u:4 N002 ( 1, 1) [000017] ------------ \--* LCL_VAR int V07 loc1 u:2 ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} ***** BB05 STMT00019 (IL ???... ???) N005 ( 0, 0) [000136] -A------R--- * ASG bool N004 ( 0, 0) [000134] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000135] ------------ \--* PHI bool N001 ( 0, 0) [000150] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 ***** BB05 STMT00015 (IL 0x04F...0x050) N002 ( 4, 3) [000073] ------------ * RETURN int N001 ( 3, 2) [000072] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} ***** BB06 STMT00014 (IL 0x036...0x037) N003 ( 5, 4) [000071] -A------R--- * ASG int N002 ( 3, 2) [000070] D------N---- +--* LCL_VAR int V06 loc0 d:5 N001 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} ***** BB07 STMT00013 (IL 0x045...0x046) N003 ( 5, 4) [000068] -A------R--- * ASG int N002 ( 3, 2) [000067] D------N---- +--* LCL_VAR int V06 loc0 d:7 N001 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Early Value Propagation *************** Starting PHASE Do value numbering *************** In fgValueNumber() Memory Initial Value in BB01 is: $85 The SSA definition for ByrefExposed (#1) at start of BB01 is $85 {InitVal($46)} The SSA definition for GcHeap (#1) at start of BB01 is $85 {InitVal($46)} ***** BB01, STMT00001(before) N003 ( 5, 4) [000008] -A------R--- * ASG int N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000006] ------------ \--* CNS_INT int 1 N001 [000006] CNS_INT 1 => $41 {IntCns 1} N002 [000007] LCL_VAR V06 loc0 d:2 => $41 {IntCns 1} N003 [000008] ASG => $41 {IntCns 1} ***** BB01, STMT00001(after) N003 ( 5, 4) [000008] -A------R--- * ASG int $41 N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR int V06 loc0 d:2 $41 N001 ( 1, 1) [000006] ------------ \--* CNS_INT int 1 $41 --------- ***** BB01, STMT00002(before) N006 ( 5, 5) [000012] -A-XG---R--- * ASG int N005 ( 1, 1) [000011] D------N---- +--* LCL_VAR int V07 loc1 d:2 N004 ( 5, 5) [000010] ---XG------- \--* ADD int N002 ( 3, 3) [000077] ---XG------- +--* ARR_LENGTH int N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 N003 ( 1, 1) [000009] ------------ \--* CNS_INT int -1 N001 [000076] LCL_VAR V13 tmp1 u:1 => $83 {InitVal($44)} N002 [000077] ARR_LENGTH => $1c0 {norm=$140 {ARR_LENGTH($83)}, exc=$180 {NullPtrExc($83)}} N003 [000009] CNS_INT -1 => $46 {IntCns -1} N004 [000010] ADD => $1c2 {norm=$1c1 {ADD($46, $140)}, exc=$180 {NullPtrExc($83)}} N005 [000011] LCL_VAR V07 loc1 d:2 => $1c1 {ADD($46, $140)} N006 [000012] ASG => $1c2 {norm=$1c1 {ADD($46, $140)}, exc=$180 {NullPtrExc($83)}} ***** BB01, STMT00002(after) N006 ( 5, 5) [000012] -A-XG---R--- * ASG int $1c2 N005 ( 1, 1) [000011] D------N---- +--* LCL_VAR int V07 loc1 d:2 $1c1 N004 ( 5, 5) [000010] ---XG------- \--* ADD int $1c2 N002 ( 3, 3) [000077] ---XG------- +--* ARR_LENGTH int $1c0 N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 $83 N003 ( 1, 1) [000009] ------------ \--* CNS_INT int -1 $46 --------- ***** BB01, STMT00003(before) N003 ( 1, 3) [000015] -A------R--- * ASG int N002 ( 1, 1) [000014] D------N---- +--* LCL_VAR int V08 loc2 d:2 N001 ( 1, 1) [000013] ------------ \--* CNS_INT int 0 N001 [000013] CNS_INT 0 => $40 {IntCns 0} N002 [000014] LCL_VAR V08 loc2 d:2 => $40 {IntCns 0} N003 [000015] ASG => $40 {IntCns 0} ***** BB01, STMT00003(after) N003 ( 1, 3) [000015] -A------R--- * ASG int $40 N002 ( 1, 1) [000014] D------N---- +--* LCL_VAR int V08 loc2 d:2 $40 N001 ( 1, 1) [000013] ------------ \--* CNS_INT int 0 $40 --------- ***** BB01, STMT00016(before) N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* GT int N001 ( 1, 1) [000125] ------------ +--* LCL_VAR int V08 loc2 u:2 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 N001 [000125] LCL_VAR V08 loc2 u:2 => $40 {IntCns 0} N002 [000126] LCL_VAR V07 loc1 u:2 => $1c1 {ADD($46, $140)} N003 [000124] GT => $1c3 { {IntCns 0} GT {ARR_LENGTH($83)}ADD {IntCns -1}} ***** BB01, STMT00016(after) N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* GT int $1c3 N001 ( 1, 1) [000125] ------------ +--* LCL_VAR int V08 loc2 u:2 $40 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 finish(BB01). Succ(BB02). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB05). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. SSA PHI definition: set VN of local 6/3 to $240 {PhiDef($6, $3, $200)} . The SSA definition for ByrefExposed (#1) at start of BB05 is $85 {InitVal($46)} The SSA definition for GcHeap (#1) at start of BB05 is $85 {InitVal($46)} ***** BB05, STMT00015(before) N002 ( 4, 3) [000073] ------------ * RETURN int N001 ( 3, 2) [000072] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) N001 [000072] LCL_VAR V06 loc0 u:3 (last use) => $240 {PhiDef($6, $3, $200)} N002 [000073] RETURN => $103 {103} ***** BB05, STMT00015(after) N002 ( 4, 3) [000073] ------------ * RETURN int $103 N001 ( 3, 2) [000072] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) $240 finish(BB05). SSA PHI definition: set VN of local 6/4 to $241 {PhiDef($6, $4, $200)} . SSA PHI definition: set VN of local 8/3 to $280 {PhiDef($8, $3, $1c4)} . Building phi application: $49 = SSA# 6. Building phi application: $41 = SSA# 1. Building phi application: $181 = phi($41, $49). The SSA definition for ByrefExposed (#2) at start of BB02 is $182 {PhiMemoryDef($2c0, $181)} Building phi application: $4a = SSA# 7. Building phi application: $41 = SSA# 1. Building phi application: $183 = phi($41, $4a). The SSA definition for GcHeap (#3) at start of BB02 is $184 {PhiMemoryDef($2c0, $183)} ***** BB02, STMT00006(before) N016 ( 18, 21) [000028] -A-XG---R--- * ASG ref N015 ( 3, 2) [000027] D------N---- +--* LCL_VAR ref V09 loc3 d:2 N014 ( 14, 18) [000100] ---XG------- \--* COMMA ref N004 ( 8, 11) [000093] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR int V08 loc2 u:3 N003 ( 3, 3) [000092] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000081] ------------ | \--* LCL_VAR ref V14 tmp2 u:1 N013 ( 6, 7) [000082] a---G------- \--* IND ref N012 ( 5, 6) [000099] -------N---- \--* ADD byref N005 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V14 tmp2 u:1 N011 ( 4, 5) [000098] -------N---- \--* ADD long N009 ( 3, 4) [000096] -------N---- +--* LSH long N007 ( 2, 3) [000094] ------------ | +--* CAST long <- int N006 ( 1, 1) [000091] i----------- | | \--* LCL_VAR int V08 loc2 u:3 N008 ( 1, 1) [000095] -------N---- | \--* CNS_INT long 3 N010 ( 1, 1) [000097] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] N001 [000022] LCL_VAR V08 loc2 u:3 => $280 {PhiDef($8, $3, $1c4)} N002 [000081] LCL_VAR V14 tmp2 u:1 => $84 {InitVal($45)} N003 [000092] ARR_LENGTH => $1c5 {norm=$141 {ARR_LENGTH($84)}, exc=$185 {NullPtrExc($84)}} N004 [000093] ARR_BOUNDS_CHECK_Rng => $18a {norm=$3 {3}, exc=$189( {NullPtrExc($84)}, {IndexOutOfRangeExc($280, $141)})} N005 [000090] LCL_VAR V14 tmp2 u:1 => $84 {InitVal($45)} N006 [000091] LCL_VAR V08 loc2 u:3 => $280 {PhiDef($8, $3, $1c4)} VNForCastOper(long) is $4b N007 [000094] CAST => $300 {Cast($280, $4b)} N008 [000095] CNS_INT 3 => $340 {LngCns: 3} N009 [000096] LSH => $301 {LSH($300, $340)} N010 [000097] CNS_INT 16 Fseq[#FirstElem] => $342 {LngCns: 16} N011 [000098] ADD => $302 {ADD($301, $342)} N012 [000099] ADD => $380 {ADD($84, $302)} VNForHandle(arrElemType: ref) is $2c1 Relabeled IND_ARR_INDEX address node [000099] with l:$3c0: {PtrToArrElem($2c1, $84, $300, $0)} VNForMapSelect($184, $2c1):ref returns $18c {$184[$2c1]} VNForMapSelect($18c, $84):ref returns $18d {$18c[$84]} VNForMapSelect($18d, $300):ref returns $18e {$18d[$300]} hAtArrType $18c is MapSelect(curGcHeap($184), ref[]). hAtArrTypeAtArr $18d is MapSelect(hAtArrType($18c), arr=$84). wholeElem $18e is MapSelect(hAtArrTypeAtArr($18d), ind=$300). N013 [000082] IND => N014 [000100] COMMA => N015 [000027] LCL_VAR V09 loc3 d:2 => N016 [000028] ASG => ***** BB02, STMT00006(after) N016 ( 18, 21) [000028] -A-XG---R--- * ASG ref N015 ( 3, 2) [000027] D------N---- +--* LCL_VAR ref V09 loc3 d:2 N014 ( 14, 18) [000100] ---XG------- \--* COMMA ref N004 ( 8, 11) [000093] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $18a N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR int V08 loc2 u:3 $280 N003 ( 3, 3) [000092] ---X-------- | \--* ARR_LENGTH int $1c5 N002 ( 1, 1) [000081] ------------ | \--* LCL_VAR ref V14 tmp2 u:1 $84 N013 ( 6, 7) [000082] a---G------- \--* IND ref N012 ( 5, 6) [000099] -------N---- \--* ADD byref $3c0 N005 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V14 tmp2 u:1 $84 N011 ( 4, 5) [000098] -------N---- \--* ADD long $302 N009 ( 3, 4) [000096] -------N---- +--* LSH long $301 N007 ( 2, 3) [000094] ------------ | +--* CAST long <- int $300 N006 ( 1, 1) [000091] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N008 ( 1, 1) [000095] -------N---- | \--* CNS_INT long 3 $340 N010 ( 1, 1) [000097] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 --------- ***** BB02, STMT00008(before) N016 ( 14, 18) [000037] -A-XG---R--- * ASG ref N015 ( 1, 1) [000036] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N014 ( 14, 18) [000111] ---XG------- \--* COMMA ref N004 ( 8, 11) [000104] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000031] ------------ | +--* LCL_VAR int V08 loc2 u:3 N003 ( 3, 3) [000103] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000086] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 N013 ( 6, 7) [000087] a---G------- \--* IND ref N012 ( 5, 6) [000110] -------N---- \--* ADD byref N005 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 u:1 N011 ( 4, 5) [000109] -------N---- \--* ADD long N009 ( 3, 4) [000107] -------N---- +--* LSH long N007 ( 2, 3) [000105] ------------ | +--* CAST long <- int N006 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 u:3 N008 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 N010 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] N001 [000031] LCL_VAR V08 loc2 u:3 => $280 {PhiDef($8, $3, $1c4)} N002 [000086] LCL_VAR V13 tmp1 u:1 => $83 {InitVal($44)} N003 [000103] ARR_LENGTH => $1c0 {norm=$140 {ARR_LENGTH($83)}, exc=$180 {NullPtrExc($83)}} N004 [000104] ARR_BOUNDS_CHECK_Rng => $195 {norm=$3 {3}, exc=$194( {NullPtrExc($83)}, {IndexOutOfRangeExc($280, $140)})} N005 [000101] LCL_VAR V13 tmp1 u:1 => $83 {InitVal($44)} N006 [000102] LCL_VAR V08 loc2 u:3 => $280 {PhiDef($8, $3, $1c4)} VNForCastOper(long) is $4b N007 [000105] CAST => $300 {Cast($280, $4b)} N008 [000106] CNS_INT 3 => $340 {LngCns: 3} N009 [000107] LSH => $301 {LSH($300, $340)} N010 [000108] CNS_INT 16 Fseq[#FirstElem] => $342 {LngCns: 16} N011 [000109] ADD => $302 {ADD($301, $342)} N012 [000110] ADD => $381 {ADD($83, $302)} VNForHandle(arrElemType: ref) is $2c1 Relabeled IND_ARR_INDEX address node [000110] with l:$3c1: {PtrToArrElem($2c1, $83, $300, $0)} VNForMapSelect($184, $2c1):ref returns $18c {$184[$2c1]} VNForMapSelect($18c, $83):ref returns $196 {$18c[$83]} VNForMapSelect($196, $300):ref returns $197 {$196[$300]} hAtArrType $18c is MapSelect(curGcHeap($184), ref[]). hAtArrTypeAtArr $196 is MapSelect(hAtArrType($18c), arr=$83). wholeElem $197 is MapSelect(hAtArrTypeAtArr($196), ind=$300). N013 [000087] IND => N014 [000111] COMMA => N015 [000036] LCL_VAR V10 loc4 d:2 => N016 [000037] ASG => ***** BB02, STMT00008(after) N016 ( 14, 18) [000037] -A-XG---R--- * ASG ref N015 ( 1, 1) [000036] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N014 ( 14, 18) [000111] ---XG------- \--* COMMA ref N004 ( 8, 11) [000104] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $195 N001 ( 1, 1) [000031] ------------ | +--* LCL_VAR int V08 loc2 u:3 $280 N003 ( 3, 3) [000103] ---X-------- | \--* ARR_LENGTH int $1c0 N002 ( 1, 1) [000086] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 $83 N013 ( 6, 7) [000087] a---G------- \--* IND ref N012 ( 5, 6) [000110] -------N---- \--* ADD byref $3c1 N005 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 u:1 $83 N011 ( 4, 5) [000109] -------N---- \--* ADD long $302 N009 ( 3, 4) [000107] -------N---- +--* LSH long $301 N007 ( 2, 3) [000105] ------------ | +--* CAST long <- int $300 N006 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N008 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 $340 N010 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 --------- ***** BB02, STMT00009(before) N003 ( 5, 4) [000040] -A--G---R--- * ASG ref N002 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V11 loc5 N001 ( 1, 1) [000038] ------------ \--* CNS_INT ref null N001 [000038] CNS_INT null => $VN.Null fgCurMemoryVN[ByrefExposed] assigned for local assign at [000040] to VN: $440. N003 [000040] ASG => $VN.Null ***** BB02, STMT00009(after) N003 ( 5, 4) [000040] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V11 loc5 N001 ( 1, 1) [000038] ------------ \--* CNS_INT ref null $VN.Null --------- ***** BB02, STMT00010(before) N017 ( 29, 26) [000052] --CXG------- * JTRUE void N016 ( 27, 24) [000051] J-CXG--N---- \--* EQ int N014 ( 25, 22) [000049] --CXG------- +--* CAST int <- bool <- int N013 ( 24, 20) [000048] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints N007 ( 3, 3) [000047] ------------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 N008 ( 1, 1) [000041] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 N009 ( 1, 1) [000042] ------------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 u:1 N010 ( 1, 1) [000043] ------------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 u:1 N015 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 N001 [000113] ARGPLACE => $404 {404} N002 [000114] ARGPLACE => $405 {405} N003 [000115] ARGPLACE => $406 {406} N004 [000116] ARGPLACE => $407 {407} N005 [000117] ARGPLACE => $408 {408} N006 [000112] ARGPLACE => $480 {480} N007 [000047] LCL_VAR_ADDR V11 loc5 => $481 {481} N008 [000041] LCL_VAR V00 arg0 u:1 => $80 {InitVal($40)} N009 [000042] LCL_VAR V01 arg1 u:1 => $81 {InitVal($41)} N010 [000043] LCL_VAR V10 loc4 u:2 => N011 [000044] LCL_VAR V09 loc3 u:2 (last use) => N012 [000045] LCL_VAR V04 arg4 u:1 => $82 {InitVal($42)} VN of ARGPLACE tree [000113] updated to $80 {InitVal($40)} VN of ARGPLACE tree [000114] updated to $81 {InitVal($41)} VN of ARGPLACE tree [000115] updated to VN of ARGPLACE tree [000116] updated to VN of ARGPLACE tree [000117] updated to $82 {InitVal($42)} VN of ARGPLACE tree [000112] updated to $481 {481} fgCurMemoryVN[GcHeap] assigned for CALL at [000048] to VN: $409. N013 [000048] CALL r2r_ind => $104 {104} VNForCastOper(bool) is $42 N014 [000049] CAST => $1c6 {Cast($104, $42)} N015 [000050] CNS_INT 0 => $40 {IntCns 0} N016 [000051] EQ => $1c7 {EQ($1c6, $40)} ***** BB02, STMT00010(after) N017 ( 29, 26) [000052] --CXG------- * JTRUE void N016 ( 27, 24) [000051] J-CXG--N---- \--* EQ int $1c7 N014 ( 25, 22) [000049] --CXG------- +--* CAST int <- bool <- int $1c6 N013 ( 24, 20) [000048] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 N007 ( 3, 3) [000047] ------------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 $481 N008 ( 1, 1) [000041] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 $80 N009 ( 1, 1) [000042] ------------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 u:1 $81 N010 ( 1, 1) [000043] ------------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 u:1 $82 N015 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40 finish(BB02). Succ(BB03). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB06). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#4) at start of BB06 is $441 {441} The SSA definition for GcHeap (#5) at start of BB06 is $409 {409} ***** BB06, STMT00014(before) N003 ( 5, 4) [000071] -A------R--- * ASG int N002 ( 3, 2) [000070] D------N---- +--* LCL_VAR int V06 loc0 d:5 N001 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 N001 [000069] CNS_INT 0 => $40 {IntCns 0} N002 [000070] LCL_VAR V06 loc0 d:5 => $40 {IntCns 0} N003 [000071] ASG => $40 {IntCns 0} ***** BB06, STMT00014(after) N003 ( 5, 4) [000071] -A------R--- * ASG int $40 N002 ( 3, 2) [000070] D------N---- +--* LCL_VAR int V06 loc0 d:5 $40 N001 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $40 finish(BB06). Succ(BB03). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 6/6 to $242 {PhiDef($6, $6, $201)} . The SSA definition for ByrefExposed (#4) at start of BB03 is $441 {441} The SSA definition for GcHeap (#5) at start of BB03 is $409 {409} ***** BB03, STMT00011(before) N011 ( 24, 18) [000060] --CXG------- * JTRUE void N010 ( 22, 16) [000059] J-CXG--N---- \--* NE int N008 ( 20, 14) [000057] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000056] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics N004 ( 3, 2) [000053] ----G------- arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 N005 ( 1, 1) [000054] ------------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 u:1 N009 ( 1, 1) [000058] ------------ \--* CNS_INT int 0 N001 [000119] ARGPLACE => $40a {40a} N002 [000120] ARGPLACE => $40b {40b} N003 [000121] ARGPLACE => $4c0 {4c0} N004 [000053] LCL_VAR V11 loc5 => $500 {ByrefExposedLoad($44, $382, $441)} N005 [000054] LCL_VAR V10 loc4 u:2 (last use) => N006 [000055] LCL_VAR V05 arg5 u:1 => $c0 {InitVal($43)} VN of ARGPLACE tree [000119] updated to $500 {ByrefExposedLoad($44, $382, $441)} VN of ARGPLACE tree [000120] updated to VN of ARGPLACE tree [000121] updated to $c0 {InitVal($43)} fgCurMemoryVN[GcHeap] assigned for CALL at [000056] to VN: $40c. N007 [000056] CALL r2r_ind => $106 {106} VNForCastOper(bool) is $42 N008 [000057] CAST => $1c8 {Cast($106, $42)} N009 [000058] CNS_INT 0 => $40 {IntCns 0} N010 [000059] NE => $1c9 {NE($1c8, $40)} ***** BB03, STMT00011(after) N011 ( 24, 18) [000060] --CXG------- * JTRUE void N010 ( 22, 16) [000059] J-CXG--N---- \--* NE int $1c9 N008 ( 20, 14) [000057] --CXG------- +--* CAST int <- bool <- int $1c8 N007 ( 19, 12) [000056] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 N004 ( 3, 2) [000053] ----G------- arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 $500 N005 ( 1, 1) [000054] ------------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 u:1 $c0 N009 ( 1, 1) [000058] ------------ \--* CNS_INT int 0 $40 finish(BB03). Succ(BB04). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB07). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#6) at start of BB07 is $442 {442} The SSA definition for GcHeap (#7) at start of BB07 is $40c {40c} ***** BB07, STMT00013(before) N003 ( 5, 4) [000068] -A------R--- * ASG int N002 ( 3, 2) [000067] D------N---- +--* LCL_VAR int V06 loc0 d:7 N001 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 N001 [000066] CNS_INT 0 => $40 {IntCns 0} N002 [000067] LCL_VAR V06 loc0 d:7 => $40 {IntCns 0} N003 [000068] ASG => $40 {IntCns 0} ***** BB07, STMT00013(after) N003 ( 5, 4) [000068] -A------R--- * ASG int $40 N002 ( 3, 2) [000067] D------N---- +--* LCL_VAR int V06 loc0 d:7 $40 N001 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 $40 finish(BB07). Succ(BB04). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 6/8 to $243 {PhiDef($6, $8, $202)} . The SSA definition for ByrefExposed (#6) at start of BB04 is $442 {442} The SSA definition for GcHeap (#7) at start of BB04 is $40c {40c} ***** BB04, STMT00012(before) N005 ( 3, 3) [000065] -A------R--- * ASG int N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 N003 ( 3, 3) [000063] ------------ \--* ADD int N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 N001 [000061] LCL_VAR V08 loc2 u:3 (last use) => $280 {PhiDef($8, $3, $1c4)} N002 [000062] CNS_INT 1 => $41 {IntCns 1} N003 [000063] ADD => $1ca {ADD($41, $280)} N004 [000064] LCL_VAR V08 loc2 d:4 => $1ca {ADD($41, $280)} N005 [000065] ASG => $1ca {ADD($41, $280)} ***** BB04, STMT00012(after) N005 ( 3, 3) [000065] -A------R--- * ASG int $1ca N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 $1ca N003 ( 3, 3) [000063] ------------ \--* ADD int $1ca N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 $41 --------- ***** BB04, STMT00004(before) N004 ( 5, 5) [000019] ------------ * JTRUE void N003 ( 3, 3) [000018] J------N---- \--* LE int N001 ( 1, 1) [000016] ------------ +--* LCL_VAR int V08 loc2 u:4 N002 ( 1, 1) [000017] ------------ \--* LCL_VAR int V07 loc1 u:2 N001 [000016] LCL_VAR V08 loc2 u:4 => $1ca {ADD($41, $280)} N002 [000017] LCL_VAR V07 loc1 u:2 => $1c1 {ADD($46, $140)} N003 [000018] LE => $1cb { {ADD($41, $280)} LE {ARR_LENGTH($83)}ADD {IntCns -1}} ***** BB04, STMT00004(after) N004 ( 5, 5) [000019] ------------ * JTRUE void N003 ( 3, 3) [000018] J------N---- \--* LE int $1cb N001 ( 1, 1) [000016] ------------ +--* LCL_VAR int V08 loc2 u:4 $1ca N002 ( 1, 1) [000017] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 finish(BB04). Succ(BB05). Succ(BB02). *************** Finishing PHASE Do value numbering *************** Starting PHASE Hoist loop code *************** Finishing PHASE Hoist loop code *************** Starting PHASE VN based copy prop *************** In optVnCopyProp() Copy Assertion for BB01 curSsaName stack: { } Live vars: {V00 V01 V04 V05 V13 V14} => {V00 V01 V04 V05 V06 V13 V14} Live vars: {V00 V01 V04 V05 V06 V13 V14} => {V00 V01 V04 V05 V06 V07 V13 V14} Live vars: {V00 V01 V04 V05 V06 V07 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V13 V14} Copy Assertion for BB05 curSsaName stack: { 13-[000076]:V13 6-[000007]:V06 7-[000011]:V07 8-[000014]:V08 } Live vars: {V06} => {} Copy Assertion for BB02 curSsaName stack: { 13-[000076]:V13 6-[000007]:V06 7-[000011]:V07 8-[000014]:V08 } Live vars: {V00 V01 V04 V05 V06 V07 V08 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V09 V13 V14} Live vars: {V00 V01 V04 V05 V06 V07 V08 V09 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V09 V10 V13 V14} Live vars: {V00 V01 V04 V05 V06 V07 V08 V09 V10 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} Copy Assertion for BB06 curSsaName stack: { 0-[000041]:V00 1-[000042]:V01 4-[000045]:V04 6-[000137]:V06 7-[000011]:V07 8-[000128]:V08 9-[000027]:V09 10-[000036]:V10 13-[000076]:V13 14-[000081]:V14 } Live vars: {V00 V01 V04 V05 V07 V08 V10 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} Copy Assertion for BB03 curSsaName stack: { 0-[000041]:V00 1-[000042]:V01 4-[000045]:V04 6-[000137]:V06 7-[000011]:V07 8-[000128]:V08 9-[000027]:V09 10-[000036]:V10 13-[000076]:V13 14-[000081]:V14 } Live vars: {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V13 V14} Copy Assertion for BB07 curSsaName stack: { 0-[000041]:V00 1-[000042]:V01 4-[000045]:V04 5-[000055]:V05 6-[000140]:V06 7-[000011]:V07 8-[000128]:V08 9-[000027]:V09 10-[000036]:V10 13-[000076]:V13 14-[000081]:V14 } Live vars: {V00 V01 V04 V05 V07 V08 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V13 V14} Copy Assertion for BB04 curSsaName stack: { 0-[000041]:V00 1-[000042]:V01 4-[000045]:V04 5-[000055]:V05 6-[000140]:V06 7-[000011]:V07 8-[000128]:V08 9-[000027]:V09 10-[000036]:V10 13-[000076]:V13 14-[000081]:V14 } Live vars: {V00 V01 V04 V05 V06 V07 V08 V13 V14} => {V00 V01 V04 V05 V06 V07 V13 V14} Live vars: {V00 V01 V04 V05 V06 V07 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V13 V14} *************** Finishing PHASE VN based copy prop *************** Starting PHASE Optimize Valnum CSEs *************** In optOptimizeCSEs() Blocks/Trees at start of optOptimizeCSE phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00001 (IL ???... ???) N003 ( 5, 4) [000008] -A------R--- * ASG int $41 N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR int V06 loc0 d:2 $41 N001 ( 1, 1) [000006] ------------ \--* CNS_INT int 1 $41 ***** BB01 STMT00002 (IL ???...0x00B) N006 ( 5, 5) [000012] -A-XG---R--- * ASG int $1c2 N005 ( 1, 1) [000011] D------N---- +--* LCL_VAR int V07 loc1 d:2 $1c1 N004 ( 5, 5) [000010] ---XG------- \--* ADD int $1c2 N002 ( 3, 3) [000077] ---XG------- +--* ARR_LENGTH int $1c0 N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 $83 N003 ( 1, 1) [000009] ------------ \--* CNS_INT int -1 $46 ***** BB01 STMT00003 (IL 0x00C...0x00D) N003 ( 1, 3) [000015] -A------R--- * ASG int $40 N002 ( 1, 1) [000014] D------N---- +--* LCL_VAR int V08 loc2 d:2 $40 N001 ( 1, 1) [000013] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00016 (IL 0x04B... ???) N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* GT int $1c3 N001 ( 1, 1) [000125] ------------ +--* LCL_VAR int V08 loc2 u:2 $40 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} ***** BB02 STMT00020 (IL ???... ???) N005 ( 0, 0) [000139] -A------R--- * ASG bool N004 ( 0, 0) [000137] D------N---- +--* LCL_VAR bool V06 loc0 d:4 N003 ( 0, 0) [000138] ------------ \--* PHI bool N001 ( 0, 0) [000151] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB02 STMT00017 (IL ???... ???) N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 ***** BB02 STMT00006 (IL ???... ???) N016 ( 18, 21) [000028] -A-XG---R--- * ASG ref N015 ( 3, 2) [000027] D------N---- +--* LCL_VAR ref V09 loc3 d:2 N014 ( 14, 18) [000100] ---XG------- \--* COMMA ref N004 ( 8, 11) [000093] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $18a N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR int V08 loc2 u:3 $280 N003 ( 3, 3) [000092] ---X-------- | \--* ARR_LENGTH int $1c5 N002 ( 1, 1) [000081] ------------ | \--* LCL_VAR ref V14 tmp2 u:1 $84 N013 ( 6, 7) [000082] a---G------- \--* IND ref N012 ( 5, 6) [000099] -------N---- \--* ADD byref $3c0 N005 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V14 tmp2 u:1 $84 N011 ( 4, 5) [000098] -------N---- \--* ADD long $302 N009 ( 3, 4) [000096] -------N---- +--* LSH long $301 N007 ( 2, 3) [000094] ------------ | +--* CAST long <- int $300 N006 ( 1, 1) [000091] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N008 ( 1, 1) [000095] -------N---- | \--* CNS_INT long 3 $340 N010 ( 1, 1) [000097] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 ***** BB02 STMT00008 (IL ???... ???) N016 ( 14, 18) [000037] -A-XG---R--- * ASG ref N015 ( 1, 1) [000036] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N014 ( 14, 18) [000111] ---XG------- \--* COMMA ref N004 ( 8, 11) [000104] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $195 N001 ( 1, 1) [000031] ------------ | +--* LCL_VAR int V08 loc2 u:3 $280 N003 ( 3, 3) [000103] ---X-------- | \--* ARR_LENGTH int $1c0 N002 ( 1, 1) [000086] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 $83 N013 ( 6, 7) [000087] a---G------- \--* IND ref N012 ( 5, 6) [000110] -------N---- \--* ADD byref $3c1 N005 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 u:1 $83 N011 ( 4, 5) [000109] -------N---- \--* ADD long $302 N009 ( 3, 4) [000107] -------N---- +--* LSH long $301 N007 ( 2, 3) [000105] ------------ | +--* CAST long <- int $300 N006 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N008 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 $340 N010 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 ***** BB02 STMT00009 (IL 0x023...0x024) N003 ( 5, 4) [000040] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V11 loc5 N001 ( 1, 1) [000038] ------------ \--* CNS_INT ref null $VN.Null ***** BB02 STMT00010 (IL 0x026...0x034) N017 ( 29, 26) [000052] --CXG------- * JTRUE void N016 ( 27, 24) [000051] J-CXG--N---- \--* EQ int $1c7 N014 ( 25, 22) [000049] --CXG------- +--* CAST int <- bool <- int $1c6 N013 ( 24, 20) [000048] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 N007 ( 3, 3) [000047] ------------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 $481 N008 ( 1, 1) [000041] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 $80 N009 ( 1, 1) [000042] ------------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 u:1 $81 N010 ( 1, 1) [000043] ------------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 u:1 $82 N015 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} ***** BB03 STMT00021 (IL ???... ???) N005 ( 0, 0) [000142] -A------R--- * ASG bool N004 ( 0, 0) [000140] D------N---- +--* LCL_VAR bool V06 loc0 d:6 N003 ( 0, 0) [000141] ------------ \--* PHI bool N001 ( 0, 0) [000147] ------------ pred BB06 +--* PHI_ARG bool V06 loc0 u:5 $40 N002 ( 0, 0) [000146] ------------ pred BB02 \--* PHI_ARG bool V06 loc0 u:4 $241 ***** BB03 STMT00011 (IL 0x038...0x043) N011 ( 24, 18) [000060] --CXG------- * JTRUE void N010 ( 22, 16) [000059] J-CXG--N---- \--* NE int $1c9 N008 ( 20, 14) [000057] --CXG------- +--* CAST int <- bool <- int $1c8 N007 ( 19, 12) [000056] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 N004 ( 3, 2) [000053] ----G------- arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 $500 N005 ( 1, 1) [000054] ------------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 u:1 $c0 N009 ( 1, 1) [000058] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} ***** BB04 STMT00018 (IL ???... ???) N005 ( 0, 0) [000133] -A------R--- * ASG bool N004 ( 0, 0) [000131] D------N---- +--* LCL_VAR bool V06 loc0 d:8 N003 ( 0, 0) [000132] ------------ \--* PHI bool N001 ( 0, 0) [000149] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:7 $40 N002 ( 0, 0) [000148] ------------ pred BB03 \--* PHI_ARG bool V06 loc0 u:6 $242 ***** BB04 STMT00012 (IL 0x047...0x04A) N005 ( 3, 3) [000065] -A------R--- * ASG int $1ca N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 $1ca N003 ( 3, 3) [000063] ------------ \--* ADD int $1ca N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00004 (IL 0x04B...0x04D) N004 ( 5, 5) [000019] ------------ * JTRUE void N003 ( 3, 3) [000018] J------N---- \--* LE int $1cb N001 ( 1, 1) [000016] ------------ +--* LCL_VAR int V08 loc2 u:4 $1ca N002 ( 1, 1) [000017] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} ***** BB05 STMT00019 (IL ???... ???) N005 ( 0, 0) [000136] -A------R--- * ASG bool N004 ( 0, 0) [000134] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000135] ------------ \--* PHI bool N001 ( 0, 0) [000150] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB05 STMT00015 (IL 0x04F...0x050) N002 ( 4, 3) [000073] ------------ * RETURN int $103 N001 ( 3, 2) [000072] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) $240 ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} ***** BB06 STMT00014 (IL 0x036...0x037) N003 ( 5, 4) [000071] -A------R--- * ASG int $40 N002 ( 3, 2) [000070] D------N---- +--* LCL_VAR int V06 loc0 d:5 $40 N001 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} ***** BB07 STMT00013 (IL 0x045...0x046) N003 ( 5, 4) [000068] -A------R--- * ASG int $40 N002 ( 3, 2) [000067] D------N---- +--* LCL_VAR int V06 loc0 d:7 $40 N001 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- *************** In optOptimizeValnumCSEs() CSE candidate #01, vn=$140 in BB02, [cost= 3, size= 3]: N003 ( 3, 3) CSE #01 (use)[000103] ---X-------- * ARR_LENGTH int $1c0 N002 ( 1, 1) [000086] ------------ \--* LCL_VAR ref V13 tmp1 u:1 $83 CSE candidate #02, vn=$300 in BB02, [cost= 2, size= 3]: N007 ( 2, 3) CSE #02 (use)[000105] ------------ * CAST long <- int $300 N006 ( 1, 1) [000102] i----------- \--* LCL_VAR int V08 loc2 u:3 $280 Blocks that generate CSE def/uses BB01 cseGen = 0000000000000003 BB02 cseGen = 0000000000000005 Performing DataFlow for ValnumCSE's StartMerge BB01 :: cseOut = 000000000000001F EndMerge BB01 :: cseIn = 0000000000000000 :: cseGen = 0000000000000003 => cseOut = 0000000000000003 != preMerge = 000000000000001F, => true StartMerge BB02 :: cseOut = 000000000000001F Merge BB02 and BB01 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000003 Merge BB02 and BB04 :: cseIn = 0000000000000003 :: cseOut = 000000000000001F => cseIn = 0000000000000003 EndMerge BB02 :: cseIn = 0000000000000003 -- cseKill = 0000000000000005 :: cseGen = 0000000000000005 => cseOut = 0000000000000005 != preMerge = 000000000000001F, => true StartMerge BB05 :: cseOut = 000000000000001F Merge BB05 and BB01 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000003 Merge BB05 and BB04 :: cseIn = 0000000000000003 :: cseOut = 000000000000001F => cseIn = 0000000000000003 EndMerge BB05 :: cseIn = 0000000000000003 :: cseGen = 0000000000000000 => cseOut = 0000000000000003 != preMerge = 000000000000001F, => true StartMerge BB03 :: cseOut = 000000000000001F Merge BB03 and BB02 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000005 Merge BB03 and BB06 :: cseIn = 0000000000000005 :: cseOut = 000000000000001F => cseIn = 0000000000000005 EndMerge BB03 :: cseIn = 0000000000000005 -- cseKill = 0000000000000005 :: cseGen = 0000000000000000 => cseOut = 0000000000000005 != preMerge = 000000000000001F, => true StartMerge BB06 :: cseOut = 000000000000001F Merge BB06 and BB02 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000005 EndMerge BB06 :: cseIn = 0000000000000005 :: cseGen = 0000000000000000 => cseOut = 0000000000000005 != preMerge = 000000000000001F, => true StartMerge BB04 :: cseOut = 000000000000001F Merge BB04 and BB03 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000005 Merge BB04 and BB07 :: cseIn = 0000000000000005 :: cseOut = 000000000000001F => cseIn = 0000000000000005 EndMerge BB04 :: cseIn = 0000000000000005 :: cseGen = 0000000000000000 => cseOut = 0000000000000005 != preMerge = 000000000000001F, => true StartMerge BB07 :: cseOut = 000000000000001F Merge BB07 and BB03 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000005 EndMerge BB07 :: cseIn = 0000000000000005 :: cseGen = 0000000000000000 => cseOut = 0000000000000005 != preMerge = 000000000000001F, => true StartMerge BB03 :: cseOut = 0000000000000005 Merge BB03 and BB02 :: cseIn = 0000000000000005 :: cseOut = 0000000000000005 => cseIn = 0000000000000005 Merge BB03 and BB06 :: cseIn = 0000000000000005 :: cseOut = 0000000000000005 => cseIn = 0000000000000005 EndMerge BB03 :: cseIn = 0000000000000005 -- cseKill = 0000000000000005 :: cseGen = 0000000000000000 => cseOut = 0000000000000005 != preMerge = 0000000000000005, => false StartMerge BB05 :: cseOut = 0000000000000003 Merge BB05 and BB01 :: cseIn = 0000000000000003 :: cseOut = 0000000000000003 => cseIn = 0000000000000003 Merge BB05 and BB04 :: cseIn = 0000000000000003 :: cseOut = 0000000000000003 => cseIn = 0000000000000001 EndMerge BB05 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0000000000000003, => true StartMerge BB02 :: cseOut = 0000000000000005 Merge BB02 and BB01 :: cseIn = 0000000000000003 :: cseOut = 0000000000000005 => cseIn = 0000000000000003 Merge BB02 and BB04 :: cseIn = 0000000000000003 :: cseOut = 0000000000000005 => cseIn = 0000000000000001 EndMerge BB02 :: cseIn = 0000000000000001 -- cseKill = 0000000000000005 :: cseGen = 0000000000000005 => cseOut = 0000000000000005 != preMerge = 0000000000000005, => false StartMerge BB04 :: cseOut = 0000000000000005 Merge BB04 and BB03 :: cseIn = 0000000000000005 :: cseOut = 0000000000000005 => cseIn = 0000000000000005 Merge BB04 and BB07 :: cseIn = 0000000000000005 :: cseOut = 0000000000000005 => cseIn = 0000000000000005 EndMerge BB04 :: cseIn = 0000000000000005 :: cseGen = 0000000000000000 => cseOut = 0000000000000005 != preMerge = 0000000000000005, => false After performing DataFlow for ValnumCSE's BB01 cseIn = 0000000000000000, cseGen = 0000000000000003, cseOut = 0000000000000003 BB02 cseIn = 0000000000000001, cseGen = 0000000000000005, cseOut = 0000000000000005 BB03 cseIn = 0000000000000005, cseGen = 0000000000000000, cseOut = 0000000000000005 BB04 cseIn = 0000000000000005, cseGen = 0000000000000000, cseOut = 0000000000000005 BB05 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB06 cseIn = 0000000000000005, cseGen = 0000000000000000, cseOut = 0000000000000005 BB07 cseIn = 0000000000000005, cseGen = 0000000000000000, cseOut = 0000000000000005 Labeling the CSEs with Use/Def information BB01 [000077] Def of CSE #01 [weight=1 ] BB02 [000094] Def of CSE #02 [weight=1.06] BB02 [000103] Use of CSE #01 [weight=1.06] *** Now Live Across Call *** BB02 [000105] Use of CSE #02 [weight=1.06] ************ Trees at start of optValnumCSE_Heuristic() ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00001 (IL ???... ???) N003 ( 5, 4) [000008] -A------R--- * ASG int $41 N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR int V06 loc0 d:2 $41 N001 ( 1, 1) [000006] ------------ \--* CNS_INT int 1 $41 ***** BB01 STMT00002 (IL ???...0x00B) N006 ( 5, 5) [000012] -A-XG---R--- * ASG int $1c2 N005 ( 1, 1) [000011] D------N---- +--* LCL_VAR int V07 loc1 d:2 $1c1 N004 ( 5, 5) [000010] ---XG------- \--* ADD int $1c2 N002 ( 3, 3) CSE #01 (def)[000077] ---XG------- +--* ARR_LENGTH int $1c0 N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 $83 N003 ( 1, 1) [000009] ------------ \--* CNS_INT int -1 $46 ***** BB01 STMT00003 (IL 0x00C...0x00D) N003 ( 1, 3) [000015] -A------R--- * ASG int $40 N002 ( 1, 1) [000014] D------N---- +--* LCL_VAR int V08 loc2 d:2 $40 N001 ( 1, 1) [000013] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00016 (IL 0x04B... ???) N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* GT int $1c3 N001 ( 1, 1) [000125] ------------ +--* LCL_VAR int V08 loc2 u:2 $40 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} ***** BB02 STMT00020 (IL ???... ???) N005 ( 0, 0) [000139] -A------R--- * ASG bool N004 ( 0, 0) [000137] D------N---- +--* LCL_VAR bool V06 loc0 d:4 N003 ( 0, 0) [000138] ------------ \--* PHI bool N001 ( 0, 0) [000151] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB02 STMT00017 (IL ???... ???) N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 ***** BB02 STMT00006 (IL ???... ???) N016 ( 18, 21) [000028] -A-XG---R--- * ASG ref N015 ( 3, 2) [000027] D------N---- +--* LCL_VAR ref V09 loc3 d:2 N014 ( 14, 18) [000100] ---XG------- \--* COMMA ref N004 ( 8, 11) [000093] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $18a N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR int V08 loc2 u:3 $280 N003 ( 3, 3) [000092] ---X-------- | \--* ARR_LENGTH int $1c5 N002 ( 1, 1) [000081] ------------ | \--* LCL_VAR ref V14 tmp2 u:1 $84 N013 ( 6, 7) [000082] a---G------- \--* IND ref N012 ( 5, 6) [000099] -------N---- \--* ADD byref $3c0 N005 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V14 tmp2 u:1 $84 N011 ( 4, 5) [000098] -------N---- \--* ADD long $302 N009 ( 3, 4) [000096] -------N---- +--* LSH long $301 N007 ( 2, 3) CSE #02 (def)[000094] ------------ | +--* CAST long <- int $300 N006 ( 1, 1) [000091] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N008 ( 1, 1) [000095] -------N---- | \--* CNS_INT long 3 $340 N010 ( 1, 1) [000097] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 ***** BB02 STMT00008 (IL ???... ???) N016 ( 14, 18) [000037] -A-XG---R--- * ASG ref N015 ( 1, 1) [000036] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N014 ( 14, 18) [000111] ---XG------- \--* COMMA ref N004 ( 8, 11) [000104] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $195 N001 ( 1, 1) [000031] ------------ | +--* LCL_VAR int V08 loc2 u:3 $280 N003 ( 3, 3) CSE #01 (use)[000103] ---X-------- | \--* ARR_LENGTH int $1c0 N002 ( 1, 1) [000086] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 $83 N013 ( 6, 7) [000087] a---G------- \--* IND ref N012 ( 5, 6) [000110] -------N---- \--* ADD byref $3c1 N005 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 u:1 $83 N011 ( 4, 5) [000109] -------N---- \--* ADD long $302 N009 ( 3, 4) [000107] -------N---- +--* LSH long $301 N007 ( 2, 3) CSE #02 (use)[000105] ------------ | +--* CAST long <- int $300 N006 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N008 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 $340 N010 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 ***** BB02 STMT00009 (IL 0x023...0x024) N003 ( 5, 4) [000040] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V11 loc5 N001 ( 1, 1) [000038] ------------ \--* CNS_INT ref null $VN.Null ***** BB02 STMT00010 (IL 0x026...0x034) N017 ( 29, 26) [000052] --CXG------- * JTRUE void N016 ( 27, 24) [000051] J-CXG--N---- \--* EQ int $1c7 N014 ( 25, 22) [000049] --CXG------- +--* CAST int <- bool <- int $1c6 N013 ( 24, 20) [000048] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 N007 ( 3, 3) [000047] ------------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 $481 N008 ( 1, 1) [000041] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 $80 N009 ( 1, 1) [000042] ------------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 u:1 $81 N010 ( 1, 1) [000043] ------------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 u:1 $82 N015 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} ***** BB03 STMT00021 (IL ???... ???) N005 ( 0, 0) [000142] -A------R--- * ASG bool N004 ( 0, 0) [000140] D------N---- +--* LCL_VAR bool V06 loc0 d:6 N003 ( 0, 0) [000141] ------------ \--* PHI bool N001 ( 0, 0) [000147] ------------ pred BB06 +--* PHI_ARG bool V06 loc0 u:5 $40 N002 ( 0, 0) [000146] ------------ pred BB02 \--* PHI_ARG bool V06 loc0 u:4 $241 ***** BB03 STMT00011 (IL 0x038...0x043) N011 ( 24, 18) [000060] --CXG------- * JTRUE void N010 ( 22, 16) [000059] J-CXG--N---- \--* NE int $1c9 N008 ( 20, 14) [000057] --CXG------- +--* CAST int <- bool <- int $1c8 N007 ( 19, 12) [000056] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 N004 ( 3, 2) [000053] ----G------- arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 $500 N005 ( 1, 1) [000054] ------------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 u:1 $c0 N009 ( 1, 1) [000058] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} ***** BB04 STMT00018 (IL ???... ???) N005 ( 0, 0) [000133] -A------R--- * ASG bool N004 ( 0, 0) [000131] D------N---- +--* LCL_VAR bool V06 loc0 d:8 N003 ( 0, 0) [000132] ------------ \--* PHI bool N001 ( 0, 0) [000149] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:7 $40 N002 ( 0, 0) [000148] ------------ pred BB03 \--* PHI_ARG bool V06 loc0 u:6 $242 ***** BB04 STMT00012 (IL 0x047...0x04A) N005 ( 3, 3) [000065] -A------R--- * ASG int $1ca N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 $1ca N003 ( 3, 3) [000063] ------------ \--* ADD int $1ca N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00004 (IL 0x04B...0x04D) N004 ( 5, 5) [000019] ------------ * JTRUE void N003 ( 3, 3) [000018] J------N---- \--* LE int $1cb N001 ( 1, 1) [000016] ------------ +--* LCL_VAR int V08 loc2 u:4 $1ca N002 ( 1, 1) [000017] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} ***** BB05 STMT00019 (IL ???... ???) N005 ( 0, 0) [000136] -A------R--- * ASG bool N004 ( 0, 0) [000134] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000135] ------------ \--* PHI bool N001 ( 0, 0) [000150] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB05 STMT00015 (IL 0x04F...0x050) N002 ( 4, 3) [000073] ------------ * RETURN int $103 N001 ( 3, 2) [000072] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) $240 ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} ***** BB06 STMT00014 (IL 0x036...0x037) N003 ( 5, 4) [000071] -A------R--- * ASG int $40 N002 ( 3, 2) [000070] D------N---- +--* LCL_VAR int V06 loc0 d:5 $40 N001 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} ***** BB07 STMT00013 (IL 0x045...0x046) N003 ( 5, 4) [000068] -A------R--- * ASG int $40 N002 ( 3, 2) [000067] D------N---- +--* LCL_VAR int V06 loc0 d:7 $40 N001 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- Aggressive CSE Promotion cutoff is 418 Moderate CSE Promotion cutoff is 100 enregCount is 11 Framesize estimate is 0x0008 We have a small frame Sorted CSE candidates: CSE #01, {$140, $180} useCnt=1: [def=100, use=106, cost= 3, call] :: N002 ( 3, 3) CSE #01 (def)[000077] ---XG------- * ARR_LENGTH int $1c0 CSE #02, {$300, $4 } useCnt=1: [def=106, use=106, cost= 2 ] :: N007 ( 2, 3) CSE #02 (def)[000094] ------------ * CAST long <- int $300 Considering CSE #01 {$140, $180} [def=100, use=106, cost= 3, call] CSE Expression : N002 ( 3, 3) CSE #01 (def)[000077] ---XG------- * ARR_LENGTH int $1c0 N001 ( 1, 1) [000076] ------------ \--* LCL_VAR ref V13 tmp1 u:1 $83 Moderate CSE Promotion (CSE is live across a call) (306 >= 100) cseRefCnt=306, aggressiveRefCnt=418, moderateRefCnt=100 defCnt=100, useCnt=106, cost=3, size=3, LiveAcrossCall def_cost=2, use_cost=2, extra_no_cost=2, extra_yes_cost=0 CSE cost savings check (320 >= 412) fails Did Not promote this CSE Considering CSE #02 {$300, $4 } [def=106, use=106, cost= 2 ] CSE Expression : N007 ( 2, 3) CSE #02 (def)[000094] ------------ * CAST long <- int $300 N006 ( 1, 1) [000091] i----------- \--* LCL_VAR int V08 loc2 u:3 $280 Moderate CSE Promotion (CSE never live at call) (318 >= 100) cseRefCnt=318, aggressiveRefCnt=418, moderateRefCnt=100 defCnt=106, useCnt=106, cost=2, size=3 def_cost=2, use_cost=1, extra_no_cost=4, extra_yes_cost=0 CSE cost savings check (216 >= 318) fails Did Not promote this CSE *************** Finishing PHASE Optimize Valnum CSEs *************** Starting PHASE Assertion prop *************** In optAssertionPropMain() Blocks/Trees at start of phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00001 (IL ???... ???) N003 ( 5, 4) [000008] -A------R--- * ASG int $41 N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR int V06 loc0 d:2 $41 N001 ( 1, 1) [000006] ------------ \--* CNS_INT int 1 $41 ***** BB01 STMT00002 (IL ???...0x00B) N006 ( 5, 5) [000012] -A-XG---R--- * ASG int $1c2 N005 ( 1, 1) [000011] D------N---- +--* LCL_VAR int V07 loc1 d:2 $1c1 N004 ( 5, 5) [000010] ---XG------- \--* ADD int $1c2 N002 ( 3, 3) [000077] ---XG------- +--* ARR_LENGTH int $1c0 N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 $83 N003 ( 1, 1) [000009] ------------ \--* CNS_INT int -1 $46 ***** BB01 STMT00003 (IL 0x00C...0x00D) N003 ( 1, 3) [000015] -A------R--- * ASG int $40 N002 ( 1, 1) [000014] D------N---- +--* LCL_VAR int V08 loc2 d:2 $40 N001 ( 1, 1) [000013] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00016 (IL 0x04B... ???) N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* GT int $1c3 N001 ( 1, 1) [000125] ------------ +--* LCL_VAR int V08 loc2 u:2 $40 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} ***** BB02 STMT00020 (IL ???... ???) N005 ( 0, 0) [000139] -A------R--- * ASG bool N004 ( 0, 0) [000137] D------N---- +--* LCL_VAR bool V06 loc0 d:4 N003 ( 0, 0) [000138] ------------ \--* PHI bool N001 ( 0, 0) [000151] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB02 STMT00017 (IL ???... ???) N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 ***** BB02 STMT00006 (IL ???... ???) N016 ( 18, 21) [000028] -A-XG---R--- * ASG ref N015 ( 3, 2) [000027] D------N---- +--* LCL_VAR ref V09 loc3 d:2 N014 ( 14, 18) [000100] ---XG------- \--* COMMA ref N004 ( 8, 11) [000093] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $18a N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR int V08 loc2 u:3 $280 N003 ( 3, 3) [000092] ---X-------- | \--* ARR_LENGTH int $1c5 N002 ( 1, 1) [000081] ------------ | \--* LCL_VAR ref V14 tmp2 u:1 $84 N013 ( 6, 7) [000082] a---G------- \--* IND ref N012 ( 5, 6) [000099] -------N---- \--* ADD byref $3c0 N005 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V14 tmp2 u:1 $84 N011 ( 4, 5) [000098] -------N---- \--* ADD long $302 N009 ( 3, 4) [000096] -------N---- +--* LSH long $301 N007 ( 2, 3) [000094] ------------ | +--* CAST long <- int $300 N006 ( 1, 1) [000091] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N008 ( 1, 1) [000095] -------N---- | \--* CNS_INT long 3 $340 N010 ( 1, 1) [000097] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 ***** BB02 STMT00008 (IL ???... ???) N016 ( 14, 18) [000037] -A-XG---R--- * ASG ref N015 ( 1, 1) [000036] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N014 ( 14, 18) [000111] ---XG------- \--* COMMA ref N004 ( 8, 11) [000104] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $195 N001 ( 1, 1) [000031] ------------ | +--* LCL_VAR int V08 loc2 u:3 $280 N003 ( 3, 3) [000103] ---X-------- | \--* ARR_LENGTH int $1c0 N002 ( 1, 1) [000086] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 $83 N013 ( 6, 7) [000087] a---G------- \--* IND ref N012 ( 5, 6) [000110] -------N---- \--* ADD byref $3c1 N005 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 u:1 $83 N011 ( 4, 5) [000109] -------N---- \--* ADD long $302 N009 ( 3, 4) [000107] -------N---- +--* LSH long $301 N007 ( 2, 3) [000105] ------------ | +--* CAST long <- int $300 N006 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N008 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 $340 N010 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 ***** BB02 STMT00009 (IL 0x023...0x024) N003 ( 5, 4) [000040] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V11 loc5 N001 ( 1, 1) [000038] ------------ \--* CNS_INT ref null $VN.Null ***** BB02 STMT00010 (IL 0x026...0x034) N017 ( 29, 26) [000052] --CXG------- * JTRUE void N016 ( 27, 24) [000051] J-CXG--N---- \--* EQ int $1c7 N014 ( 25, 22) [000049] --CXG------- +--* CAST int <- bool <- int $1c6 N013 ( 24, 20) [000048] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 N007 ( 3, 3) [000047] ------------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 $481 N008 ( 1, 1) [000041] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 $80 N009 ( 1, 1) [000042] ------------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 u:1 $81 N010 ( 1, 1) [000043] ------------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 u:1 $82 N015 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} ***** BB03 STMT00021 (IL ???... ???) N005 ( 0, 0) [000142] -A------R--- * ASG bool N004 ( 0, 0) [000140] D------N---- +--* LCL_VAR bool V06 loc0 d:6 N003 ( 0, 0) [000141] ------------ \--* PHI bool N001 ( 0, 0) [000147] ------------ pred BB06 +--* PHI_ARG bool V06 loc0 u:5 $40 N002 ( 0, 0) [000146] ------------ pred BB02 \--* PHI_ARG bool V06 loc0 u:4 $241 ***** BB03 STMT00011 (IL 0x038...0x043) N011 ( 24, 18) [000060] --CXG------- * JTRUE void N010 ( 22, 16) [000059] J-CXG--N---- \--* NE int $1c9 N008 ( 20, 14) [000057] --CXG------- +--* CAST int <- bool <- int $1c8 N007 ( 19, 12) [000056] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 N004 ( 3, 2) [000053] ----G------- arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 $500 N005 ( 1, 1) [000054] ------------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 u:1 $c0 N009 ( 1, 1) [000058] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} ***** BB04 STMT00018 (IL ???... ???) N005 ( 0, 0) [000133] -A------R--- * ASG bool N004 ( 0, 0) [000131] D------N---- +--* LCL_VAR bool V06 loc0 d:8 N003 ( 0, 0) [000132] ------------ \--* PHI bool N001 ( 0, 0) [000149] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:7 $40 N002 ( 0, 0) [000148] ------------ pred BB03 \--* PHI_ARG bool V06 loc0 u:6 $242 ***** BB04 STMT00012 (IL 0x047...0x04A) N005 ( 3, 3) [000065] -A------R--- * ASG int $1ca N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 $1ca N003 ( 3, 3) [000063] ------------ \--* ADD int $1ca N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00004 (IL 0x04B...0x04D) N004 ( 5, 5) [000019] ------------ * JTRUE void N003 ( 3, 3) [000018] J------N---- \--* LE int $1cb N001 ( 1, 1) [000016] ------------ +--* LCL_VAR int V08 loc2 u:4 $1ca N002 ( 1, 1) [000017] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} ***** BB05 STMT00019 (IL ???... ???) N005 ( 0, 0) [000136] -A------R--- * ASG bool N004 ( 0, 0) [000134] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000135] ------------ \--* PHI bool N001 ( 0, 0) [000150] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB05 STMT00015 (IL 0x04F...0x050) N002 ( 4, 3) [000073] ------------ * RETURN int $103 N001 ( 3, 2) [000072] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) $240 ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} ***** BB06 STMT00014 (IL 0x036...0x037) N003 ( 5, 4) [000071] -A------R--- * ASG int $40 N002 ( 3, 2) [000070] D------N---- +--* LCL_VAR int V06 loc0 d:5 $40 N001 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} ***** BB07 STMT00013 (IL 0x045...0x046) N003 ( 5, 4) [000068] -A------R--- * ASG int $40 N002 ( 3, 2) [000067] D------N---- +--* LCL_VAR int V06 loc0 d:7 $40 N001 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- GenTreeNode creates assertion: N002 ( 3, 3) [000077] ---XG------- * ARR_LENGTH int $1c0 In BB01 New Global Constant Assertion: (131, 0) ($83,$0) V13.01 != null index=#01, mask=0000000000000001 After constant propagation on [000125]: STMT00016 (IL 0x04B... ???) N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* GT int $1c3 [000153] ------------ +--* CNS_INT int 0 $40 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 fgMorphTree (before 88): N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* GT int $1c3 [000153] ------------ +--* CNS_INT int 0 $40 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 fgMorphTree (before 89): N003 ( 3, 3) [000124] J------N---- * GT int $1c3 [000153] ------------ +--* CNS_INT int 0 $40 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 fgMorphTree (before 90): [000153] ------------ * CNS_INT int 0 $40 fgMorphTree (after 90): [000153] ------------ * CNS_INT int 0 $40 fgMorphTree (before 91): N002 ( 1, 1) [000126] ------------ * LCL_VAR int V07 loc1 u:2 $1c1 fgMorphTree (after 91): N002 ( 1, 1) [000126] ------------ * LCL_VAR int V07 loc1 u:2 $1c1 fgMorphTree (after 89): N003 ( 3, 3) [000124] J------N---- * GT int $1c3 [000153] ------------ +--* CNS_INT int 0 $40 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 fgMorphTree (after 88): N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* GT int $1c3 [000153] ------------ +--* CNS_INT int 0 $40 N002 ( 1, 1) [000126] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 optVNAssertionPropCurStmt morphed tree: N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* LT int $1c3 N001 ( 1, 1) [000126] ------------ +--* LCL_VAR int V07 loc1 u:2 $1c1 N002 ( 1, 1) [000153] ------------ \--* CNS_INT int 0 $40 GenTreeNode creates assertion: N004 ( 5, 5) [000127] ------------ * JTRUE void In BB01 New Global Constant Assertion: (451, 64) ($1c3,$40) Oper_Bnd { {IntCns 0} GT {ARR_LENGTH($83)}ADD {IntCns -1}} is not {IntCns 0} index=#02, mask=0000000000000002 GenTreeNode creates assertion: N004 ( 5, 5) [000127] ------------ * JTRUE void In BB01 New Global Constant Assertion: (451, 64) ($1c3,$40) Oper_Bnd { {IntCns 0} GT {ARR_LENGTH($83)}ADD {IntCns -1}} is {IntCns 0} index=#03, mask=0000000000000004 GenTreeNode creates assertion: N003 ( 3, 3) [000092] ---X-------- * ARR_LENGTH int $1c5 In BB02 New Global Constant Assertion: (132, 0) ($84,$0) V14.01 != null index=#04, mask=0000000000000008 GenTreeNode creates assertion: N004 ( 8, 11) [000093] ---X-------- * ARR_BOUNDS_CHECK_Rng void $18a In BB02 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {PhiDef($8, $3, $1c4)};len: {ARR_LENGTH($84)}] in range index=#05, mask=0000000000000010 GenTreeNode creates assertion: N004 ( 8, 11) [000104] ---X-------- * ARR_BOUNDS_CHECK_Rng void $195 In BB02 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {PhiDef($8, $3, $1c4)};len: {ARR_LENGTH($83)}] in range index=#06, mask=0000000000000020 GenTreeNode creates assertion: N004 ( 5, 5) [000019] ------------ * JTRUE void In BB04 New Global Constant Assertion: (459, 64) ($1cb,$40) Oper_Bnd { {ADD($41, $280)} LE {ARR_LENGTH($83)}ADD {IntCns -1}} is not {IntCns 0} index=#07, mask=0000000000000040 GenTreeNode creates assertion: N004 ( 5, 5) [000019] ------------ * JTRUE void In BB04 New Global Constant Assertion: (459, 64) ($1cb,$40) Oper_Bnd { {ADD($41, $280)} LE {ARR_LENGTH($83)}ADD {IntCns -1}} is {IntCns 0} index=#08, mask=0000000000000080 BB01 valueGen = 0000000000000005 => BB05 valueGen = 0000000000000003, BB02 valueGen = 0000000000000039 => BB06 valueGen = 0000000000000039, BB03 valueGen = 0000000000000000 => BB07 valueGen = 0000000000000000, BB04 valueGen = 0000000000000080 => BB02 valueGen = 0000000000000040, BB05 valueGen = 0000000000000000 BB06 valueGen = 0000000000000000 BB07 valueGen = 0000000000000000 AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000 AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000 AssertionPropCallback::Changed : BB01 before out -> 00000000000000FF; after out -> 0000000000000005; jumpDest before out -> 00000000000000FF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB02 in -> 00000000000000FF AssertionPropCallback::Merge : BB02 in -> 00000000000000FF, predBlock BB01 out -> 0000000000000005 AssertionPropCallback::Merge : BB02 in -> 0000000000000005, predBlock BB04 out -> 00000000000000FF AssertionPropCallback::EndMerge : BB02 in -> 0000000000000005 AssertionPropCallback::Changed : BB02 before out -> 00000000000000FF; after out -> 000000000000003D; jumpDest before out -> 00000000000000FF; jumpDest after out -> 000000000000003D; AssertionPropCallback::StartMerge: BB05 in -> 00000000000000FF AssertionPropCallback::Merge : BB05 in -> 00000000000000FF, predBlock BB01 out -> 0000000000000005 AssertionPropCallback::Merge : BB05 in -> 0000000000000003, predBlock BB04 out -> 00000000000000FF AssertionPropCallback::EndMerge : BB05 in -> 0000000000000003 AssertionPropCallback::Changed : BB05 before out -> 00000000000000FF; after out -> 0000000000000003; jumpDest before out -> 00000000000000FF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB03 in -> 00000000000000FF AssertionPropCallback::Merge : BB03 in -> 00000000000000FF, predBlock BB02 out -> 000000000000003D AssertionPropCallback::Merge : BB03 in -> 000000000000003D, predBlock BB06 out -> 00000000000000FF AssertionPropCallback::EndMerge : BB03 in -> 000000000000003D AssertionPropCallback::Changed : BB03 before out -> 00000000000000FF; after out -> 000000000000003D; jumpDest before out -> 00000000000000FF; jumpDest after out -> 000000000000003D; AssertionPropCallback::StartMerge: BB06 in -> 00000000000000FF AssertionPropCallback::Merge : BB06 in -> 00000000000000FF, predBlock BB02 out -> 000000000000003D AssertionPropCallback::EndMerge : BB06 in -> 000000000000003D AssertionPropCallback::Changed : BB06 before out -> 00000000000000FF; after out -> 000000000000003D; jumpDest before out -> 00000000000000FF; jumpDest after out -> 000000000000003D; AssertionPropCallback::StartMerge: BB04 in -> 00000000000000FF AssertionPropCallback::Merge : BB04 in -> 00000000000000FF, predBlock BB03 out -> 000000000000003D AssertionPropCallback::Merge : BB04 in -> 000000000000003D, predBlock BB07 out -> 00000000000000FF AssertionPropCallback::EndMerge : BB04 in -> 000000000000003D AssertionPropCallback::Changed : BB04 before out -> 00000000000000FF; after out -> 00000000000000BD; jumpDest before out -> 00000000000000FF; jumpDest after out -> 000000000000007D; AssertionPropCallback::StartMerge: BB07 in -> 00000000000000FF AssertionPropCallback::Merge : BB07 in -> 00000000000000FF, predBlock BB03 out -> 000000000000003D AssertionPropCallback::EndMerge : BB07 in -> 000000000000003D AssertionPropCallback::Changed : BB07 before out -> 00000000000000FF; after out -> 000000000000003D; jumpDest before out -> 00000000000000FF; jumpDest after out -> 000000000000003D; AssertionPropCallback::StartMerge: BB03 in -> 000000000000003D AssertionPropCallback::Merge : BB03 in -> 000000000000003D, predBlock BB02 out -> 000000000000003D AssertionPropCallback::Merge : BB03 in -> 000000000000003D, predBlock BB06 out -> 000000000000003D AssertionPropCallback::EndMerge : BB03 in -> 000000000000003D AssertionPropCallback::Unchanged : BB03 out -> 000000000000003D; jumpDest out -> 000000000000003D AssertionPropCallback::StartMerge: BB05 in -> 0000000000000003 AssertionPropCallback::Merge : BB05 in -> 0000000000000003, predBlock BB01 out -> 0000000000000005 AssertionPropCallback::Merge : BB05 in -> 0000000000000003, predBlock BB04 out -> 00000000000000BD AssertionPropCallback::EndMerge : BB05 in -> 0000000000000001 AssertionPropCallback::Changed : BB05 before out -> 0000000000000003; after out -> 0000000000000001; jumpDest before out -> 0000000000000003; jumpDest after out -> 0000000000000001; AssertionPropCallback::StartMerge: BB02 in -> 0000000000000005 AssertionPropCallback::Merge : BB02 in -> 0000000000000005, predBlock BB01 out -> 0000000000000005 AssertionPropCallback::Merge : BB02 in -> 0000000000000005, predBlock BB04 out -> 00000000000000BD AssertionPropCallback::EndMerge : BB02 in -> 0000000000000005 AssertionPropCallback::Unchanged : BB02 out -> 000000000000003D; jumpDest out -> 000000000000003D AssertionPropCallback::StartMerge: BB04 in -> 000000000000003D AssertionPropCallback::Merge : BB04 in -> 000000000000003D, predBlock BB03 out -> 000000000000003D AssertionPropCallback::Merge : BB04 in -> 000000000000003D, predBlock BB07 out -> 000000000000003D AssertionPropCallback::EndMerge : BB04 in -> 000000000000003D AssertionPropCallback::Unchanged : BB04 out -> 00000000000000BD; jumpDest out -> 000000000000007D BB01 valueIn = 0000000000000000 valueOut = 0000000000000005 => BB05 valueOut= 0000000000000003 BB02 valueIn = 0000000000000005 valueOut = 000000000000003D => BB06 valueOut= 000000000000003D BB03 valueIn = 000000000000003D valueOut = 000000000000003D => BB07 valueOut= 000000000000003D BB04 valueIn = 000000000000003D valueOut = 00000000000000BD => BB02 valueOut= 000000000000007D BB05 valueIn = 0000000000000001 valueOut = 0000000000000001 BB06 valueIn = 000000000000003D valueOut = 000000000000003D BB07 valueIn = 000000000000003D valueOut = 000000000000003D Propagating 0000000000000000 assertions for BB01, stmt STMT00001, tree [000006], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00001, tree [000007], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00001, tree [000008], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000076], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00002, tree [000077], tree -> 1 Propagating 0000000000000001 assertions for BB01, stmt STMT00002, tree [000009], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00002, tree [000010], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00002, tree [000011], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00002, tree [000012], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000013], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000014], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00003, tree [000015], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00016, tree [000126], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00016, tree [000153], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00016, tree [000124], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00016, tree [000127], tree -> 2 Propagating 0000000000000005 assertions for BB02, stmt STMT00006, tree [000022], tree -> 0 Propagating 0000000000000005 assertions for BB02, stmt STMT00006, tree [000081], tree -> 0 Propagating 0000000000000005 assertions for BB02, stmt STMT00006, tree [000092], tree -> 4 Propagating 000000000000000D assertions for BB02, stmt STMT00006, tree [000093], tree -> 5 Propagating 000000000000001D assertions for BB02, stmt STMT00006, tree [000090], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00006, tree [000091], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00006, tree [000094], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00006, tree [000095], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00006, tree [000096], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00006, tree [000097], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00006, tree [000098], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00006, tree [000099], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00006, tree [000082], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00006, tree [000100], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00006, tree [000027], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00006, tree [000028], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00008, tree [000031], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00008, tree [000086], tree -> 0 Propagating 000000000000001D assertions for BB02, stmt STMT00008, tree [000103], tree -> 1 Propagating 000000000000001D assertions for BB02, stmt STMT00008, tree [000104], tree -> 6 Propagating 000000000000003D assertions for BB02, stmt STMT00008, tree [000101], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00008, tree [000102], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00008, tree [000105], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00008, tree [000106], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00008, tree [000107], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00008, tree [000108], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00008, tree [000109], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00008, tree [000110], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00008, tree [000087], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00008, tree [000111], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00008, tree [000036], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00008, tree [000037], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00009, tree [000038], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00009, tree [000039], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00009, tree [000040], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000113], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000114], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000115], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000116], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000117], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000112], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000047], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000041], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000042], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000043], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000044], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000045], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000048], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000049], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000050], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000051], tree -> 0 Propagating 000000000000003D assertions for BB02, stmt STMT00010, tree [000052], tree -> 0 Propagating 000000000000003D assertions for BB03, stmt STMT00011, tree [000119], tree -> 0 Propagating 000000000000003D assertions for BB03, stmt STMT00011, tree [000120], tree -> 0 Propagating 000000000000003D assertions for BB03, stmt STMT00011, tree [000121], tree -> 0 Propagating 000000000000003D assertions for BB03, stmt STMT00011, tree [000053], tree -> 0 Propagating 000000000000003D assertions for BB03, stmt STMT00011, tree [000054], tree -> 0 Propagating 000000000000003D assertions for BB03, stmt STMT00011, tree [000055], tree -> 0 Propagating 000000000000003D assertions for BB03, stmt STMT00011, tree [000056], tree -> 0 Propagating 000000000000003D assertions for BB03, stmt STMT00011, tree [000057], tree -> 0 Propagating 000000000000003D assertions for BB03, stmt STMT00011, tree [000058], tree -> 0 Propagating 000000000000003D assertions for BB03, stmt STMT00011, tree [000059], tree -> 0 Propagating 000000000000003D assertions for BB03, stmt STMT00011, tree [000060], tree -> 0 Propagating 000000000000003D assertions for BB04, stmt STMT00012, tree [000061], tree -> 0 Propagating 000000000000003D assertions for BB04, stmt STMT00012, tree [000062], tree -> 0 Propagating 000000000000003D assertions for BB04, stmt STMT00012, tree [000063], tree -> 0 Propagating 000000000000003D assertions for BB04, stmt STMT00012, tree [000064], tree -> 0 Propagating 000000000000003D assertions for BB04, stmt STMT00012, tree [000065], tree -> 0 Propagating 000000000000003D assertions for BB04, stmt STMT00004, tree [000016], tree -> 0 Propagating 000000000000003D assertions for BB04, stmt STMT00004, tree [000017], tree -> 0 Propagating 000000000000003D assertions for BB04, stmt STMT00004, tree [000018], tree -> 0 Propagating 000000000000003D assertions for BB04, stmt STMT00004, tree [000019], tree -> 7 Propagating 0000000000000001 assertions for BB05, stmt STMT00015, tree [000072], tree -> 0 Propagating 0000000000000001 assertions for BB05, stmt STMT00015, tree [000073], tree -> 0 Propagating 000000000000003D assertions for BB06, stmt STMT00014, tree [000069], tree -> 0 Propagating 000000000000003D assertions for BB06, stmt STMT00014, tree [000070], tree -> 0 Propagating 000000000000003D assertions for BB06, stmt STMT00014, tree [000071], tree -> 0 Propagating 000000000000003D assertions for BB07, stmt STMT00013, tree [000066], tree -> 0 Propagating 000000000000003D assertions for BB07, stmt STMT00013, tree [000067], tree -> 0 Propagating 000000000000003D assertions for BB07, stmt STMT00013, tree [000068], tree -> 0 *************** In fgDebugCheckBBlist *************** Finishing PHASE Assertion prop *************** Starting PHASE Optimize index checks *************** In OptimizeRangeChecks() Blocks/trees before phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00001 (IL ???... ???) N003 ( 5, 4) [000008] -A------R--- * ASG int $41 N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR int V06 loc0 d:2 $41 N001 ( 1, 1) [000006] ------------ \--* CNS_INT int 1 $41 ***** BB01 STMT00002 (IL ???...0x00B) N006 ( 5, 5) [000012] -A-XG---R--- * ASG int $1c2 N005 ( 1, 1) [000011] D------N---- +--* LCL_VAR int V07 loc1 d:2 $1c1 N004 ( 5, 5) [000010] ---XG------- \--* ADD int $1c2 N002 ( 3, 3) [000077] ---XG------- +--* ARR_LENGTH int $1c0 N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 $83 N003 ( 1, 1) [000009] ------------ \--* CNS_INT int -1 $46 ***** BB01 STMT00003 (IL 0x00C...0x00D) N003 ( 1, 3) [000015] -A------R--- * ASG int $40 N002 ( 1, 1) [000014] D------N---- +--* LCL_VAR int V08 loc2 d:2 $40 N001 ( 1, 1) [000013] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00016 (IL 0x04B... ???) N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* LT int $1c3 N001 ( 1, 1) [000126] ------------ +--* LCL_VAR int V07 loc1 u:2 $1c1 N002 ( 1, 1) [000153] ------------ \--* CNS_INT int 0 $40 ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} ***** BB02 STMT00020 (IL ???... ???) N005 ( 0, 0) [000139] -A------R--- * ASG bool N004 ( 0, 0) [000137] D------N---- +--* LCL_VAR bool V06 loc0 d:4 N003 ( 0, 0) [000138] ------------ \--* PHI bool N001 ( 0, 0) [000151] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB02 STMT00017 (IL ???... ???) N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 ***** BB02 STMT00006 (IL ???... ???) N016 ( 18, 21) [000028] -A-XG---R--- * ASG ref N015 ( 3, 2) [000027] D------N---- +--* LCL_VAR ref V09 loc3 d:2 N014 ( 14, 18) [000100] ---XG------- \--* COMMA ref N004 ( 8, 11) [000093] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $18a N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR int V08 loc2 u:3 $280 N003 ( 3, 3) [000092] ---X-------- | \--* ARR_LENGTH int $1c5 N002 ( 1, 1) [000081] ------------ | \--* LCL_VAR ref V14 tmp2 u:1 $84 N013 ( 6, 7) [000082] a---G------- \--* IND ref N012 ( 5, 6) [000099] -------N---- \--* ADD byref $3c0 N005 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V14 tmp2 u:1 $84 N011 ( 4, 5) [000098] -------N---- \--* ADD long $302 N009 ( 3, 4) [000096] -------N---- +--* LSH long $301 N007 ( 2, 3) [000094] ------------ | +--* CAST long <- int $300 N006 ( 1, 1) [000091] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N008 ( 1, 1) [000095] -------N---- | \--* CNS_INT long 3 $340 N010 ( 1, 1) [000097] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 ***** BB02 STMT00008 (IL ???... ???) N016 ( 14, 18) [000037] -A-XG---R--- * ASG ref N015 ( 1, 1) [000036] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N014 ( 14, 18) [000111] ---XG------- \--* COMMA ref N004 ( 8, 11) [000104] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $195 N001 ( 1, 1) [000031] ------------ | +--* LCL_VAR int V08 loc2 u:3 $280 N003 ( 3, 3) [000103] ---X-------- | \--* ARR_LENGTH int $1c0 N002 ( 1, 1) [000086] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 $83 N013 ( 6, 7) [000087] a---G------- \--* IND ref N012 ( 5, 6) [000110] -------N---- \--* ADD byref $3c1 N005 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 u:1 $83 N011 ( 4, 5) [000109] -------N---- \--* ADD long $302 N009 ( 3, 4) [000107] -------N---- +--* LSH long $301 N007 ( 2, 3) [000105] ------------ | +--* CAST long <- int $300 N006 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N008 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 $340 N010 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 ***** BB02 STMT00009 (IL 0x023...0x024) N003 ( 5, 4) [000040] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V11 loc5 N001 ( 1, 1) [000038] ------------ \--* CNS_INT ref null $VN.Null ***** BB02 STMT00010 (IL 0x026...0x034) N017 ( 29, 26) [000052] --CXG------- * JTRUE void N016 ( 27, 24) [000051] J-CXG--N---- \--* EQ int $1c7 N014 ( 25, 22) [000049] --CXG------- +--* CAST int <- bool <- int $1c6 N013 ( 24, 20) [000048] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 N007 ( 3, 3) [000047] ------------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 $481 N008 ( 1, 1) [000041] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 $80 N009 ( 1, 1) [000042] ------------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 u:1 $81 N010 ( 1, 1) [000043] ------------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 u:1 $82 N015 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} ***** BB03 STMT00021 (IL ???... ???) N005 ( 0, 0) [000142] -A------R--- * ASG bool N004 ( 0, 0) [000140] D------N---- +--* LCL_VAR bool V06 loc0 d:6 N003 ( 0, 0) [000141] ------------ \--* PHI bool N001 ( 0, 0) [000147] ------------ pred BB06 +--* PHI_ARG bool V06 loc0 u:5 $40 N002 ( 0, 0) [000146] ------------ pred BB02 \--* PHI_ARG bool V06 loc0 u:4 $241 ***** BB03 STMT00011 (IL 0x038...0x043) N011 ( 24, 18) [000060] --CXG------- * JTRUE void N010 ( 22, 16) [000059] J-CXG--N---- \--* NE int $1c9 N008 ( 20, 14) [000057] --CXG------- +--* CAST int <- bool <- int $1c8 N007 ( 19, 12) [000056] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 N004 ( 3, 2) [000053] ----G------- arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 $500 N005 ( 1, 1) [000054] ------------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 u:1 $c0 N009 ( 1, 1) [000058] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} ***** BB04 STMT00018 (IL ???... ???) N005 ( 0, 0) [000133] -A------R--- * ASG bool N004 ( 0, 0) [000131] D------N---- +--* LCL_VAR bool V06 loc0 d:8 N003 ( 0, 0) [000132] ------------ \--* PHI bool N001 ( 0, 0) [000149] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:7 $40 N002 ( 0, 0) [000148] ------------ pred BB03 \--* PHI_ARG bool V06 loc0 u:6 $242 ***** BB04 STMT00012 (IL 0x047...0x04A) N005 ( 3, 3) [000065] -A------R--- * ASG int $1ca N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 $1ca N003 ( 3, 3) [000063] ------------ \--* ADD int $1ca N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00004 (IL 0x04B...0x04D) N004 ( 5, 5) [000019] ------------ * JTRUE void N003 ( 3, 3) [000018] J------N---- \--* LE int $1cb N001 ( 1, 1) [000016] ------------ +--* LCL_VAR int V08 loc2 u:4 $1ca N002 ( 1, 1) [000017] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} ***** BB05 STMT00019 (IL ???... ???) N005 ( 0, 0) [000136] -A------R--- * ASG bool N004 ( 0, 0) [000134] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000135] ------------ \--* PHI bool N001 ( 0, 0) [000150] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB05 STMT00015 (IL 0x04F...0x050) N002 ( 4, 3) [000073] ------------ * RETURN int $103 N001 ( 3, 2) [000072] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) $240 ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} ***** BB06 STMT00014 (IL 0x036...0x037) N003 ( 5, 4) [000071] -A------R--- * ASG int $40 N002 ( 3, 2) [000070] D------N---- +--* LCL_VAR int V06 loc0 d:5 $40 N001 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} ***** BB07 STMT00013 (IL 0x045...0x046) N003 ( 5, 4) [000068] -A------R--- * ASG int $40 N002 ( 3, 2) [000067] D------N---- +--* LCL_VAR int V06 loc0 d:7 $40 N001 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- ArrSize for lengthVN:141 = 0 [RangeCheck::GetRange] BB02N001 ( 1, 1) [000022] ------------ * LCL_VAR int V08 loc2 u:3 $280 { ---------------------------------------------------- N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 ---------------------------------------------------- [RangeCheck::GetRange] BB02N003 ( 0, 0) [000129] ------------ * PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 { [RangeCheck::GetRange] BB02N001 ( 0, 0) [000152] ------------ * PHI_ARG int V08 loc2 u:4 { ---------------------------------------------------- N005 ( 3, 3) [000065] -A------R--- * ASG int $1ca N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 $1ca N003 ( 3, 3) [000063] ------------ \--* ADD int $1ca N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 $41 ---------------------------------------------------- [RangeCheck::GetRange] BB04N003 ( 3, 3) [000063] ------------ * ADD int $1ca N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 $41 { [RangeCheck::GetRange] BB04N001 ( 1, 1) [000061] ------------ * LCL_VAR int V08 loc2 u:3 (last use) $280 { ---------------------------------------------------- N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 ---------------------------------------------------- [RangeCheck::GetRange] BB02N003 ( 0, 0) [000129] ------------ * PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 { PhiArg [000152] is already being computed Merging assertions from pred edges of BB02 for op [000152] $ffffffff Merge assertions from pred BB04 JTrue edge: 000000000000007D Constant Assertion: (459, 64) ($1cb,$40) Oper_Bnd { {ADD($41, $280)} LE {ARR_LENGTH($83)}ADD {IntCns -1}} is not {IntCns 0} index=#07, mask=0000000000000040 The range after edge merging: Merging ranges : [RangeCheck::GetRange] BB02N002 ( 0, 0) [000144] ------------ * PHI_ARG int V08 loc2 u:2 $40 { Computed Range [000144] => <0, 0> } Merging assertions from pred edges of BB02 for op [000144] $40 Merge assertions from pred BB01 edge: 0000000000000005 Constant Assertion: (451, 64) ($1c3,$40) Oper_Bnd { {IntCns 0} GT {ARR_LENGTH($83)}ADD {IntCns -1}} is {IntCns 0} index=#03, mask=0000000000000004 Merging ranges <0, 0>: Computed Range [000129] => } Merge assertions from BB04:000000000000003D for assignment about [000128] done merging Merging assertions from pred edges of BB04 for op [000061] $280 Computed Range [000061] => } Merging assertions from pred edges of BB04 for op [000061] $280 [RangeCheck::GetRange] BB04N002 ( 1, 1) [000062] ------------ * CNS_INT int 1 $41 { Computed Range [000062] => <1, 1> } Merging assertions from pred edges of BB04 for op [000062] $41 BinOp add ranges <1, 1> = Computed Range [000063] => } Merge assertions from BB02:0000000000000005 for assignment about [000064] done merging Merging assertions from pred edges of BB02 for op [000152] $ffffffff Merge assertions from pred BB04 JTrue edge: 000000000000007D Constant Assertion: (459, 64) ($1cb,$40) Oper_Bnd { {ADD($41, $280)} LE {ARR_LENGTH($83)}ADD {IntCns -1}} is not {IntCns 0} index=#07, mask=0000000000000040 The range after edge merging: Computed Range [000152] => } Merging assertions from pred edges of BB02 for op [000152] $ffffffff Merge assertions from pred BB04 JTrue edge: 000000000000007D Constant Assertion: (459, 64) ($1cb,$40) Oper_Bnd { {ADD($41, $280)} LE {ARR_LENGTH($83)}ADD {IntCns -1}} is not {IntCns 0} index=#07, mask=0000000000000040 The range after edge merging: Merging ranges : [RangeCheck::GetRange] BB02N002 ( 0, 0) [000144] ------------ * PHI_ARG int V08 loc2 u:2 $40 { Cached Range [000144] => <0, 0> } Merging assertions from pred edges of BB02 for op [000144] $40 Merge assertions from pred BB01 edge: 0000000000000005 Constant Assertion: (451, 64) ($1c3,$40) Oper_Bnd { {IntCns 0} GT {ARR_LENGTH($83)}ADD {IntCns -1}} is {IntCns 0} index=#03, mask=0000000000000004 Merging ranges <0, 0>: Computed Range [000129] => } Merge assertions from BB02:0000000000000005 for assignment about [000128] done merging Merging assertions from pred edges of BB02 for op [000022] $280 Computed Range [000022] => } ArrSize for lengthVN:140 = 0 [RangeCheck::GetRange] BB02N001 ( 1, 1) [000031] ------------ * LCL_VAR int V08 loc2 u:3 $280 { ---------------------------------------------------- N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 ---------------------------------------------------- [RangeCheck::GetRange] BB02N003 ( 0, 0) [000129] ------------ * PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 { [RangeCheck::GetRange] BB02N001 ( 0, 0) [000152] ------------ * PHI_ARG int V08 loc2 u:4 { ---------------------------------------------------- N005 ( 3, 3) [000065] -A------R--- * ASG int $1ca N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 $1ca N003 ( 3, 3) [000063] ------------ \--* ADD int $1ca N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 $41 ---------------------------------------------------- [RangeCheck::GetRange] BB04N003 ( 3, 3) [000063] ------------ * ADD int $1ca N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 $41 { [RangeCheck::GetRange] BB04N001 ( 1, 1) [000061] ------------ * LCL_VAR int V08 loc2 u:3 (last use) $280 { ---------------------------------------------------- N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 ---------------------------------------------------- [RangeCheck::GetRange] BB02N003 ( 0, 0) [000129] ------------ * PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 { PhiArg [000152] is already being computed Merging assertions from pred edges of BB02 for op [000152] $ffffffff Merge assertions from pred BB04 JTrue edge: 000000000000007D Constant Assertion: (459, 64) ($1cb,$40) Oper_Bnd { {ADD($41, $280)} LE {ARR_LENGTH($83)}ADD {IntCns -1}} is not {IntCns 0} index=#07, mask=0000000000000040 The range after edge merging: Merging ranges : [RangeCheck::GetRange] BB02N002 ( 0, 0) [000144] ------------ * PHI_ARG int V08 loc2 u:2 $40 { Computed Range [000144] => <0, 0> } Merging assertions from pred edges of BB02 for op [000144] $40 Merge assertions from pred BB01 edge: 0000000000000005 Constant Assertion: (451, 64) ($1c3,$40) Oper_Bnd { {IntCns 0} GT {ARR_LENGTH($83)}ADD {IntCns -1}} is {IntCns 0} index=#03, mask=0000000000000004 The range after edge merging:<0, $140 + -1> Merging ranges <0, $140 + -1>: Computed Range [000129] => } Merge assertions from BB04:000000000000003D for assignment about [000128] done merging Merging assertions from pred edges of BB04 for op [000061] $280 Computed Range [000061] => } Merging assertions from pred edges of BB04 for op [000061] $280 [RangeCheck::GetRange] BB04N002 ( 1, 1) [000062] ------------ * CNS_INT int 1 $41 { Computed Range [000062] => <1, 1> } Merging assertions from pred edges of BB04 for op [000062] $41 BinOp add ranges <1, 1> = Computed Range [000063] => } Merge assertions from BB02:0000000000000005 for assignment about [000064] done merging Merging assertions from pred edges of BB02 for op [000152] $ffffffff Merge assertions from pred BB04 JTrue edge: 000000000000007D Constant Assertion: (459, 64) ($1cb,$40) Oper_Bnd { {ADD($41, $280)} LE {ARR_LENGTH($83)}ADD {IntCns -1}} is not {IntCns 0} index=#07, mask=0000000000000040 The range after edge merging: Computed Range [000152] => } Merging assertions from pred edges of BB02 for op [000152] $ffffffff Merge assertions from pred BB04 JTrue edge: 000000000000007D Constant Assertion: (459, 64) ($1cb,$40) Oper_Bnd { {ADD($41, $280)} LE {ARR_LENGTH($83)}ADD {IntCns -1}} is not {IntCns 0} index=#07, mask=0000000000000040 Bound limit -1 doesn't tighten current bound -1 Merging ranges : [RangeCheck::GetRange] BB02N002 ( 0, 0) [000144] ------------ * PHI_ARG int V08 loc2 u:2 $40 { Cached Range [000144] => <0, 0> } Merging assertions from pred edges of BB02 for op [000144] $40 Merge assertions from pred BB01 edge: 0000000000000005 Constant Assertion: (451, 64) ($1c3,$40) Oper_Bnd { {IntCns 0} GT {ARR_LENGTH($83)}ADD {IntCns -1}} is {IntCns 0} index=#03, mask=0000000000000004 The range after edge merging:<0, $140 + -1> Merging ranges <0, $140 + -1>: Computed Range [000129] => } Merge assertions from BB02:0000000000000005 for assignment about [000128] done merging Merging assertions from pred edges of BB02 for op [000031] $280 Computed Range [000031] => } Does overflow [000031]? Does overflow [000129]? Does overflow [000152]? Does overflow [000063]? Does overflow [000061]? Does overflow [000129]? Does overflow [000144]? [000144] does not overflow [000129] does not overflow [000061] does not overflow Does overflow [000062]? [000062] does not overflow Checking bin op overflow <1, 1> [000063] does not overflow [000152] does not overflow [000129] does not overflow [000031] does not overflow Range value [RangeCheck::Widen] BB02, [000031] [RangeCheck::IsMonotonicallyIncreasing] [000031] [RangeCheck::IsMonotonicallyIncreasing] [000129] [RangeCheck::IsMonotonicallyIncreasing] [000152] [RangeCheck::IsMonotonicallyIncreasing] [000063] [RangeCheck::IsBinOpMonotonicallyIncreasing] [000061], [000062] [RangeCheck::IsMonotonicallyIncreasing] [000061] [RangeCheck::IsMonotonicallyIncreasing] [000129] [RangeCheck::IsMonotonicallyIncreasing] [000144] [000031] is monotonically increasing. [RangeCheck::GetRange] BB02N001 ( 1, 1) [000031] ------------ * LCL_VAR int V08 loc2 u:3 $280 { ---------------------------------------------------- N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 ---------------------------------------------------- [RangeCheck::GetRange] BB02N003 ( 0, 0) [000129] ------------ * PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 { [RangeCheck::GetRange] BB02N001 ( 0, 0) [000152] ------------ * PHI_ARG int V08 loc2 u:4 { ---------------------------------------------------- N005 ( 3, 3) [000065] -A------R--- * ASG int $1ca N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 $1ca N003 ( 3, 3) [000063] ------------ \--* ADD int $1ca N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 $41 ---------------------------------------------------- [RangeCheck::GetRange] BB04N003 ( 3, 3) [000063] ------------ * ADD int $1ca N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 $41 { [RangeCheck::GetRange] BB04N001 ( 1, 1) [000061] ------------ * LCL_VAR int V08 loc2 u:3 (last use) $280 { ---------------------------------------------------- N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 ---------------------------------------------------- [RangeCheck::GetRange] BB02N003 ( 0, 0) [000129] ------------ * PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 { PhiArg [000152] is already being computed Merging assertions from pred edges of BB02 for op [000152] $ffffffff Merge assertions from pred BB04 JTrue edge: 000000000000007D Constant Assertion: (459, 64) ($1cb,$40) Oper_Bnd { {ADD($41, $280)} LE {ARR_LENGTH($83)}ADD {IntCns -1}} is not {IntCns 0} index=#07, mask=0000000000000040 The range after edge merging: Merging ranges : [RangeCheck::GetRange] BB02N002 ( 0, 0) [000144] ------------ * PHI_ARG int V08 loc2 u:2 $40 { Computed Range [000144] => <0, 0> } Merging assertions from pred edges of BB02 for op [000144] $40 Merge assertions from pred BB01 edge: 0000000000000005 Constant Assertion: (451, 64) ($1c3,$40) Oper_Bnd { {IntCns 0} GT {ARR_LENGTH($83)}ADD {IntCns -1}} is {IntCns 0} index=#03, mask=0000000000000004 The range after edge merging:<0, $140 + -1> Merging ranges <0, $140 + -1>:<0, $140 + -1> Computed Range [000129] => <0, $140 + -1> } Merge assertions from BB04:000000000000003D for assignment about [000128] done merging Merging assertions from pred edges of BB04 for op [000061] $280 Computed Range [000061] => <0, $140 + -1> } Merging assertions from pred edges of BB04 for op [000061] $280 [RangeCheck::GetRange] BB04N002 ( 1, 1) [000062] ------------ * CNS_INT int 1 $41 { Computed Range [000062] => <1, 1> } Merging assertions from pred edges of BB04 for op [000062] $41 BinOp add ranges <0, $140 + -1> <1, 1> = <1, $140 + 0> Computed Range [000063] => <1, $140 + 0> } Merge assertions from BB02:0000000000000005 for assignment about [000064] done merging Merging assertions from pred edges of BB02 for op [000152] $ffffffff Merge assertions from pred BB04 JTrue edge: 000000000000007D Constant Assertion: (459, 64) ($1cb,$40) Oper_Bnd { {ADD($41, $280)} LE {ARR_LENGTH($83)}ADD {IntCns -1}} is not {IntCns 0} index=#07, mask=0000000000000040 The range after edge merging:<1, $140 + -1> Computed Range [000152] => <1, $140 + -1> } Merging assertions from pred edges of BB02 for op [000152] $ffffffff Merge assertions from pred BB04 JTrue edge: 000000000000007D Constant Assertion: (459, 64) ($1cb,$40) Oper_Bnd { {ADD($41, $280)} LE {ARR_LENGTH($83)}ADD {IntCns -1}} is not {IntCns 0} index=#07, mask=0000000000000040 Bound limit -1 doesn't tighten current bound -1 Merging ranges <1, $140 + -1>:<1, $140 + -1> [RangeCheck::GetRange] BB02N002 ( 0, 0) [000144] ------------ * PHI_ARG int V08 loc2 u:2 $40 { Cached Range [000144] => <0, 0> } Merging assertions from pred edges of BB02 for op [000144] $40 Merge assertions from pred BB01 edge: 0000000000000005 Constant Assertion: (451, 64) ($1c3,$40) Oper_Bnd { {IntCns 0} GT {ARR_LENGTH($83)}ADD {IntCns -1}} is {IntCns 0} index=#03, mask=0000000000000004 The range after edge merging:<0, $140 + -1> Merging ranges <1, $140 + -1> <0, $140 + -1>:<0, $140 + -1> Computed Range [000129] => <0, $140 + -1> } Merge assertions from BB02:0000000000000005 for assignment about [000128] done merging Merging assertions from pred edges of BB02 for op [000031] $280 Computed Range [000031] => <0, $140 + -1> } <0, $140 + -1> BetweenBounds <0, [000103]> $140 upper bound is: {ARR_LENGTH($83)} Array size is: 0 [RangeCheck::OptimizeRangeCheck] Between bounds Before optRemoveRangeCheck: N014 ( 14, 18) [000111] ---XG------- * COMMA ref N004 ( 8, 11) [000104] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $195 N001 ( 1, 1) [000031] ------------ | +--* LCL_VAR int V08 loc2 u:3 $280 N003 ( 3, 3) [000103] ---X-------- | \--* ARR_LENGTH int $1c0 N002 ( 1, 1) [000086] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 $83 N013 ( 6, 7) [000087] a---G------- \--* IND ref N012 ( 5, 6) [000110] -------N---- \--* ADD byref $3c1 N005 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 u:1 $83 N011 ( 4, 5) [000109] -------N---- \--* ADD long $302 N009 ( 3, 4) [000107] -------N---- +--* LSH long $301 N007 ( 2, 3) [000105] ------------ | +--* CAST long <- int $300 N006 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N008 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 $340 N010 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 After optRemoveRangeCheck: N011 ( 6, 7) [000111] ----G--N---- * COMMA ref N001 ( 0, 0) [000154] ------------ +--* NOP void N010 ( 6, 7) [000087] a---G------- \--* IND ref N009 ( 5, 6) [000110] -------N---- \--* ADD byref $3c1 N002 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 u:1 $83 N008 ( 4, 5) [000109] -------N---- \--* ADD long $302 N006 ( 3, 4) [000107] -------N---- +--* LSH long $301 N004 ( 2, 3) [000105] ------------ | +--* CAST long <- int $300 N003 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N005 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 $340 N007 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 *************** Finishing PHASE Optimize index checks *************** Starting PHASE Determine first cold block *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block Trees before Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} ***** BB01 STMT00001 (IL ???... ???) N003 ( 5, 4) [000008] -A------R--- * ASG int $41 N002 ( 3, 2) [000007] D------N---- +--* LCL_VAR int V06 loc0 d:2 $41 N001 ( 1, 1) [000006] ------------ \--* CNS_INT int 1 $41 ***** BB01 STMT00002 (IL ???...0x00B) N006 ( 5, 5) [000012] -A-XG---R--- * ASG int $1c2 N005 ( 1, 1) [000011] D------N---- +--* LCL_VAR int V07 loc1 d:2 $1c1 N004 ( 5, 5) [000010] ---XG------- \--* ADD int $1c2 N002 ( 3, 3) [000077] ---XG------- +--* ARR_LENGTH int $1c0 N001 ( 1, 1) [000076] ------------ | \--* LCL_VAR ref V13 tmp1 u:1 $83 N003 ( 1, 1) [000009] ------------ \--* CNS_INT int -1 $46 ***** BB01 STMT00003 (IL 0x00C...0x00D) N003 ( 1, 3) [000015] -A------R--- * ASG int $40 N002 ( 1, 1) [000014] D------N---- +--* LCL_VAR int V08 loc2 d:2 $40 N001 ( 1, 1) [000013] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00016 (IL 0x04B... ???) N004 ( 5, 5) [000127] ------------ * JTRUE void N003 ( 3, 3) [000124] J------N---- \--* LT int $1c3 N001 ( 1, 1) [000126] ------------ +--* LCL_VAR int V07 loc1 u:2 $1c1 N002 ( 1, 1) [000153] ------------ \--* CNS_INT int 0 $40 ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} ***** BB02 STMT00020 (IL ???... ???) N005 ( 0, 0) [000139] -A------R--- * ASG bool N004 ( 0, 0) [000137] D------N---- +--* LCL_VAR bool V06 loc0 d:4 N003 ( 0, 0) [000138] ------------ \--* PHI bool N001 ( 0, 0) [000151] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB02 STMT00017 (IL ???... ???) N005 ( 0, 0) [000130] -A------R--- * ASG int N004 ( 0, 0) [000128] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000129] ------------ \--* PHI int N001 ( 0, 0) [000152] ------------ pred BB04 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ pred BB01 \--* PHI_ARG int V08 loc2 u:2 $40 ***** BB02 STMT00006 (IL ???... ???) N016 ( 18, 21) [000028] -A-XG---R--- * ASG ref N015 ( 3, 2) [000027] D------N---- +--* LCL_VAR ref V09 loc3 d:2 N014 ( 14, 18) [000100] ---XG------- \--* COMMA ref N004 ( 8, 11) [000093] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $18a N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR int V08 loc2 u:3 $280 N003 ( 3, 3) [000092] ---X-------- | \--* ARR_LENGTH int $1c5 N002 ( 1, 1) [000081] ------------ | \--* LCL_VAR ref V14 tmp2 u:1 $84 N013 ( 6, 7) [000082] a---G------- \--* IND ref N012 ( 5, 6) [000099] -------N---- \--* ADD byref $3c0 N005 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V14 tmp2 u:1 $84 N011 ( 4, 5) [000098] -------N---- \--* ADD long $302 N009 ( 3, 4) [000096] -------N---- +--* LSH long $301 N007 ( 2, 3) [000094] ------------ | +--* CAST long <- int $300 N006 ( 1, 1) [000091] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N008 ( 1, 1) [000095] -------N---- | \--* CNS_INT long 3 $340 N010 ( 1, 1) [000097] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 ***** BB02 STMT00008 (IL ???... ???) N013 ( 6, 7) [000037] -A--G---R--- * ASG ref N012 ( 1, 1) [000036] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N011 ( 6, 7) [000111] ----G--N---- \--* COMMA ref N001 ( 0, 0) [000154] ------------ +--* NOP void N010 ( 6, 7) [000087] a---G------- \--* IND ref N009 ( 5, 6) [000110] -------N---- \--* ADD byref $3c1 N002 ( 1, 1) [000101] ------------ +--* LCL_VAR ref V13 tmp1 u:1 $83 N008 ( 4, 5) [000109] -------N---- \--* ADD long $302 N006 ( 3, 4) [000107] -------N---- +--* LSH long $301 N004 ( 2, 3) [000105] ------------ | +--* CAST long <- int $300 N003 ( 1, 1) [000102] i----------- | | \--* LCL_VAR int V08 loc2 u:3 $280 N005 ( 1, 1) [000106] -------N---- | \--* CNS_INT long 3 $340 N007 ( 1, 1) [000108] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $342 ***** BB02 STMT00009 (IL 0x023...0x024) N003 ( 5, 4) [000040] -A--G---R--- * ASG ref $VN.Null N002 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V11 loc5 N001 ( 1, 1) [000038] ------------ \--* CNS_INT ref null $VN.Null ***** BB02 STMT00010 (IL 0x026...0x034) N017 ( 29, 26) [000052] --CXG------- * JTRUE void N016 ( 27, 24) [000051] J-CXG--N---- \--* EQ int $1c7 N014 ( 25, 22) [000049] --CXG------- +--* CAST int <- bool <- int $1c6 N013 ( 24, 20) [000048] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 N007 ( 3, 3) [000047] ------------ arg5 in r9 | +--* LCL_VAR_ADDR long V11 loc5 $481 N008 ( 1, 1) [000041] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 $80 N009 ( 1, 1) [000042] ------------ arg1 in rsi | +--* LCL_VAR ref V01 arg1 u:1 $81 N010 ( 1, 1) [000043] ------------ arg2 in rdx | +--* LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ arg3 in rcx | +--* LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ arg4 in r8 | \--* LCL_VAR ref V04 arg4 u:1 $82 N015 ( 1, 1) [000050] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} ***** BB03 STMT00021 (IL ???... ???) N005 ( 0, 0) [000142] -A------R--- * ASG bool N004 ( 0, 0) [000140] D------N---- +--* LCL_VAR bool V06 loc0 d:6 N003 ( 0, 0) [000141] ------------ \--* PHI bool N001 ( 0, 0) [000147] ------------ pred BB06 +--* PHI_ARG bool V06 loc0 u:5 $40 N002 ( 0, 0) [000146] ------------ pred BB02 \--* PHI_ARG bool V06 loc0 u:4 $241 ***** BB03 STMT00011 (IL 0x038...0x043) N011 ( 24, 18) [000060] --CXG------- * JTRUE void N010 ( 22, 16) [000059] J-CXG--N---- \--* NE int $1c9 N008 ( 20, 14) [000057] --CXG------- +--* CAST int <- bool <- int $1c8 N007 ( 19, 12) [000056] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 N004 ( 3, 2) [000053] ----G------- arg0 in rdi | +--* LCL_VAR ref (AX) V11 loc5 $500 N005 ( 1, 1) [000054] ------------ arg1 in rsi | +--* LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ arg2 in rdx | \--* LCL_VAR byref V05 arg5 u:1 $c0 N009 ( 1, 1) [000058] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} ***** BB04 STMT00018 (IL ???... ???) N005 ( 0, 0) [000133] -A------R--- * ASG bool N004 ( 0, 0) [000131] D------N---- +--* LCL_VAR bool V06 loc0 d:8 N003 ( 0, 0) [000132] ------------ \--* PHI bool N001 ( 0, 0) [000149] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:7 $40 N002 ( 0, 0) [000148] ------------ pred BB03 \--* PHI_ARG bool V06 loc0 u:6 $242 ***** BB04 STMT00012 (IL 0x047...0x04A) N005 ( 3, 3) [000065] -A------R--- * ASG int $1ca N004 ( 1, 1) [000064] D------N---- +--* LCL_VAR int V08 loc2 d:4 $1ca N003 ( 3, 3) [000063] ------------ \--* ADD int $1ca N001 ( 1, 1) [000061] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00004 (IL 0x04B...0x04D) N004 ( 5, 5) [000019] ------------ * JTRUE void N003 ( 3, 3) [000018] J------N---- \--* LE int $1cb N001 ( 1, 1) [000016] ------------ +--* LCL_VAR int V08 loc2 u:4 $1ca N002 ( 1, 1) [000017] ------------ \--* LCL_VAR int V07 loc1 u:2 $1c1 ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} ***** BB05 STMT00019 (IL ???... ???) N005 ( 0, 0) [000136] -A------R--- * ASG bool N004 ( 0, 0) [000134] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000135] ------------ \--* PHI bool N001 ( 0, 0) [000150] ------------ pred BB04 +--* PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ pred BB01 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB05 STMT00015 (IL 0x04F...0x050) N002 ( 4, 3) [000073] ------------ * RETURN int $103 N001 ( 3, 2) [000072] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) $240 ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} ***** BB06 STMT00014 (IL 0x036...0x037) N003 ( 5, 4) [000071] -A------R--- * ASG int $40 N002 ( 3, 2) [000070] D------N---- +--* LCL_VAR int V06 loc0 d:5 $40 N001 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} ***** BB07 STMT00013 (IL 0x045...0x046) N003 ( 5, 4) [000068] -A------R--- * ASG int $40 N002 ( 3, 2) [000067] D------N---- +--* LCL_VAR int V06 loc0 d:7 $40 N001 ( 1, 1) [000066] ------------ \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Rationalize IR rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000008] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 5, 5) [000012] DA-XG------- * STORE_LCL_VAR int V07 loc1 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000139] DA---------- * STORE_LCL_VAR bool V06 loc0 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000130] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N016 ( 18, 21) [000028] DA-XG------- * STORE_LCL_VAR ref V09 loc3 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N013 ( 6, 7) [000037] DA--G------- * STORE_LCL_VAR ref V10 loc4 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000040] DA--G------- * STORE_LCL_VAR ref (AX) V11 loc5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000142] DA---------- * STORE_LCL_VAR bool V06 loc0 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000133] DA---------- * STORE_LCL_VAR bool V06 loc0 d:8 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000136] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000071] DA---------- * STORE_LCL_VAR int V06 loc0 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000068] DA---------- * STORE_LCL_VAR int V06 loc0 d:7 *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC LIR BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC LIR BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC LIR BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC LIR BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC LIR BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC LIR BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} N001 ( 1, 1) [000006] ------------ t6 = CNS_INT int 1 $41 /--* t6 int N003 ( 5, 4) [000008] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000076] ------------ t76 = LCL_VAR ref V13 tmp1 u:1 $83 /--* t76 ref N002 ( 3, 3) [000077] ---XG------- t77 = * ARR_LENGTH int $1c0 N003 ( 1, 1) [000009] ------------ t9 = CNS_INT int -1 $46 /--* t77 int +--* t9 int N004 ( 5, 5) [000010] ---XG------- t10 = * ADD int $1c2 /--* t10 int N006 ( 5, 5) [000012] DA-XG------- * STORE_LCL_VAR int V07 loc1 d:2 [000155] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000013] ------------ t13 = CNS_INT int 0 $40 /--* t13 int N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 [000156] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR int V07 loc1 u:2 $1c1 N002 ( 1, 1) [000153] ------------ t153 = CNS_INT int 0 $40 /--* t126 int +--* t153 int N003 ( 3, 3) [000124] J------N---- t124 = * LT int $1c3 /--* t124 int N004 ( 5, 5) [000127] ------------ * JTRUE void ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} N001 ( 0, 0) [000151] ------------ t151 = PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ t143 = PHI_ARG bool V06 loc0 u:2 $41 /--* t151 bool +--* t143 bool N003 ( 0, 0) [000138] ------------ t138 = * PHI bool /--* t138 bool N005 ( 0, 0) [000139] DA---------- * STORE_LCL_VAR bool V06 loc0 d:4 N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ t144 = PHI_ARG int V08 loc2 u:2 $40 /--* t152 int +--* t144 int N003 ( 0, 0) [000129] ------------ t129 = * PHI int /--* t129 int N005 ( 0, 0) [000130] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V08 loc2 u:3 $280 N002 ( 1, 1) [000081] ------------ t81 = LCL_VAR ref V14 tmp2 u:1 $84 /--* t81 ref N003 ( 3, 3) [000092] ---X-------- t92 = * ARR_LENGTH int $1c5 /--* t22 int +--* t92 int N004 ( 8, 11) [000093] ---X-------- * ARR_BOUNDS_CHECK_Rng void $18a N005 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V14 tmp2 u:1 $84 N006 ( 1, 1) [000091] ------------ t91 = LCL_VAR int V08 loc2 u:3 $280 /--* t91 int N007 ( 2, 3) [000094] ------------ t94 = * CAST long <- int $300 N008 ( 1, 1) [000095] -------N---- t95 = CNS_INT long 3 $340 /--* t94 long +--* t95 long N009 ( 3, 4) [000096] -------N---- t96 = * LSH long $301 N010 ( 1, 1) [000097] ------------ t97 = CNS_INT long 16 Fseq[#FirstElem] $342 /--* t96 long +--* t97 long N011 ( 4, 5) [000098] -------N---- t98 = * ADD long $302 /--* t90 ref +--* t98 long N012 ( 5, 6) [000099] -------N---- t99 = * ADD byref $3c0 /--* t99 byref N013 ( 6, 7) [000082] a---G------- t82 = * IND ref /--* t82 ref N016 ( 18, 21) [000028] DA-XG------- * STORE_LCL_VAR ref V09 loc3 d:2 N002 ( 1, 1) [000101] ------------ t101 = LCL_VAR ref V13 tmp1 u:1 $83 N003 ( 1, 1) [000102] ------------ t102 = LCL_VAR int V08 loc2 u:3 $280 /--* t102 int N004 ( 2, 3) [000105] ------------ t105 = * CAST long <- int $300 N005 ( 1, 1) [000106] -------N---- t106 = CNS_INT long 3 $340 /--* t105 long +--* t106 long N006 ( 3, 4) [000107] -------N---- t107 = * LSH long $301 N007 ( 1, 1) [000108] ------------ t108 = CNS_INT long 16 Fseq[#FirstElem] $342 /--* t107 long +--* t108 long N008 ( 4, 5) [000109] -------N---- t109 = * ADD long $302 /--* t101 ref +--* t109 long N009 ( 5, 6) [000110] -------N---- t110 = * ADD byref $3c1 /--* t110 byref N010 ( 6, 7) [000087] a---G------- t87 = * IND ref /--* t87 ref N013 ( 6, 7) [000037] DA--G------- * STORE_LCL_VAR ref V10 loc4 d:2 [000157] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 1) [000038] ------------ t38 = CNS_INT ref null $VN.Null /--* t38 ref N003 ( 5, 4) [000040] DA--G------- * STORE_LCL_VAR ref (AX) V11 loc5 [000158] ------------ IL_OFFSET void IL offset: 0x26 N007 ( 3, 3) [000047] ------------ t47 = LCL_VAR_ADDR long V11 loc5 $481 N008 ( 1, 1) [000041] ------------ t41 = LCL_VAR ref V00 arg0 u:1 $80 N009 ( 1, 1) [000042] ------------ t42 = LCL_VAR ref V01 arg1 u:1 $81 N010 ( 1, 1) [000043] ------------ t43 = LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ t44 = LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ t45 = LCL_VAR ref V04 arg4 u:1 $82 /--* t47 long arg5 in r9 +--* t41 ref arg0 in rdi +--* t42 ref arg1 in rsi +--* t43 ref arg2 in rdx +--* t44 ref arg3 in rcx +--* t45 ref arg4 in r8 N013 ( 24, 20) [000048] --CXG------- t48 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 /--* t48 int N014 ( 25, 22) [000049] ---XG------- t49 = * CAST int <- bool <- int $1c6 N015 ( 1, 1) [000050] ------------ t50 = CNS_INT int 0 $40 /--* t49 int +--* t50 int N016 ( 27, 24) [000051] J--XG--N---- t51 = * EQ int $1c7 /--* t51 int N017 ( 29, 26) [000052] ---XG------- * JTRUE void ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} N001 ( 0, 0) [000147] ------------ t147 = PHI_ARG bool V06 loc0 u:5 $40 N002 ( 0, 0) [000146] ------------ t146 = PHI_ARG bool V06 loc0 u:4 $241 /--* t147 bool +--* t146 bool N003 ( 0, 0) [000141] ------------ t141 = * PHI bool /--* t141 bool N005 ( 0, 0) [000142] DA---------- * STORE_LCL_VAR bool V06 loc0 d:6 [000159] ------------ IL_OFFSET void IL offset: 0x38 N004 ( 3, 2) [000053] ------------ t53 = LCL_VAR ref (AX) V11 loc5 $500 N005 ( 1, 1) [000054] ------------ t54 = LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ t55 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t53 ref arg0 in rdi +--* t54 ref arg1 in rsi +--* t55 byref arg2 in rdx N007 ( 19, 12) [000056] --CXG------- t56 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 /--* t56 int N008 ( 20, 14) [000057] ---XG------- t57 = * CAST int <- bool <- int $1c8 N009 ( 1, 1) [000058] ------------ t58 = CNS_INT int 0 $40 /--* t57 int +--* t58 int N010 ( 22, 16) [000059] J--XG--N---- t59 = * NE int $1c9 /--* t59 int N011 ( 24, 18) [000060] ---XG------- * JTRUE void ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} N001 ( 0, 0) [000149] ------------ t149 = PHI_ARG bool V06 loc0 u:7 $40 N002 ( 0, 0) [000148] ------------ t148 = PHI_ARG bool V06 loc0 u:6 $242 /--* t149 bool +--* t148 bool N003 ( 0, 0) [000132] ------------ t132 = * PHI bool /--* t132 bool N005 ( 0, 0) [000133] DA---------- * STORE_LCL_VAR bool V06 loc0 d:8 [000160] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ t62 = CNS_INT int 1 $41 /--* t61 int +--* t62 int N003 ( 3, 3) [000063] ------------ t63 = * ADD int $1ca /--* t63 int N005 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 [000161] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR int V08 loc2 u:4 $1ca N002 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V07 loc1 u:2 $1c1 /--* t16 int +--* t17 int N003 ( 3, 3) [000018] J------N---- t18 = * LE int $1cb /--* t18 int N004 ( 5, 5) [000019] ------------ * JTRUE void ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ t145 = PHI_ARG bool V06 loc0 u:2 $41 /--* t150 bool +--* t145 bool N003 ( 0, 0) [000135] ------------ t135 = * PHI bool /--* t135 bool N005 ( 0, 0) [000136] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 [000162] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 3, 2) [000072] ------------ t72 = LCL_VAR int V06 loc0 u:3 (last use) $240 /--* t72 int N002 ( 4, 3) [000073] ------------ * RETURN int $103 ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} [000163] ------------ IL_OFFSET void IL offset: 0x36 N001 ( 1, 1) [000069] ------------ t69 = CNS_INT int 0 $40 /--* t69 int N003 ( 5, 4) [000071] DA---------- * STORE_LCL_VAR int V06 loc0 d:5 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} [000164] ------------ IL_OFFSET void IL offset: 0x45 N001 ( 1, 1) [000066] ------------ t66 = CNS_INT int 0 $40 /--* t66 int N003 ( 5, 4) [000068] DA---------- * STORE_LCL_VAR int V06 loc0 d:7 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Do 'simple' lowering *** Computing fgRngChkTarget for block BB02 fgNewBBinRegion(jumpKind=3, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=true, insertAtEnd=true): inserting after BB07 New Basic Block BB08 [0011] created. fgAddCodeRef - Add BB in non-EH region for RNGCHK_FAIL, new block BB08 [0011] Initializing arg info for 169.CALL: ArgTable for 169.CALL after fgInitArgInfo: Morphing args for 169.CALL: argSlots=0, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 169.CALL after fgMorphArgs: outgoingArgSpaceSize 0 sufficient for call [000048], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000056], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000169], which needs 0 After fgSimpleLowering() added some RngChk throw blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC LIR BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC LIR BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC LIR BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC LIR BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC LIR BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC LIR BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC LIR BB08 [0011] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Do 'simple' lowering *************** In fgDebugCheckBBlist Trees before Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC LIR BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC LIR BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC LIR BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC LIR BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC LIR BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC LIR BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC LIR BB08 [0011] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} N001 ( 1, 1) [000006] ------------ t6 = CNS_INT int 1 $41 /--* t6 int N003 ( 5, 4) [000008] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000076] ------------ t76 = LCL_VAR ref V13 tmp1 u:1 $83 [000165] ------------ t165 = CNS_INT long 8 /--* t76 ref +--* t165 long [000166] ------------ t166 = * ADD ref /--* t166 ref N002 ( 3, 3) [000077] ---XG------- t77 = * IND int $1c0 N003 ( 1, 1) [000009] ------------ t9 = CNS_INT int -1 $46 /--* t77 int +--* t9 int N004 ( 5, 5) [000010] ---XG------- t10 = * ADD int $1c2 /--* t10 int N006 ( 5, 5) [000012] DA-XG------- * STORE_LCL_VAR int V07 loc1 d:2 [000155] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000013] ------------ t13 = CNS_INT int 0 $40 /--* t13 int N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 [000156] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR int V07 loc1 u:2 $1c1 N002 ( 1, 1) [000153] ------------ t153 = CNS_INT int 0 $40 /--* t126 int +--* t153 int N003 ( 3, 3) [000124] J------N---- t124 = * LT int $1c3 /--* t124 int N004 ( 5, 5) [000127] ------------ * JTRUE void ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} N001 ( 0, 0) [000151] ------------ t151 = PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ t143 = PHI_ARG bool V06 loc0 u:2 $41 /--* t151 bool +--* t143 bool N003 ( 0, 0) [000138] ------------ t138 = * PHI bool /--* t138 bool N005 ( 0, 0) [000139] DA---------- * STORE_LCL_VAR bool V06 loc0 d:4 N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ t144 = PHI_ARG int V08 loc2 u:2 $40 /--* t152 int +--* t144 int N003 ( 0, 0) [000129] ------------ t129 = * PHI int /--* t129 int N005 ( 0, 0) [000130] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V08 loc2 u:3 $280 N002 ( 1, 1) [000081] ------------ t81 = LCL_VAR ref V14 tmp2 u:1 $84 [000167] ------------ t167 = CNS_INT long 8 /--* t81 ref +--* t167 long [000168] ------------ t168 = * ADD ref /--* t168 ref N003 ( 3, 3) [000092] ---X-------- t92 = * IND int $1c5 /--* t22 int +--* t92 int N004 ( 8, 11) [000093] ---X-------- * ARR_BOUNDS_CHECK_Rng void $18a N005 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V14 tmp2 u:1 $84 N006 ( 1, 1) [000091] ------------ t91 = LCL_VAR int V08 loc2 u:3 $280 /--* t91 int N007 ( 2, 3) [000094] ------------ t94 = * CAST long <- int $300 N008 ( 1, 1) [000095] -------N---- t95 = CNS_INT long 3 $340 /--* t94 long +--* t95 long N009 ( 3, 4) [000096] -------N---- t96 = * LSH long $301 N010 ( 1, 1) [000097] ------------ t97 = CNS_INT long 16 Fseq[#FirstElem] $342 /--* t96 long +--* t97 long N011 ( 4, 5) [000098] -------N---- t98 = * ADD long $302 /--* t90 ref +--* t98 long N012 ( 5, 6) [000099] -------N---- t99 = * ADD byref $3c0 /--* t99 byref N013 ( 6, 7) [000082] a---G------- t82 = * IND ref /--* t82 ref N016 ( 18, 21) [000028] DA-XG------- * STORE_LCL_VAR ref V09 loc3 d:2 N002 ( 1, 1) [000101] ------------ t101 = LCL_VAR ref V13 tmp1 u:1 $83 N003 ( 1, 1) [000102] ------------ t102 = LCL_VAR int V08 loc2 u:3 $280 /--* t102 int N004 ( 2, 3) [000105] ------------ t105 = * CAST long <- int $300 N005 ( 1, 1) [000106] -------N---- t106 = CNS_INT long 3 $340 /--* t105 long +--* t106 long N006 ( 3, 4) [000107] -------N---- t107 = * LSH long $301 N007 ( 1, 1) [000108] ------------ t108 = CNS_INT long 16 Fseq[#FirstElem] $342 /--* t107 long +--* t108 long N008 ( 4, 5) [000109] -------N---- t109 = * ADD long $302 /--* t101 ref +--* t109 long N009 ( 5, 6) [000110] -------N---- t110 = * ADD byref $3c1 /--* t110 byref N010 ( 6, 7) [000087] a---G------- t87 = * IND ref /--* t87 ref N013 ( 6, 7) [000037] DA--G------- * STORE_LCL_VAR ref V10 loc4 d:2 [000157] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 1) [000038] ------------ t38 = CNS_INT ref null $VN.Null /--* t38 ref N003 ( 5, 4) [000040] DA--G------- * STORE_LCL_VAR ref (AX) V11 loc5 [000158] ------------ IL_OFFSET void IL offset: 0x26 N007 ( 3, 3) [000047] ------------ t47 = LCL_VAR_ADDR long V11 loc5 $481 N008 ( 1, 1) [000041] ------------ t41 = LCL_VAR ref V00 arg0 u:1 $80 N009 ( 1, 1) [000042] ------------ t42 = LCL_VAR ref V01 arg1 u:1 $81 N010 ( 1, 1) [000043] ------------ t43 = LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ t44 = LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ t45 = LCL_VAR ref V04 arg4 u:1 $82 /--* t47 long arg5 in r9 +--* t41 ref arg0 in rdi +--* t42 ref arg1 in rsi +--* t43 ref arg2 in rdx +--* t44 ref arg3 in rcx +--* t45 ref arg4 in r8 N013 ( 24, 20) [000048] --CXG------- t48 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 /--* t48 int N014 ( 25, 22) [000049] ---XG------- t49 = * CAST int <- bool <- int $1c6 N015 ( 1, 1) [000050] ------------ t50 = CNS_INT int 0 $40 /--* t49 int +--* t50 int N016 ( 27, 24) [000051] J--XG--N---- t51 = * EQ int $1c7 /--* t51 int N017 ( 29, 26) [000052] ---XG------- * JTRUE void ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} N001 ( 0, 0) [000147] ------------ t147 = PHI_ARG bool V06 loc0 u:5 $40 N002 ( 0, 0) [000146] ------------ t146 = PHI_ARG bool V06 loc0 u:4 $241 /--* t147 bool +--* t146 bool N003 ( 0, 0) [000141] ------------ t141 = * PHI bool /--* t141 bool N005 ( 0, 0) [000142] DA---------- * STORE_LCL_VAR bool V06 loc0 d:6 [000159] ------------ IL_OFFSET void IL offset: 0x38 N004 ( 3, 2) [000053] ------------ t53 = LCL_VAR ref (AX) V11 loc5 $500 N005 ( 1, 1) [000054] ------------ t54 = LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ t55 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t53 ref arg0 in rdi +--* t54 ref arg1 in rsi +--* t55 byref arg2 in rdx N007 ( 19, 12) [000056] --CXG------- t56 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 /--* t56 int N008 ( 20, 14) [000057] ---XG------- t57 = * CAST int <- bool <- int $1c8 N009 ( 1, 1) [000058] ------------ t58 = CNS_INT int 0 $40 /--* t57 int +--* t58 int N010 ( 22, 16) [000059] J--XG--N---- t59 = * NE int $1c9 /--* t59 int N011 ( 24, 18) [000060] ---XG------- * JTRUE void ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} N001 ( 0, 0) [000149] ------------ t149 = PHI_ARG bool V06 loc0 u:7 $40 N002 ( 0, 0) [000148] ------------ t148 = PHI_ARG bool V06 loc0 u:6 $242 /--* t149 bool +--* t148 bool N003 ( 0, 0) [000132] ------------ t132 = * PHI bool /--* t132 bool N005 ( 0, 0) [000133] DA---------- * STORE_LCL_VAR bool V06 loc0 d:8 [000160] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] ------------ t62 = CNS_INT int 1 $41 /--* t61 int +--* t62 int N003 ( 3, 3) [000063] ------------ t63 = * ADD int $1ca /--* t63 int N005 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 [000161] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR int V08 loc2 u:4 $1ca N002 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V07 loc1 u:2 $1c1 /--* t16 int +--* t17 int N003 ( 3, 3) [000018] J------N---- t18 = * LE int $1cb /--* t18 int N004 ( 5, 5) [000019] ------------ * JTRUE void ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ t145 = PHI_ARG bool V06 loc0 u:2 $41 /--* t150 bool +--* t145 bool N003 ( 0, 0) [000135] ------------ t135 = * PHI bool /--* t135 bool N005 ( 0, 0) [000136] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 [000162] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 3, 2) [000072] ------------ t72 = LCL_VAR int V06 loc0 u:3 (last use) $240 /--* t72 int N002 ( 4, 3) [000073] ------------ * RETURN int $103 ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} [000163] ------------ IL_OFFSET void IL offset: 0x36 N001 ( 1, 1) [000069] ------------ t69 = CNS_INT int 0 $40 /--* t69 int N003 ( 5, 4) [000071] DA---------- * STORE_LCL_VAR int V06 loc0 d:5 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} [000164] ------------ IL_OFFSET void IL offset: 0x45 N001 ( 1, 1) [000066] ------------ t66 = CNS_INT int 0 $40 /--* t66 int N003 ( 5, 4) [000068] DA---------- * STORE_LCL_VAR int V06 loc0 d:7 ------------ BB08 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [000169] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Lowering nodeinfo Addressing mode: Base N001 ( 1, 1) [000076] ------------ * LCL_VAR ref V13 tmp1 u:1 $83 + 8 Removing unused node: [000165] -c---------- * CNS_INT long 8 New addressing mode node: [000166] ------------ * LEA(b+8) ref Addressing mode: Base N002 ( 1, 1) [000081] ------------ * LCL_VAR ref V14 tmp2 u:1 $84 + 8 Removing unused node: [000167] -c---------- * CNS_INT long 8 New addressing mode node: [000168] ------------ * LEA(b+8) ref Addressing mode: Base N005 ( 1, 1) [000090] ------------ * LCL_VAR ref V14 tmp2 u:1 $84 + Index * 8 + 16 N007 ( 2, 3) [000094] ------------ * CAST long <- int $300 Removing unused node: N011 ( 4, 5) [000098] -------N---- * ADD long $302 Removing unused node: N010 ( 1, 1) [000097] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $342 Removing unused node: N009 ( 3, 4) [000096] -------N---- * LSH long $301 Removing unused node: N008 ( 1, 1) [000095] -c-----N---- * CNS_INT long 3 $340 New addressing mode node: N012 ( 5, 6) [000099] ------------ * LEA(b+(i*8)+16) byref Addressing mode: Base N002 ( 1, 1) [000101] ------------ * LCL_VAR ref V13 tmp1 u:1 $83 + Index * 8 + 16 N004 ( 2, 3) [000105] ------------ * CAST long <- int $300 Removing unused node: N008 ( 4, 5) [000109] -------N---- * ADD long $302 Removing unused node: N007 ( 1, 1) [000108] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $342 Removing unused node: N006 ( 3, 4) [000107] -------N---- * LSH long $301 Removing unused node: N005 ( 1, 1) [000106] -c-----N---- * CNS_INT long 3 $340 New addressing mode node: N009 ( 5, 6) [000110] ------------ * LEA(b+(i*8)+16) byref lowering call (before): N007 ( 3, 3) [000047] ------------ t47 = LCL_VAR_ADDR long V11 loc5 $481 N008 ( 1, 1) [000041] ------------ t41 = LCL_VAR ref V00 arg0 u:1 $80 N009 ( 1, 1) [000042] ------------ t42 = LCL_VAR ref V01 arg1 u:1 $81 N010 ( 1, 1) [000043] ------------ t43 = LCL_VAR ref V10 loc4 u:2 N011 ( 3, 2) [000044] ------------ t44 = LCL_VAR ref V09 loc3 u:2 (last use) N012 ( 1, 1) [000045] ------------ t45 = LCL_VAR ref V04 arg4 u:1 $82 /--* t47 long arg5 in r9 +--* t41 ref arg0 in rdi +--* t42 ref arg1 in rsi +--* t43 ref arg2 in rdx +--* t44 ref arg3 in rcx +--* t45 ref arg4 in r8 N013 ( 24, 20) [000048] --CXG------- t48 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000113] ----------L- * ARGPLACE ref $80 lowering arg : N002 ( 0, 0) [000114] ----------L- * ARGPLACE ref $81 lowering arg : N003 ( 0, 0) [000115] ----------L- * ARGPLACE ref lowering arg : N004 ( 0, 0) [000116] ----------L- * ARGPLACE ref lowering arg : N005 ( 0, 0) [000117] ----------L- * ARGPLACE ref $82 lowering arg : N006 ( 0, 0) [000112] ----------L- * ARGPLACE long $481 late: ====== lowering arg : N007 ( 3, 3) [000047] ------------ * LCL_VAR_ADDR long V11 loc5 $481 new node is : [000170] ------------ * PUTARG_REG long REG r9 lowering arg : N008 ( 1, 1) [000041] ------------ * LCL_VAR ref V00 arg0 u:1 $80 new node is : [000171] ------------ * PUTARG_REG ref REG rdi lowering arg : N009 ( 1, 1) [000042] ------------ * LCL_VAR ref V01 arg1 u:1 $81 new node is : [000172] ------------ * PUTARG_REG ref REG rsi lowering arg : N010 ( 1, 1) [000043] ------------ * LCL_VAR ref V10 loc4 u:2 new node is : [000173] ------------ * PUTARG_REG ref REG rdx lowering arg : N011 ( 3, 2) [000044] ------------ * LCL_VAR ref V09 loc3 u:2 (last use) new node is : [000174] ------------ * PUTARG_REG ref REG rcx lowering arg : N012 ( 1, 1) [000045] ------------ * LCL_VAR ref V04 arg4 u:1 $82 new node is : [000175] ------------ * PUTARG_REG ref REG r8 results of lowering call: N001 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0xd1ffab1e ftn /--* t176 long N002 ( 5, 12) [000177] ------------ t177 = * IND long lowering call (after): N007 ( 3, 3) [000047] ------------ t47 = LCL_VAR_ADDR long V11 loc5 $481 /--* t47 long [000170] ------------ t170 = * PUTARG_REG long REG r9 N008 ( 1, 1) [000041] ------------ t41 = LCL_VAR ref V00 arg0 u:1 $80 /--* t41 ref [000171] ------------ t171 = * PUTARG_REG ref REG rdi N009 ( 1, 1) [000042] ------------ t42 = LCL_VAR ref V01 arg1 u:1 $81 /--* t42 ref [000172] ------------ t172 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000043] ------------ t43 = LCL_VAR ref V10 loc4 u:2 /--* t43 ref [000173] ------------ t173 = * PUTARG_REG ref REG rdx N011 ( 3, 2) [000044] ------------ t44 = LCL_VAR ref V09 loc3 u:2 (last use) /--* t44 ref [000174] ------------ t174 = * PUTARG_REG ref REG rcx N012 ( 1, 1) [000045] ------------ t45 = LCL_VAR ref V04 arg4 u:1 $82 /--* t45 ref [000175] ------------ t175 = * PUTARG_REG ref REG r8 N001 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0xd1ffab1e ftn /--* t176 long N002 ( 5, 12) [000177] -c---------- t177 = * IND long REG NA /--* t170 long arg5 in r9 +--* t171 ref arg0 in rdi +--* t172 ref arg1 in rsi +--* t173 ref arg2 in rdx +--* t174 ref arg3 in rcx +--* t175 ref arg4 in r8 +--* t177 long control expr N013 ( 24, 20) [000048] --CXG------- t48 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 lowering call (before): N004 ( 3, 2) [000053] ------------ t53 = LCL_VAR ref (AX) V11 loc5 $500 N005 ( 1, 1) [000054] ------------ t54 = LCL_VAR ref V10 loc4 u:2 (last use) N006 ( 1, 1) [000055] ------------ t55 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t53 ref arg0 in rdi +--* t54 ref arg1 in rsi +--* t55 byref arg2 in rdx N007 ( 19, 12) [000056] --CXG------- t56 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000119] ----------L- * ARGPLACE ref $500 lowering arg : N002 ( 0, 0) [000120] ----------L- * ARGPLACE ref lowering arg : N003 ( 0, 0) [000121] ----------L- * ARGPLACE byref $c0 late: ====== lowering arg : N004 ( 3, 2) [000053] ------------ * LCL_VAR ref (AX) V11 loc5 $500 new node is : [000178] ------------ * PUTARG_REG ref REG rdi lowering arg : N005 ( 1, 1) [000054] ------------ * LCL_VAR ref V10 loc4 u:2 (last use) new node is : [000179] ------------ * PUTARG_REG ref REG rsi lowering arg : N006 ( 1, 1) [000055] ------------ * LCL_VAR byref V05 arg5 u:1 $c0 new node is : [000180] ------------ * PUTARG_REG byref REG rdx results of lowering call: N001 ( 3, 10) [000181] ------------ t181 = CNS_INT(h) long 0xd1ffab1e ftn /--* t181 long N002 ( 5, 12) [000182] ------------ t182 = * IND long lowering call (after): N004 ( 3, 2) [000053] ------------ t53 = LCL_VAR ref (AX) V11 loc5 $500 /--* t53 ref [000178] ------------ t178 = * PUTARG_REG ref REG rdi N005 ( 1, 1) [000054] ------------ t54 = LCL_VAR ref V10 loc4 u:2 (last use) /--* t54 ref [000179] ------------ t179 = * PUTARG_REG ref REG rsi N006 ( 1, 1) [000055] ------------ t55 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t55 byref [000180] ------------ t180 = * PUTARG_REG byref REG rdx N001 ( 3, 10) [000181] ------------ t181 = CNS_INT(h) long 0xd1ffab1e ftn /--* t181 long N002 ( 5, 12) [000182] -c---------- t182 = * IND long REG NA /--* t178 ref arg0 in rdi +--* t179 ref arg1 in rsi +--* t180 byref arg2 in rdx +--* t182 long control expr N007 ( 19, 12) [000056] --CXG------- t56 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 lowering GT_RETURN N002 ( 4, 3) [000073] ------------ * RETURN int $103 ============lowering call (before): N001 ( 14, 5) [000169] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL objp: ====== args: ====== late: ====== lowering call (after): N001 ( 14, 5) [000169] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC LIR BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC LIR BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC LIR BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC LIR BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC LIR BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC LIR BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC LIR BB08 [0011] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} N001 ( 1, 1) [000006] -c---------- t6 = CNS_INT int 1 $41 /--* t6 int N003 ( 5, 4) [000008] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000076] ------------ t76 = LCL_VAR ref V13 tmp1 u:1 $83 /--* t76 ref [000166] -c---------- t166 = * LEA(b+8) ref /--* t166 ref N002 ( 3, 3) [000077] ---XG------- t77 = * IND int $1c0 N003 ( 1, 1) [000009] -c---------- t9 = CNS_INT int -1 $46 /--* t77 int +--* t9 int N004 ( 5, 5) [000010] ---XG------- t10 = * ADD int $1c2 /--* t10 int N006 ( 5, 5) [000012] DA-XG------- * STORE_LCL_VAR int V07 loc1 d:2 [000155] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000013] ------------ t13 = CNS_INT int 0 $40 /--* t13 int N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 [000156] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR int V07 loc1 u:2 $1c1 N002 ( 1, 1) [000153] -c---------- t153 = CNS_INT int 0 $40 /--* t126 int +--* t153 int N003 ( 3, 3) [000124] J------N---- * LT void $1c3 N004 ( 5, 5) [000127] ------------ * JTRUE void ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} N001 ( 0, 0) [000151] ------------ t151 = PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ t143 = PHI_ARG bool V06 loc0 u:2 $41 /--* t151 bool +--* t143 bool N003 ( 0, 0) [000138] ------------ t138 = * PHI bool /--* t138 bool N005 ( 0, 0) [000139] DA---------- * STORE_LCL_VAR bool V06 loc0 d:4 N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ t144 = PHI_ARG int V08 loc2 u:2 $40 /--* t152 int +--* t144 int N003 ( 0, 0) [000129] ------------ t129 = * PHI int /--* t129 int N005 ( 0, 0) [000130] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V08 loc2 u:3 $280 N002 ( 1, 1) [000081] ------------ t81 = LCL_VAR ref V14 tmp2 u:1 $84 /--* t81 ref [000168] -c---------- t168 = * LEA(b+8) ref /--* t168 ref N003 ( 3, 3) [000092] -c-X-------- t92 = * IND int $1c5 /--* t22 int +--* t92 int N004 ( 8, 11) [000093] ---X-------- * ARR_BOUNDS_CHECK_Rng void $18a N005 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V14 tmp2 u:1 $84 N006 ( 1, 1) [000091] ------------ t91 = LCL_VAR int V08 loc2 u:3 $280 /--* t91 int N007 ( 2, 3) [000094] ------------ t94 = * CAST long <- int $300 /--* t90 ref +--* t94 long N012 ( 5, 6) [000099] -c---------- t99 = * LEA(b+(i*8)+16) byref /--* t99 byref N013 ( 6, 7) [000082] a---G------- t82 = * IND ref /--* t82 ref N016 ( 18, 21) [000028] DA-XG------- * STORE_LCL_VAR ref V09 loc3 d:2 N002 ( 1, 1) [000101] ------------ t101 = LCL_VAR ref V13 tmp1 u:1 $83 N003 ( 1, 1) [000102] ------------ t102 = LCL_VAR int V08 loc2 u:3 $280 /--* t102 int N004 ( 2, 3) [000105] ------------ t105 = * CAST long <- int $300 /--* t101 ref +--* t105 long N009 ( 5, 6) [000110] -c---------- t110 = * LEA(b+(i*8)+16) byref /--* t110 byref N010 ( 6, 7) [000087] a---G------- t87 = * IND ref /--* t87 ref N013 ( 6, 7) [000037] DA--G------- * STORE_LCL_VAR ref V10 loc4 d:2 [000157] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 1) [000038] ------------ t38 = CNS_INT ref null $VN.Null /--* t38 ref N003 ( 5, 4) [000040] DA--G------- * STORE_LCL_VAR ref (AX) V11 loc5 [000158] ------------ IL_OFFSET void IL offset: 0x26 N007 ( 3, 3) [000047] ------------ t47 = LCL_VAR_ADDR long V11 loc5 $481 /--* t47 long [000170] ------------ t170 = * PUTARG_REG long REG r9 N008 ( 1, 1) [000041] ------------ t41 = LCL_VAR ref V00 arg0 u:1 $80 /--* t41 ref [000171] ------------ t171 = * PUTARG_REG ref REG rdi N009 ( 1, 1) [000042] ------------ t42 = LCL_VAR ref V01 arg1 u:1 $81 /--* t42 ref [000172] ------------ t172 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000043] ------------ t43 = LCL_VAR ref V10 loc4 u:2 /--* t43 ref [000173] ------------ t173 = * PUTARG_REG ref REG rdx N011 ( 3, 2) [000044] ------------ t44 = LCL_VAR ref V09 loc3 u:2 (last use) /--* t44 ref [000174] ------------ t174 = * PUTARG_REG ref REG rcx N012 ( 1, 1) [000045] ------------ t45 = LCL_VAR ref V04 arg4 u:1 $82 /--* t45 ref [000175] ------------ t175 = * PUTARG_REG ref REG r8 N001 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0xd1ffab1e ftn /--* t176 long N002 ( 5, 12) [000177] -c---------- t177 = * IND long REG NA /--* t170 long arg5 in r9 +--* t171 ref arg0 in rdi +--* t172 ref arg1 in rsi +--* t173 ref arg2 in rdx +--* t174 ref arg3 in rcx +--* t175 ref arg4 in r8 +--* t177 long control expr N013 ( 24, 20) [000048] --CXG------- t48 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 N015 ( 1, 1) [000050] -c---------- t50 = CNS_INT bool 0 $40 /--* t48 bool +--* t50 bool N016 ( 27, 24) [000051] J--XG--N-U-- * EQ void $1c7 N017 ( 29, 26) [000052] ---XG------- * JTRUE void ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} N001 ( 0, 0) [000147] ------------ t147 = PHI_ARG bool V06 loc0 u:5 $40 N002 ( 0, 0) [000146] ------------ t146 = PHI_ARG bool V06 loc0 u:4 $241 /--* t147 bool +--* t146 bool N003 ( 0, 0) [000141] ------------ t141 = * PHI bool /--* t141 bool N005 ( 0, 0) [000142] DA---------- * STORE_LCL_VAR bool V06 loc0 d:6 [000159] ------------ IL_OFFSET void IL offset: 0x38 N004 ( 3, 2) [000053] ------------ t53 = LCL_VAR ref (AX) V11 loc5 $500 /--* t53 ref [000178] ------------ t178 = * PUTARG_REG ref REG rdi N005 ( 1, 1) [000054] ------------ t54 = LCL_VAR ref V10 loc4 u:2 (last use) /--* t54 ref [000179] ------------ t179 = * PUTARG_REG ref REG rsi N006 ( 1, 1) [000055] ------------ t55 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t55 byref [000180] ------------ t180 = * PUTARG_REG byref REG rdx N001 ( 3, 10) [000181] ------------ t181 = CNS_INT(h) long 0xd1ffab1e ftn /--* t181 long N002 ( 5, 12) [000182] -c---------- t182 = * IND long REG NA /--* t178 ref arg0 in rdi +--* t179 ref arg1 in rsi +--* t180 byref arg2 in rdx +--* t182 long control expr N007 ( 19, 12) [000056] --CXG------- t56 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 N009 ( 1, 1) [000058] -c---------- t58 = CNS_INT bool 0 $40 /--* t56 bool +--* t58 bool N010 ( 22, 16) [000059] J--XG--N-U-- * NE void $1c9 N011 ( 24, 18) [000060] ---XG------- * JTRUE void ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} N001 ( 0, 0) [000149] ------------ t149 = PHI_ARG bool V06 loc0 u:7 $40 N002 ( 0, 0) [000148] ------------ t148 = PHI_ARG bool V06 loc0 u:6 $242 /--* t149 bool +--* t148 bool N003 ( 0, 0) [000132] ------------ t132 = * PHI bool /--* t132 bool N005 ( 0, 0) [000133] DA---------- * STORE_LCL_VAR bool V06 loc0 d:8 [000160] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] -c---------- t62 = CNS_INT int 1 $41 /--* t61 int +--* t62 int N003 ( 3, 3) [000063] ------------ t63 = * ADD int $1ca /--* t63 int N005 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 [000161] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR int V08 loc2 u:4 $1ca N002 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V07 loc1 u:2 $1c1 /--* t16 int +--* t17 int N003 ( 3, 3) [000018] J------N---- * LE void $1cb N004 ( 5, 5) [000019] ------------ * JTRUE void ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ t145 = PHI_ARG bool V06 loc0 u:2 $41 /--* t150 bool +--* t145 bool N003 ( 0, 0) [000135] ------------ t135 = * PHI bool /--* t135 bool N005 ( 0, 0) [000136] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 [000162] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 3, 2) [000072] ------------ t72 = LCL_VAR int V06 loc0 u:3 (last use) $240 /--* t72 int N002 ( 4, 3) [000073] ------------ * RETURN int $103 ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} [000163] ------------ IL_OFFSET void IL offset: 0x36 N001 ( 1, 1) [000069] ------------ t69 = CNS_INT int 0 $40 /--* t69 int N003 ( 5, 4) [000071] DA---------- * STORE_LCL_VAR int V06 loc0 d:5 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} [000164] ------------ IL_OFFSET void IL offset: 0x45 N001 ( 1, 1) [000066] ------------ t66 = CNS_INT int 0 $40 /--* t66 int N003 ( 5, 4) [000068] DA---------- * STORE_LCL_VAR int V06 loc0 d:7 ------------ BB08 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [000169] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V06: refCnt = 1, refCntWtd = 1 New refCnts for V13: refCnt = 1, refCntWtd = 1 New refCnts for V07: refCnt = 1, refCntWtd = 1 New refCnts for V08: refCnt = 1, refCntWtd = 1 New refCnts for V07: refCnt = 2, refCntWtd = 2 New refCnts for V08: refCnt = 2, refCntWtd = 2.06 New refCnts for V14: refCnt = 1, refCntWtd = 1.06 New refCnts for V14: refCnt = 2, refCntWtd = 2.12 New refCnts for V08: refCnt = 3, refCntWtd = 3.12 New refCnts for V09: refCnt = 1, refCntWtd = 1.06 New refCnts for V13: refCnt = 2, refCntWtd = 2.06 New refCnts for V08: refCnt = 4, refCntWtd = 4.18 New refCnts for V10: refCnt = 1, refCntWtd = 1.06 New refCnts for V11: refCnt = 1, refCntWtd = 1.06 New refCnts for V11: refCnt = 2, refCntWtd = 2.12 New refCnts for V00: refCnt = 1, refCntWtd = 1.06 New refCnts for V01: refCnt = 1, refCntWtd = 1.06 New refCnts for V10: refCnt = 2, refCntWtd = 2.12 New refCnts for V09: refCnt = 2, refCntWtd = 2.12 New refCnts for V04: refCnt = 1, refCntWtd = 1.06 New refCnts for V11: refCnt = 3, refCntWtd = 3.18 New refCnts for V10: refCnt = 3, refCntWtd = 3.18 New refCnts for V05: refCnt = 1, refCntWtd = 1.06 New refCnts for V08: refCnt = 5, refCntWtd = 5.24 New refCnts for V08: refCnt = 6, refCntWtd = 6.30 New refCnts for V08: refCnt = 7, refCntWtd = 7.36 New refCnts for V07: refCnt = 3, refCntWtd = 3.06 New refCnts for V06: refCnt = 2, refCntWtd = 2 New refCnts for V06: refCnt = 3, refCntWtd = 2.03 New refCnts for V06: refCnt = 4, refCntWtd = 2.03 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 2, refCntWtd = 2.06 New refCnts for V00: refCnt = 3, refCntWtd = 3.06 New refCnts for V01: refCnt = 2, refCntWtd = 2.06 New refCnts for V01: refCnt = 3, refCntWtd = 3.06 New refCnts for V04: refCnt = 2, refCntWtd = 2.06 New refCnts for V04: refCnt = 3, refCntWtd = 3.06 New refCnts for V05: refCnt = 2, refCntWtd = 2.06 New refCnts for V05: refCnt = 3, refCntWtd = 3.06 New refCnts for V13: refCnt = 3, refCntWtd = 3.06 New refCnts for V14: refCnt = 3, refCntWtd = 3.12 *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 arg0 ref class-hnd ; V01 arg1 ref class-hnd ; V02 arg2 struct ld-addr-op ; V03 arg3 struct ld-addr-op ; V04 arg4 ref class-hnd ; V05 arg5 byref ; V06 loc0 bool ; V07 loc1 int ; V08 loc2 int ; V09 loc3 ref class-hnd ; V10 loc4 ref class-hnd ; V11 loc5 ref do-not-enreg[X] addr-exposed ld-addr-op class-hnd ; V12 OutArgs lclBlk <0> "OutgoingArgSpace" ; V13 tmp1 ref V02.array(offs=0x00) P-INDEP "field V02.array (fldOffset=0x0)" ; V14 tmp2 ref V03.array(offs=0x00) P-INDEP "field V03.array (fldOffset=0x0)" In fgLocalVarLivenessInit Tracked variable (11 out of 15) table: V08 loc2 [ int]: refCnt = 7, refCntWtd = 7.36 V14 tmp2 [ ref]: refCnt = 3, refCntWtd = 3.12 V00 arg0 [ ref]: refCnt = 3, refCntWtd = 3.06 V01 arg1 [ ref]: refCnt = 3, refCntWtd = 3.06 V04 arg4 [ ref]: refCnt = 3, refCntWtd = 3.06 V05 arg5 [ byref]: refCnt = 3, refCntWtd = 3.06 V13 tmp1 [ ref]: refCnt = 3, refCntWtd = 3.06 V10 loc4 [ ref]: refCnt = 3, refCntWtd = 3.18 V07 loc1 [ int]: refCnt = 3, refCntWtd = 3.06 V09 loc3 [ ref]: refCnt = 2, refCntWtd = 2.12 V06 loc0 [ bool]: refCnt = 4, refCntWtd = 2.03 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={ V13 } + ByrefExposed + GcHeap DEF(3)={V08 V07 V06} BB02 USE(6)={V08 V14 V00 V01 V04 V13 } + ByrefExposed + GcHeap DEF(2)={ V10 V09} + ByrefExposed* + GcHeap* BB03 USE(2)={V05 V10} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB04 USE(2)={V08 V07} DEF(1)={V08 } BB05 USE(1)={V06} DEF(0)={ } BB06 USE(0)={ } DEF(1)={V06} BB07 USE(0)={ } DEF(1)={V06} BB08 USE(0)={} DEF(0)={} ** Memory liveness computed, GcHeap states and ByrefExposed states diverge *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (6)={ V14 V00 V01 V04 V05 V13 } + ByrefExposed + GcHeap OUT(9)={V08 V14 V00 V01 V04 V05 V13 V07 V06} + ByrefExposed + GcHeap BB02 IN (9)={V08 V14 V00 V01 V04 V05 V13 V07 V06} + ByrefExposed + GcHeap OUT(10)={V08 V14 V00 V01 V04 V05 V13 V10 V07 V06} + ByrefExposed + GcHeap BB03 IN (10)={V08 V14 V00 V01 V04 V05 V13 V10 V07 V06} + ByrefExposed + GcHeap OUT(9)={V08 V14 V00 V01 V04 V05 V13 V07 V06} + ByrefExposed + GcHeap BB04 IN (9)={V08 V14 V00 V01 V04 V05 V13 V07 V06} + ByrefExposed + GcHeap OUT(9)={V08 V14 V00 V01 V04 V05 V13 V07 V06} + ByrefExposed + GcHeap BB05 IN (1)={V06} OUT(0)={ } BB06 IN (9)={V08 V14 V00 V01 V04 V05 V13 V10 V07 } + ByrefExposed + GcHeap OUT(10)={V08 V14 V00 V01 V04 V05 V13 V10 V07 V06} + ByrefExposed + GcHeap BB07 IN (8)={V08 V14 V00 V01 V04 V05 V13 V07 } + ByrefExposed + GcHeap OUT(9)={V08 V14 V00 V01 V04 V05 V13 V07 V06} + ByrefExposed + GcHeap BB08 IN (0)={} OUT(0)={} *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC LIR BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC LIR BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC LIR BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC LIR BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC LIR BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC LIR BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC LIR BB08 [0011] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V06: refCnt = 1, refCntWtd = 1 New refCnts for V13: refCnt = 1, refCntWtd = 1 New refCnts for V07: refCnt = 1, refCntWtd = 1 New refCnts for V08: refCnt = 1, refCntWtd = 1 New refCnts for V07: refCnt = 2, refCntWtd = 2 New refCnts for V08: refCnt = 2, refCntWtd = 2.06 New refCnts for V14: refCnt = 1, refCntWtd = 1.06 New refCnts for V14: refCnt = 2, refCntWtd = 2.12 New refCnts for V08: refCnt = 3, refCntWtd = 3.12 New refCnts for V09: refCnt = 1, refCntWtd = 1.06 New refCnts for V13: refCnt = 2, refCntWtd = 2.06 New refCnts for V08: refCnt = 4, refCntWtd = 4.18 New refCnts for V10: refCnt = 1, refCntWtd = 1.06 New refCnts for V11: refCnt = 1, refCntWtd = 1.06 New refCnts for V11: refCnt = 2, refCntWtd = 2.12 New refCnts for V00: refCnt = 1, refCntWtd = 1.06 New refCnts for V01: refCnt = 1, refCntWtd = 1.06 New refCnts for V10: refCnt = 2, refCntWtd = 2.12 New refCnts for V09: refCnt = 2, refCntWtd = 2.12 New refCnts for V04: refCnt = 1, refCntWtd = 1.06 New refCnts for V11: refCnt = 3, refCntWtd = 3.18 New refCnts for V10: refCnt = 3, refCntWtd = 3.18 New refCnts for V05: refCnt = 1, refCntWtd = 1.06 New refCnts for V08: refCnt = 5, refCntWtd = 5.24 New refCnts for V08: refCnt = 6, refCntWtd = 6.30 New refCnts for V08: refCnt = 7, refCntWtd = 7.36 New refCnts for V07: refCnt = 3, refCntWtd = 3.06 New refCnts for V06: refCnt = 2, refCntWtd = 2 New refCnts for V06: refCnt = 3, refCntWtd = 2.03 New refCnts for V06: refCnt = 4, refCntWtd = 2.03 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 2, refCntWtd = 2.06 New refCnts for V00: refCnt = 3, refCntWtd = 3.06 New refCnts for V01: refCnt = 2, refCntWtd = 2.06 New refCnts for V01: refCnt = 3, refCntWtd = 3.06 New refCnts for V04: refCnt = 2, refCntWtd = 2.06 New refCnts for V04: refCnt = 3, refCntWtd = 3.06 New refCnts for V05: refCnt = 2, refCntWtd = 2.06 New refCnts for V05: refCnt = 3, refCntWtd = 3.06 New refCnts for V13: refCnt = 3, refCntWtd = 3.06 New refCnts for V14: refCnt = 3, refCntWtd = 3.12 *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC LIR BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC LIR BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC LIR BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC LIR BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC LIR BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC LIR BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC LIR BB08 [0011] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} N001 ( 1, 1) [000006] -c---------- t6 = CNS_INT int 1 $41 /--* t6 int N003 ( 5, 4) [000008] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000076] ------------ t76 = LCL_VAR ref V13 tmp1 u:1 $83 /--* t76 ref [000166] -c---------- t166 = * LEA(b+8) ref /--* t166 ref N002 ( 3, 3) [000077] ---XG------- t77 = * IND int $1c0 N003 ( 1, 1) [000009] -c---------- t9 = CNS_INT int -1 $46 /--* t77 int +--* t9 int N004 ( 5, 5) [000010] ---XG------- t10 = * ADD int $1c2 /--* t10 int N006 ( 5, 5) [000012] DA-XG------- * STORE_LCL_VAR int V07 loc1 d:2 [000155] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000013] ------------ t13 = CNS_INT int 0 $40 /--* t13 int N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 [000156] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR int V07 loc1 u:2 $1c1 N002 ( 1, 1) [000153] -c---------- t153 = CNS_INT int 0 $40 /--* t126 int +--* t153 int N003 ( 3, 3) [000124] J------N---- * LT void $1c3 N004 ( 5, 5) [000127] ------------ * JTRUE void ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} N001 ( 0, 0) [000151] ------------ t151 = PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ t143 = PHI_ARG bool V06 loc0 u:2 $41 /--* t151 bool +--* t143 bool N003 ( 0, 0) [000138] ------------ t138 = * PHI bool /--* t138 bool N005 ( 0, 0) [000139] DA---------- * STORE_LCL_VAR bool V06 loc0 d:4 N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ t144 = PHI_ARG int V08 loc2 u:2 $40 /--* t152 int +--* t144 int N003 ( 0, 0) [000129] ------------ t129 = * PHI int /--* t129 int N005 ( 0, 0) [000130] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V08 loc2 u:3 $280 N002 ( 1, 1) [000081] ------------ t81 = LCL_VAR ref V14 tmp2 u:1 $84 /--* t81 ref [000168] -c---------- t168 = * LEA(b+8) ref /--* t168 ref N003 ( 3, 3) [000092] -c-X-------- t92 = * IND int $1c5 /--* t22 int +--* t92 int N004 ( 8, 11) [000093] ---X-------- * ARR_BOUNDS_CHECK_Rng void $18a N005 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V14 tmp2 u:1 $84 N006 ( 1, 1) [000091] ------------ t91 = LCL_VAR int V08 loc2 u:3 $280 /--* t91 int N007 ( 2, 3) [000094] ------------ t94 = * CAST long <- int $300 /--* t90 ref +--* t94 long N012 ( 5, 6) [000099] -c---------- t99 = * LEA(b+(i*8)+16) byref /--* t99 byref N013 ( 6, 7) [000082] a---G------- t82 = * IND ref /--* t82 ref N016 ( 18, 21) [000028] DA-XG------- * STORE_LCL_VAR ref V09 loc3 d:2 N002 ( 1, 1) [000101] ------------ t101 = LCL_VAR ref V13 tmp1 u:1 $83 N003 ( 1, 1) [000102] ------------ t102 = LCL_VAR int V08 loc2 u:3 $280 /--* t102 int N004 ( 2, 3) [000105] ------------ t105 = * CAST long <- int $300 /--* t101 ref +--* t105 long N009 ( 5, 6) [000110] -c---------- t110 = * LEA(b+(i*8)+16) byref /--* t110 byref N010 ( 6, 7) [000087] a---G------- t87 = * IND ref /--* t87 ref N013 ( 6, 7) [000037] DA--G------- * STORE_LCL_VAR ref V10 loc4 d:2 [000157] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 1) [000038] ------------ t38 = CNS_INT ref null $VN.Null /--* t38 ref N003 ( 5, 4) [000040] DA--G------- * STORE_LCL_VAR ref (AX) V11 loc5 [000158] ------------ IL_OFFSET void IL offset: 0x26 N007 ( 3, 3) [000047] ------------ t47 = LCL_VAR_ADDR long V11 loc5 $481 /--* t47 long [000170] ------------ t170 = * PUTARG_REG long REG r9 N008 ( 1, 1) [000041] ------------ t41 = LCL_VAR ref V00 arg0 u:1 $80 /--* t41 ref [000171] ------------ t171 = * PUTARG_REG ref REG rdi N009 ( 1, 1) [000042] ------------ t42 = LCL_VAR ref V01 arg1 u:1 $81 /--* t42 ref [000172] ------------ t172 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000043] ------------ t43 = LCL_VAR ref V10 loc4 u:2 /--* t43 ref [000173] ------------ t173 = * PUTARG_REG ref REG rdx N011 ( 3, 2) [000044] ------------ t44 = LCL_VAR ref V09 loc3 u:2 (last use) /--* t44 ref [000174] ------------ t174 = * PUTARG_REG ref REG rcx N012 ( 1, 1) [000045] ------------ t45 = LCL_VAR ref V04 arg4 u:1 $82 /--* t45 ref [000175] ------------ t175 = * PUTARG_REG ref REG r8 N001 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0xd1ffab1e ftn /--* t176 long N002 ( 5, 12) [000177] -c---------- t177 = * IND long REG NA /--* t170 long arg5 in r9 +--* t171 ref arg0 in rdi +--* t172 ref arg1 in rsi +--* t173 ref arg2 in rdx +--* t174 ref arg3 in rcx +--* t175 ref arg4 in r8 +--* t177 long control expr N013 ( 24, 20) [000048] --CXG------- t48 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 N015 ( 1, 1) [000050] -c---------- t50 = CNS_INT bool 0 $40 /--* t48 bool +--* t50 bool N016 ( 27, 24) [000051] J--XG--N-U-- * EQ void $1c7 N017 ( 29, 26) [000052] ---XG------- * JTRUE void ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} N001 ( 0, 0) [000147] ------------ t147 = PHI_ARG bool V06 loc0 u:5 $40 N002 ( 0, 0) [000146] ------------ t146 = PHI_ARG bool V06 loc0 u:4 $241 /--* t147 bool +--* t146 bool N003 ( 0, 0) [000141] ------------ t141 = * PHI bool /--* t141 bool N005 ( 0, 0) [000142] DA---------- * STORE_LCL_VAR bool V06 loc0 d:6 [000159] ------------ IL_OFFSET void IL offset: 0x38 N004 ( 3, 2) [000053] ------------ t53 = LCL_VAR ref (AX) V11 loc5 $500 /--* t53 ref [000178] ------------ t178 = * PUTARG_REG ref REG rdi N005 ( 1, 1) [000054] ------------ t54 = LCL_VAR ref V10 loc4 u:2 (last use) /--* t54 ref [000179] ------------ t179 = * PUTARG_REG ref REG rsi N006 ( 1, 1) [000055] ------------ t55 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t55 byref [000180] ------------ t180 = * PUTARG_REG byref REG rdx N001 ( 3, 10) [000181] ------------ t181 = CNS_INT(h) long 0xd1ffab1e ftn /--* t181 long N002 ( 5, 12) [000182] -c---------- t182 = * IND long REG NA /--* t178 ref arg0 in rdi +--* t179 ref arg1 in rsi +--* t180 byref arg2 in rdx +--* t182 long control expr N007 ( 19, 12) [000056] --CXG------- t56 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 N009 ( 1, 1) [000058] -c---------- t58 = CNS_INT bool 0 $40 /--* t56 bool +--* t58 bool N010 ( 22, 16) [000059] J--XG--N-U-- * NE void $1c9 N011 ( 24, 18) [000060] ---XG------- * JTRUE void ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} N001 ( 0, 0) [000149] ------------ t149 = PHI_ARG bool V06 loc0 u:7 $40 N002 ( 0, 0) [000148] ------------ t148 = PHI_ARG bool V06 loc0 u:6 $242 /--* t149 bool +--* t148 bool N003 ( 0, 0) [000132] ------------ t132 = * PHI bool /--* t132 bool N005 ( 0, 0) [000133] DA---------- * STORE_LCL_VAR bool V06 loc0 d:8 [000160] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] -c---------- t62 = CNS_INT int 1 $41 /--* t61 int +--* t62 int N003 ( 3, 3) [000063] ------------ t63 = * ADD int $1ca /--* t63 int N005 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 [000161] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR int V08 loc2 u:4 $1ca N002 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V07 loc1 u:2 $1c1 /--* t16 int +--* t17 int N003 ( 3, 3) [000018] J------N---- * LE void $1cb N004 ( 5, 5) [000019] ------------ * JTRUE void ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ t145 = PHI_ARG bool V06 loc0 u:2 $41 /--* t150 bool +--* t145 bool N003 ( 0, 0) [000135] ------------ t135 = * PHI bool /--* t135 bool N005 ( 0, 0) [000136] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 [000162] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 3, 2) [000072] ------------ t72 = LCL_VAR int V06 loc0 u:3 (last use) $240 /--* t72 int N002 ( 4, 3) [000073] ------------ * RETURN int $103 ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} [000163] ------------ IL_OFFSET void IL offset: 0x36 N001 ( 1, 1) [000069] ------------ t69 = CNS_INT int 0 $40 /--* t69 int N003 ( 5, 4) [000071] DA---------- * STORE_LCL_VAR int V06 loc0 d:5 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} [000164] ------------ IL_OFFSET void IL offset: 0x45 N001 ( 1, 1) [000066] ------------ t66 = CNS_INT int 0 $40 /--* t66 int N003 ( 5, 4) [000068] DA---------- * STORE_LCL_VAR int V06 loc0 d:7 ------------ BB08 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [000169] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Trees before Calculate stack level slots ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC LIR BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC LIR BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC LIR BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC LIR BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC LIR BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC LIR BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC LIR BB08 [0011] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} N001 ( 1, 1) [000006] -c---------- t6 = CNS_INT int 1 $41 /--* t6 int N003 ( 5, 4) [000008] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000076] ------------ t76 = LCL_VAR ref V13 tmp1 u:1 $83 /--* t76 ref [000166] -c---------- t166 = * LEA(b+8) ref /--* t166 ref N002 ( 3, 3) [000077] ---XG------- t77 = * IND int $1c0 N003 ( 1, 1) [000009] -c---------- t9 = CNS_INT int -1 $46 /--* t77 int +--* t9 int N004 ( 5, 5) [000010] ---XG------- t10 = * ADD int $1c2 /--* t10 int N006 ( 5, 5) [000012] DA-XG------- * STORE_LCL_VAR int V07 loc1 d:2 [000155] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 1) [000013] ------------ t13 = CNS_INT int 0 $40 /--* t13 int N003 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 [000156] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR int V07 loc1 u:2 $1c1 N002 ( 1, 1) [000153] -c---------- t153 = CNS_INT int 0 $40 /--* t126 int +--* t153 int N003 ( 3, 3) [000124] J------N---- * LT void $1c3 N004 ( 5, 5) [000127] ------------ * JTRUE void ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} N001 ( 0, 0) [000151] ------------ t151 = PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ t143 = PHI_ARG bool V06 loc0 u:2 $41 /--* t151 bool +--* t143 bool N003 ( 0, 0) [000138] ------------ t138 = * PHI bool /--* t138 bool N005 ( 0, 0) [000139] DA---------- * STORE_LCL_VAR bool V06 loc0 d:4 N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ t144 = PHI_ARG int V08 loc2 u:2 $40 /--* t152 int +--* t144 int N003 ( 0, 0) [000129] ------------ t129 = * PHI int /--* t129 int N005 ( 0, 0) [000130] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V08 loc2 u:3 $280 N002 ( 1, 1) [000081] ------------ t81 = LCL_VAR ref V14 tmp2 u:1 $84 /--* t81 ref [000168] -c---------- t168 = * LEA(b+8) ref /--* t168 ref N003 ( 3, 3) [000092] -c-X-------- t92 = * IND int $1c5 /--* t22 int +--* t92 int N004 ( 8, 11) [000093] ---X-------- * ARR_BOUNDS_CHECK_Rng void $18a N005 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V14 tmp2 u:1 $84 N006 ( 1, 1) [000091] ------------ t91 = LCL_VAR int V08 loc2 u:3 $280 /--* t91 int N007 ( 2, 3) [000094] ------------ t94 = * CAST long <- int $300 /--* t90 ref +--* t94 long N012 ( 5, 6) [000099] -c---------- t99 = * LEA(b+(i*8)+16) byref /--* t99 byref N013 ( 6, 7) [000082] a---G------- t82 = * IND ref /--* t82 ref N016 ( 18, 21) [000028] DA-XG------- * STORE_LCL_VAR ref V09 loc3 d:2 N002 ( 1, 1) [000101] ------------ t101 = LCL_VAR ref V13 tmp1 u:1 $83 N003 ( 1, 1) [000102] ------------ t102 = LCL_VAR int V08 loc2 u:3 $280 /--* t102 int N004 ( 2, 3) [000105] ------------ t105 = * CAST long <- int $300 /--* t101 ref +--* t105 long N009 ( 5, 6) [000110] -c---------- t110 = * LEA(b+(i*8)+16) byref /--* t110 byref N010 ( 6, 7) [000087] a---G------- t87 = * IND ref /--* t87 ref N013 ( 6, 7) [000037] DA--G------- * STORE_LCL_VAR ref V10 loc4 d:2 [000157] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 1) [000038] ------------ t38 = CNS_INT ref null $VN.Null /--* t38 ref N003 ( 5, 4) [000040] DA--G------- * STORE_LCL_VAR ref (AX) V11 loc5 [000158] ------------ IL_OFFSET void IL offset: 0x26 N007 ( 3, 3) [000047] ------------ t47 = LCL_VAR_ADDR long V11 loc5 $481 /--* t47 long [000170] ------------ t170 = * PUTARG_REG long REG r9 N008 ( 1, 1) [000041] ------------ t41 = LCL_VAR ref V00 arg0 u:1 $80 /--* t41 ref [000171] ------------ t171 = * PUTARG_REG ref REG rdi N009 ( 1, 1) [000042] ------------ t42 = LCL_VAR ref V01 arg1 u:1 $81 /--* t42 ref [000172] ------------ t172 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000043] ------------ t43 = LCL_VAR ref V10 loc4 u:2 /--* t43 ref [000173] ------------ t173 = * PUTARG_REG ref REG rdx N011 ( 3, 2) [000044] ------------ t44 = LCL_VAR ref V09 loc3 u:2 (last use) /--* t44 ref [000174] ------------ t174 = * PUTARG_REG ref REG rcx N012 ( 1, 1) [000045] ------------ t45 = LCL_VAR ref V04 arg4 u:1 $82 /--* t45 ref [000175] ------------ t175 = * PUTARG_REG ref REG r8 N001 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0xd1ffab1e ftn /--* t176 long N002 ( 5, 12) [000177] -c---------- t177 = * IND long REG NA /--* t170 long arg5 in r9 +--* t171 ref arg0 in rdi +--* t172 ref arg1 in rsi +--* t173 ref arg2 in rdx +--* t174 ref arg3 in rcx +--* t175 ref arg4 in r8 +--* t177 long control expr N013 ( 24, 20) [000048] --CXG------- t48 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints $104 N015 ( 1, 1) [000050] -c---------- t50 = CNS_INT bool 0 $40 /--* t48 bool +--* t50 bool N016 ( 27, 24) [000051] J--XG--N-U-- * EQ void $1c7 N017 ( 29, 26) [000052] ---XG------- * JTRUE void ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} N001 ( 0, 0) [000147] ------------ t147 = PHI_ARG bool V06 loc0 u:5 $40 N002 ( 0, 0) [000146] ------------ t146 = PHI_ARG bool V06 loc0 u:4 $241 /--* t147 bool +--* t146 bool N003 ( 0, 0) [000141] ------------ t141 = * PHI bool /--* t141 bool N005 ( 0, 0) [000142] DA---------- * STORE_LCL_VAR bool V06 loc0 d:6 [000159] ------------ IL_OFFSET void IL offset: 0x38 N004 ( 3, 2) [000053] ------------ t53 = LCL_VAR ref (AX) V11 loc5 $500 /--* t53 ref [000178] ------------ t178 = * PUTARG_REG ref REG rdi N005 ( 1, 1) [000054] ------------ t54 = LCL_VAR ref V10 loc4 u:2 (last use) /--* t54 ref [000179] ------------ t179 = * PUTARG_REG ref REG rsi N006 ( 1, 1) [000055] ------------ t55 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t55 byref [000180] ------------ t180 = * PUTARG_REG byref REG rdx N001 ( 3, 10) [000181] ------------ t181 = CNS_INT(h) long 0xd1ffab1e ftn /--* t181 long N002 ( 5, 12) [000182] -c---------- t182 = * IND long REG NA /--* t178 ref arg0 in rdi +--* t179 ref arg1 in rsi +--* t180 byref arg2 in rdx +--* t182 long control expr N007 ( 19, 12) [000056] --CXG------- t56 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics $106 N009 ( 1, 1) [000058] -c---------- t58 = CNS_INT bool 0 $40 /--* t56 bool +--* t58 bool N010 ( 22, 16) [000059] J--XG--N-U-- * NE void $1c9 N011 ( 24, 18) [000060] ---XG------- * JTRUE void ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} N001 ( 0, 0) [000149] ------------ t149 = PHI_ARG bool V06 loc0 u:7 $40 N002 ( 0, 0) [000148] ------------ t148 = PHI_ARG bool V06 loc0 u:6 $242 /--* t149 bool +--* t148 bool N003 ( 0, 0) [000132] ------------ t132 = * PHI bool /--* t132 bool N005 ( 0, 0) [000133] DA---------- * STORE_LCL_VAR bool V06 loc0 d:8 [000160] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 1, 1) [000061] ------------ t61 = LCL_VAR int V08 loc2 u:3 (last use) $280 N002 ( 1, 1) [000062] -c---------- t62 = CNS_INT int 1 $41 /--* t61 int +--* t62 int N003 ( 3, 3) [000063] ------------ t63 = * ADD int $1ca /--* t63 int N005 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 [000161] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000016] ------------ t16 = LCL_VAR int V08 loc2 u:4 $1ca N002 ( 1, 1) [000017] ------------ t17 = LCL_VAR int V07 loc1 u:2 $1c1 /--* t16 int +--* t17 int N003 ( 3, 3) [000018] J------N---- * LE void $1cb N004 ( 5, 5) [000019] ------------ * JTRUE void ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ t145 = PHI_ARG bool V06 loc0 u:2 $41 /--* t150 bool +--* t145 bool N003 ( 0, 0) [000135] ------------ t135 = * PHI bool /--* t135 bool N005 ( 0, 0) [000136] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 [000162] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 3, 2) [000072] ------------ t72 = LCL_VAR int V06 loc0 u:3 (last use) $240 /--* t72 int N002 ( 4, 3) [000073] ------------ * RETURN int $103 ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} [000163] ------------ IL_OFFSET void IL offset: 0x36 N001 ( 1, 1) [000069] ------------ t69 = CNS_INT int 0 $40 /--* t69 int N003 ( 5, 4) [000071] DA---------- * STORE_LCL_VAR int V06 loc0 d:5 ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} [000164] ------------ IL_OFFSET void IL offset: 0x45 N001 ( 1, 1) [000066] ------------ t66 = CNS_INT int 0 $40 /--* t66 int N003 ( 5, 4) [000068] DA---------- * STORE_LCL_VAR int V06 loc0 d:7 ------------ BB08 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [000169] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Calculate stack level slots *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {V13} {V06 V07 V08} {V00 V01 V04 V05 V13 V14} {V00 V01 V04 V05 V06 V07 V08 V13 V14} BB02 use def in out {V00 V01 V04 V08 V13 V14} {V09 V10} {V00 V01 V04 V05 V06 V07 V08 V13 V14} {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} BB03 use def in out {V05 V10} {} {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} {V00 V01 V04 V05 V06 V07 V08 V13 V14} BB04 use def in out {V07 V08} {V08} {V00 V01 V04 V05 V06 V07 V08 V13 V14} {V00 V01 V04 V05 V06 V07 V08 V13 V14} BB05 use def in out {V06} {} {V06} {} BB06 use def in out {} {V06} {V00 V01 V04 V05 V07 V08 V10 V13 V14} {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} BB07 use def in out {} {V06} {V00 V01 V04 V05 V07 V08 V13 V14} {V00 V01 V04 V05 V06 V07 V08 V13 V14} BB08 use def in out {} {} {} {} Interval 0: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 0: (V00) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: (V01) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: (V04) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 3: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 3: (V05) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 4: int RefPositions {} physReg:NA Preferences=[allInt] Interval 4: (V06) int RefPositions {} physReg:NA Preferences=[allInt] Interval 5: int RefPositions {} physReg:NA Preferences=[allInt] Interval 5: (V07) int RefPositions {} physReg:NA Preferences=[allInt] Interval 6: int RefPositions {} physReg:NA Preferences=[allInt] Interval 6: (V08) int RefPositions {} physReg:NA Preferences=[allInt] Interval 7: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 7: (V09) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 8: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 8: (V10) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 9: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 9: (V13) ref (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 10: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 10: (V14) ref (field) RefPositions {} physReg:NA Preferences=[allInt] FP callee save candidate vars: None floatVarCount = 0; hasLoops = 1, singleExit = 1 ; Decided to create an EBP based frame for ETW stackwalking (BasicBlock Count) TUPLE STYLE DUMP BEFORE LSRA New BlockSet epoch 4, # of blocks (including unused BB00): 9, bitset array size: 1 (short) LSRA Block Sequence: BB01( 1 ) BB02( 1.06) BB03( 1.06) BB04( 1.06) BB05( 1 ) BB06( 0.03) BB07( 0 ) BB08( 0 ) BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} ===== N001. CNS_INT 1 N003. V06(t8) N001. V13(t76) N000. t166 = LEA(b+8) ; t76 N002. t77 = IND ; t166 N003. CNS_INT -1 N004. t10 = ADD ; t77 N006. V07(t12); t10 N000. IL_OFFSET IL offset: 0xc N001. t13 = CNS_INT 0 N003. V08(t15); t13 N000. IL_OFFSET IL offset: 0x4b N001. V07(t126) N002. CNS_INT 0 N003. LT ; t126 N004. JTRUE BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} ===== N001. V08(t22) N002. V14(t81) N000. t168 = LEA(b+8) ; t81 N003. t92 = IND ; t168 N004. ARR_BOUNDS_CHECK_Rng; t22,t92 N005. V14(t90) N006. V08(t91) N007. t94 = CAST ; t91 N012. t99 = LEA(b+(i*8)+16); t90,t94 N013. t82 = IND ; t99 N016. V09(t28); t82 N002. V13(t101) N003. V08(t102) N004. t105 = CAST ; t102 N009. t110 = LEA(b+(i*8)+16); t101,t105 N010. t87 = IND ; t110 N013. V10(t37); t87 N000. IL_OFFSET IL offset: 0x23 N001. t38 = CNS_INT null N003. V11 MEM; t38 N000. IL_OFFSET IL offset: 0x26 N007. t47 = LCL_VAR_ADDR V11 loc5 N000. t170 = PUTARG_REG; t47 N008. V00(t41) N000. t171 = PUTARG_REG; t41 N009. V01(t42) N000. t172 = PUTARG_REG; t42 N010. V10(t43) N000. t173 = PUTARG_REG; t43 N011. V09(t44*) N000. t174 = PUTARG_REG; t44* N012. V04(t45) N000. t175 = PUTARG_REG; t45 N001. t176 = CNS_INT(h) 0xd1ffab1e ftn N002. t177 = IND ; t176 N013. t48 = CALL r2r_ind; t170,t171,t172,t173,t174,t175,t177 N015. CNS_INT 0 N016. EQ ; t48 N017. JTRUE BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} ===== N000. IL_OFFSET IL offset: 0x38 N004. t53 = V11 MEM N000. t178 = PUTARG_REG; t53 N005. V10(t54*) N000. t179 = PUTARG_REG; t54* N006. V05(t55) N000. t180 = PUTARG_REG; t55 N001. t181 = CNS_INT(h) 0xd1ffab1e ftn N002. t182 = IND ; t181 N007. t56 = CALL r2r_ind; t178,t179,t180,t182 N009. CNS_INT 0 N010. NE ; t56 N011. JTRUE BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} ===== N000. IL_OFFSET IL offset: 0x47 N001. V08(t61*) N002. CNS_INT 1 N003. t63 = ADD ; t61* N005. V08(t65); t63 N000. IL_OFFSET IL offset: 0x4b N001. V08(t16) N002. V07(t17) N003. LE ; t16,t17 N004. JTRUE BB05 [04F..051) (return), preds={BB01,BB04} succs={} ===== N000. IL_OFFSET IL offset: 0x4f N001. V06(t72*) N002. RETURN ; t72* BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} ===== N000. IL_OFFSET IL offset: 0x36 N001. t69 = CNS_INT 0 N003. V06(t71); t69 BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} ===== N000. IL_OFFSET IL offset: 0x45 N001. t66 = CNS_INT 0 N003. V06(t68); t66 BB08 [???..???) (throw), preds={} succs={} ===== N001. CALL help buildIntervals second part ======== Int arg V14 in reg rcx (second half) in reg STK BB00 regmask=[rcx] minReg=1 fixed> Int arg V00 in reg rdi BB00 regmask=[rdi] minReg=1 fixed> Int arg V01 in reg rsi BB00 regmask=[rsi] minReg=1 fixed> Int arg V04 in reg r8 BB00 regmask=[r8] minReg=1 fixed> Int arg V05 in reg r9 BB00 regmask=[r9] minReg=1 fixed> Int arg V13 in reg rdx (second half) in reg STK BB00 regmask=[rdx] minReg=1 fixed> NEW BLOCK BB01 DefList: { } N003 ( 1, 1) [000006] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N005 ( 5, 4) [000008] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 NA REG NA STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N007 ( 1, 1) [000076] ------------ * LCL_VAR ref V13 tmp1 u:1 NA REG NA $83 DefList: { } N009 (???,???) [000166] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N011 ( 3, 3) [000077] ---XG------- * IND int REG NA $1c0 LCL_VAR BB01 regmask=[allInt] minReg=1 last> Interval 11: int RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N011.t77. IND } N013 ( 1, 1) [000009] -c---------- * CNS_INT int -1 REG NA $46 Contained DefList: { N011.t77. IND } N015 ( 5, 5) [000010] ---XG------- * ADD int REG NA $1c2 BB01 regmask=[allInt] minReg=1 last> Interval 12: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB01 regmask=[allInt] minReg=1> Assigning related to DefList: { N015.t10. ADD } N017 ( 5, 5) [000012] DA-XG------- * STORE_LCL_VAR int V07 loc1 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N019 (???,???) [000155] ------------ * IL_OFFSET void IL offset: 0xc REG NA DefList: { } N021 ( 1, 1) [000013] ------------ * CNS_INT int 0 REG NA $40 Interval 13: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N021.t13. CNS_INT } N023 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N025 (???,???) [000156] ------------ * IL_OFFSET void IL offset: 0x4b REG NA DefList: { } N027 ( 1, 1) [000126] ------------ * LCL_VAR int V07 loc1 u:2 NA REG NA $1c1 DefList: { } N029 ( 1, 1) [000153] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N031 ( 3, 3) [000124] J------N---- * LT void REG NA $1c3 LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N033 ( 5, 5) [000127] ------------ * JTRUE void REG NA CHECKING LAST USES for BB01, liveout={V00 V01 V04 V05 V06 V07 V08 V13 V14} ============================== use: {V13} def: {V06 V07 V08} NEW BLOCK BB02 Setting BB01 as the predecessor for determining incoming variable registers of BB02 DefList: { } N037 ( 1, 1) [000022] ------------ * LCL_VAR int V08 loc2 u:3 NA REG NA $280 DefList: { } N039 ( 1, 1) [000081] ------------ * LCL_VAR ref V14 tmp2 u:1 NA REG NA $84 DefList: { } N041 (???,???) [000168] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N043 ( 3, 3) [000092] -c-X-------- * IND int REG NA $1c5 Contained DefList: { } N045 ( 8, 11) [000093] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA $18a LCL_VAR BB02 regmask=[allInt] minReg=1 last> LCL_VAR BB02 regmask=[allInt] minReg=1 last> DefList: { } N047 ( 1, 1) [000090] ------------ * LCL_VAR ref V14 tmp2 u:1 NA REG NA $84 DefList: { } N049 ( 1, 1) [000091] ------------ * LCL_VAR int V08 loc2 u:3 NA REG NA $280 DefList: { } N051 ( 2, 3) [000094] ------------ * CAST long <- int REG NA $300 LCL_VAR BB02 regmask=[allInt] minReg=1 last> Interval 14: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB02 regmask=[allInt] minReg=1> DefList: { N051.t94. CAST } N053 ( 5, 6) [000099] -c---------- * LEA(b+(i*8)+16) byref REG NA Contained DefList: { N051.t94. CAST } N055 ( 6, 7) [000082] a---G------- * IND ref REG NA LCL_VAR BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[allInt] minReg=1 last> Interval 15: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB02 regmask=[allInt] minReg=1> DefList: { N055.t82. IND } N057 ( 18, 21) [000028] DA-XG------- * STORE_LCL_VAR ref V09 loc3 d:2 NA REG NA BB02 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last> DefList: { } N059 ( 1, 1) [000101] ------------ * LCL_VAR ref V13 tmp1 u:1 NA REG NA $83 DefList: { } N061 ( 1, 1) [000102] ------------ * LCL_VAR int V08 loc2 u:3 NA REG NA $280 DefList: { } N063 ( 2, 3) [000105] ------------ * CAST long <- int REG NA $300 LCL_VAR BB02 regmask=[allInt] minReg=1 last> Interval 16: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB02 regmask=[allInt] minReg=1> DefList: { N063.t105. CAST } N065 ( 5, 6) [000110] -c---------- * LEA(b+(i*8)+16) byref REG NA Contained DefList: { N063.t105. CAST } N067 ( 6, 7) [000087] a---G------- * IND ref REG NA LCL_VAR BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[allInt] minReg=1 last> Interval 17: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB02 regmask=[allInt] minReg=1> DefList: { N067.t87. IND } N069 ( 6, 7) [000037] DA--G------- * STORE_LCL_VAR ref V10 loc4 d:2 NA REG NA BB02 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last> DefList: { } N071 (???,???) [000157] ------------ * IL_OFFSET void IL offset: 0x23 REG NA DefList: { } N073 ( 1, 1) [000038] ------------ * CNS_INT ref null REG NA $VN.Null Interval 18: ref RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB02 regmask=[allInt] minReg=1> DefList: { N073.t38. CNS_INT } N075 ( 5, 4) [000040] DA--G------- * STORE_LCL_VAR ref (AX) V11 loc5 NA REG NA BB02 regmask=[allInt] minReg=1 last> DefList: { } N077 (???,???) [000158] ------------ * IL_OFFSET void IL offset: 0x26 REG NA DefList: { } N079 ( 3, 3) [000047] ------------ * LCL_VAR_ADDR long V11 loc5 NA REG NA $481 Interval 19: long RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB02 regmask=[allInt] minReg=1> DefList: { N079.t47. LCL_VAR_ADDR } N081 (???,???) [000170] ------------ * PUTARG_REG long REG r9 BB02 regmask=[r9] minReg=1> BB02 regmask=[r9] minReg=1 last fixed> Interval 20: long RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[r9] minReg=1> PUTARG_REG BB02 regmask=[r9] minReg=1 fixed> DefList: { N081.t170. PUTARG_REG } N083 ( 1, 1) [000041] ------------ * LCL_VAR ref V00 arg0 u:1 NA REG NA $80 DefList: { N081.t170. PUTARG_REG } N085 (???,???) [000171] ------------ * PUTARG_REG ref REG rdi BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 21: ref RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N081.t170. PUTARG_REG; N085.t171. PUTARG_REG } N087 ( 1, 1) [000042] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $81 DefList: { N081.t170. PUTARG_REG; N085.t171. PUTARG_REG } N089 (???,???) [000172] ------------ * PUTARG_REG ref REG rsi BB02 regmask=[rsi] minReg=1> LCL_VAR BB02 regmask=[rsi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 22: ref RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rsi] minReg=1> PUTARG_REG BB02 regmask=[rsi] minReg=1 fixed> Assigning related to DefList: { N081.t170. PUTARG_REG; N085.t171. PUTARG_REG; N089.t172. PUTARG_REG } N091 ( 1, 1) [000043] ------------ * LCL_VAR ref V10 loc4 u:2 NA REG NA DefList: { N081.t170. PUTARG_REG; N085.t171. PUTARG_REG; N089.t172. PUTARG_REG } N093 (???,???) [000173] ------------ * PUTARG_REG ref REG rdx BB02 regmask=[rdx] minReg=1> LCL_VAR BB02 regmask=[rdx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 23: ref RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rdx] minReg=1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> Assigning related to DefList: { N081.t170. PUTARG_REG; N085.t171. PUTARG_REG; N089.t172. PUTARG_REG; N093.t173. PUTARG_REG } N095 ( 3, 2) [000044] ------------ * LCL_VAR ref V09 loc3 u:2 NA (last use) REG NA DefList: { N081.t170. PUTARG_REG; N085.t171. PUTARG_REG; N089.t172. PUTARG_REG; N093.t173. PUTARG_REG } N097 (???,???) [000174] ------------ * PUTARG_REG ref REG rcx BB02 regmask=[rcx] minReg=1> LCL_VAR BB02 regmask=[rcx] minReg=1 last fixed> Interval 24: ref RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rcx] minReg=1> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> DefList: { N081.t170. PUTARG_REG; N085.t171. PUTARG_REG; N089.t172. PUTARG_REG; N093.t173. PUTARG_REG; N097.t174. PUTARG_REG } N099 ( 1, 1) [000045] ------------ * LCL_VAR ref V04 arg4 u:1 NA REG NA $82 DefList: { N081.t170. PUTARG_REG; N085.t171. PUTARG_REG; N089.t172. PUTARG_REG; N093.t173. PUTARG_REG; N097.t174. PUTARG_REG } N101 (???,???) [000175] ------------ * PUTARG_REG ref REG r8 BB02 regmask=[r8] minReg=1> LCL_VAR BB02 regmask=[r8] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 25: ref RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[r8] minReg=1> PUTARG_REG BB02 regmask=[r8] minReg=1 fixed> Assigning related to DefList: { N081.t170. PUTARG_REG; N085.t171. PUTARG_REG; N089.t172. PUTARG_REG; N093.t173. PUTARG_REG; N097.t174. PUTARG_REG; N101.t175. PUTARG_REG } N103 ( 3, 10) [000176] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 26: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB02 regmask=[allInt] minReg=1> DefList: { N081.t170. PUTARG_REG; N085.t171. PUTARG_REG; N089.t172. PUTARG_REG; N093.t173. PUTARG_REG; N097.t174. PUTARG_REG; N101.t175. PUTARG_REG; N103.t176. CNS_INT } N105 ( 5, 12) [000177] -c---------- * IND long REG NA Contained DefList: { N081.t170. PUTARG_REG; N085.t171. PUTARG_REG; N089.t172. PUTARG_REG; N093.t173. PUTARG_REG; N097.t174. PUTARG_REG; N101.t175. PUTARG_REG; N103.t176. CNS_INT } N107 ( 24, 20) [000048] --CXG------- * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints REG NA $104 BB02 regmask=[r9] minReg=1> BB02 regmask=[r9] minReg=1 last fixed> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[r8] minReg=1> BB02 regmask=[r8] minReg=1 last fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[rax] minReg=1> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[r8] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r10] minReg=1> BB02 regmask=[r11] minReg=1> Interval 27: bool RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> DefList: { N107.t48. CALL } N109 ( 1, 1) [000050] -c---------- * CNS_INT bool 0 REG NA $40 Contained DefList: { N107.t48. CALL } N111 ( 27, 24) [000051] J--XG--N-U-- * EQ void REG NA $1c7 BB02 regmask=[allInt] minReg=1 last> DefList: { } N113 ( 29, 26) [000052] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB02, liveout={V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} ============================== use: {V00 V01 V04 V08 V13 V14} def: {V09 V10} NEW BLOCK BB03 Setting BB02 as the predecessor for determining incoming variable registers of BB03 DefList: { } N117 (???,???) [000159] ------------ * IL_OFFSET void IL offset: 0x38 REG NA DefList: { } N119 ( 3, 2) [000053] ------------ * LCL_VAR ref (AX) V11 loc5 NA REG NA $500 Interval 28: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB03 regmask=[allInt] minReg=1> DefList: { N119.t53. LCL_VAR } N121 (???,???) [000178] ------------ * PUTARG_REG ref REG rdi BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1 last fixed> Interval 29: ref RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rdi] minReg=1> PUTARG_REG BB03 regmask=[rdi] minReg=1 fixed> DefList: { N121.t178. PUTARG_REG } N123 ( 1, 1) [000054] ------------ * LCL_VAR ref V10 loc4 u:2 NA (last use) REG NA DefList: { N121.t178. PUTARG_REG } N125 (???,???) [000179] ------------ * PUTARG_REG ref REG rsi BB03 regmask=[rsi] minReg=1> LCL_VAR BB03 regmask=[rsi] minReg=1 last fixed> Interval 30: ref RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rsi] minReg=1> PUTARG_REG BB03 regmask=[rsi] minReg=1 fixed> DefList: { N121.t178. PUTARG_REG; N125.t179. PUTARG_REG } N127 ( 1, 1) [000055] ------------ * LCL_VAR byref V05 arg5 u:1 NA REG NA $c0 DefList: { N121.t178. PUTARG_REG; N125.t179. PUTARG_REG } N129 (???,???) [000180] ------------ * PUTARG_REG byref REG rdx BB03 regmask=[rdx] minReg=1> LCL_VAR BB03 regmask=[rdx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 31: byref RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rdx] minReg=1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed> Assigning related to DefList: { N121.t178. PUTARG_REG; N125.t179. PUTARG_REG; N129.t180. PUTARG_REG } N131 ( 3, 10) [000181] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 32: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB03 regmask=[allInt] minReg=1> DefList: { N121.t178. PUTARG_REG; N125.t179. PUTARG_REG; N129.t180. PUTARG_REG; N131.t181. CNS_INT } N133 ( 5, 12) [000182] -c---------- * IND long REG NA Contained DefList: { N121.t178. PUTARG_REG; N125.t179. PUTARG_REG; N129.t180. PUTARG_REG; N131.t181. CNS_INT } N135 ( 19, 12) [000056] --CXG------- * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics REG NA $106 BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1 last fixed> BB03 regmask=[rsi] minReg=1> BB03 regmask=[rsi] minReg=1 last fixed> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> BB03 regmask=[allInt] minReg=1 last> BB03 regmask=[rax] minReg=1> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rsi] minReg=1> BB03 regmask=[rdi] minReg=1> BB03 regmask=[r8] minReg=1> BB03 regmask=[r9] minReg=1> BB03 regmask=[r10] minReg=1> BB03 regmask=[r11] minReg=1> Interval 33: bool RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> DefList: { N135.t56. CALL } N137 ( 1, 1) [000058] -c---------- * CNS_INT bool 0 REG NA $40 Contained DefList: { N135.t56. CALL } N139 ( 22, 16) [000059] J--XG--N-U-- * NE void REG NA $1c9 BB03 regmask=[allInt] minReg=1 last> DefList: { } N141 ( 24, 18) [000060] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB03, liveout={V00 V01 V04 V05 V06 V07 V08 V13 V14} ============================== use: {V05 V10} def: {} NEW BLOCK BB04 Setting BB03 as the predecessor for determining incoming variable registers of BB04 DefList: { } N145 (???,???) [000160] ------------ * IL_OFFSET void IL offset: 0x47 REG NA DefList: { } N147 ( 1, 1) [000061] ------------ * LCL_VAR int V08 loc2 u:3 NA (last use) REG NA $280 DefList: { } N149 ( 1, 1) [000062] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N151 ( 3, 3) [000063] ------------ * ADD int REG NA $1ca LCL_VAR BB04 regmask=[allInt] minReg=1 last> Interval 34: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB04 regmask=[allInt] minReg=1> Assigning related to DefList: { N151.t63. ADD } N153 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 NA REG NA BB04 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last> DefList: { } N155 (???,???) [000161] ------------ * IL_OFFSET void IL offset: 0x4b REG NA DefList: { } N157 ( 1, 1) [000016] ------------ * LCL_VAR int V08 loc2 u:4 NA REG NA $1ca DefList: { } N159 ( 1, 1) [000017] ------------ * LCL_VAR int V07 loc1 u:2 NA REG NA $1c1 DefList: { } N161 ( 3, 3) [000018] J------N---- * LE void REG NA $1cb LCL_VAR BB04 regmask=[allInt] minReg=1 last> LCL_VAR BB04 regmask=[allInt] minReg=1 last> DefList: { } N163 ( 5, 5) [000019] ------------ * JTRUE void REG NA Exposed uses: BB04 regmask=[allInt] minReg=1> V08 BB04 regmask=[allInt] minReg=1> V14 BB04 regmask=[allInt] minReg=1> V00 BB04 regmask=[allInt] minReg=1> V01 BB04 regmask=[allInt] minReg=1> V04 BB04 regmask=[allInt] minReg=1> V05 BB04 regmask=[allInt] minReg=1> V13 BB04 regmask=[allInt] minReg=1> V07 CHECKING LAST USES for BB04, liveout={V00 V01 V04 V05 V06 V07 V08 V13 V14} ============================== use: {V07 V08} def: {V08} NEW BLOCK BB05 Setting BB04 as the predecessor for determining incoming variable registers of BB05 DefList: { } N167 (???,???) [000162] ------------ * IL_OFFSET void IL offset: 0x4f REG NA DefList: { } N169 ( 3, 2) [000072] ------------ * LCL_VAR int V06 loc0 u:3 NA (last use) REG NA $240 DefList: { } N171 ( 4, 3) [000073] ------------ * RETURN int REG NA $103 BB05 regmask=[rax] minReg=1> LCL_VAR BB05 regmask=[rax] minReg=1 last fixed> CHECKING LAST USES for BB05, liveout={} ============================== use: {V06} def: {} NEW BLOCK BB06 Setting BB02 as the predecessor for determining incoming variable registers of BB06 DefList: { } N175 (???,???) [000163] ------------ * IL_OFFSET void IL offset: 0x36 REG NA DefList: { } N177 ( 1, 1) [000069] ------------ * CNS_INT int 0 REG NA $40 Interval 35: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB06 regmask=[allInt] minReg=1> DefList: { N177.t69. CNS_INT } N179 ( 5, 4) [000071] DA---------- * STORE_LCL_VAR int V06 loc0 d:5 NA REG NA BB06 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last> Exposed uses: BB06 regmask=[allInt] minReg=1> V10 BB06 regmask=[allInt] minReg=1> V06 CHECKING LAST USES for BB06, liveout={V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} ============================== use: {} def: {V06} NEW BLOCK BB07 Setting BB03 as the predecessor for determining incoming variable registers of BB07 firstColdLoc = 183 DefList: { } N183 (???,???) [000164] ------------ * IL_OFFSET void IL offset: 0x45 REG NA DefList: { } N185 ( 1, 1) [000066] ------------ * CNS_INT int 0 REG NA $40 Interval 36: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB07 regmask=[allInt] minReg=1> DefList: { N185.t66. CNS_INT } N187 ( 5, 4) [000068] DA---------- * STORE_LCL_VAR int V06 loc0 d:7 NA REG NA BB07 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB07 regmask=[allInt] minReg=1 last> Exposed uses: BB07 regmask=[allInt] minReg=1> V08 BB07 regmask=[allInt] minReg=1> V14 BB07 regmask=[allInt] minReg=1> V00 BB07 regmask=[allInt] minReg=1> V01 BB07 regmask=[allInt] minReg=1> V04 BB07 regmask=[allInt] minReg=1> V05 BB07 regmask=[allInt] minReg=1> V13 BB07 regmask=[allInt] minReg=1> V07 BB07 regmask=[allInt] minReg=1> V06 CHECKING LAST USES for BB07, liveout={V00 V01 V04 V05 V06 V07 V08 V13 V14} ============================== use: {} def: {V06} NEW BLOCK BB08 No predecessor; Setting BB07 as the predecessor for determining incoming variable registers of BB08 DefList: { } N191 ( 14, 5) [000169] --CXG------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL REG NA BB08 regmask=[rax] minReg=1> BB08 regmask=[rcx] minReg=1> BB08 regmask=[rdx] minReg=1> BB08 regmask=[rsi] minReg=1> BB08 regmask=[rdi] minReg=1> BB08 regmask=[r8] minReg=1> BB08 regmask=[r9] minReg=1> BB08 regmask=[r10] minReg=1> BB08 regmask=[r11] minReg=1> CHECKING LAST USES for BB08, liveout={} ============================== use: {} def: {} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) ref RefPositions {#1@0 #43@85 #131@165 #152@189} physReg:rdi Preferences=[rbx r12-r15] Interval 1: (V01) ref RefPositions {#2@0 #47@89 #132@165 #153@189} physReg:rsi Preferences=[rbx r12-r15] Interval 2: (V04) ref RefPositions {#3@0 #59@101 #133@165 #154@189} physReg:r8 Preferences=[rbx r12-r15] Interval 3: (V05) byref RefPositions {#4@0 #99@129 #134@165 #155@189} physReg:r9 Preferences=[rbx r12-r15] Interval 4: (V06) int RefPositions {#7@6 #139@171 #143@180 #145@181 #149@188 #158@189} physReg:NA Preferences=[rbx r12-r15] Interval 5: (V07) int RefPositions {#13@18 #17@31 #128@161 #136@165 #157@189} physReg:NA Preferences=[rbx r12-r15] Interval 6: (V08) int RefPositions {#16@24 #19@45 #21@51 #28@63 #123@151 #126@154 #127@161 #129@165 #150@189} physReg:NA Preferences=[rbx r12-r15] RelatedInterval Interval 7: (V09) ref RefPositions {#27@58 #55@97} physReg:NA Preferences=[rcx] Interval 8: (V10) ref RefPositions {#34@70 #51@93 #95@125 #144@181} physReg:NA Preferences=[rbx r12-r15] Interval 9: (V13) ref (field) RefPositions {#5@0 #8@11 #30@67 #135@165 #156@189} physReg:rdx Preferences=[rbx r12-r15] Interval 10: (V14) ref (field) RefPositions {#0@0 #20@45 #23@55 #130@165 #151@189} physReg:rcx Preferences=[rbx r12-r15] Interval 11: int RefPositions {#9@12 #10@15} physReg:NA Preferences=[allInt] RelatedInterval Interval 12: int RefPositions {#11@16 #12@17} physReg:NA Preferences=[allInt] RelatedInterval Interval 13: int (constant) RefPositions {#14@22 #15@23} physReg:NA Preferences=[allInt] RelatedInterval Interval 14: long RefPositions {#22@52 #24@55} physReg:NA Preferences=[allInt] Interval 15: ref RefPositions {#25@56 #26@57} physReg:NA Preferences=[allInt] RelatedInterval Interval 16: long RefPositions {#29@64 #31@67} physReg:NA Preferences=[allInt] Interval 17: ref RefPositions {#32@68 #33@69} physReg:NA Preferences=[allInt] RelatedInterval Interval 18: ref (constant) RefPositions {#35@74 #36@75} physReg:NA Preferences=[allInt] Interval 19: long RefPositions {#37@80 #39@81} physReg:NA Preferences=[r9] Interval 20: long RefPositions {#41@82 #64@107} physReg:NA Preferences=[r9] Interval 21: ref (specialPutArg) RefPositions {#45@86 #66@107} physReg:NA Preferences=[rdi] RelatedInterval Interval 22: ref (specialPutArg) RefPositions {#49@90 #68@107} physReg:NA Preferences=[rsi] RelatedInterval Interval 23: ref (specialPutArg) RefPositions {#53@94 #70@107} physReg:NA Preferences=[rdx] RelatedInterval Interval 24: ref RefPositions {#57@98 #72@107} physReg:NA Preferences=[rcx] Interval 25: ref (specialPutArg) RefPositions {#61@102 #74@107} physReg:NA Preferences=[r8] RelatedInterval Interval 26: long (constant) RefPositions {#62@104 #75@107} physReg:NA Preferences=[allInt] Interval 27: bool RefPositions {#86@108 #87@111} physReg:NA Preferences=[rax] Interval 28: ref RefPositions {#89@120 #91@121} physReg:NA Preferences=[rdi] Interval 29: ref RefPositions {#93@122 #104@135} physReg:NA Preferences=[rdi] Interval 30: ref RefPositions {#97@126 #106@135} physReg:NA Preferences=[rsi] Interval 31: byref (specialPutArg) RefPositions {#101@130 #108@135} physReg:NA Preferences=[rdx] RelatedInterval Interval 32: long (constant) RefPositions {#102@132 #109@135} physReg:NA Preferences=[allInt] Interval 33: bool RefPositions {#120@136 #121@139} physReg:NA Preferences=[rax] Interval 34: int RefPositions {#124@152 #125@153} physReg:NA Preferences=[allInt] RelatedInterval Interval 35: int (constant) RefPositions {#141@178 #142@179} physReg:NA Preferences=[allInt] RelatedInterval Interval 36: int (constant) RefPositions {#147@186 #148@187} physReg:NA Preferences=[allInt] RelatedInterval ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ BB00 regmask=[rcx] minReg=1 fixed regOptional> BB00 regmask=[rdi] minReg=1 fixed regOptional> BB00 regmask=[rsi] minReg=1 fixed regOptional> BB00 regmask=[r8] minReg=1 fixed regOptional> BB00 regmask=[r9] minReg=1 fixed regOptional> BB00 regmask=[rdx] minReg=1 fixed regOptional> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> ADD BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> CAST BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> IND BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> CAST BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> IND BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> CNS_INT BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB02 regmask=[r9] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r9] minReg=1 last fixed> BB02 regmask=[r9] minReg=1> PUTARG_REG BB02 regmask=[r9] minReg=1 fixed> BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[rsi] minReg=1> LCL_VAR BB02 regmask=[rsi] minReg=1 fixed> BB02 regmask=[rsi] minReg=1> PUTARG_REG BB02 regmask=[rsi] minReg=1 fixed> BB02 regmask=[rdx] minReg=1> LCL_VAR BB02 regmask=[rdx] minReg=1 fixed> BB02 regmask=[rdx] minReg=1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> BB02 regmask=[rcx] minReg=1> LCL_VAR BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> BB02 regmask=[r8] minReg=1> LCL_VAR BB02 regmask=[r8] minReg=1 fixed> BB02 regmask=[r8] minReg=1> PUTARG_REG BB02 regmask=[r8] minReg=1 fixed> CNS_INT BB02 regmask=[allInt] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r9] minReg=1 last fixed> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[r8] minReg=1> BB02 regmask=[r8] minReg=1 last fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1 last fixed> BB03 regmask=[rdi] minReg=1> PUTARG_REG BB03 regmask=[rdi] minReg=1 fixed> BB03 regmask=[rsi] minReg=1> LCL_VAR BB03 regmask=[rsi] minReg=1 last fixed> BB03 regmask=[rsi] minReg=1> PUTARG_REG BB03 regmask=[rsi] minReg=1 fixed> BB03 regmask=[rdx] minReg=1> LCL_VAR BB03 regmask=[rdx] minReg=1 fixed> BB03 regmask=[rdx] minReg=1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed> CNS_INT BB03 regmask=[allInt] minReg=1> BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1 last fixed> BB03 regmask=[rsi] minReg=1> BB03 regmask=[rsi] minReg=1 last fixed> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> BB03 regmask=[allInt] minReg=1 last> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[rsi] minReg=1 last> BB03 regmask=[rdi] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> BB03 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB04 regmask=[allInt] minReg=1 last> ADD BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB05 regmask=[rax] minReg=1> LCL_VAR BB05 regmask=[rax] minReg=1 last fixed> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 regOptional> BB06 regmask=[allInt] minReg=1 regOptional> CNS_INT BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB08 regmask=[rax] minReg=1 last> BB08 regmask=[rcx] minReg=1 last> BB08 regmask=[rdx] minReg=1 last> BB08 regmask=[rsi] minReg=1 last> BB08 regmask=[rdi] minReg=1 last> BB08 regmask=[r8] minReg=1 last> BB08 regmask=[r9] minReg=1 last> BB08 regmask=[r10] minReg=1 last> BB08 regmask=[r11] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> ----------------- BB00 regmask=[rcx] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> ----------------- BB00 regmask=[rdi] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[rdi] minReg=1 fixed> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> ----------------- BB00 regmask=[rsi] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[rsi] minReg=1 fixed> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> ----------------- BB00 regmask=[r8] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[r8] minReg=1 fixed> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> ----------------- BB00 regmask=[r9] minReg=1 fixed regOptional> LCL_VAR BB03 regmask=[rdx] minReg=1 fixed> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> ----------------- BB00 regmask=[rdx] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[rdx] minReg=1 fixed> LCL_VAR BB03 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[allInt] minReg=1 regOptional> CheckConstraints: LocalVar V10: undefined use at 181 ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB05 regmask=[rax] minReg=1 last fixed> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V14 V00 V01 V04 V05 V13 BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} ===== N003. CNS_INT 1 N005. V06(L4) Def:(#7) N007. V13(L9) N009. LEA(b+8) N011. IND Use:(#8) Def:(#9) Pref: N013. CNS_INT -1 N015. ADD Use:(#10) * Def:(#11) Pref: N017. V07(L5) Use:(#12) * Def:(#13) N019. IL_OFFSET IL offset: 0xc N021. CNS_INT 0 Def:(#14) Pref: N023. V08(L6) Use:(#15) * Def:(#16) Pref: N025. IL_OFFSET IL offset: 0x4b N027. V07(L5) N029. CNS_INT 0 N031. LT Use:(#17) N033. JTRUE BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} ===== N037. V08(L6) N039. V14(L10) N041. LEA(b+8) N043. IND N045. ARR_BOUNDS_CHECK_Rng Use:(#19) Use:(#20) N047. V14(L10) N049. V08(L6) N051. CAST Use:(#21) Def:(#22) N053. LEA(b+(i*8)+16) N055. IND Use:(#23) Use:(#24) * Def:(#25) Pref: N057. V09(L7) Use:(#26) * Def:(#27) N059. V13(L9) N061. V08(L6) N063. CAST Use:(#28) Def:(#29) N065. LEA(b+(i*8)+16) N067. IND Use:(#30) Use:(#31) * Def:(#32) Pref: N069. V10(L8) Use:(#33) * Def:(#34) N071. IL_OFFSET IL offset: 0x23 N073. CNS_INT null Def:(#35) N075. V11 MEM Use:(#36) * N077. IL_OFFSET IL offset: 0x26 N079. LCL_VAR_ADDR V11 loc5 NA Def:(#37) N081. PUTARG_REG Use:(#39) Fixed:r9(#38) * Def:(#41) r9 N083. V00(L0) N085. PUTARG_REG Use:(#43) Fixed:rdi(#42) Def:(#45) rdi Pref: N087. V01(L1) N089. PUTARG_REG Use:(#47) Fixed:rsi(#46) Def:(#49) rsi Pref: N091. V10(L8) N093. PUTARG_REG Use:(#51) Fixed:rdx(#50) Def:(#53) rdx Pref: N095. V09(L7) N097. PUTARG_REG Use:(#55) Fixed:rcx(#54) * Def:(#57) rcx N099. V04(L2) N101. PUTARG_REG Use:(#59) Fixed:r8(#58) Def:(#61) r8 Pref: N103. CNS_INT(h) 0xd1ffab1e ftn Def:(#62) N105. IND N107. CALL r2r_ind Use:(#64) Fixed:r9(#63) * Use:(#66) Fixed:rdi(#65) * Use:(#68) Fixed:rsi(#67) * Use:(#70) Fixed:rdx(#69) * Use:(#72) Fixed:rcx(#71) * Use:(#74) Fixed:r8(#73) * Use:(#75) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#86) rax N109. CNS_INT 0 N111. EQ Use:(#87) * N113. JTRUE BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} ===== N117. IL_OFFSET IL offset: 0x38 N119. V11 MEM Def:(#89) N121. PUTARG_REG Use:(#91) Fixed:rdi(#90) * Def:(#93) rdi N123. V10(L8) N125. PUTARG_REG Use:(#95) Fixed:rsi(#94) * Def:(#97) rsi N127. V05(L3) N129. PUTARG_REG Use:(#99) Fixed:rdx(#98) Def:(#101) rdx Pref: N131. CNS_INT(h) 0xd1ffab1e ftn Def:(#102) N133. IND N135. CALL r2r_ind Use:(#104) Fixed:rdi(#103) * Use:(#106) Fixed:rsi(#105) * Use:(#108) Fixed:rdx(#107) * Use:(#109) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#120) rax N137. CNS_INT 0 N139. NE Use:(#121) * N141. JTRUE BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} ===== N145. IL_OFFSET IL offset: 0x47 N147. V08(L6) N149. CNS_INT 1 N151. ADD Use:(#123) * Def:(#124) Pref: N153. V08(L6) Use:(#125) * Def:(#126) Pref: N155. IL_OFFSET IL offset: 0x4b N157. V08(L6) N159. V07(L5) N161. LE Use:(#127) Use:(#128) N163. JTRUE Exposed use of V08 at #129 Exposed use of V14 at #130 Exposed use of V00 at #131 Exposed use of V01 at #132 Exposed use of V04 at #133 Exposed use of V05 at #134 Exposed use of V13 at #135 Exposed use of V07 at #136 BB05 [04F..051) (return), preds={BB01,BB04} succs={} ===== N167. IL_OFFSET IL offset: 0x4f N169. V06(L4) N171. RETURN Use:(#139) Fixed:rax(#138) * BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} ===== N175. IL_OFFSET IL offset: 0x36 N177. CNS_INT 0 Def:(#141) Pref: N179. V06(L4) Use:(#142) * Def:(#143) Exposed use of V10 at #144 Exposed use of V06 at #145 BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} ===== N183. IL_OFFSET IL offset: 0x45 N185. CNS_INT 0 Def:(#147) Pref: N187. V06(L4) Use:(#148) * Def:(#149) Exposed use of V08 at #150 Exposed use of V14 at #151 Exposed use of V00 at #152 Exposed use of V01 at #153 Exposed use of V04 at #154 Exposed use of V05 at #155 Exposed use of V13 at #156 Exposed use of V07 at #157 Exposed use of V06 at #158 BB08 [???..???) (throw), preds={} succs={} ===== N191. CALL help Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Linear scan intervals after buildIntervals: Interval 0: (V00) ref RefPositions {#1@0 #43@85 #131@165 #152@189} physReg:rdi Preferences=[rbx r12-r15] Interval 1: (V01) ref RefPositions {#2@0 #47@89 #132@165 #153@189} physReg:rsi Preferences=[rbx r12-r15] Interval 2: (V04) ref RefPositions {#3@0 #59@101 #133@165 #154@189} physReg:r8 Preferences=[rbx r12-r15] Interval 3: (V05) byref RefPositions {#4@0 #99@129 #134@165 #155@189} physReg:r9 Preferences=[rbx r12-r15] Interval 4: (V06) int RefPositions {#7@6 #139@171 #143@180 #145@181 #149@188 #158@189} physReg:NA Preferences=[rbx r12-r15] Interval 5: (V07) int RefPositions {#13@18 #17@31 #128@161 #136@165 #157@189} physReg:NA Preferences=[rbx r12-r15] Interval 6: (V08) int RefPositions {#16@24 #19@45 #21@51 #28@63 #123@151 #126@154 #127@161 #129@165 #150@189} physReg:NA Preferences=[rbx r12-r15] RelatedInterval Interval 7: (V09) ref RefPositions {#27@58 #55@97} physReg:NA Preferences=[rcx] Interval 8: (V10) ref RefPositions {#34@70 #51@93 #95@125 #144@181} physReg:NA Preferences=[rbx r12-r15] Interval 9: (V13) ref (field) RefPositions {#5@0 #8@11 #30@67 #135@165 #156@189} physReg:rdx Preferences=[rbx r12-r15] Interval 10: (V14) ref (field) RefPositions {#0@0 #20@45 #23@55 #130@165 #151@189} physReg:rcx Preferences=[rbx r12-r15] Interval 11: int RefPositions {#9@12 #10@15} physReg:NA Preferences=[allInt] RelatedInterval Interval 12: int RefPositions {#11@16 #12@17} physReg:NA Preferences=[allInt] RelatedInterval Interval 13: int (constant) RefPositions {#14@22 #15@23} physReg:NA Preferences=[allInt] RelatedInterval Interval 14: long RefPositions {#22@52 #24@55} physReg:NA Preferences=[allInt] Interval 15: ref RefPositions {#25@56 #26@57} physReg:NA Preferences=[allInt] RelatedInterval Interval 16: long RefPositions {#29@64 #31@67} physReg:NA Preferences=[allInt] Interval 17: ref RefPositions {#32@68 #33@69} physReg:NA Preferences=[allInt] RelatedInterval Interval 18: ref (constant) RefPositions {#35@74 #36@75} physReg:NA Preferences=[allInt] Interval 19: long RefPositions {#37@80 #39@81} physReg:NA Preferences=[r9] Interval 20: long RefPositions {#41@82 #64@107} physReg:NA Preferences=[r9] Interval 21: ref (specialPutArg) RefPositions {#45@86 #66@107} physReg:NA Preferences=[rdi] RelatedInterval Interval 22: ref (specialPutArg) RefPositions {#49@90 #68@107} physReg:NA Preferences=[rsi] RelatedInterval Interval 23: ref (specialPutArg) RefPositions {#53@94 #70@107} physReg:NA Preferences=[rdx] RelatedInterval Interval 24: ref RefPositions {#57@98 #72@107} physReg:NA Preferences=[rcx] Interval 25: ref (specialPutArg) RefPositions {#61@102 #74@107} physReg:NA Preferences=[r8] RelatedInterval Interval 26: long (constant) RefPositions {#62@104 #75@107} physReg:NA Preferences=[allInt] Interval 27: bool RefPositions {#86@108 #87@111} physReg:NA Preferences=[rax] Interval 28: ref RefPositions {#89@120 #91@121} physReg:NA Preferences=[rdi] Interval 29: ref RefPositions {#93@122 #104@135} physReg:NA Preferences=[rdi] Interval 30: ref RefPositions {#97@126 #106@135} physReg:NA Preferences=[rsi] Interval 31: byref (specialPutArg) RefPositions {#101@130 #108@135} physReg:NA Preferences=[rdx] RelatedInterval Interval 32: long (constant) RefPositions {#102@132 #109@135} physReg:NA Preferences=[allInt] Interval 33: bool RefPositions {#120@136 #121@139} physReg:NA Preferences=[rax] Interval 34: int RefPositions {#124@152 #125@153} physReg:NA Preferences=[allInt] RelatedInterval Interval 35: int (constant) RefPositions {#141@178 #142@179} physReg:NA Preferences=[allInt] RelatedInterval Interval 36: int (constant) RefPositions {#147@186 #148@187} physReg:NA Preferences=[allInt] RelatedInterval *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) ref RefPositions {#1@0 #43@85 #131@165 #152@189} physReg:rdi Preferences=[rbx r12-r15] Interval 1: (V01) ref RefPositions {#2@0 #47@89 #132@165 #153@189} physReg:rsi Preferences=[rbx r12-r15] Interval 2: (V04) ref RefPositions {#3@0 #59@101 #133@165 #154@189} physReg:r8 Preferences=[rbx r12-r15] Interval 3: (V05) byref RefPositions {#4@0 #99@129 #134@165 #155@189} physReg:r9 Preferences=[rbx r12-r15] Interval 4: (V06) int RefPositions {#7@6 #139@171 #143@180 #145@181 #149@188 #158@189} physReg:NA Preferences=[rbx r12-r15] Interval 5: (V07) int RefPositions {#13@18 #17@31 #128@161 #136@165 #157@189} physReg:NA Preferences=[rbx r12-r15] Interval 6: (V08) int RefPositions {#16@24 #19@45 #21@51 #28@63 #123@151 #126@154 #127@161 #129@165 #150@189} physReg:NA Preferences=[rbx r12-r15] RelatedInterval Interval 7: (V09) ref RefPositions {#27@58 #55@97} physReg:NA Preferences=[rcx] Interval 8: (V10) ref RefPositions {#34@70 #51@93 #95@125 #144@181} physReg:NA Preferences=[rbx r12-r15] Interval 9: (V13) ref (field) RefPositions {#5@0 #8@11 #30@67 #135@165 #156@189} physReg:rdx Preferences=[rbx r12-r15] Interval 10: (V14) ref (field) RefPositions {#0@0 #20@45 #23@55 #130@165 #151@189} physReg:rcx Preferences=[rbx r12-r15] Interval 11: int RefPositions {#9@12 #10@15} physReg:NA Preferences=[allInt] RelatedInterval Interval 12: int RefPositions {#11@16 #12@17} physReg:NA Preferences=[allInt] RelatedInterval Interval 13: int (constant) RefPositions {#14@22 #15@23} physReg:NA Preferences=[allInt] RelatedInterval Interval 14: long RefPositions {#22@52 #24@55} physReg:NA Preferences=[allInt] Interval 15: ref RefPositions {#25@56 #26@57} physReg:NA Preferences=[allInt] RelatedInterval Interval 16: long RefPositions {#29@64 #31@67} physReg:NA Preferences=[allInt] Interval 17: ref RefPositions {#32@68 #33@69} physReg:NA Preferences=[allInt] RelatedInterval Interval 18: ref (constant) RefPositions {#35@74 #36@75} physReg:NA Preferences=[allInt] Interval 19: long RefPositions {#37@80 #39@81} physReg:NA Preferences=[r9] Interval 20: long RefPositions {#41@82 #64@107} physReg:NA Preferences=[r9] Interval 21: ref (specialPutArg) RefPositions {#45@86 #66@107} physReg:NA Preferences=[rdi] RelatedInterval Interval 22: ref (specialPutArg) RefPositions {#49@90 #68@107} physReg:NA Preferences=[rsi] RelatedInterval Interval 23: ref (specialPutArg) RefPositions {#53@94 #70@107} physReg:NA Preferences=[rdx] RelatedInterval Interval 24: ref RefPositions {#57@98 #72@107} physReg:NA Preferences=[rcx] Interval 25: ref (specialPutArg) RefPositions {#61@102 #74@107} physReg:NA Preferences=[r8] RelatedInterval Interval 26: long (constant) RefPositions {#62@104 #75@107} physReg:NA Preferences=[allInt] Interval 27: bool RefPositions {#86@108 #87@111} physReg:NA Preferences=[rax] Interval 28: ref RefPositions {#89@120 #91@121} physReg:NA Preferences=[rdi] Interval 29: ref RefPositions {#93@122 #104@135} physReg:NA Preferences=[rdi] Interval 30: ref RefPositions {#97@126 #106@135} physReg:NA Preferences=[rsi] Interval 31: byref (specialPutArg) RefPositions {#101@130 #108@135} physReg:NA Preferences=[rdx] RelatedInterval Interval 32: long (constant) RefPositions {#102@132 #109@135} physReg:NA Preferences=[allInt] Interval 33: bool RefPositions {#120@136 #121@139} physReg:NA Preferences=[rax] Interval 34: int RefPositions {#124@152 #125@153} physReg:NA Preferences=[allInt] RelatedInterval Interval 35: int (constant) RefPositions {#141@178 #142@179} physReg:NA Preferences=[allInt] RelatedInterval Interval 36: int (constant) RefPositions {#147@186 #148@187} physReg:NA Preferences=[allInt] RelatedInterval ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ BB00 regmask=[rcx] minReg=1 fixed regOptional> BB00 regmask=[rdi] minReg=1 fixed regOptional> BB00 regmask=[rsi] minReg=1 fixed regOptional> BB00 regmask=[r8] minReg=1 fixed regOptional> BB00 regmask=[r9] minReg=1 fixed regOptional> BB00 regmask=[rdx] minReg=1 fixed regOptional> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> ADD BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> CAST BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> IND BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> CAST BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> IND BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> CNS_INT BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB02 regmask=[r9] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r9] minReg=1 last fixed> BB02 regmask=[r9] minReg=1> PUTARG_REG BB02 regmask=[r9] minReg=1 fixed> BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[rsi] minReg=1> LCL_VAR BB02 regmask=[rsi] minReg=1 fixed> BB02 regmask=[rsi] minReg=1> PUTARG_REG BB02 regmask=[rsi] minReg=1 fixed> BB02 regmask=[rdx] minReg=1> LCL_VAR BB02 regmask=[rdx] minReg=1 fixed> BB02 regmask=[rdx] minReg=1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> BB02 regmask=[rcx] minReg=1> LCL_VAR BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> BB02 regmask=[r8] minReg=1> LCL_VAR BB02 regmask=[r8] minReg=1 fixed> BB02 regmask=[r8] minReg=1> PUTARG_REG BB02 regmask=[r8] minReg=1 fixed> CNS_INT BB02 regmask=[allInt] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r9] minReg=1 last fixed> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[r8] minReg=1> BB02 regmask=[r8] minReg=1 last fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1 last fixed> BB03 regmask=[rdi] minReg=1> PUTARG_REG BB03 regmask=[rdi] minReg=1 fixed> BB03 regmask=[rsi] minReg=1> LCL_VAR BB03 regmask=[rsi] minReg=1 last fixed> BB03 regmask=[rsi] minReg=1> PUTARG_REG BB03 regmask=[rsi] minReg=1 fixed> BB03 regmask=[rdx] minReg=1> LCL_VAR BB03 regmask=[rdx] minReg=1 fixed> BB03 regmask=[rdx] minReg=1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed> CNS_INT BB03 regmask=[allInt] minReg=1> BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1 last fixed> BB03 regmask=[rsi] minReg=1> BB03 regmask=[rsi] minReg=1 last fixed> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> BB03 regmask=[allInt] minReg=1 last> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[rsi] minReg=1 last> BB03 regmask=[rdi] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> BB03 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB04 regmask=[allInt] minReg=1 last> ADD BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB05 regmask=[rax] minReg=1> LCL_VAR BB05 regmask=[rax] minReg=1 last fixed> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 regOptional> BB06 regmask=[allInt] minReg=1 regOptional> CNS_INT BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB08 regmask=[rax] minReg=1 last> BB08 regmask=[rcx] minReg=1 last> BB08 regmask=[rdx] minReg=1 last> BB08 regmask=[rsi] minReg=1 last> BB08 regmask=[rdi] minReg=1 last> BB08 regmask=[r8] minReg=1 last> BB08 regmask=[r9] minReg=1 last> BB08 regmask=[r10] minReg=1 last> BB08 regmask=[r11] minReg=1 last> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 (Interval 0) BB00 regmask=[rdi] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[rdi] minReg=1 fixed> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> --- V01 (Interval 1) BB00 regmask=[rsi] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[rsi] minReg=1 fixed> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> --- V02 --- V03 --- V04 (Interval 2) BB00 regmask=[r8] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[r8] minReg=1 fixed> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> --- V05 (Interval 3) BB00 regmask=[r9] minReg=1 fixed regOptional> LCL_VAR BB03 regmask=[rdx] minReg=1 fixed> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> --- V06 (Interval 4) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB05 regmask=[rax] minReg=1 last fixed> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> --- V07 (Interval 5) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> --- V08 (Interval 6) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> --- V09 (Interval 7) STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[rcx] minReg=1 last fixed> --- V10 (Interval 8) STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[rdx] minReg=1 fixed> LCL_VAR BB03 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[allInt] minReg=1 regOptional> --- V11 --- V12 --- V13 (Interval 9) BB00 regmask=[rdx] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> --- V14 (Interval 10) BB00 regmask=[rcx] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ | |V14a|V13a| |V1 a|V0 a|V4 a|V5 a| | | 0.#0 V14 Parm Alloc rbx | | |V13a|V14a|V1 a|V0 a|V4 a|V5 a| | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 0.#1 V0 Parm Alloc r14 | | |V13a|V14a|V1 a| |V4 a|V5 a| | |V0 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 0.#2 V1 Parm Alloc r15 | | |V13a|V14a| | |V4 a|V5 a| | |V0 a|V1 a| 0.#3 V4 Parm Alloc r12 | | |V13a|V14a| | | |V5 a|V4 a| |V0 a|V1 a| 0.#4 V5 Parm Alloc r13 | | |V13a|V14a| | | | |V4 a|V5 a|V0 a|V1 a| 0.#5 V13 Parm Alloc rax |V13a| | |V14a| | | | |V4 a|V5 a|V0 a|V1 a| 1.#6 BB1 PredBB0 |V13a| | |V14a| | | | |V4 a|V5 a|V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+ 6.#7 V6 Def Alloc r10 |V13a| | |V14a| | | | |V6 a|V4 a|V5 a|V0 a|V1 a| 11.#8 V13 Use Keep rax |V13a| | |V14a| | | | |V6 a|V4 a|V5 a|V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 12.#9 I11 Def Alloc r11 |V13a| | |V14a| | | | |V6 a|I11a|V4 a|V5 a|V0 a|V1 a| 15.#10 I11 Use * Keep r11 |V13a| | |V14a| | | | |V6 a|I11a|V4 a|V5 a|V0 a|V1 a| 16.#11 I12 Def Alloc r11 |V13a| | |V14a| | | | |V6 a|I12a|V4 a|V5 a|V0 a|V1 a| 17.#12 I12 Use * Keep r11 |V13a| | |V14a| | | | |V6 a|I12a|V4 a|V5 a|V0 a|V1 a| 18.#13 V7 Def Alloc r11 |V13a| | |V14a| | | | |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 22.#14 C13 Def Alloc r8 |V13a| | |V14a| | |C13a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 23.#15 C13 Use * Keep r8 |V13a| | |V14a| | |C13a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 24.#16 V8 Def Alloc r8 |V13a| | |V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 31.#17 V7 Use Keep r11 |V13a| | |V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 35.#18 BB2 PredBB1 |V13a| | |V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 45.#19 V8 Use Keep r8 |V13a| | |V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 45.#20 V14 Use Keep rbx |V13a| | |V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 51.#21 V8 Use Keep r8 |V13a| | |V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 52.#22 I14 Def Alloc r9 |V13a| | |V14a| | |V8 a|I14a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 55.#23 V14 Use Keep rbx |V13a| | |V14a| | |V8 a|I14a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 55.#24 I14 Use * Keep r9 |V13a| | |V14a| | |V8 a|I14a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 56.#25 I15 Def Alloc rcx |V13a|I15a| |V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 57.#26 I15 Use * Keep rcx |V13a|I15a| |V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 58.#27 V9 Def Alloc rcx |V13a|V9 a| |V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 63.#28 V8 Use Keep r8 |V13a|V9 a| |V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 64.#29 I16 Def Alloc r9 |V13a|V9 a| |V14a| | |V8 a|I16a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 67.#30 V13 Use Keep rax |V13a|V9 a| |V14a| | |V8 a|I16a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 67.#31 I16 Use * Keep r9 |V13a|V9 a| |V14a| | |V8 a|I16a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 68.#32 I17 Def Alloc rdx |V13a|V9 a|I17a|V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 69.#33 I17 Use * Keep rdx |V13a|V9 a|I17a|V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 70.#34 V10 Def Alloc rdx |V13a|V9 a|V10a|V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 74.#35 C18 Def Alloc r9 |V13a|V9 a|V10a|V14a| | |V8 a|C18a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 75.#36 C18 Use * Keep r9 |V13a|V9 a|V10a|V14a| | |V8 a|C18a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 80.#37 I19 Def Alloc r9 |V13a|V9 a|V10a|V14a| | |V8 a|I19a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 81.#38 r9 Fixd Keep r9 |V13a|V9 a|V10a|V14a| | |V8 a|I19a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 81.#39 I19 Use * Keep r9 |V13a|V9 a|V10a|V14a| | |V8 a|I19a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 82.#40 r9 Fixd Keep r9 |V13a|V9 a|V10a|V14a| | |V8 a| |V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 82.#41 I20 Def Alloc r9 |V13a|V9 a|V10a|V14a| | |V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 85.#42 rdi Fixd Keep rdi |V13a|V9 a|V10a|V14a| | |V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 85.#43 V0 Use Copy rdi |V13a|V9 a|V10a|V14a| |V0 a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 86.#44 rdi Fixd Keep rdi |V13a|V9 a|V10a|V14a| |V0 a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 86.#45 I21 Def Alloc rdi |V13a|V9 a|V10a|V14a| |I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 89.#46 rsi Fixd Keep rsi |V13a|V9 a|V10a|V14a| |I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 89.#47 V1 Use Copy rsi |V13a|V9 a|V10a|V14a|V1 a|I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 90.#48 rsi Fixd Keep rsi |V13a|V9 a|V10a|V14a|V1 a|I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 90.#49 I22 Def Alloc rsi |V13a|V9 a|V10a|V14a|I22a|I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 93.#50 rdx Fixd Keep rdx |V13a|V9 a|V10a|V14a|I22a|I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 93.#51 V10 Use Keep rdx |V13a|V9 a|V10a|V14a|I22a|I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 94.#52 rdx Fixd Keep rdx |V13a|V9 a|V10a|V14a|I22a|I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 94.#53 I23 Def PtArg rdx |V13a|V9 a|V10a|V14a|I22a|I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 97.#54 rcx Fixd Keep rcx |V13a|V9 a|V10a|V14a|I22a|I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 97.#55 V9 Use * Keep rcx |V13a|V9 a|V10a|V14a|I22a|I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 98.#56 rcx Fixd Keep rcx |V13a| |V10a|V14a|I22a|I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 98.#57 I24 Def Alloc rcx |V13a|I24a|V10a|V14a|I22a|I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 101.#58 r8 Fixd Keep r8 |V13a|I24a|V10a|V14a|I22a|I21a|V8 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 101.#59 V4 Use Spill r8 |V13a|I24a|V10a|V14a|I22a|I21a| |I20a|V6 a|V7 a|V4 i|V5 a|V0 a|V1 a| Copy r8 |V13a|I24a|V10a|V14a|I22a|I21a|V4 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 102.#60 r8 Fixd Keep r8 |V13a|I24a|V10a|V14a|I22a|I21a|V4 a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 102.#61 I25 Def Alloc r8 |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|V5 a|V0 a|V1 a| 104.#62 C26 Def Spill r13 |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a| |V0 a|V1 a| Steal r13 |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 107.#63 r9 Fixd Keep r9 |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 107.#64 I20 Use * Keep r9 |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 107.#65 rdi Fixd Keep rdi |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 107.#66 I21 Use * Keep rdi |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 107.#67 rsi Fixd Keep rsi |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 107.#68 I22 Use * Keep rsi |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 107.#69 rdx Fixd Keep rdx |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 107.#70 I23 Use * PtArg rdx |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 107.#71 rcx Fixd Keep rcx |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 107.#72 I24 Use * Keep rcx |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 107.#73 r8 Fixd Keep r8 |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 107.#74 I25 Use * Keep r8 |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 107.#75 C26 Use * Keep r13 |V13a|I24a|V10a|V14a|I22a|I21a|I25a|I20a|V6 a|V7 a|V4 a|C26a|V0 a|V1 a| 108.#76 rax Kill Spill rax | | |V10a|V14a| | | | |V6 a|V7 a|V4 a|C26i|V0 a|V1 a| Keep rax | | |V10a|V14a| | | | |V6 a|V7 a|V4 a|C26i|V0 a|V1 a| 108.#77 rcx Kill Keep rcx | | |V10a|V14a| | | | |V6 a|V7 a|V4 a|C26i|V0 a|V1 a| 108.#78 rdx Kill Spill rdx | | |Busy|V14a| | | | |V6 a|V7 a|V4 a|C26i|V0 a|V1 a| Keep rdx | | | |V14a| | | | |V6 a|V7 a|V4 a|C26i|V0 a|V1 a| 108.#79 rsi Kill Keep rsi | | | |V14a| | | | |V6 a|V7 a|V4 a|C26i|V0 a|V1 a| 108.#80 rdi Kill Keep rdi | | | |V14a| | | | |V6 a|V7 a|V4 a|C26i|V0 a|V1 a| 108.#81 r8 Kill Keep r8 | | | |V14a| | | | |V6 a|V7 a|V4 a|C26i|V0 a|V1 a| 108.#82 r9 Kill Keep r9 | | | |V14a| | | | |V6 a|V7 a|V4 a|C26i|V0 a|V1 a| 108.#83 r10 Kill Spill r10 | | | |V14a| | | | | |V7 a|V4 a|C26i|V0 a|V1 a| Keep r10 | | | |V14a| | | | | |V7 a|V4 a|C26i|V0 a|V1 a| 108.#84 r11 Kill Spill r11 | | | |V14a| | | | | | |V4 a|C26i|V0 a|V1 a| Keep r11 | | | |V14a| | | | | | |V4 a|C26i|V0 a|V1 a| 108.#85 rax Fixd Keep rax | | | |V14a| | | | | | |V4 a|C26i|V0 a|V1 a| 108.#86 I27 Def Alloc rax |I27a| | |V14a| | | | | | |V4 a|C26i|V0 a|V1 a| 111.#87 I27 Use * Keep rax |I27a| | |V14a| | | | | | |V4 a|C26i|V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 115.#88 BB3 PredBB2 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 120.#89 I28 Def Alloc rdi | | | |V14a| |I28a| | | | |V4 a| |V0 a|V1 a| 121.#90 rdi Fixd Keep rdi | | | |V14a| |I28a| | | | |V4 a| |V0 a|V1 a| 121.#91 I28 Use * Keep rdi | | | |V14a| |I28a| | | | |V4 a| |V0 a|V1 a| 122.#92 rdi Fixd Keep rdi | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 122.#93 I29 Def Alloc rdi | | | |V14a| |I29a| | | | |V4 a| |V0 a|V1 a| 125.#94 rsi Fixd Keep rsi | | | |V14a| |I29a| | | | |V4 a| |V0 a|V1 a| 125.#95 V10 Use * ReLod NA | | | |V14a| |I29a| | | | |V4 a| |V0 a|V1 a| Alloc rsi | | | |V14a|V10i|I29a| | | | |V4 a| |V0 a|V1 a| 126.#96 rsi Fixd Keep rsi | | | |V14a|V10i|I29a| | | | |V4 a| |V0 a|V1 a| 126.#97 I30 Def Alloc rsi | | | |V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 129.#98 rdx Fixd Keep rdx | | | |V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 129.#99 V5 Use ReLod NA | | | |V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| Alloc rdx | | |V5 a|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 130.#100 rdx Fixd Keep rdx | | |V5 a|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 130.#101 I31 Def PtArg rdx | | |V5 a|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 132.#102 C32 Def Alloc rax |C32a| |V5 a|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 135.#103 rdi Fixd Keep rdi |C32a| |V5 a|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 135.#104 I29 Use * Keep rdi |C32a| |V5 a|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 135.#105 rsi Fixd Keep rsi |C32a| |V5 a|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 135.#106 I30 Use * Keep rsi |C32a| |V5 a|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 135.#107 rdx Fixd Keep rdx |C32a| |V5 a|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 135.#108 I31 Use * PtArg rdx |C32a| |V5 a|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 135.#109 C32 Use * Keep rax |C32a| |V5 a|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| Restr rsi |C32i| |V5 a|V14a|V10i|I29a| | | | |V4 a| |V0 a|V1 a| 136.#110 rax Kill Keep rax | | |V5 a|V14a|V10i| | | | | |V4 a| |V0 a|V1 a| 136.#111 rcx Kill Keep rcx | | |V5 a|V14a|V10i| | | | | |V4 a| |V0 a|V1 a| 136.#112 rdx Kill Spill rdx | | |Busy|V14a|V10i| | | | | |V4 a| |V0 a|V1 a| Keep rdx | | | |V14a|V10i| | | | | |V4 a| |V0 a|V1 a| 136.#113 rsi Kill Keep rsi | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#114 rdi Kill Keep rdi | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#115 r8 Kill Keep r8 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#116 r9 Kill Keep r9 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#117 r10 Kill Keep r10 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#118 r11 Kill Keep r11 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#119 rax Fixd Keep rax | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#120 I33 Def Alloc rax |I33a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 139.#121 I33 Use * Keep rax |I33a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 143.#122 BB4 PredBB3 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 151.#123 V8 Use * ReLod NA | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| Alloc r13 | | | |V14a| | | | | | |V4 a|V8 i|V0 a|V1 a| 152.#124 I34 Def Alloc r13 | | | |V14a| | | | | | |V4 a|I34a|V0 a|V1 a| 153.#125 I34 Use * Keep r13 | | | |V14a| | | | | | |V4 a|I34a|V0 a|V1 a| Restr r13 | | | |V14a| | | | | | |V4 a|V8 i|V0 a|V1 a| 154.#126 V8 Def Alloc r13 | | | |V14a| | | | | | |V4 a|V8 a|V0 a|V1 a| 161.#127 V8 Use Keep r13 | | | |V14a| | | | | | |V4 a|V8 a|V0 a|V1 a| 161.#128 V7 Use ReLod NA | | | |V14a| | | | | | |V4 a|V8 a|V0 a|V1 a| Alloc r11 | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#129 V8 ExpU Keep NA | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#130 V14 ExpU Keep NA | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#131 V0 ExpU Keep NA | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#132 V1 ExpU Keep NA | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#133 V4 ExpU Keep NA | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#134 V5 ExpU Keep NA | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#135 V13 ExpU Keep NA | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#136 V7 ExpU Keep NA | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 165.#137 BB5 PredBB4 | | | |V14i| | | | | |V7 i|V4 i|V8 i|V0 i|V1 i| 171.#138 rax Fixd Keep rax | | | |V14i| | | | | |V7 i|V4 i|V8 i|V0 i|V1 i| 171.#139 V6 Use * ReLod NA | | | |V14i| | | | | |V7 i|V4 i|V8 i|V0 i|V1 i| Alloc rax |V6 i| | |V14i| | | | | |V7 i|V4 i|V8 i|V0 i|V1 i| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 173.#140 BB6 PredBB2 |V6 i| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 178.#141 C35 Def Alloc rax |C35a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 179.#142 C35 Use * Keep rax |C35a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 180.#143 V6 Def Alloc rax |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 181.#144 V10 ExpU Keep NA |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 181.#145 V6 ExpU Keep NA |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 181.#146 BB7 PredBB3 |V6 i| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 186.#147 C36 Def Alloc rax |C36a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 187.#148 C36 Use * Keep rax |C36a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 188.#149 V6 Def Alloc rax |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 189.#150 V8 ExpU Keep NA |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 189.#151 V14 ExpU Keep NA |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 189.#152 V0 ExpU Keep NA |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 189.#153 V1 ExpU Keep NA |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 189.#154 V4 ExpU Keep NA |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 189.#155 V5 ExpU Keep NA |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 189.#156 V13 ExpU Keep NA |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 189.#157 V7 ExpU Keep NA |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 189.#158 V6 ExpU Keep NA |V6 a| | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 189.#159 BB8 PredBB7 | | | | | | | | | | | | | | | 192.#160 rax Kill Keep rax | | | | | | | | | | | | | | | 192.#161 rcx Kill Keep rcx | | | | | | | | | | | | | | | 192.#162 rdx Kill Keep rdx | | | | | | | | | | | | | | | 192.#163 rsi Kill Keep rsi | | | | | | | | | | | | | | | 192.#164 rdi Kill Keep rdi | | | | | | | | | | | | | | | 192.#165 r8 Kill Keep r8 | | | | | | | | | | | | | | | 192.#166 r9 Kill Keep r9 | | | | | | | | | | | | | | | 192.#167 r10 Kill Keep r10 | | | | | | | | | | | | | | | 192.#168 r11 Kill Keep r11 | | | | | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ BB00 regmask=[rbx] minReg=1 fixed regOptional> BB00 regmask=[r14] minReg=1 fixed regOptional> BB00 regmask=[r15] minReg=1 fixed regOptional> BB00 regmask=[r12] minReg=1 fixed regOptional> BB00 regmask=[] minReg=1 fixed regOptional> BB00 regmask=[rax] minReg=1 fixed regOptional> STORE_LCL_VAR BB01 regmask=[r10] minReg=1 spillAfter> LCL_VAR BB01 regmask=[rax] minReg=1> IND BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last> ADD BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last> STORE_LCL_VAR BB01 regmask=[r11] minReg=1> CNS_INT BB01 regmask=[r8] minReg=1> BB01 regmask=[r8] minReg=1 last> STORE_LCL_VAR BB01 regmask=[r8] minReg=1> LCL_VAR BB01 regmask=[r11] minReg=1 spillAfter regOptional> LCL_VAR BB02 regmask=[r8] minReg=1> LCL_VAR BB02 regmask=[rbx] minReg=1> LCL_VAR BB02 regmask=[r8] minReg=1> CAST BB02 regmask=[r9] minReg=1> LCL_VAR BB02 regmask=[rbx] minReg=1> BB02 regmask=[r9] minReg=1 last> IND BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB02 regmask=[rcx] minReg=1> LCL_VAR BB02 regmask=[r8] minReg=1 spillAfter> CAST BB02 regmask=[r9] minReg=1> LCL_VAR BB02 regmask=[rax] minReg=1 spillAfter> BB02 regmask=[r9] minReg=1 last> IND BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB02 regmask=[rdx] minReg=1> CNS_INT BB02 regmask=[r9] minReg=1> BB02 regmask=[r9] minReg=1 last> LCL_VAR_ADDR BB02 regmask=[r9] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r9] minReg=1 last fixed> BB02 regmask=[r9] minReg=1> PUTARG_REG BB02 regmask=[r9] minReg=1 fixed> BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 copy fixed> BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[rsi] minReg=1> LCL_VAR BB02 regmask=[rsi] minReg=1 copy fixed> BB02 regmask=[rsi] minReg=1> PUTARG_REG BB02 regmask=[rsi] minReg=1 fixed> BB02 regmask=[rdx] minReg=1> LCL_VAR BB02 regmask=[rdx] minReg=1 spillAfter fixed> BB02 regmask=[rdx] minReg=1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> BB02 regmask=[rcx] minReg=1> LCL_VAR BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> BB02 regmask=[r8] minReg=1> LCL_VAR BB02 regmask=[r8] minReg=1 copy fixed> BB02 regmask=[r8] minReg=1> PUTARG_REG BB02 regmask=[r8] minReg=1 fixed> CNS_INT BB02 regmask=[r13] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r9] minReg=1 last fixed> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[r8] minReg=1> BB02 regmask=[r8] minReg=1 last fixed> BB02 regmask=[r13] minReg=1 last> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[rax] minReg=1 last regOptional> LCL_VAR BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1 last fixed> BB03 regmask=[rdi] minReg=1> PUTARG_REG BB03 regmask=[rdi] minReg=1 fixed> BB03 regmask=[rsi] minReg=1> LCL_VAR BB03 regmask=[rsi] minReg=1 last reload fixed> BB03 regmask=[rsi] minReg=1> PUTARG_REG BB03 regmask=[rsi] minReg=1 fixed> BB03 regmask=[rdx] minReg=1> LCL_VAR BB03 regmask=[rdx] minReg=1 reload spillAfter fixed> BB03 regmask=[rdx] minReg=1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed> CNS_INT BB03 regmask=[rax] minReg=1> BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1 last fixed> BB03 regmask=[rsi] minReg=1> BB03 regmask=[rsi] minReg=1 last fixed> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[rsi] minReg=1 last> BB03 regmask=[rdi] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> BB03 regmask=[rax] minReg=1 last regOptional> LCL_VAR BB04 regmask=[r13] minReg=1 last reload> ADD BB04 regmask=[r13] minReg=1> BB04 regmask=[r13] minReg=1 last> STORE_LCL_VAR BB04 regmask=[r13] minReg=1> LCL_VAR BB04 regmask=[r13] minReg=1> LCL_VAR BB04 regmask=[r11] minReg=1 reload regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB05 regmask=[rax] minReg=1> LCL_VAR BB05 regmask=[rax] minReg=1 last reload fixed> CNS_INT BB06 regmask=[rax] minReg=1> BB06 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB06 regmask=[rax] minReg=1> BB06 regmask=[allInt] minReg=1 regOptional> BB06 regmask=[allInt] minReg=1 regOptional> CNS_INT BB07 regmask=[rax] minReg=1> BB07 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB07 regmask=[rax] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 outOfOrder regOptional> BB07 regmask=[allInt] minReg=1 outOfOrder regOptional> BB07 regmask=[allInt] minReg=1 outOfOrder regOptional> BB07 regmask=[allInt] minReg=1 outOfOrder regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB08 regmask=[rax] minReg=1 last> BB08 regmask=[rcx] minReg=1 last> BB08 regmask=[rdx] minReg=1 last> BB08 regmask=[rsi] minReg=1 last> BB08 regmask=[rdi] minReg=1 last> BB08 regmask=[r8] minReg=1 last> BB08 regmask=[r9] minReg=1 last> BB08 regmask=[r10] minReg=1 last> BB08 regmask=[r11] minReg=1 last> VAR REFPOSITIONS AFTER ALLOCATION --- V00 (Interval 0) BB00 regmask=[r14] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[rdi] minReg=1 copy fixed> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 outOfOrder regOptional> --- V01 (Interval 1) BB00 regmask=[r15] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[rsi] minReg=1 copy fixed> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 outOfOrder regOptional> --- V02 --- V03 --- V04 (Interval 2) BB00 regmask=[r12] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[r8] minReg=1 copy fixed> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 outOfOrder regOptional> --- V05 (Interval 3) BB00 regmask=[] minReg=1 fixed regOptional> LCL_VAR BB03 regmask=[rdx] minReg=1 reload spillAfter fixed> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> --- V06 (Interval 4) STORE_LCL_VAR BB01 regmask=[r10] minReg=1 spillAfter> LCL_VAR BB05 regmask=[rax] minReg=1 last reload fixed> STORE_LCL_VAR BB06 regmask=[rax] minReg=1> BB06 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB07 regmask=[rax] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> --- V07 (Interval 5) STORE_LCL_VAR BB01 regmask=[r11] minReg=1> LCL_VAR BB01 regmask=[r11] minReg=1 spillAfter regOptional> LCL_VAR BB04 regmask=[r11] minReg=1 reload regOptional> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> --- V08 (Interval 6) STORE_LCL_VAR BB01 regmask=[r8] minReg=1> LCL_VAR BB02 regmask=[r8] minReg=1> LCL_VAR BB02 regmask=[r8] minReg=1> LCL_VAR BB02 regmask=[r8] minReg=1 spillAfter> LCL_VAR BB04 regmask=[r13] minReg=1 last reload> STORE_LCL_VAR BB04 regmask=[r13] minReg=1> LCL_VAR BB04 regmask=[r13] minReg=1> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> --- V09 (Interval 7) STORE_LCL_VAR BB02 regmask=[rcx] minReg=1> LCL_VAR BB02 regmask=[rcx] minReg=1 last fixed> --- V10 (Interval 8) STORE_LCL_VAR BB02 regmask=[rdx] minReg=1> LCL_VAR BB02 regmask=[rdx] minReg=1 spillAfter fixed> LCL_VAR BB03 regmask=[rsi] minReg=1 last reload fixed> BB06 regmask=[allInt] minReg=1 regOptional> --- V11 --- V12 --- V13 (Interval 9) BB00 regmask=[rax] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[rax] minReg=1> LCL_VAR BB02 regmask=[rax] minReg=1 spillAfter> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> --- V14 (Interval 10) BB00 regmask=[rbx] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[rbx] minReg=1> LCL_VAR BB02 regmask=[rbx] minReg=1> BB04 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 outOfOrder regOptional> Active intervals at end of allocation: ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} Has Critical Edges Prior to Resolution BB01 use def in out {V13} {V06 V07 V08} {V00 V01 V04 V05 V13 V14} {V00 V01 V04 V05 V06 V07 V08 V13 V14} Var=Reg beg of BB01: V14=rbx V00=r14 V01=r15 V04=r12 V13=rax Var=Reg end of BB01: V08=r8 V14=rbx V00=r14 V01=r15 V04=r12 V13=rax BB02 use def in out {V00 V01 V04 V08 V13 V14} {V09 V10} {V00 V01 V04 V05 V06 V07 V08 V13 V14} {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} Var=Reg beg of BB02: V08=r8 V14=rbx V00=r14 V01=r15 V04=r12 V13=rax Var=Reg end of BB02: V14=rbx V00=r14 V01=r15 V04=r12 BB03 use def in out {V05 V10} {} {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} {V00 V01 V04 V05 V06 V07 V08 V13 V14} Var=Reg beg of BB03: V14=rbx V00=r14 V01=r15 V04=r12 Var=Reg end of BB03: V14=rbx V00=r14 V01=r15 V04=r12 BB04 use def in out {V07 V08} {V08} {V00 V01 V04 V05 V06 V07 V08 V13 V14} {V00 V01 V04 V05 V06 V07 V08 V13 V14} Var=Reg beg of BB04: V14=rbx V00=r14 V01=r15 V04=r12 Var=Reg end of BB04: V08=r13 V14=rbx V00=r14 V01=r15 V04=r12 V07=r11 BB05 use def in out {V06} {} {V06} {} Var=Reg beg of BB05: none Var=Reg end of BB05: none BB06 use def in out {} {V06} {V00 V01 V04 V05 V07 V08 V10 V13 V14} {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} Var=Reg beg of BB06: V14=rbx V00=r14 V01=r15 V04=r12 Var=Reg end of BB06: V14=rbx V00=r14 V01=r15 V04=r12 V06=rax BB07 use def in out {} {V06} {V00 V01 V04 V05 V07 V08 V13 V14} {V00 V01 V04 V05 V06 V07 V08 V13 V14} Var=Reg beg of BB07: V14=rbx V00=r14 V01=r15 V04=r12 Var=Reg end of BB07: V14=rbx V00=r14 V01=r15 V04=r12 V06=rax BB08 use def in out {} {} {} {} Var=Reg beg of BB08: none Var=Reg end of BB08: none RESOLVING EDGES BB04 bottom: move V07 from r11 to STK (SharedCritical) BB04 bottom: move V08 from r13 to r8 (SharedCritical) BB04 bottom: move V13 from STK to rax (SharedCritical) BB06 bottom: move V06 from rax to STK (Join) BB07 bottom: move V06 from rax to STK (Join) Set V00 argument initial register to r14 Set V01 argument initial register to r15 Set V04 argument initial register to r12 Set V05 argument initial register to STK Set V13 argument initial register to rax Set V14 argument initial register to rbx Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC LIR BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC LIR BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC LIR BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC LIR BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC LIR BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC LIR BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC LIR BB08 [0011] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} N003 ( 1, 1) [000006] -c---------- t6 = CNS_INT int 1 REG NA $41 /--* t6 int N005 ( 5, 4) [000008] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 NA REG NA N007 ( 1, 1) [000076] ------------ t76 = LCL_VAR ref V13 tmp1 u:1 rax REG rax $83 /--* t76 ref N009 (???,???) [000166] -c---------- t166 = * LEA(b+8) ref REG NA /--* t166 ref N011 ( 3, 3) [000077] ---XG------- t77 = * IND int REG r11 $1c0 N013 ( 1, 1) [000009] -c---------- t9 = CNS_INT int -1 REG NA $46 /--* t77 int +--* t9 int N015 ( 5, 5) [000010] ---XG------- t10 = * ADD int REG r11 $1c2 /--* t10 int N017 ( 5, 5) [000012] DA-XG------- * STORE_LCL_VAR int V07 loc1 d:2 r11 REG r11 N019 (???,???) [000155] ------------ IL_OFFSET void IL offset: 0xc REG NA N021 ( 1, 1) [000013] ------------ t13 = CNS_INT int 0 REG r8 $40 /--* t13 int N023 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 r8 REG r8 N025 (???,???) [000156] ------------ IL_OFFSET void IL offset: 0x4b REG NA N027 ( 1, 1) [000126] -----------Z t126 = LCL_VAR int V07 loc1 u:2 r11 REG r11 $1c1 N029 ( 1, 1) [000153] -c---------- t153 = CNS_INT int 0 REG NA $40 /--* t126 int +--* t153 int N031 ( 3, 3) [000124] J------N---- * LT void REG NA $1c3 N033 ( 5, 5) [000127] ------------ * JTRUE void REG NA ------------ BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} N001 ( 0, 0) [000151] ------------ t151 = PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000143] ------------ t143 = PHI_ARG bool V06 loc0 u:2 $41 /--* t151 bool +--* t143 bool N003 ( 0, 0) [000138] ------------ t138 = * PHI bool /--* t138 bool N005 ( 0, 0) [000139] DA---------- * STORE_LCL_VAR bool V06 loc0 d:4 N001 ( 0, 0) [000152] ------------ t152 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000144] ------------ t144 = PHI_ARG int V08 loc2 u:2 $40 /--* t152 int +--* t144 int N003 ( 0, 0) [000129] ------------ t129 = * PHI int /--* t129 int N005 ( 0, 0) [000130] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 N037 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V08 loc2 u:3 r8 REG r8 $280 N039 ( 1, 1) [000081] ------------ t81 = LCL_VAR ref V14 tmp2 u:1 rbx REG rbx $84 /--* t81 ref N041 (???,???) [000168] -c---------- t168 = * LEA(b+8) ref REG NA /--* t168 ref N043 ( 3, 3) [000092] -c-X-------- t92 = * IND int REG NA $1c5 /--* t22 int +--* t92 int N045 ( 8, 11) [000093] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA $18a N047 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V14 tmp2 u:1 rbx REG rbx $84 N049 ( 1, 1) [000091] ------------ t91 = LCL_VAR int V08 loc2 u:3 r8 REG r8 $280 /--* t91 int N051 ( 2, 3) [000094] ------------ t94 = * CAST long <- int REG r9 $300 /--* t90 ref +--* t94 long N053 ( 5, 6) [000099] -c---------- t99 = * LEA(b+(i*8)+16) byref REG NA /--* t99 byref N055 ( 6, 7) [000082] a---G------- t82 = * IND ref REG rcx /--* t82 ref N057 ( 18, 21) [000028] DA-XG------- * STORE_LCL_VAR ref V09 loc3 d:2 rcx REG rcx N059 ( 1, 1) [000101] -----------Z t101 = LCL_VAR ref V13 tmp1 u:1 rax REG rax $83 N061 ( 1, 1) [000102] -----------Z t102 = LCL_VAR int V08 loc2 u:3 r8 REG r8 $280 /--* t102 int N063 ( 2, 3) [000105] ------------ t105 = * CAST long <- int REG r9 $300 /--* t101 ref +--* t105 long N065 ( 5, 6) [000110] -c---------- t110 = * LEA(b+(i*8)+16) byref REG NA /--* t110 byref N067 ( 6, 7) [000087] a---G------- t87 = * IND ref REG rdx /--* t87 ref N069 ( 6, 7) [000037] DA--G------- * STORE_LCL_VAR ref V10 loc4 d:2 rdx REG rdx N071 (???,???) [000157] ------------ IL_OFFSET void IL offset: 0x23 REG NA N073 ( 1, 1) [000038] ------------ t38 = CNS_INT ref null REG r9 $VN.Null /--* t38 ref N075 ( 5, 4) [000040] DA--G------- * STORE_LCL_VAR ref (AX) V11 loc5 NA REG NA N077 (???,???) [000158] ------------ IL_OFFSET void IL offset: 0x26 REG NA N079 ( 3, 3) [000047] ------------ t47 = LCL_VAR_ADDR long V11 loc5 r9 REG r9 $481 /--* t47 long N081 (???,???) [000170] ------------ t170 = * PUTARG_REG long REG r9 N083 ( 1, 1) [000041] ------------ t41 = LCL_VAR ref V00 arg0 u:1 r14 REG r14 $80 /--* t41 ref N085 (???,???) [000171] ------------ t171 = * PUTARG_REG ref REG rdi N087 ( 1, 1) [000042] ------------ t42 = LCL_VAR ref V01 arg1 u:1 r15 REG r15 $81 /--* t42 ref N089 (???,???) [000172] ------------ t172 = * PUTARG_REG ref REG rsi N091 ( 1, 1) [000043] -----------Z t43 = LCL_VAR ref V10 loc4 u:2 rdx REG rdx /--* t43 ref N093 (???,???) [000173] ------------ t173 = * PUTARG_REG ref REG rdx N095 ( 3, 2) [000044] ------------ t44 = LCL_VAR ref V09 loc3 u:2 rcx (last use) REG rcx /--* t44 ref N097 (???,???) [000174] ------------ t174 = * PUTARG_REG ref REG rcx N099 ( 1, 1) [000045] ------------ t45 = LCL_VAR ref V04 arg4 u:1 r12 REG r12 $82 /--* t45 ref N101 (???,???) [000175] ------------ t175 = * PUTARG_REG ref REG r8 N103 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0xd1ffab1e ftn REG r13 /--* t176 long N105 ( 5, 12) [000177] -c---------- t177 = * IND long REG NA /--* t170 long arg5 in r9 +--* t171 ref arg0 in rdi +--* t172 ref arg1 in rsi +--* t173 ref arg2 in rdx +--* t174 ref arg3 in rcx +--* t175 ref arg4 in r8 +--* t177 long control expr N107 ( 24, 20) [000048] --CXG------- t48 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints REG rax $104 N109 ( 1, 1) [000050] -c---------- t50 = CNS_INT bool 0 REG NA $40 /--* t48 bool +--* t50 bool N111 ( 27, 24) [000051] J--XG--N-U-- * EQ void REG NA $1c7 N113 ( 29, 26) [000052] ---XG------- * JTRUE void REG NA ------------ BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} N001 ( 0, 0) [000147] ------------ t147 = PHI_ARG bool V06 loc0 u:5 $40 N002 ( 0, 0) [000146] ------------ t146 = PHI_ARG bool V06 loc0 u:4 $241 /--* t147 bool +--* t146 bool N003 ( 0, 0) [000141] ------------ t141 = * PHI bool /--* t141 bool N005 ( 0, 0) [000142] DA---------- * STORE_LCL_VAR bool V06 loc0 d:6 N117 (???,???) [000159] ------------ IL_OFFSET void IL offset: 0x38 REG NA N119 ( 3, 2) [000053] ------------ t53 = LCL_VAR ref (AX) V11 loc5 rdi REG rdi $500 /--* t53 ref N121 (???,???) [000178] ------------ t178 = * PUTARG_REG ref REG rdi N123 ( 1, 1) [000054] -----------z t54 = LCL_VAR ref V10 loc4 u:2 rsi (last use) REG rsi /--* t54 ref N125 (???,???) [000179] ------------ t179 = * PUTARG_REG ref REG rsi N127 ( 1, 1) [000055] -----------z t55 = LCL_VAR byref V05 arg5 u:1 rdx REG rdx $c0 /--* t55 byref N129 (???,???) [000180] ------------ t180 = * PUTARG_REG byref REG rdx N131 ( 3, 10) [000181] ------------ t181 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t181 long N133 ( 5, 12) [000182] -c---------- t182 = * IND long REG NA /--* t178 ref arg0 in rdi +--* t179 ref arg1 in rsi +--* t180 byref arg2 in rdx +--* t182 long control expr N135 ( 19, 12) [000056] --CXG------- t56 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics REG rax $106 N137 ( 1, 1) [000058] -c---------- t58 = CNS_INT bool 0 REG NA $40 /--* t56 bool +--* t58 bool N139 ( 22, 16) [000059] J--XG--N-U-- * NE void REG NA $1c9 N141 ( 24, 18) [000060] ---XG------- * JTRUE void REG NA ------------ BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} N001 ( 0, 0) [000149] ------------ t149 = PHI_ARG bool V06 loc0 u:7 $40 N002 ( 0, 0) [000148] ------------ t148 = PHI_ARG bool V06 loc0 u:6 $242 /--* t149 bool +--* t148 bool N003 ( 0, 0) [000132] ------------ t132 = * PHI bool /--* t132 bool N005 ( 0, 0) [000133] DA---------- * STORE_LCL_VAR bool V06 loc0 d:8 N145 (???,???) [000160] ------------ IL_OFFSET void IL offset: 0x47 REG NA N147 ( 1, 1) [000061] -----------z t61 = LCL_VAR int V08 loc2 u:3 r13 (last use) REG r13 $280 N149 ( 1, 1) [000062] -c---------- t62 = CNS_INT int 1 REG NA $41 /--* t61 int +--* t62 int N151 ( 3, 3) [000063] ------------ t63 = * ADD int REG r13 $1ca /--* t63 int N153 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 r13 REG r13 N155 (???,???) [000161] ------------ IL_OFFSET void IL offset: 0x4b REG NA N157 ( 1, 1) [000016] ------------ t16 = LCL_VAR int V08 loc2 u:4 r13 REG r13 $1ca N159 ( 1, 1) [000017] -----------z t17 = LCL_VAR int V07 loc1 u:2 r11 REG r11 $1c1 /--* t16 int +--* t17 int N161 ( 3, 3) [000018] J------N---- * LE void REG NA $1cb N001 ( 1, 1) [000183] -----------Z t183 = LCL_VAR int V07 loc1 r11 REG r11 N001 ( 1, 1) [000184] ------------ t184 = LCL_VAR int V08 loc2 r13 REG r13 /--* t184 int N002 ( 2, 2) [000185] ------------ t185 = * COPY int REG r8 N001 ( 1, 1) [000186] -----------z t186 = LCL_VAR ref V13 tmp1 rax REG rax N163 ( 5, 5) [000019] ------------ * JTRUE void REG NA ------------ BB05 [04F..051) (return), preds={BB01,BB04} succs={} N001 ( 0, 0) [000150] ------------ t150 = PHI_ARG bool V06 loc0 u:8 N002 ( 0, 0) [000145] ------------ t145 = PHI_ARG bool V06 loc0 u:2 $41 /--* t150 bool +--* t145 bool N003 ( 0, 0) [000135] ------------ t135 = * PHI bool /--* t135 bool N005 ( 0, 0) [000136] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 N167 (???,???) [000162] ------------ IL_OFFSET void IL offset: 0x4f REG NA N169 ( 3, 2) [000072] -----------z t72 = LCL_VAR int V06 loc0 u:3 rax (last use) REG rax $240 /--* t72 int N171 ( 4, 3) [000073] ------------ * RETURN int REG NA $103 ------------ BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} N175 (???,???) [000163] ------------ IL_OFFSET void IL offset: 0x36 REG NA N177 ( 1, 1) [000069] ------------ t69 = CNS_INT int 0 REG rax $40 /--* t69 int N179 ( 5, 4) [000071] DA---------- * STORE_LCL_VAR int V06 loc0 d:5 rax REG rax N001 ( 4, 3) [000187] -----------Z t187 = LCL_VAR bool V06 loc0 rax REG rax ------------ BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} N183 (???,???) [000164] ------------ IL_OFFSET void IL offset: 0x45 REG NA N185 ( 1, 1) [000066] ------------ t66 = CNS_INT int 0 REG rax $40 /--* t66 int N187 ( 5, 4) [000068] DA---------- * STORE_LCL_VAR int V06 loc0 d:7 rax REG rax N001 ( 4, 3) [000188] -----------Z t188 = LCL_VAR bool V06 loc0 rax REG rax ------------ BB08 [???..???) (throw), preds={} succs={} N191 ( 14, 5) [000169] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL REG NA ------------------------------------------------------------------------------------------------------------------- Final allocation --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 0.#0 V14 Parm Alloc rbx | | | |V14a| | | | | | | | | | | 0.#1 V0 Parm Alloc r14 | | | |V14a| | | | | | | | |V0 a| | 0.#2 V1 Parm Alloc r15 | | | |V14a| | | | | | | | |V0 a|V1 a| 0.#3 V4 Parm Alloc r12 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 0.#4 V5 Parm NoReg | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 0.#5 V13 Parm Alloc rax |V13a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 1.#6 BB1 PredBB0 |V13a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 6.#7 V6 Def Alloc r10 |V13a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| Spill r10 |V13a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 11.#8 V13 Use Keep rax |V13a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 12.#9 I11 Def Alloc r11 |V13a| | |V14a| | | | | |I11a|V4 a| |V0 a|V1 a| 15.#10 I11 Use * Keep r11 |V13a| | |V14a| | | | | |I11i|V4 a| |V0 a|V1 a| 16.#11 I12 Def Alloc r11 |V13a| | |V14a| | | | | |I12a|V4 a| |V0 a|V1 a| 17.#12 I12 Use * Keep r11 |V13a| | |V14a| | | | | |I12i|V4 a| |V0 a|V1 a| 18.#13 V7 Def Alloc r11 |V13a| | |V14a| | | | | |V7 a|V4 a| |V0 a|V1 a| 22.#14 C13 Def Alloc r8 |V13a| | |V14a| | |C13a| | |V7 a|V4 a| |V0 a|V1 a| 23.#15 C13 Use * Keep r8 |V13a| | |V14a| | |C13i| | |V7 a|V4 a| |V0 a|V1 a| 24.#16 V8 Def Alloc r8 |V13a| | |V14a| | |V8 a| | |V7 a|V4 a| |V0 a|V1 a| 31.#17 V7 Use Keep r11 |V13a| | |V14a| | |V8 a| | |V7 i|V4 a| |V0 a|V1 a| Spill r11 |V13a| | |V14a| | |V8 a| | |V7 i|V4 a| |V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 35.#18 BB2 PredBB1 |V13a| | |V14a| | |V8 a| | | |V4 a| |V0 a|V1 a| 45.#19 V8 Use Keep r8 |V13a| | |V14a| | |V8 a| | | |V4 a| |V0 a|V1 a| 45.#20 V14 Use Keep rbx |V13a| | |V14a| | |V8 a| | | |V4 a| |V0 a|V1 a| 51.#21 V8 Use Keep r8 |V13a| | |V14a| | |V8 a| | | |V4 a| |V0 a|V1 a| 52.#22 I14 Def Alloc r9 |V13a| | |V14a| | |V8 a|I14a| | |V4 a| |V0 a|V1 a| 55.#23 V14 Use Keep rbx |V13a| | |V14a| | |V8 a|I14a| | |V4 a| |V0 a|V1 a| 55.#24 I14 Use * Keep r9 |V13a| | |V14a| | |V8 a|I14i| | |V4 a| |V0 a|V1 a| 56.#25 I15 Def Alloc rcx |V13a|I15a| |V14a| | |V8 a| | | |V4 a| |V0 a|V1 a| 57.#26 I15 Use * Keep rcx |V13a|I15i| |V14a| | |V8 a| | | |V4 a| |V0 a|V1 a| 58.#27 V9 Def Alloc rcx |V13a|V9 a| |V14a| | |V8 a| | | |V4 a| |V0 a|V1 a| 63.#28 V8 Use Keep r8 |V13a|V9 a| |V14a| | |V8 i| | | |V4 a| |V0 a|V1 a| Spill r8 |V13a|V9 a| |V14a| | |V8 i| | | |V4 a| |V0 a|V1 a| 64.#29 I16 Def Alloc r9 |V13a|V9 a| |V14a| | | |I16a| | |V4 a| |V0 a|V1 a| 67.#30 V13 Use Keep rax |V13i|V9 a| |V14a| | | |I16a| | |V4 a| |V0 a|V1 a| Spill rax |V13i|V9 a| |V14a| | | |I16a| | |V4 a| |V0 a|V1 a| 67.#31 I16 Use * Keep r9 | |V9 a| |V14a| | | |I16i| | |V4 a| |V0 a|V1 a| 68.#32 I17 Def Alloc rdx | |V9 a|I17a|V14a| | | | | | |V4 a| |V0 a|V1 a| 69.#33 I17 Use * Keep rdx | |V9 a|I17i|V14a| | | | | | |V4 a| |V0 a|V1 a| 70.#34 V10 Def Alloc rdx | |V9 a|V10a|V14a| | | | | | |V4 a| |V0 a|V1 a| 74.#35 C18 Def Alloc r9 | |V9 a|V10a|V14a| | | |C18a| | |V4 a| |V0 a|V1 a| 75.#36 C18 Use * Keep r9 | |V9 a|V10a|V14a| | | |C18i| | |V4 a| |V0 a|V1 a| 80.#37 I19 Def Alloc r9 | |V9 a|V10a|V14a| | | |I19a| | |V4 a| |V0 a|V1 a| 81.#38 r9 Fixd Keep r9 | |V9 a|V10a|V14a| | | |I19a| | |V4 a| |V0 a|V1 a| 81.#39 I19 Use * Keep r9 | |V9 a|V10a|V14a| | | |I19i| | |V4 a| |V0 a|V1 a| 82.#40 r9 Fixd Keep r9 | |V9 a|V10a|V14a| | | | | | |V4 a| |V0 a|V1 a| 82.#41 I20 Def Alloc r9 | |V9 a|V10a|V14a| | | |I20a| | |V4 a| |V0 a|V1 a| 85.#42 rdi Fixd Keep rdi | |V9 a|V10a|V14a| | | |I20a| | |V4 a| |V0 a|V1 a| 85.#43 V0 Use Copy rdi | |V9 a|V10a|V14a| |V0 a| |I20a| | |V4 a| |V0 a|V1 a| 86.#44 rdi Fixd Keep rdi | |V9 a|V10a|V14a| | | |I20a| | |V4 a| |V0 a|V1 a| 86.#45 I21 Def Alloc rdi | |V9 a|V10a|V14a| |I21a| |I20a| | |V4 a| |V0 a|V1 a| 89.#46 rsi Fixd Keep rsi | |V9 a|V10a|V14a| |I21a| |I20a| | |V4 a| |V0 a|V1 a| 89.#47 V1 Use Copy rsi | |V9 a|V10a|V14a|V1 a|I21a| |I20a| | |V4 a| |V0 a|V1 a| 90.#48 rsi Fixd Keep rsi | |V9 a|V10a|V14a| |I21a| |I20a| | |V4 a| |V0 a|V1 a| 90.#49 I22 Def Alloc rsi | |V9 a|V10a|V14a|I22a|I21a| |I20a| | |V4 a| |V0 a|V1 a| 93.#50 rdx Fixd Keep rdx | |V9 a|V10a|V14a|I22a|I21a| |I20a| | |V4 a| |V0 a|V1 a| 93.#51 V10 Use Keep rdx | |V9 a|V10i|V14a|I22a|I21a| |I20a| | |V4 a| |V0 a|V1 a| Spill rdx | |V9 a|V10i|V14a|I22a|I21a| |I20a| | |V4 a| |V0 a|V1 a| 94.#52 rdx Fixd Keep rdx | |V9 a| |V14a|I22a|I21a| |I20a| | |V4 a| |V0 a|V1 a| 94.#53 I23 Def PtArg rdx | |V9 a| |V14a|I22a|I21a| |I20a| | |V4 a| |V0 a|V1 a| 97.#54 rcx Fixd Keep rcx | |V9 a| |V14a|I22a|I21a| |I20a| | |V4 a| |V0 a|V1 a| 97.#55 V9 Use * Keep rcx | |V9 i| |V14a|I22a|I21a| |I20a| | |V4 a| |V0 a|V1 a| 98.#56 rcx Fixd Keep rcx | | | |V14a|I22a|I21a| |I20a| | |V4 a| |V0 a|V1 a| 98.#57 I24 Def Alloc rcx | |I24a| |V14a|I22a|I21a| |I20a| | |V4 a| |V0 a|V1 a| 101.#58 r8 Fixd Keep r8 | |I24a| |V14a|I22a|I21a| |I20a| | |V4 a| |V0 a|V1 a| 101.#59 V4 Use Copy r8 | |I24a| |V14a|I22a|I21a|V4 a|I20a| | |V4 a| |V0 a|V1 a| 102.#60 r8 Fixd Keep r8 | |I24a| |V14a|I22a|I21a| |I20a| | |V4 a| |V0 a|V1 a| 102.#61 I25 Def Alloc r8 | |I24a| |V14a|I22a|I21a|I25a|I20a| | |V4 a| |V0 a|V1 a| 104.#62 C26 Def Alloc r13 | |I24a| |V14a|I22a|I21a|I25a|I20a| | |V4 a|C26a|V0 a|V1 a| 107.#63 r9 Fixd Keep r9 | |I24a| |V14a|I22a|I21a|I25a|I20a| | |V4 a|C26a|V0 a|V1 a| 107.#64 I20 Use * Keep r9 | |I24a| |V14a|I22a|I21a|I25a|I20i| | |V4 a|C26a|V0 a|V1 a| 107.#65 rdi Fixd Keep rdi | |I24a| |V14a|I22a|I21a|I25a| | | |V4 a|C26a|V0 a|V1 a| 107.#66 I21 Use * Keep rdi | |I24a| |V14a|I22a|I21i|I25a| | | |V4 a|C26a|V0 a|V1 a| 107.#67 rsi Fixd Keep rsi | |I24a| |V14a|I22a| |I25a| | | |V4 a|C26a|V0 a|V1 a| 107.#68 I22 Use * Keep rsi | |I24a| |V14a|I22i| |I25a| | | |V4 a|C26a|V0 a|V1 a| 107.#69 rdx Fixd Keep rdx | |I24a| |V14a| | |I25a| | | |V4 a|C26a|V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 107.#70 I23 Use * PtArg rdx | |I24a| |V14a| | |I25a| | | |V4 a|C26a|V0 a|V1 a| 107.#71 rcx Fixd Keep rcx | |I24a| |V14a| | |I25a| | | |V4 a|C26a|V0 a|V1 a| 107.#72 I24 Use * Keep rcx | |I24i| |V14a| | |I25a| | | |V4 a|C26a|V0 a|V1 a| 107.#73 r8 Fixd Keep r8 | | | |V14a| | |I25a| | | |V4 a|C26a|V0 a|V1 a| 107.#74 I25 Use * Keep r8 | | | |V14a| | |I25i| | | |V4 a|C26a|V0 a|V1 a| 107.#75 C26 Use * Keep r13 | | | |V14a| | | | | | |V4 a|C26i|V0 a|V1 a| 108.#76 rax Kill Keep rax | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 108.#77 rcx Kill Keep rcx | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 108.#78 rdx Kill Keep rdx | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 108.#79 rsi Kill Keep rsi | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 108.#80 rdi Kill Keep rdi | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 108.#81 r8 Kill Keep r8 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 108.#82 r9 Kill Keep r9 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 108.#83 r10 Kill Keep r10 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 108.#84 r11 Kill Keep r11 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 108.#85 rax Fixd Keep rax | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 108.#86 I27 Def Alloc rax |I27a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 111.#87 I27 Use * Keep rax |I27i| | |V14a| | | | | | |V4 a| |V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 115.#88 BB3 PredBB2 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 120.#89 I28 Def Alloc rdi | | | |V14a| |I28a| | | | |V4 a| |V0 a|V1 a| 121.#90 rdi Fixd Keep rdi | | | |V14a| |I28a| | | | |V4 a| |V0 a|V1 a| 121.#91 I28 Use * Keep rdi | | | |V14a| |I28i| | | | |V4 a| |V0 a|V1 a| 122.#92 rdi Fixd Keep rdi | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 122.#93 I29 Def Alloc rdi | | | |V14a| |I29a| | | | |V4 a| |V0 a|V1 a| 125.#94 rsi Fixd Keep rsi | | | |V14a| |I29a| | | | |V4 a| |V0 a|V1 a| 125.#95 V10 Use * ReLod rsi | | | |V14a|V10a|I29a| | | | |V4 a| |V0 a|V1 a| Keep rsi | | | |V14a|V10i|I29a| | | | |V4 a| |V0 a|V1 a| 126.#96 rsi Fixd Keep rsi | | | |V14a| |I29a| | | | |V4 a| |V0 a|V1 a| 126.#97 I30 Def Alloc rsi | | | |V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 129.#98 rdx Fixd Keep rdx | | | |V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 129.#99 V5 Use ReLod rdx | | |V5 a|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| Keep rdx | | |V5 i|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| Spill rdx | | |V5 i|V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 130.#100 rdx Fixd Keep rdx | | | |V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 130.#101 I31 Def PtArg rdx | | | |V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 132.#102 C32 Def Alloc rax |C32a| | |V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 135.#103 rdi Fixd Keep rdi |C32a| | |V14a|I30a|I29a| | | | |V4 a| |V0 a|V1 a| 135.#104 I29 Use * Keep rdi |C32a| | |V14a|I30a|I29i| | | | |V4 a| |V0 a|V1 a| 135.#105 rsi Fixd Keep rsi |C32a| | |V14a|I30a| | | | | |V4 a| |V0 a|V1 a| 135.#106 I30 Use * Keep rsi |C32a| | |V14a|I30i| | | | | |V4 a| |V0 a|V1 a| 135.#107 rdx Fixd Keep rdx |C32a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 135.#108 I31 Use * PtArg rdx |C32a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 135.#109 C32 Use * Keep rax |C32i| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#110 rax Kill Keep rax | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#111 rcx Kill Keep rcx | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#112 rdx Kill Keep rdx | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#113 rsi Kill Keep rsi | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#114 rdi Kill Keep rdi | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#115 r8 Kill Keep r8 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#116 r9 Kill Keep r9 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#117 r10 Kill Keep r10 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#118 r11 Kill Keep r11 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#119 rax Fixd Keep rax | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 136.#120 I33 Def Alloc rax |I33a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 139.#121 I33 Use * Keep rax |I33i| | |V14a| | | | | | |V4 a| |V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 143.#122 BB4 PredBB3 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 151.#123 V8 Use * ReLod r13 | | | |V14a| | | | | | |V4 a|V8 a|V0 a|V1 a| Keep r13 | | | |V14a| | | | | | |V4 a|V8 i|V0 a|V1 a| 152.#124 I34 Def Alloc r13 | | | |V14a| | | | | | |V4 a|I34a|V0 a|V1 a| 153.#125 I34 Use * Keep r13 | | | |V14a| | | | | | |V4 a|I34i|V0 a|V1 a| 154.#126 V8 Def Alloc r13 | | | |V14a| | | | | | |V4 a|V8 a|V0 a|V1 a| 161.#127 V8 Use Keep r13 | | | |V14a| | | | | | |V4 a|V8 a|V0 a|V1 a| 161.#128 V7 Use ReLod r11 | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| Keep r11 | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#129 V8 ExpU | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#130 V14 ExpU | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#131 V0 ExpU | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#132 V1 ExpU | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#133 V4 ExpU | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#134 V5 ExpU | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#135 V13 ExpU | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#136 V7 ExpU | | | |V14a| | | | | |V7 a|V4 a|V8 a|V0 a|V1 a| 165.#0 V7 Move STK | | | |V14a| | | | | | |V4 a|V8 a|V0 a|V1 a| 165.#0 V8 Move r8 | | | |V14a| | |V8 a| | | |V4 a| |V0 a|V1 a| 165.#0 V13 Move rax |V13a| | |V14a| | |V8 a| | | |V4 a| |V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 165.#137 BB5 PredBB4 | | | | | | | | | | | | | | | 171.#138 rax Fixd Keep rax | | | | | | | | | | | | | | | 171.#139 V6 Use * ReLod rax |V6 a| | | | | | | | | | | | | | Keep rax |V6 i| | | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 173.#140 BB6 PredBB2 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 178.#141 C35 Def Alloc rax |C35a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 179.#142 C35 Use * Keep rax |C35i| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 180.#143 V6 Def Alloc rax |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 181.#144 V10 ExpU |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 181.#145 V6 ExpU |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 181.#0 V6 Move STK | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 181.#146 BB7 PredBB3 | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| 186.#147 C36 Def Alloc rax |C36a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 187.#148 C36 Use * Keep rax |C36i| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 188.#149 V6 Def Alloc rax |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 189.#150 V8 ExpU |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 189.#151 V14 ExpU |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 189.#152 V0 ExpU |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 189.#153 V1 ExpU |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 189.#154 V4 ExpU |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 189.#155 V5 ExpU |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 189.#156 V13 ExpU |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 189.#157 V7 ExpU |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 189.#158 V6 ExpU |V6 a| | |V14a| | | | | | |V4 a| |V0 a|V1 a| 189.#0 V6 Move STK | | | |V14a| | | | | | |V4 a| |V0 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 189.#159 BB8 PredBB7 | | | | | | | | | | | | | | | 192.#160 rax Kill Keep rax | | | | | | | | | | | | | | | 192.#161 rcx Kill Keep rcx | | | | | | | | | | | | | | | 192.#162 rdx Kill Keep rdx | | | | | | | | | | | | | | | 192.#163 rsi Kill Keep rsi | | | | | | | | | | | | | | | 192.#164 rdi Kill Keep rdi | | | | | | | | | | | | | | | 192.#165 r8 Kill Keep r8 | | | | | | | | | | | | | | | 192.#166 r9 Kill Keep r9 | | | | | | | | | | | | | | | 192.#167 r10 Kill Keep r10 | | | | | | | | | | | | | | | 192.#168 r11 Kill Keep r11 | | | | | | | | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- BB01 [ 19862]: SpillCount = 2, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0 BB02 [ 20988]: SpillCount = 3, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0 BB03 [ 20988]: SpillCount = 1, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0 BB04 [ 20988]: SpillCount = 0, ResolutionMovs = 3, SplitEdges = 0, CopyReg = 0 BB06 [ 501]: SpillCount = 0, ResolutionMovs = 1, SplitEdges = 0, CopyReg = 0 BB07 [ 0]: SpillCount = 0, ResolutionMovs = 1, SplitEdges = 0, CopyReg = 0 Total Tracked Vars: 11 Total Reg Cand Vars: 11 Total number of Intervals: 36 Total number of RefPositions: 168 Total Spill Count: 6 Weighted: 123676 Total CopyReg Count: 0 Weighted: 0 Total ResolutionMov Count: 5 Weighted: 63465 Total number of split edges: 0 Total Number of spill temps created: 0 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V14(rcx=>rbx) V00(rdi=>r14) V01(rsi=>r15) V04(r8=>r12) V05(r9=>STK) V13(rdx=>rax) BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} ===== N003. CNS_INT 1 N005. V06(STK) N007. V13(rax) N009. STK = LEA(b+8) ; rax N011. r11 = IND ; STK N013. CNS_INT -1 N015. r11 = ADD ; r11 * N017. V07(r11); r11 N019. IL_OFFSET IL offset: 0xc N021. r8 = CNS_INT 0 * N023. V08(r8); r8 N025. IL_OFFSET IL offset: 0x4b S N027. V07(r11) N029. CNS_INT 0 N031. LT ; r11 N033. JTRUE Var=Reg end of BB01: V08=r8 V14=rbx V00=r14 V01=r15 V04=r12 V13=rax BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB02: V08=r8 V14=rbx V00=r14 V01=r15 V04=r12 V13=rax N037. V08(r8) N039. V14(rbx) N041. STK = LEA(b+8) ; rbx N043. STK = IND ; STK N045. ARR_BOUNDS_CHECK_Rng; r8,STK N047. V14(rbx) N049. V08(r8) N051. r9 = CAST ; r8 N053. STK = LEA(b+(i*8)+16); rbx,r9 N055. rcx = IND ; STK * N057. V09(rcx); rcx S N059. V13(rax) S N061. V08(r8) N063. r9 = CAST ; r8 N065. STK = LEA(b+(i*8)+16); rax,r9 N067. rdx = IND ; STK * N069. V10(rdx); rdx N071. IL_OFFSET IL offset: 0x23 N073. r9 = CNS_INT null N075. V11 MEM; r9 N077. IL_OFFSET IL offset: 0x26 N079. r9 = LCL_VAR_ADDR V11 loc5 r9 N081. r9 = PUTARG_REG; r9 N083. V00(r14) N085. rdi = PUTARG_REG; r14 N087. V01(r15) N089. rsi = PUTARG_REG; r15 S N091. V10(rdx) N093. rdx = PUTARG_REG; rdx N095. V09(rcx*) N097. rcx = PUTARG_REG; rcx* N099. V04(r12) N101. r8 = PUTARG_REG; r12 N103. r13 = CNS_INT(h) 0xd1ffab1e ftn N105. STK = IND ; r13 N107. rax = CALL r2r_ind; r9,rdi,rsi,rdx,rcx,r8,STK N109. CNS_INT 0 N111. EQ ; rax N113. JTRUE Var=Reg end of BB02: V14=rbx V00=r14 V01=r15 V04=r12 BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} ===== Predecessor for variable locations: BB02 Var=Reg beg of BB03: V14=rbx V00=r14 V01=r15 V04=r12 N117. IL_OFFSET IL offset: 0x38 N119. rdi = V11 MEM N121. rdi = PUTARG_REG; rdi N123. V10(rsi*)R N125. rsi = PUTARG_REG; rsi* S N127. V05(rdx)R N129. rdx = PUTARG_REG; rdx N131. rax = CNS_INT(h) 0xd1ffab1e ftn N133. STK = IND ; rax N135. rax = CALL r2r_ind; rdi,rsi,rdx,STK N137. CNS_INT 0 N139. NE ; rax N141. JTRUE Var=Reg end of BB03: V14=rbx V00=r14 V01=r15 V04=r12 BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} ===== Predecessor for variable locations: BB03 Var=Reg beg of BB04: V14=rbx V00=r14 V01=r15 V04=r12 N145. IL_OFFSET IL offset: 0x47 N147. V08(r13*)R N149. CNS_INT 1 N151. r13 = ADD ; r13* * N153. V08(r13); r13 N155. IL_OFFSET IL offset: 0x4b N157. V08(r13) N159. V07(r11)R N161. LE ; r13,r11 $ N001. V07(r11) N001. V08(r13) * N002. r8 = COPY ; r13 * N001. V13(rax)R N163. JTRUE Var=Reg end of BB04: V08=r8 V14=rbx V00=r14 V01=r15 V04=r12 V13=rax BB05 [04F..051) (return), preds={BB01,BB04} succs={} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB05: none N167. IL_OFFSET IL offset: 0x4f N169. V06(rax*)R N171. RETURN ; rax* Var=Reg end of BB05: none BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} ===== Predecessor for variable locations: BB02 Var=Reg beg of BB06: V14=rbx V00=r14 V01=r15 V04=r12 N175. IL_OFFSET IL offset: 0x36 N177. rax = CNS_INT 0 * N179. V06(rax); rax $ N001. V06(rax) Var=Reg end of BB06: V14=rbx V00=r14 V01=r15 V04=r12 BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} ===== Predecessor for variable locations: BB03 Var=Reg beg of BB07: V14=rbx V00=r14 V01=r15 V04=r12 N183. IL_OFFSET IL offset: 0x45 N185. rax = CNS_INT 0 * N187. V06(rax); rax $ N001. V06(rax) Var=Reg end of BB07: V14=rbx V00=r14 V01=r15 V04=r12 BB08 [???..???) (throw), preds={} succs={} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB08: none N191. CALL help Var=Reg end of BB08: none *************** Finishing PHASE Linear scan register alloc *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 19862 [000..010)-> BB05 ( cond ) i label target idxlen IBC LIR BB02 [0001] 2 BB01,BB04 1.06 20988 [010..036)-> BB06 ( cond ) i Loop label target gcsafe idxlen bwd bwd-target IBC LIR BB03 [0003] 2 BB02,BB06 1.06 20988 [038..045)-> BB07 ( cond ) i Loop label target gcsafe bwd IBC LIR BB04 [0005] 2 BB03,BB07 1.06 20988 [047..04F)-> BB02 ( cond ) i Loop label target gcsafe bwd IBC LIR BB05 [0007] 2 BB01,BB04 1 19862 [04F..051) (return) i label target IBC LIR BB06 [0002] 1 BB02 0.03 501 [036..038)-> BB03 (always) i label target gcsafe bwd IBC LIR BB07 [0004] 1 BB03 0 0 [045..047)-> BB04 (always) i rare label target gcsafe bwd IBC LIR BB08 [0011] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V14(rbx) V00(r14) V01(r15) V04(r12) V13(rax) Modified regs: [rax rcx rdx rbx rsi rdi r8-r15] Callee-saved registers pushed: 5 [rbx r12-r15] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V06 loc0, size=4, stkOffs=-0x3c Assign V07 loc1, size=4, stkOffs=-0x40 Assign V08 loc2, size=4, stkOffs=-0x44 Pad V11 loc5, size=8, stkOffs=-0x48, pad=4 Assign V11 loc5, size=8, stkOffs=-0x50 Assign V05 arg5, size=8, stkOffs=-0x58 Assign V10 loc4, size=8, stkOffs=-0x60 Assign V13 tmp1, size=8, stkOffs=-0x68 --- delta bump 8 for RA --- delta bump 8 for FP --- delta bump 0 for RBP frame --- virtual stack offset to actual stack offset delta is 16 -- V00 was 0, now 16 -- V01 was 0, now 16 -- V02 was 0, now 16 -- V03 was 0, now 16 -- V04 was 0, now 16 -- V05 was -88, now -72 -- V06 was -60, now -44 -- V07 was -64, now -48 -- V08 was -68, now -52 -- V10 was -96, now -80 -- V11 was -80, now -64 -- V12 was 0, now 16 -- V13 was -104, now -88 -- V14 was 0, now 16 ; Final local variable assignments ; ; V00 arg0 [V00,T02] ( 3, 3.06) ref -> r14 class-hnd ; V01 arg1 [V01,T03] ( 3, 3.06) ref -> r15 class-hnd ;* V02 arg2 [V02 ] ( 0, 0 ) struct ( 8) zero-ref ld-addr-op ;* V03 arg3 [V03 ] ( 0, 0 ) struct ( 8) zero-ref ld-addr-op ; V04 arg4 [V04,T04] ( 3, 3.06) ref -> r12 class-hnd ; V05 arg5 [V05,T05] ( 3, 3.06) byref -> [rbp-0x48] ; V06 loc0 [V06,T10] ( 4, 2.03) bool -> [rbp-0x2C] ; V07 loc1 [V07,T08] ( 3, 3.06) int -> [rbp-0x30] ; V08 loc2 [V08,T00] ( 7, 7.36) int -> [rbp-0x34] ; V09 loc3 [V09,T09] ( 2, 2.12) ref -> rcx class-hnd ; V10 loc4 [V10,T07] ( 3, 3.18) ref -> [rbp-0x50] class-hnd ; V11 loc5 [V11 ] ( 3, 3.18) ref -> [rbp-0x40] do-not-enreg[X] must-init addr-exposed ld-addr-op class-hnd ;# V12 OutArgs [V12 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00] "OutgoingArgSpace" ; V13 tmp1 [V13,T06] ( 3, 3.06) ref -> [rbp-0x58] V02.array(offs=0x00) P-INDEP "field V02.array (fldOffset=0x0)" ; V14 tmp2 [V14,T01] ( 3, 3.12) ref -> rbx V03.array(offs=0x00) P-INDEP "field V03.array (fldOffset=0x0)" ; ; Lcl frame size = 56 Setting stack level from -572662307 to 0 =============== Generating BB01 [000..010) -> BB05 (cond), preds={} succs={BB02,BB05} flags=0x00000000.60230020: i label target idxlen IBC LIR BB01 IN (6)={ V14 V00 V01 V04 V05 V13 } + ByrefExposed + GcHeap OUT(9)={V08 V14 V00 V01 V04 V05 V13 V07 V06} + ByrefExposed + GcHeap Recording Var Locations at start of BB01 V14(rbx) V00(r14) V01(r15) V04(r12) V13(rax) Change life 0000000000000000 {} -> 000000000000007E {V00 V01 V04 V05 V13 V14} V14 in reg rbx is becoming live [------] Live regs: 00000000 {} => 00000008 {rbx} V00 in reg r14 is becoming live [------] Live regs: 00000008 {rbx} => 00004008 {rbx r14} V01 in reg r15 is becoming live [------] Live regs: 00004008 {rbx r14} => 0000C008 {rbx r14 r15} V04 in reg r12 is becoming live [------] Live regs: 0000C008 {rbx r14 r15} => 0000D008 {rbx r12 r14 r15} V05 becoming live V13 in reg rax is becoming live [------] Live regs: 0000D008 {rbx r12 r14 r15} => 0000D009 {rax rbx r12 r14 r15} Live regs: (unchanged) 0000D009 {rax rbx r12 r14 r15} GC regs: (unchanged) 0000D009 {rax rbx r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M12932_BB01: Label: IG02, GCvars=0000000000000020 {V05}, gcrefRegs=0000D009 {rax rbx r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB01, IL range [000..010) Scope info: open scopes = 0 (V00 arg0) [000..051) 1 (V01 arg1) [000..051) 4 (V04 arg4) [000..051) 5 (V05 arg5) [000..051) Generating: N003 ( 1, 1) [000006] -c---------- t6 = CNS_INT int 1 REG NA $41 /--* t6 int Generating: N005 ( 5, 4) [000008] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 NA REG NA IN0001: mov dword ptr [V06 rbp-2CH], 1 Live vars: {V00 V01 V04 V05 V13 V14} => {V00 V01 V04 V05 V06 V13 V14} Generating: N007 ( 1, 1) [000076] ------------ t76 = LCL_VAR ref V13 tmp1 u:1 rax REG rax $83 /--* t76 ref Generating: N009 (???,???) [000166] -c---------- t166 = * LEA(b+8) ref REG NA /--* t166 ref Generating: N011 ( 3, 3) [000077] ---XG------- t77 = * IND int REG r11 $1c0 IN0002: mov r11d, dword ptr [rax+8] Generating: N013 ( 1, 1) [000009] -c---------- t9 = CNS_INT int -1 REG NA $46 /--* t77 int +--* t9 int Generating: N015 ( 5, 5) [000010] ---XG------- t10 = * ADD int REG r11 $1c2 IN0003: dec r11d /--* t10 int Generating: N017 ( 5, 5) [000012] DA-XG------- * STORE_LCL_VAR int V07 loc1 d:2 r11 REG r11 V07 in reg r11 is becoming live [000012] Live regs: 0000D009 {rax rbx r12 r14 r15} => 0000D809 {rax rbx r11 r12 r14 r15} Live vars: {V00 V01 V04 V05 V06 V13 V14} => {V00 V01 V04 V05 V06 V07 V13 V14} Added IP mapping: 0x000C STACK_EMPTY (G_M12932_IG02,ins#3,ofs#14) label Generating: N019 (???,???) [000155] ------------ IL_OFFSET void IL offset: 0xc REG NA Generating: N021 ( 1, 1) [000013] ------------ t13 = CNS_INT int 0 REG r8 $40 IN0004: xor r8d, r8d /--* t13 int Generating: N023 ( 1, 3) [000015] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 r8 REG r8 V08 in reg r8 is becoming live [000015] Live regs: 0000D809 {rax rbx r11 r12 r14 r15} => 0000D909 {rax rbx r8 r11 r12 r14 r15} Live vars: {V00 V01 V04 V05 V06 V07 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V13 V14} Added IP mapping: 0x004B STACK_EMPTY (G_M12932_IG02,ins#4,ofs#17) Generating: N025 (???,???) [000156] ------------ IL_OFFSET void IL offset: 0x4b REG NA Generating: N027 ( 1, 1) [000126] -----------Z t126 = LCL_VAR int V07 loc1 u:2 r11 REG r11 $1c1 Generating: N029 ( 1, 1) [000153] -c---------- t153 = CNS_INT int 0 REG NA $40 /--* t126 int +--* t153 int Generating: N031 ( 3, 3) [000124] J------N---- * LT void REG NA $1c3 IN0005: mov dword ptr [V07 rbp-30H], r11d V07 in reg r11 is becoming dead [000126] Live regs: 0000D909 {rax rbx r8 r11 r12 r14 r15} => 0000D109 {rax rbx r8 r12 r14 r15} IN0006: test r11d, r11d Generating: N033 ( 5, 5) [000127] ------------ * JTRUE void REG NA IN0007: jl L_M12932_BB05 Scope info: end block BB01, IL range [000..010) Scope info: open scopes = 0 (V00 arg0) [000..051) 1 (V01 arg1) [000..051) 4 (V04 arg4) [000..051) 5 (V05 arg5) [000..051) =============== Generating BB02 [010..036) -> BB06 (cond), preds={BB01,BB04} succs={BB03,BB06} flags=0x00000014.622b2020: i Loop label target gcsafe idxlen bwd bwd-target IBC LIR BB02 IN (9)={V08 V14 V00 V01 V04 V05 V13 V07 V06} + ByrefExposed + GcHeap OUT(10)={V08 V14 V00 V01 V04 V05 V13 V10 V07 V06} + ByrefExposed + GcHeap Recording Var Locations at start of BB02 V08(r8) V14(rbx) V00(r14) V01(r15) V04(r12) V13(rax) Liveness not changing: 000000000000057F {V00 V01 V04 V05 V06 V07 V08 V13 V14} Live regs: 00000000 {} => 0000D109 {rax rbx r8 r12 r14 r15} GC regs: 00000000 {} => 0000D009 {rax rbx r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M12932_BB02: G_M12932_IG02: ; offs=000000H, funclet=00, bbWeight=1 Label: IG03, GCvars=0000000000000020 {V05}, gcrefRegs=0000D009 {rax rbx r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB02, IL range [010..036) Scope info: open scopes = 0 (V00 arg0) [000..051) 1 (V01 arg1) [000..051) 4 (V04 arg4) [000..051) 5 (V05 arg5) [000..051) 8 (V08 loc2) [000..051) 7 (V07 loc1) [000..051) 6 (V06 loc0) [000..051) Generating: N037 ( 1, 1) [000022] ------------ t22 = LCL_VAR int V08 loc2 u:3 r8 REG r8 $280 Generating: N039 ( 1, 1) [000081] ------------ t81 = LCL_VAR ref V14 tmp2 u:1 rbx REG rbx $84 /--* t81 ref Generating: N041 (???,???) [000168] -c---------- t168 = * LEA(b+8) ref REG NA /--* t168 ref Generating: N043 ( 3, 3) [000092] -c-X-------- t92 = * IND int REG NA $1c5 /--* t22 int +--* t92 int Generating: N045 ( 8, 11) [000093] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA $18a IN0008: cmp r8d, dword ptr [rbx+8] IN0009: jae L_M12932_BB08 Generating: N047 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V14 tmp2 u:1 rbx REG rbx $84 Generating: N049 ( 1, 1) [000091] ------------ t91 = LCL_VAR int V08 loc2 u:3 r8 REG r8 $280 /--* t91 int Generating: N051 ( 2, 3) [000094] ------------ t94 = * CAST long <- int REG r9 $300 IN000a: movsxd r9, r8d /--* t90 ref +--* t94 long Generating: N053 ( 5, 6) [000099] -c---------- t99 = * LEA(b+(i*8)+16) byref REG NA /--* t99 byref Generating: N055 ( 6, 7) [000082] a---G------- t82 = * IND ref REG rcx IN000b: mov rcx, gword ptr [rbx+8*r9+16] GC regs: 0000D009 {rax rbx r12 r14 r15} => 0000D00B {rax rcx rbx r12 r14 r15} /--* t82 ref Generating: N057 ( 18, 21) [000028] DA-XG------- * STORE_LCL_VAR ref V09 loc3 d:2 rcx REG rcx GC regs: 0000D00B {rax rcx rbx r12 r14 r15} => 0000D009 {rax rbx r12 r14 r15} V09 in reg rcx is becoming live [000028] Live regs: 0000D109 {rax rbx r8 r12 r14 r15} => 0000D10B {rax rcx rbx r8 r12 r14 r15} Live vars: {V00 V01 V04 V05 V06 V07 V08 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V09 V13 V14} GC regs: 0000D009 {rax rbx r12 r14 r15} => 0000D00B {rax rcx rbx r12 r14 r15} Generating: N059 ( 1, 1) [000101] -----------Z t101 = LCL_VAR ref V13 tmp1 u:1 rax REG rax $83 Generating: N061 ( 1, 1) [000102] -----------Z t102 = LCL_VAR int V08 loc2 u:3 r8 REG r8 $280 /--* t102 int Generating: N063 ( 2, 3) [000105] ------------ t105 = * CAST long <- int REG r9 $300 IN000c: mov dword ptr [V08 rbp-34H], r8d V08 in reg r8 is becoming dead [000102] Live regs: 0000D10B {rax rcx rbx r8 r12 r14 r15} => 0000D00B {rax rcx rbx r12 r14 r15} IN000d: movsxd r9, r8d /--* t101 ref +--* t105 long Generating: N065 ( 5, 6) [000110] -c---------- t110 = * LEA(b+(i*8)+16) byref REG NA /--* t110 byref Generating: N067 ( 6, 7) [000087] a---G------- t87 = * IND ref REG rdx IN000e: mov gword ptr [V13 rbp-58H], rax V13 in reg rax is becoming dead [000101] Live regs: 0000D00B {rax rcx rbx r12 r14 r15} => 0000D00A {rcx rbx r12 r14 r15} GC regs: 0000D00B {rax rcx rbx r12 r14 r15} => 0000D00A {rcx rbx r12 r14 r15} Var V13 becoming live IN000f: mov rdx, gword ptr [rax+8*r9+16] GC regs: 0000D00A {rcx rbx r12 r14 r15} => 0000D00E {rcx rdx rbx r12 r14 r15} /--* t87 ref Generating: N069 ( 6, 7) [000037] DA--G------- * STORE_LCL_VAR ref V10 loc4 d:2 rdx REG rdx GC regs: 0000D00E {rcx rdx rbx r12 r14 r15} => 0000D00A {rcx rbx r12 r14 r15} V10 in reg rdx is becoming live [000037] Live regs: 0000D00A {rcx rbx r12 r14 r15} => 0000D00E {rcx rdx rbx r12 r14 r15} Live vars: {V00 V01 V04 V05 V06 V07 V08 V09 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V09 V10 V13 V14} GC regs: 0000D00A {rcx rbx r12 r14 r15} => 0000D00E {rcx rdx rbx r12 r14 r15} Added IP mapping: 0x0023 STACK_EMPTY (G_M12932_IG03,ins#8,ofs#34) label Generating: N071 (???,???) [000157] ------------ IL_OFFSET void IL offset: 0x23 REG NA Generating: N073 ( 1, 1) [000038] ------------ t38 = CNS_INT ref null REG r9 $VN.Null IN0010: xor r9, r9 GC regs: 0000D00E {rcx rdx rbx r12 r14 r15} => 0000D20E {rcx rdx rbx r9 r12 r14 r15} /--* t38 ref Generating: N075 ( 5, 4) [000040] DA--G------- * STORE_LCL_VAR ref (AX) V11 loc5 NA REG NA GC regs: 0000D20E {rcx rdx rbx r9 r12 r14 r15} => 0000D00E {rcx rdx rbx r12 r14 r15} IN0011: mov gword ptr [V11 rbp-40H], r9 Added IP mapping: 0x0026 STACK_EMPTY (G_M12932_IG03,ins#10,ofs#41) Generating: N077 (???,???) [000158] ------------ IL_OFFSET void IL offset: 0x26 REG NA Generating: N079 ( 3, 3) [000047] ------------ t47 = LCL_VAR_ADDR long V11 loc5 r9 REG r9 $481 IN0012: lea r9, [V11 rbp-40H] /--* t47 long Generating: N081 (???,???) [000170] ------------ t170 = * PUTARG_REG long REG r9 Generating: N083 ( 1, 1) [000041] ------------ t41 = LCL_VAR ref V00 arg0 u:1 r14 REG r14 $80 /--* t41 ref Generating: N085 (???,???) [000171] ------------ t171 = * PUTARG_REG ref REG rdi IN0013: mov rdi, r14 GC regs: 0000D00E {rcx rdx rbx r12 r14 r15} => 0000D08E {rcx rdx rbx rdi r12 r14 r15} Generating: N087 ( 1, 1) [000042] ------------ t42 = LCL_VAR ref V01 arg1 u:1 r15 REG r15 $81 /--* t42 ref Generating: N089 (???,???) [000172] ------------ t172 = * PUTARG_REG ref REG rsi IN0014: mov rsi, r15 GC regs: 0000D08E {rcx rdx rbx rdi r12 r14 r15} => 0000D0CE {rcx rdx rbx rsi rdi r12 r14 r15} Generating: N091 ( 1, 1) [000043] -----------Z t43 = LCL_VAR ref V10 loc4 u:2 rdx REG rdx /--* t43 ref Generating: N093 (???,???) [000173] ------------ t173 = * PUTARG_REG ref REG rdx IN0015: mov gword ptr [V10 rbp-50H], rdx V10 in reg rdx is becoming dead [000043] Live regs: 0000D00E {rcx rdx rbx r12 r14 r15} => 0000D00A {rcx rbx r12 r14 r15} GC regs: 0000D0CE {rcx rdx rbx rsi rdi r12 r14 r15} => 0000D0CA {rcx rbx rsi rdi r12 r14 r15} Var V10 becoming live GC regs: 0000D0CA {rcx rbx rsi rdi r12 r14 r15} => 0000D0CE {rcx rdx rbx rsi rdi r12 r14 r15} Generating: N095 ( 3, 2) [000044] ------------ t44 = LCL_VAR ref V09 loc3 u:2 rcx (last use) REG rcx /--* t44 ref Generating: N097 (???,???) [000174] ------------ t174 = * PUTARG_REG ref REG rcx V09 in reg rcx is becoming dead [000044] Live regs: 0000D00A {rcx rbx r12 r14 r15} => 0000D008 {rbx r12 r14 r15} Live vars: {V00 V01 V04 V05 V06 V07 V08 V09 V10 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} GC regs: 0000D0CE {rcx rdx rbx rsi rdi r12 r14 r15} => 0000D0CC {rdx rbx rsi rdi r12 r14 r15} GC regs: 0000D0CC {rdx rbx rsi rdi r12 r14 r15} => 0000D0CE {rcx rdx rbx rsi rdi r12 r14 r15} Generating: N099 ( 1, 1) [000045] ------------ t45 = LCL_VAR ref V04 arg4 u:1 r12 REG r12 $82 /--* t45 ref Generating: N101 (???,???) [000175] ------------ t175 = * PUTARG_REG ref REG r8 IN0016: mov r8, r12 GC regs: 0000D0CE {rcx rdx rbx rsi rdi r12 r14 r15} => 0000D1CE {rcx rdx rbx rsi rdi r8 r12 r14 r15} Generating: N103 ( 3, 10) [000176] ------------ t176 = CNS_INT(h) long 0xd1ffab1e ftn REG r13 IN0017: mov r13, (reloc 0xd1ffab1e) /--* t176 long Generating: N105 ( 5, 12) [000177] -c---------- t177 = * IND long REG NA /--* t170 long arg5 in r9 +--* t171 ref arg0 in rdi +--* t172 ref arg1 in rsi +--* t173 ref arg2 in rdx +--* t174 ref arg3 in rcx +--* t175 ref arg4 in r8 +--* t177 long control expr Generating: N107 ( 24, 20) [000048] --CXG------- t48 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.CheckConstraints REG rax $104 GC regs: 0000D1CE {rcx rdx rbx rsi rdi r8 r12 r14 r15} => 0000D14E {rcx rdx rbx rsi r8 r12 r14 r15} GC regs: 0000D14E {rcx rdx rbx rsi r8 r12 r14 r15} => 0000D10E {rcx rdx rbx r8 r12 r14 r15} GC regs: 0000D10E {rcx rdx rbx r8 r12 r14 r15} => 0000D10A {rcx rbx r8 r12 r14 r15} GC regs: 0000D10A {rcx rbx r8 r12 r14 r15} => 0000D108 {rbx r8 r12 r14 r15} GC regs: 0000D108 {rbx r8 r12 r14 r15} => 0000D008 {rbx r12 r14 r15} Call: GCvars=00000000000000E0 {V05 V10 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {} IN0018: call qword ptr [r13]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool Generating: N109 ( 1, 1) [000050] -c---------- t50 = CNS_INT bool 0 REG NA $40 /--* t48 bool +--* t50 bool Generating: N111 ( 27, 24) [000051] J--XG--N-U-- * EQ void REG NA $1c7 IN0019: test al, al Generating: N113 ( 29, 26) [000052] ---XG------- * JTRUE void REG NA IN001a: je L_M12932_BB06 Scope info: end block BB02, IL range [010..036) Scope info: open scopes = 0 (V00 arg0) [000..051) 1 (V01 arg1) [000..051) 4 (V04 arg4) [000..051) 5 (V05 arg5) [000..051) 8 (V08 loc2) [000..051) 7 (V07 loc1) [000..051) 6 (V06 loc0) [000..051) =============== Generating BB03 [038..045) -> BB07 (cond), preds={BB02,BB06} succs={BB04,BB07} flags=0x00000004.620b2020: i Loop label target gcsafe bwd IBC LIR BB03 IN (10)={V08 V14 V00 V01 V04 V05 V13 V10 V07 V06} + ByrefExposed + GcHeap OUT(9)={V08 V14 V00 V01 V04 V05 V13 V07 V06} + ByrefExposed + GcHeap Recording Var Locations at start of BB03 V14(rbx) V00(r14) V01(r15) V04(r12) Liveness not changing: 00000000000005FF {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} Live regs: 00000000 {} => 0000D008 {rbx r12 r14 r15} GC regs: 00000000 {} => 0000D008 {rbx r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M12932_BB03: G_M12932_IG03: ; offs=00001EH, funclet=00, bbWeight=1.06 Label: IG04, GCvars=00000000000000E0 {V05 V10 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB03, IL range [038..045) Scope info: open scopes = 0 (V00 arg0) [000..051) 1 (V01 arg1) [000..051) 4 (V04 arg4) [000..051) 5 (V05 arg5) [000..051) 8 (V08 loc2) [000..051) 7 (V07 loc1) [000..051) 6 (V06 loc0) [000..051) 10 (V10 loc4) [000..051) Added IP mapping: 0x0038 STACK_EMPTY (G_M12932_IG04,ins#0,ofs#0) label Generating: N117 (???,???) [000159] ------------ IL_OFFSET void IL offset: 0x38 REG NA Generating: N119 ( 3, 2) [000053] ------------ t53 = LCL_VAR ref (AX) V11 loc5 rdi REG rdi $500 IN001b: mov rdi, gword ptr [V11 rbp-40H] GC regs: 0000D008 {rbx r12 r14 r15} => 0000D088 {rbx rdi r12 r14 r15} /--* t53 ref Generating: N121 (???,???) [000178] ------------ t178 = * PUTARG_REG ref REG rdi GC regs: 0000D088 {rbx rdi r12 r14 r15} => 0000D008 {rbx r12 r14 r15} GC regs: 0000D008 {rbx r12 r14 r15} => 0000D088 {rbx rdi r12 r14 r15} Generating: N123 ( 1, 1) [000054] -----------z t54 = LCL_VAR ref V10 loc4 u:2 rsi (last use) REG rsi /--* t54 ref Generating: N125 (???,???) [000179] ------------ t179 = * PUTARG_REG ref REG rsi IN001c: mov rsi, gword ptr [V10 rbp-50H] Removing V10 from gcVarPtrSetCur V10 in reg rsi is becoming live [000054] Live regs: 0000D008 {rbx r12 r14 r15} => 0000D048 {rbx rsi r12 r14 r15} GC regs: 0000D088 {rbx rdi r12 r14 r15} => 0000D0C8 {rbx rsi rdi r12 r14 r15} V10 in reg rsi is becoming dead [000054] Live regs: 0000D048 {rbx rsi r12 r14 r15} => 0000D008 {rbx r12 r14 r15} Live vars: {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V13 V14} GC regs: 0000D0C8 {rbx rsi rdi r12 r14 r15} => 0000D088 {rbx rdi r12 r14 r15} GC regs: 0000D088 {rbx rdi r12 r14 r15} => 0000D0C8 {rbx rsi rdi r12 r14 r15} Generating: N127 ( 1, 1) [000055] -----------z t55 = LCL_VAR byref V05 arg5 u:1 rdx REG rdx $c0 /--* t55 byref Generating: N129 (???,???) [000180] ------------ t180 = * PUTARG_REG byref REG rdx IN001d: mov rdx, bword ptr [V05 rbp-48H] Byref regs: 00000000 {} => 00000004 {rdx} Byref regs: 00000004 {rdx} => 00000000 {} Byref regs: 00000000 {} => 00000004 {rdx} Generating: N131 ( 3, 10) [000181] ------------ t181 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN001e: mov rax, (reloc 0xd1ffab1e) /--* t181 long Generating: N133 ( 5, 12) [000182] -c---------- t182 = * IND long REG NA /--* t178 ref arg0 in rdi +--* t179 ref arg1 in rsi +--* t180 byref arg2 in rdx +--* t182 long control expr Generating: N135 ( 19, 12) [000056] --CXG------- t56 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.AppendUseSiteDiagnostics REG rax $106 GC regs: 0000D0C8 {rbx rsi rdi r12 r14 r15} => 0000D048 {rbx rsi r12 r14 r15} GC regs: 0000D048 {rbx rsi r12 r14 r15} => 0000D008 {rbx r12 r14 r15} Byref regs: 00000004 {rdx} => 00000000 {} Call: GCvars=0000000000000060 {V05 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {} IN001f: call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:AppendUseSiteDiagnostics(System.Collections.Generic.HashSet`1[[Microsoft.CodeAnalysis.DiagnosticInfo, Microsoft.CodeAnalysis, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,byref):bool Generating: N137 ( 1, 1) [000058] -c---------- t58 = CNS_INT bool 0 REG NA $40 /--* t56 bool +--* t58 bool Generating: N139 ( 22, 16) [000059] J--XG--N-U-- * NE void REG NA $1c9 IN0020: test al, al Generating: N141 ( 24, 18) [000060] ---XG------- * JTRUE void REG NA IN0021: jne L_M12932_BB07 Scope info: end block BB03, IL range [038..045) Scope info: open scopes = 0 (V00 arg0) [000..051) 1 (V01 arg1) [000..051) 4 (V04 arg4) [000..051) 5 (V05 arg5) [000..051) 8 (V08 loc2) [000..051) 7 (V07 loc1) [000..051) 6 (V06 loc0) [000..051) =============== Generating BB04 [047..04F) -> BB02 (cond), preds={BB03,BB07} succs={BB05,BB02} flags=0x00000000.620b2020: i Loop label target gcsafe bwd IBC LIR BB04 IN (9)={V08 V14 V00 V01 V04 V05 V13 V07 V06} + ByrefExposed + GcHeap OUT(9)={V08 V14 V00 V01 V04 V05 V13 V07 V06} + ByrefExposed + GcHeap Recording Var Locations at start of BB04 V14(rbx) V00(r14) V01(r15) V04(r12) Liveness not changing: 000000000000057F {V00 V01 V04 V05 V06 V07 V08 V13 V14} Live regs: 00000000 {} => 0000D008 {rbx r12 r14 r15} GC regs: 00000000 {} => 0000D008 {rbx r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M12932_BB04: G_M12932_IG04: ; offs=00006EH, funclet=00, bbWeight=1.06 Label: IG05, GCvars=0000000000000060 {V05 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB04, IL range [047..04F) Scope info: open scopes = 0 (V00 arg0) [000..051) 1 (V01 arg1) [000..051) 4 (V04 arg4) [000..051) 5 (V05 arg5) [000..051) 8 (V08 loc2) [000..051) 7 (V07 loc1) [000..051) 6 (V06 loc0) [000..051) Added IP mapping: 0x0047 STACK_EMPTY (G_M12932_IG05,ins#0,ofs#0) label Generating: N145 (???,???) [000160] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N147 ( 1, 1) [000061] -----------z t61 = LCL_VAR int V08 loc2 u:3 r13 (last use) REG r13 $280 Generating: N149 ( 1, 1) [000062] -c---------- t62 = CNS_INT int 1 REG NA $41 /--* t61 int +--* t62 int Generating: N151 ( 3, 3) [000063] ------------ t63 = * ADD int REG r13 $1ca IN0022: mov r13d, dword ptr [V08 rbp-34H] V08 in reg r13 is becoming live [000061] Live regs: 0000D008 {rbx r12 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} V08 in reg r13 is becoming dead [000061] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000D008 {rbx r12 r14 r15} Live vars: {V00 V01 V04 V05 V06 V07 V08 V13 V14} => {V00 V01 V04 V05 V06 V07 V13 V14} IN0023: inc r13d /--* t63 int Generating: N153 ( 3, 3) [000065] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 r13 REG r13 V08 in reg r13 is becoming live [000065] Live regs: 0000D008 {rbx r12 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live vars: {V00 V01 V04 V05 V06 V07 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V13 V14} Added IP mapping: 0x004B STACK_EMPTY (G_M12932_IG05,ins#2,ofs#7) Generating: N155 (???,???) [000161] ------------ IL_OFFSET void IL offset: 0x4b REG NA Generating: N157 ( 1, 1) [000016] ------------ t16 = LCL_VAR int V08 loc2 u:4 r13 REG r13 $1ca Generating: N159 ( 1, 1) [000017] -----------z t17 = LCL_VAR int V07 loc1 u:2 r11 REG r11 $1c1 /--* t16 int +--* t17 int Generating: N161 ( 3, 3) [000018] J------N---- * LE void REG NA $1cb IN0024: mov r11d, dword ptr [V07 rbp-30H] V07 in reg r11 is becoming live [000017] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F808 {rbx r11 r12 r13 r14 r15} IN0025: cmp r13d, r11d Generating: N001 ( 1, 1) [000183] -----------Z t183 = LCL_VAR int V07 loc1 r11 REG r11 IN0026: mov dword ptr [V07 rbp-30H], r11d V07 in reg r11 is becoming dead [000183] Live regs: 0000F808 {rbx r11 r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Generating: N001 ( 1, 1) [000184] ------------ t184 = LCL_VAR int V08 loc2 r13 REG r13 /--* t184 int Generating: N002 ( 2, 2) [000185] ------------ t185 = * COPY int REG r8 IN0027: mov r8d, r13d V08 in reg r13 is becoming dead [000184] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000D008 {rbx r12 r14 r15} V08 in reg r8 is becoming live [000185] Live regs: 0000D008 {rbx r12 r14 r15} => 0000D108 {rbx r8 r12 r14 r15} Generating: N001 ( 1, 1) [000186] -----------z t186 = LCL_VAR ref V13 tmp1 rax REG rax IN0028: mov rax, gword ptr [V13 rbp-58H] Removing V13 from gcVarPtrSetCur V13 in reg rax is becoming live [000186] Live regs: 0000D108 {rbx r8 r12 r14 r15} => 0000D109 {rax rbx r8 r12 r14 r15} GC regs: 0000D008 {rbx r12 r14 r15} => 0000D009 {rax rbx r12 r14 r15} Generating: N163 ( 5, 5) [000019] ------------ * JTRUE void REG NA IN0029: jle L_M12932_BB02 Scope info: end block BB04, IL range [047..04F) Scope info: open scopes = 0 (V00 arg0) [000..051) 1 (V01 arg1) [000..051) 4 (V04 arg4) [000..051) 5 (V05 arg5) [000..051) 7 (V07 loc1) [000..051) 6 (V06 loc0) [000..051) =============== Generating BB05 [04F..051) (return), preds={BB01,BB04} succs={} flags=0x00000000.60030020: i label target IBC LIR BB05 IN (1)={V06} OUT(0)={ } Recording Var Locations at start of BB05 Change life 000000000000057F {V00 V01 V04 V05 V06 V07 V08 V13 V14} -> 0000000000000400 {V06} V08 in reg r8 is becoming dead [------] Live regs: (unchanged) 00000000 {} V14 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V00 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V01 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V04 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V05 becoming dead V13 in reg rax is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M12932_BB05: G_M12932_IG05: ; offs=00008EH, funclet=00, bbWeight=1.06 Label: IG06, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB05, IL range [04F..051) Scope info: open scopes = 6 (V06 loc0) [000..051) Added IP mapping: 0x004F STACK_EMPTY (G_M12932_IG06,ins#0,ofs#0) label Generating: N167 (???,???) [000162] ------------ IL_OFFSET void IL offset: 0x4f REG NA Generating: N169 ( 3, 2) [000072] -----------z t72 = LCL_VAR int V06 loc0 u:3 rax (last use) REG rax $240 /--* t72 int Generating: N171 ( 4, 3) [000073] ------------ * RETURN int REG NA $103 IN002a: mov eax, dword ptr [V06 rbp-2CH] V06 in reg rax is becoming live [000072] Live regs: 00000000 {} => 00000001 {rax} V06 in reg rax is becoming dead [000072] Live regs: 00000001 {rax} => 00000000 {} Live vars: {V06} => {} Scope info: end block BB05, IL range [04F..051) Scope info: ending scope, LVnum=0 [000..051) Scope info: ending scope, LVnum=1 [000..051) Scope info: ending scope, LVnum=2 [000..051) siEndScope: Failed to end scope for V02 Scope info: ending scope, LVnum=3 [000..051) siEndScope: Failed to end scope for V03 Scope info: ending scope, LVnum=4 [000..051) Scope info: ending scope, LVnum=5 [000..051) Scope info: ending scope, LVnum=6 [000..051) Scope info: ending scope, LVnum=7 [000..051) Scope info: ending scope, LVnum=8 [000..051) Scope info: ending scope, LVnum=9 [000..051) Scope info: ending scope, LVnum=10 [000..051) Scope info: ending scope, LVnum=11 [000..051) siEndScope: Failed to end scope for V11 Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M12932_IG06,ins#1,ofs#3) label Reserving epilog IG for block BB05 G_M12932_IG06: ; offs=0000ADH, funclet=00, bbWeight=1 *************** After placeholder IG creation G_M12932_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M12932_IG02: ; offs=000000H, size=001EH, gcVars=0000000000000020 {V05}, gcrefRegs=0000D009 {rax rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M12932_IG03: ; offs=00001EH, size=0050H, gcrefRegs=0000D009 {rax rbx r12 r14 r15}, byrefRegs=00000000 {}, byref G_M12932_IG04: ; offs=00006EH, size=0020H, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, byref G_M12932_IG05: ; offs=00008EH, size=001FH, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, byref G_M12932_IG06: ; offs=0000ADH, size=0003H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref G_M12932_IG07: ; epilog placeholder, next placeholder=, BB05 [0007], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000060 {V05 V13}, PrevGCrefRegs=0000D008 {rbx r12 r14 r15}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} G_M12932_IG08: ; offs=0001B0H, size=0000H, gcrefRegs=00000000 {} <-- Current IG =============== Generating BB06 [036..038) -> BB03 (always), preds={BB02} succs={BB03} flags=0x00000000.620b0020: i label target gcsafe bwd IBC LIR BB06 IN (9)={V08 V14 V00 V01 V04 V05 V13 V10 V07 } + ByrefExposed + GcHeap OUT(10)={V08 V14 V00 V01 V04 V05 V13 V10 V07 V06} + ByrefExposed + GcHeap Recording Var Locations at start of BB06 V08(r8->STK) V14(rbx) V00(r14) V01(r15) V04(r12) V13(rax->STK) V10(rsi->STK) Change life 0000000000000000 {} -> 00000000000001FF {V00 V01 V04 V05 V07 V08 V10 V13 V14} V14 in reg rbx is becoming live [------] Live regs: 00000000 {} => 00000008 {rbx} V00 in reg r14 is becoming live [------] Live regs: 00000008 {rbx} => 00004008 {rbx r14} V01 in reg r15 is becoming live [------] Live regs: 00004008 {rbx r14} => 0000C008 {rbx r14 r15} V04 in reg r12 is becoming live [------] Live regs: 0000C008 {rbx r14 r15} => 0000D008 {rbx r12 r14 r15} V05 becoming live V13 becoming live V10 becoming live Live regs: (unchanged) 0000D008 {rbx r12 r14 r15} GC regs: (unchanged) 0000D008 {rbx r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M12932_BB06: Label: IG08, GCvars=00000000000000E0 {V05 V10 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB06, IL range [036..038) Scope info: open scopes = 8 (V08 loc2) [000..051) 0 (V00 arg0) [000..051) 1 (V01 arg1) [000..051) 4 (V04 arg4) [000..051) 5 (V05 arg5) [000..051) 10 (V10 loc4) [000..051) 7 (V07 loc1) [000..051) Added IP mapping: 0x0036 STACK_EMPTY (G_M12932_IG08,ins#0,ofs#0) label Generating: N175 (???,???) [000163] ------------ IL_OFFSET void IL offset: 0x36 REG NA Generating: N177 ( 1, 1) [000069] ------------ t69 = CNS_INT int 0 REG rax $40 IN002b: xor eax, eax /--* t69 int Generating: N179 ( 5, 4) [000071] DA---------- * STORE_LCL_VAR int V06 loc0 d:5 rax REG rax V06 in reg rax is becoming live [000071] Live regs: 0000D008 {rbx r12 r14 r15} => 0000D009 {rax rbx r12 r14 r15} Live vars: {V00 V01 V04 V05 V07 V08 V10 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} Generating: N001 ( 4, 3) [000187] -----------Z t187 = LCL_VAR bool V06 loc0 rax REG rax IN002c: mov dword ptr [V06 rbp-2CH], eax V06 in reg rax is becoming dead [000187] Live regs: 0000D009 {rax rbx r12 r14 r15} => 0000D008 {rbx r12 r14 r15} Scope info: end block BB06, IL range [036..038) Scope info: open scopes = 8 (V08 loc2) [000..051) 0 (V00 arg0) [000..051) 1 (V01 arg1) [000..051) 4 (V04 arg4) [000..051) 5 (V05 arg5) [000..051) 10 (V10 loc4) [000..051) 7 (V07 loc1) [000..051) IN002d: jmp L_M12932_BB03 =============== Generating BB07 [045..047) -> BB04 (always), preds={BB03} succs={BB04} flags=0x00000000.620b1020: i rare label target gcsafe bwd IBC LIR BB07 IN (8)={V08 V14 V00 V01 V04 V05 V13 V07 } + ByrefExposed + GcHeap OUT(9)={V08 V14 V00 V01 V04 V05 V13 V07 V06} + ByrefExposed + GcHeap Recording Var Locations at start of BB07 V14(rbx) V00(r14) V01(r15) V04(r12) Change life 00000000000005FF {V00 V01 V04 V05 V06 V07 V08 V10 V13 V14} -> 000000000000017F {V00 V01 V04 V05 V07 V08 V13 V14} V10 becoming dead Live regs: 00000000 {} => 0000D008 {rbx r12 r14 r15} GC regs: 00000000 {} => 0000D008 {rbx r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M12932_BB07: G_M12932_IG08: ; offs=0001B0H, funclet=00, bbWeight=0.03 Label: IG09, GCvars=0000000000000060 {V05 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB07, IL range [045..047) Scope info: open scopes = 8 (V08 loc2) [000..051) 0 (V00 arg0) [000..051) 1 (V01 arg1) [000..051) 4 (V04 arg4) [000..051) 5 (V05 arg5) [000..051) 7 (V07 loc1) [000..051) Added IP mapping: 0x0045 STACK_EMPTY (G_M12932_IG09,ins#0,ofs#0) label Generating: N183 (???,???) [000164] ------------ IL_OFFSET void IL offset: 0x45 REG NA Generating: N185 ( 1, 1) [000066] ------------ t66 = CNS_INT int 0 REG rax $40 IN002e: xor eax, eax /--* t66 int Generating: N187 ( 5, 4) [000068] DA---------- * STORE_LCL_VAR int V06 loc0 d:7 rax REG rax V06 in reg rax is becoming live [000068] Live regs: 0000D008 {rbx r12 r14 r15} => 0000D009 {rax rbx r12 r14 r15} Live vars: {V00 V01 V04 V05 V07 V08 V13 V14} => {V00 V01 V04 V05 V06 V07 V08 V13 V14} Generating: N001 ( 4, 3) [000188] -----------Z t188 = LCL_VAR bool V06 loc0 rax REG rax IN002f: mov dword ptr [V06 rbp-2CH], eax V06 in reg rax is becoming dead [000188] Live regs: 0000D009 {rax rbx r12 r14 r15} => 0000D008 {rbx r12 r14 r15} Scope info: end block BB07, IL range [045..047) Scope info: open scopes = 8 (V08 loc2) [000..051) 0 (V00 arg0) [000..051) 1 (V01 arg1) [000..051) 4 (V04 arg4) [000..051) 5 (V05 arg5) [000..051) 7 (V07 loc1) [000..051) IN0030: jmp L_M12932_BB04 =============== Generating BB08 [???..???) (throw), preds={} succs={} flags=0x00000000.40031070: keep i internal rare label target LIR BB08 IN (0)={} OUT(0)={} Recording Var Locations at start of BB08 Change life 000000000000057F {V00 V01 V04 V05 V06 V07 V08 V13 V14} -> 0000000000000000 {} V14 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V00 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V01 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V04 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V05 becoming dead V13 becoming dead Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M12932_BB08: G_M12932_IG09: ; offs=0001BAH, funclet=00, bbWeight=0 Label: IG10, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB08, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M12932_IG10,ins#0,ofs#0) label Generating: N191 ( 14, 5) [000169] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL REG NA Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0031: call CORINFO_HELP_RNGCHKFAIL Scope info: end block BB08, IL range [???..???) Scope info: ignoring block end IN0032: int3 Liveness not changing: 0000000000000000 {} # compCycleEstimate = 120, compSizeEstimate = 112 Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool ; Final local variable assignments ; ; V00 arg0 [V00,T02] ( 3, 3.06) ref -> r14 class-hnd ; V01 arg1 [V01,T03] ( 3, 3.06) ref -> r15 class-hnd ;* V02 arg2 [V02 ] ( 0, 0 ) struct ( 8) zero-ref ld-addr-op ;* V03 arg3 [V03 ] ( 0, 0 ) struct ( 8) zero-ref ld-addr-op ; V04 arg4 [V04,T04] ( 3, 3.06) ref -> r12 class-hnd ; V05 arg5 [V05,T05] ( 3, 3.06) byref -> [rbp-0x48] ; V06 loc0 [V06,T10] ( 4, 2.03) bool -> [rbp-0x2C] ; V07 loc1 [V07,T08] ( 3, 3.06) int -> [rbp-0x30] ; V08 loc2 [V08,T00] ( 7, 7.36) int -> [rbp-0x34] ; V09 loc3 [V09,T09] ( 2, 2.12) ref -> rcx class-hnd ; V10 loc4 [V10,T07] ( 3, 3.18) ref -> [rbp-0x50] class-hnd ; V11 loc5 [V11 ] ( 3, 3.18) ref -> [rbp-0x40] do-not-enreg[X] must-init addr-exposed ld-addr-op class-hnd ;# V12 OutArgs [V12 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00] "OutgoingArgSpace" ; V13 tmp1 [V13,T06] ( 3, 3.06) ref -> [rbp-0x58] V02.array(offs=0x00) P-INDEP "field V02.array (fldOffset=0x0)" ; V14 tmp2 [V14,T01] ( 3, 3.12) ref -> rbx V03.array(offs=0x00) P-INDEP "field V03.array (fldOffset=0x0)" ; ; Lcl frame size = 56 *************** Before prolog / epilog generation G_M12932_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M12932_IG02: ; offs=000000H, size=001EH, gcVars=0000000000000020 {V05}, gcrefRegs=0000D009 {rax rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M12932_IG03: ; offs=00001EH, size=0050H, gcrefRegs=0000D009 {rax rbx r12 r14 r15}, byrefRegs=00000000 {}, byref G_M12932_IG04: ; offs=00006EH, size=0020H, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, byref G_M12932_IG05: ; offs=00008EH, size=001FH, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, byref G_M12932_IG06: ; offs=0000ADH, size=0003H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref G_M12932_IG07: ; epilog placeholder, next placeholder=, BB05 [0007], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000060 {V05 V13}, PrevGCrefRegs=0000D008 {rbx r12 r14 r15}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} G_M12932_IG08: ; offs=0001B0H, size=000AH, gcVars=00000000000000E0 {V05 V10 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M12932_IG09: ; offs=0001BAH, size=000AH, gcVars=0000000000000060 {V05 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M12932_IG10: ; offs=0001C4H, size=0000H, gcrefRegs=00000000 {} <-- Current IG Recording Var Locations at start of BB01 V14(rbx) V00(r14) V01(r15) V04(r12) V13(STK->rax) G_M12932_IG10: ; offs=0001C4H, funclet=00, bbWeight=0 *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M12932_IG01,ins#0,ofs#0) label __prolog: **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 1 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 1 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 Found 2 lvMustInit int-sized stack slots, frame offsets 64 through 56 IN0033: push rbp IN0034: push r15 IN0035: push r14 IN0036: push r13 IN0037: push r12 IN0038: push rbx IN0039: sub rsp, 56 IN003a: lea rbp, [rsp+60H] IN003b: xor rax, rax IN003c: mov qword ptr [V11 rbp-40H], rax *************** In genClearStackVec3ArgUpperBits() *************** In genFnPrologCalleeRegArgs() for int regs IN003d: mov bword ptr [V05 rbp-48H], r9 IN003e: mov r14, rdi IN003f: mov r15, rsi IN0040: mov rax, rdx IN0041: mov rbx, rcx IN0042: mov r12, r8 *************** In genEnregisterIncomingStackArgs() 3 tracked GC refs are at stack offsets -0058 ... FFFFFFC0 G_M12932_IG01: ; offs=000000H, funclet=00, bbWeight=1 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {} IN0043: lea rsp, [rbp-28H] IN0044: pop rbx IN0045: pop r12 IN0046: pop r13 IN0047: pop r14 IN0048: pop r15 IN0049: pop rbp IN004a: ret G_M12932_IG07: ; offs=0000B0H, funclet=00, bbWeight=1 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M12932_IG01: ; func=00, offs=000000H, size=002CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M12932_IG02: ; offs=00002CH, size=001EH, gcVars=0000000000000020 {V05}, gcrefRegs=0000D009 {rax rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M12932_IG03: ; offs=00004AH, size=0050H, gcrefRegs=0000D009 {rax rbx r12 r14 r15}, byrefRegs=00000000 {}, byref G_M12932_IG04: ; offs=00009AH, size=0020H, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, byref G_M12932_IG05: ; offs=0000BAH, size=001FH, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, byref G_M12932_IG06: ; offs=0000D9H, size=0003H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref G_M12932_IG07: ; offs=0000DCH, size=000FH, epilog, nogc, extend G_M12932_IG08: ; offs=0000EBH, size=000AH, gcVars=00000000000000E0 {V05 V10 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M12932_IG09: ; offs=0000F5H, size=000AH, gcVars=0000000000000060 {V05 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M12932_IG10: ; offs=0000FFH, size=0006H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref *************** In emitJumpDistBind() Binding: IN0007: 000000 jl L_M12932_BB05 Binding L_M12932_BB05to G_M12932_IG06 Estimate of fwd jump [D1FFAB1E/007]: 0044 -> 00D9 = 0093 Adjusted offset of BB03 from 004A to 004A Binding: IN0009: 000000 jae L_M12932_BB08 Binding L_M12932_BB08to G_M12932_IG10 Estimate of fwd jump [D1FFAB1E/009]: 004E -> 00FF = 00AF Binding: IN001a: 000000 je L_M12932_BB06 Binding L_M12932_BB06to G_M12932_IG08 Estimate of fwd jump [D1FFAB1E/026]: 0094 -> 00EB = 0055 Shrinking jump [D1FFAB1E/026] Adjusted offset of BB04 from 009A to 0096 Binding: IN0021: 000000 jne L_M12932_BB07 Binding L_M12932_BB07to G_M12932_IG09 Estimate of fwd jump [D1FFAB1E/033]: 00B0 -> 00F1 = 003F Shrinking jump [D1FFAB1E/033] Adjusted offset of BB05 from 00BA to 00B2 Binding: IN0029: 000000 jle L_M12932_BB02 Binding L_M12932_BB02to G_M12932_IG03 Estimate of bwd jump [D1FFAB1E/041]: 00CB -> 004A = 0083 Adjusted offset of BB06 from 00D9 to 00D1 Adjusted offset of BB07 from 00DC to 00D4 Adjusted offset of BB08 from 00EB to 00E3 Binding: IN002d: 000000 jmp L_M12932_BB03 Binding L_M12932_BB03to G_M12932_IG04 Estimate of bwd jump [D1FFAB1E/045]: 00E8 -> 0096 = 0054 Shrinking jump [D1FFAB1E/045] Adjusted offset of BB09 from 00F5 to 00EA Binding: IN0030: 000000 jmp L_M12932_BB04 Binding L_M12932_BB04to G_M12932_IG05 Estimate of bwd jump [D1FFAB1E/048]: 00EF -> 00B2 = 003F Shrinking jump [D1FFAB1E/048] Adjusted offset of BB10 from 00FF to 00F1 Total shrinkage = 14, min extra jump size = 3 Iterating branch shortening. Iteration = 2 Estimate of fwd jump [D1FFAB1E/007]: 0044 -> 00D1 = 008B Adjusted offset of BB03 from 004A to 004A Estimate of fwd jump [D1FFAB1E/009]: 004E -> 00F1 = 00A1 Adjusted offset of BB04 from 0096 to 0096 Adjusted offset of BB05 from 00B2 to 00B2 Estimate of bwd jump [D1FFAB1E/041]: 00CB -> 004A = 0083 Adjusted offset of BB06 from 00D1 to 00D1 Adjusted offset of BB07 from 00D4 to 00D4 Adjusted offset of BB08 from 00E3 to 00E3 Adjusted offset of BB09 from 00EA to 00EA *************** Finishing PHASE Generate code *************** Starting PHASE Emit code Hot code size = 0xF7 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x12) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M12932_IG01: ; func=00, offs=000000H, size=002CH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN0033: 000000 push rbp IN0034: 000001 push r15 IN0035: 000003 push r14 IN0036: 000005 push r13 IN0037: 000007 push r12 IN0038: 000009 push rbx IN0039: 00000A sub rsp, 56 IN003a: 00000E lea rbp, [rsp+60H] IN003b: 000013 xor rax, rax IN003c: 000015 mov qword ptr [rbp-40H], rax [D1FFAB1E] byr var born at [rbp-48H] IN003d: 000019 mov bword ptr [rbp-48H], r9 gcrReg +[r14] IN003e: 00001D mov r14, rdi gcrReg +[r15] IN003f: 000020 mov r15, rsi gcrReg +[rax] IN0040: 000023 mov rax, rdx gcrReg +[rbx] IN0041: 000026 mov rbx, rcx gcrReg +[r12] IN0042: 000029 mov r12, r8 ;; bbWeight=1 PerfScore 10.25 G_M12932_IG02: ; func=00, offs=00002CH, size=001EH, gcVars=0000000000000020 {V05}, gcrefRegs=0000D009 {rax rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref New GC ref live vars=0000000000000020 {V05} IN0001: 00002C mov dword ptr [rbp-2CH], 1 IN0002: 000033 mov r11d, dword ptr [rax+8] IN0003: 000037 dec r11d IN0004: 00003A xor r8d, r8d IN0005: 00003D mov dword ptr [rbp-30H], r11d IN0006: 000041 test r11d, r11d IN0007: 000044 jl G_M12932_IG06 ;; bbWeight=1 PerfScore 5.75 G_M12932_IG03: ; func=00, offs=00004AH, size=004CH, gcrefRegs=0000D009 {rax rbx r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0008: 00004A cmp r8d, dword ptr [rbx+8] IN0009: 00004E jae G_M12932_IG10 IN000a: 000054 movsxd r9, r8d gcrReg +[rcx] IN000b: 000057 mov rcx, gword ptr [rbx+8*r9+16] IN000c: 00005C mov dword ptr [rbp-34H], r8d IN000d: 000060 movsxd r9, r8d [D1FFAB1E] gcr var born at [rbp-58H] IN000e: 000063 mov gword ptr [rbp-58H], rax gcrReg +[rdx] IN000f: 000067 mov rdx, gword ptr [rax+8*r9+16] gcrReg +[r9] IN0010: 00006C xor r9, r9 IN0011: 00006F mov gword ptr [rbp-40H], r9 gcrReg -[r9] IN0012: 000073 lea r9, [rbp-40H] gcrReg +[rdi] IN0013: 000077 mov rdi, r14 gcrReg +[rsi] IN0014: 00007A mov rsi, r15 [D1FFAB1E] gcr var born at [rbp-50H] IN0015: 00007D mov gword ptr [rbp-50H], rdx gcrReg +[r8] IN0016: 000081 mov r8, r12 IN0017: 000084 mov r13, (reloc 0xd1ffab1e) New GC ref live vars=00000000000000E0 {V05 V10 V13} New gcrReg live regs=0000D008 {rbx r12 r14 r15} ; Call at 008E [stk=0], GCvars=[rbp-58H] [rbp-50H] [rbp-48H], gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {} IN0018: 00008E call qword ptr [r13]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool IN0019: 000092 test al, al IN001a: 000094 je SHORT G_M12932_IG08 ;; bbWeight=1.06 PerfScore 18.55 G_M12932_IG04: ; func=00, offs=000096H, size=001CH, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, byref, isz gcrReg +[rdi] IN001b: 000096 mov rdi, gword ptr [rbp-40H] gcrReg +[rsi] IN001c: 00009A mov rsi, gword ptr [rbp-50H] byrReg +[rdx] IN001d: 00009E mov rdx, bword ptr [rbp-48H] IN001e: 0000A2 mov rax, (reloc 0xd1ffab1e) New GC ref live vars=0000000000000060 {V05 V13} [D1FFAB1E] gcr var died at [rbp-50H] New gcrReg live regs=0000D008 {rbx r12 r14 r15} New byrReg live regs=00000000 {} ; Call at 00AC [stk=0], GCvars=[rbp-58H] [rbp-48H], gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {} IN001f: 0000AC call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:AppendUseSiteDiagnostics(System.Collections.Generic.HashSet`1[[Microsoft.CodeAnalysis.DiagnosticInfo, Microsoft.CodeAnalysis, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,byref):bool IN0020: 0000AE test al, al IN0021: 0000B0 jne SHORT G_M12932_IG09 ;; bbWeight=1.06 PerfScore 7.95 G_M12932_IG05: ; func=00, offs=0000B2H, size=001FH, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, byref IN0022: 0000B2 mov r13d, dword ptr [rbp-34H] IN0023: 0000B6 inc r13d IN0024: 0000B9 mov r11d, dword ptr [rbp-30H] IN0025: 0000BD cmp r13d, r11d IN0026: 0000C0 mov dword ptr [rbp-30H], r11d IN0027: 0000C4 mov r8d, r13d gcrReg +[rax] IN0028: 0000C7 mov rax, gword ptr [rbp-58H] IN0029: 0000CB jle G_M12932_IG03 ;; bbWeight=1.06 PerfScore 6.10 G_M12932_IG06: ; func=00, offs=0000D1H, size=0003H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref New GC ref live vars=0000000000000000 {} [D1FFAB1E] byr var died at [rbp-48H] [D1FFAB1E] gcr var died at [rbp-58H] New gcrReg live regs=00000000 {} IN002a: 0000D1 mov eax, dword ptr [rbp-2CH] ;; bbWeight=1 PerfScore 1.00 G_M12932_IG07: ; func=00, offs=0000D4H, size=000FH, epilog, nogc, extend IN0043: 0000D4 lea rsp, [rbp-28H] IN0044: 0000D8 pop rbx IN0045: 0000D9 pop r12 IN0046: 0000DB pop r13 IN0047: 0000DD pop r14 IN0048: 0000DF pop r15 IN0049: 0000E1 pop rbp IN004a: 0000E2 ret ;; bbWeight=1 PerfScore 4.50 G_M12932_IG08: ; func=00, offs=0000E3H, size=0007H, gcVars=00000000000000E0 {V05 V10 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz New GC ref live vars=00000000000000E0 {V05 V10 V13} [D1FFAB1E] byr var born at [rbp-48H] [D1FFAB1E] gcr var born at [rbp-58H] [D1FFAB1E] gcr var born at [rbp-50H] New gcrReg live regs=0000D008 {rbx r12 r14 r15} IN002b: 0000E3 xor eax, eax IN002c: 0000E5 mov dword ptr [rbp-2CH], eax IN002d: 0000E8 jmp SHORT G_M12932_IG04 ;; bbWeight=0.03 PerfScore 0.10 G_M12932_IG09: ; func=00, offs=0000EAH, size=0007H, gcVars=0000000000000060 {V05 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz New GC ref live vars=0000000000000060 {V05 V13} [D1FFAB1E] gcr var died at [rbp-50H] IN002e: 0000EA xor eax, eax IN002f: 0000EC mov dword ptr [rbp-2CH], eax IN0030: 0000EF jmp SHORT G_M12932_IG05 ;; bbWeight=0 PerfScore 0.00 G_M12932_IG10: ; func=00, offs=0000F1H, size=0006H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref New GC ref live vars=0000000000000000 {} [D1FFAB1E] byr var died at [rbp-48H] [D1FFAB1E] gcr var died at [rbp-58H] New gcrReg live regs=00000000 {} ; Call at 00F1 [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0031: 0000F1 call CORINFO_HELP_RNGCHKFAIL IN0032: 0000F6 int3 ;; bbWeight=0 PerfScore 0.00Allocated method code size = 247 , actual size = 247 ; Total bytes of code 247, prolog size 25, PerfScore 78.89, (MethodHash=c68acd7b) for method Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool ; ============================================================ *************** After end code gen, before unwindEmit() G_M12932_IG01: ; func=00, offs=000000H, size=002CH, bbWeight=1 PerfScore 10.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN0033: 000000 push rbp IN0034: 000001 push r15 IN0035: 000003 push r14 IN0036: 000005 push r13 IN0037: 000007 push r12 IN0038: 000009 push rbx IN0039: 00000A sub rsp, 56 IN003a: 00000E lea rbp, [rsp+60H] IN003b: 000013 xor rax, rax IN003c: 000015 mov qword ptr [V11 rbp-40H], rax IN003d: 000019 mov bword ptr [V05 rbp-48H], r9 IN003e: 00001D mov r14, rdi IN003f: 000020 mov r15, rsi IN0040: 000023 mov rax, rdx IN0041: 000026 mov rbx, rcx IN0042: 000029 mov r12, r8 G_M12932_IG02: ; offs=00002CH, size=001EH, bbWeight=1 PerfScore 5.75, gcVars=0000000000000020 {V05}, gcrefRegs=0000D009 {rax rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref IN0001: 00002C mov dword ptr [V06 rbp-2CH], 1 IN0002: 000033 mov r11d, dword ptr [rax+8] IN0003: 000037 dec r11d IN0004: 00003A xor r8d, r8d IN0005: 00003D mov dword ptr [V07 rbp-30H], r11d IN0006: 000041 test r11d, r11d IN0007: 000044 jl G_M12932_IG06 G_M12932_IG03: ; offs=00004AH, size=004CH, bbWeight=1.06 PerfScore 18.55, gcrefRegs=0000D009 {rax rbx r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0008: 00004A cmp r8d, dword ptr [rbx+8] IN0009: 00004E jae G_M12932_IG10 IN000a: 000054 movsxd r9, r8d IN000b: 000057 mov rcx, gword ptr [rbx+8*r9+16] IN000c: 00005C mov dword ptr [V08 rbp-34H], r8d IN000d: 000060 movsxd r9, r8d IN000e: 000063 mov gword ptr [V13 rbp-58H], rax IN000f: 000067 mov rdx, gword ptr [rax+8*r9+16] IN0010: 00006C xor r9, r9 IN0011: 00006F mov gword ptr [V11 rbp-40H], r9 IN0012: 000073 lea r9, [V11 rbp-40H] IN0013: 000077 mov rdi, r14 IN0014: 00007A mov rsi, r15 IN0015: 00007D mov gword ptr [V10 rbp-50H], rdx IN0016: 000081 mov r8, r12 IN0017: 000084 mov r13, (reloc 0xd1ffab1e) IN0018: 00008E call qword ptr [r13]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool IN0019: 000092 test al, al IN001a: 000094 je SHORT G_M12932_IG08 G_M12932_IG04: ; offs=000096H, size=001CH, bbWeight=1.06 PerfScore 7.95, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN001b: 000096 mov rdi, gword ptr [V11 rbp-40H] IN001c: 00009A mov rsi, gword ptr [V10 rbp-50H] IN001d: 00009E mov rdx, bword ptr [V05 rbp-48H] IN001e: 0000A2 mov rax, (reloc 0xd1ffab1e) IN001f: 0000AC call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:AppendUseSiteDiagnostics(System.Collections.Generic.HashSet`1[[Microsoft.CodeAnalysis.DiagnosticInfo, Microsoft.CodeAnalysis, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,byref):bool IN0020: 0000AE test al, al IN0021: 0000B0 jne SHORT G_M12932_IG09 G_M12932_IG05: ; offs=0000B2H, size=001FH, bbWeight=1.06 PerfScore 6.10, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, byref IN0022: 0000B2 mov r13d, dword ptr [V08 rbp-34H] IN0023: 0000B6 inc r13d IN0024: 0000B9 mov r11d, dword ptr [V07 rbp-30H] IN0025: 0000BD cmp r13d, r11d IN0026: 0000C0 mov dword ptr [V07 rbp-30H], r11d IN0027: 0000C4 mov r8d, r13d IN0028: 0000C7 mov rax, gword ptr [V13 rbp-58H] IN0029: 0000CB jle G_M12932_IG03 G_M12932_IG06: ; offs=0000D1H, size=0003H, bbWeight=1 PerfScore 1.00, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref IN002a: 0000D1 mov eax, dword ptr [V06 rbp-2CH] G_M12932_IG07: ; offs=0000D4H, size=000FH, bbWeight=1 PerfScore 4.50, epilog, nogc, extend IN0043: 0000D4 lea rsp, [rbp-28H] IN0044: 0000D8 pop rbx IN0045: 0000D9 pop r12 IN0046: 0000DB pop r13 IN0047: 0000DD pop r14 IN0048: 0000DF pop r15 IN0049: 0000E1 pop rbp IN004a: 0000E2 ret G_M12932_IG08: ; offs=0000E3H, size=0007H, bbWeight=0.03 PerfScore 0.10, gcVars=00000000000000E0 {V05 V10 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz IN002b: 0000E3 xor eax, eax IN002c: 0000E5 mov dword ptr [V06 rbp-2CH], eax IN002d: 0000E8 jmp SHORT G_M12932_IG04 G_M12932_IG09: ; offs=0000EAH, size=0007H, bbWeight=0 PerfScore 0.00, gcVars=0000000000000060 {V05 V13}, gcrefRegs=0000D008 {rbx r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz IN002e: 0000EA xor eax, eax IN002f: 0000EC mov dword ptr [V06 rbp-2CH], eax IN0030: 0000EF jmp SHORT G_M12932_IG05 G_M12932_IG10: ; offs=0000F1H, size=0006H, bbWeight=0 PerfScore 0.00, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref IN0031: 0000F1 call CORINFO_HELP_RNGCHKFAIL IN0032: 0000F6 int3 *************** Finishing PHASE Emit code *************** Starting PHASE Emit GC+EH tables Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0xd1ffab1e (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x0E CountOfUnwindCodes: 7 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x0E UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 6 * 8 + 8 = 56 = 0x38 CodeOffset: 0x0A UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3) CodeOffset: 0x09 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r12 (12) CodeOffset: 0x07 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r13 (13) CodeOffset: 0x05 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14) CodeOffset: 0x03 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r15 (15) CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) allocUnwindInfo(pHotCode=0x00000000D1FFAB1E, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0xf7, unwindSize=0x12, pUnwindBlock=0x00000000D1FFAB1E, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 13 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x000C : 0x0000003A ( STACK_EMPTY ) IL offs 0x004B : 0x0000003D ( STACK_EMPTY ) IL offs 0x0023 : 0x0000006C ( STACK_EMPTY ) IL offs 0x0026 : 0x00000073 ( STACK_EMPTY ) IL offs 0x0038 : 0x00000096 ( STACK_EMPTY ) IL offs 0x0047 : 0x000000B2 ( STACK_EMPTY ) IL offs 0x004B : 0x000000B9 ( STACK_EMPTY ) IL offs 0x004F : 0x000000D1 ( STACK_EMPTY ) IL offs EPILOG : 0x000000D4 ( STACK_EMPTY ) IL offs 0x0036 : 0x000000E3 ( STACK_EMPTY ) IL offs 0x0045 : 0x000000EA ( STACK_EMPTY ) IL offs NO_MAP : 0x000000F1 ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 21 *************** Variable debug info 21 live ranges 0( UNKNOWN) : From 00000000h to 0000002Ch, in rdi 1( UNKNOWN) : From 00000000h to 0000002Ch, in rsi 2( UNKNOWN) : From 00000000h to 0000002Ch, in rdx 3( UNKNOWN) : From 00000000h to 0000002Ch, in rcx 4( UNKNOWN) : From 00000000h to 0000002Ch, in r8 5( UNKNOWN) : From 00000000h to 0000002Ch, in r9 10( UNKNOWN) : From 00000096h to 0000009Eh, in rbp[-80] (1 slot) 8( UNKNOWN) : From 0000004Ah to 000000B6h, in rbp[-52] (1 slot) 0( UNKNOWN) : From 0000002Ch to 000000D1h, in r14 1( UNKNOWN) : From 0000002Ch to 000000D1h, in r15 4( UNKNOWN) : From 0000002Ch to 000000D1h, in r12 5( UNKNOWN) : From 0000002Ch to 000000D1h, in rbp[-72] (1 slot) 7( UNKNOWN) : From 0000004Ah to 000000D1h, in rbp[-48] (1 slot) 6( UNKNOWN) : From 0000004Ah to 000000D4h, in rbp[-44] (1 slot) 10( UNKNOWN) : From 000000E3h to 000000EAh, in rbp[-80] (1 slot) 8( UNKNOWN) : From 000000E3h to 000000F1h, in rbp[-52] (1 slot) 0( UNKNOWN) : From 000000E3h to 000000F1h, in r14 1( UNKNOWN) : From 000000E3h to 000000F1h, in r15 4( UNKNOWN) : From 000000E3h to 000000F1h, in r12 5( UNKNOWN) : From 000000E3h to 000000F1h, in rbp[-72] (1 slot) 7( UNKNOWN) : From 000000E3h to 000000F1h, in rbp[-48] (1 slot) *************** In gcInfoBlockHdrSave() Set code length to 247. Set ReturnKind to Scalar. Set stack base register to rbp. Set Outgoing stack arg area size to 0. Stack slot id for offset -64 (0xffffffc0) (frame) (untracked) = 0. Stack slot id for offset -72 (0xffffffb8) (frame) (byref) = 1. Stack slot id for offset -88 (0xffffffa8) (frame) = 2. Stack slot id for offset -80 (0xffffffb0) (frame) = 3. Register slot id for reg rbx = 4. Register slot id for reg r12 = 5. Register slot id for reg r14 = 6. Register slot id for reg r15 = 7. Set state of slot 1 at instr offset 0x1d to Live. Set state of slot 1 at instr offset 0xd1 to Dead. Set state of slot 2 at instr offset 0x67 to Live. Set state of slot 2 at instr offset 0xd1 to Dead. Set state of slot 3 at instr offset 0x81 to Live. Set state of slot 3 at instr offset 0xac to Dead. Set state of slot 1 at instr offset 0xe3 to Live. Set state of slot 1 at instr offset 0xf1 to Dead. Set state of slot 2 at instr offset 0xe3 to Live. Set state of slot 2 at instr offset 0xf1 to Dead. Set state of slot 3 at instr offset 0xe3 to Live. Set state of slot 3 at instr offset 0xea to Dead. Set state of slot 4 at instr offset 0x8e to Live. Set state of slot 5 at instr offset 0x8e to Live. Set state of slot 6 at instr offset 0x8e to Live. Set state of slot 7 at instr offset 0x8e to Live. Set state of slot 4 at instr offset 0x92 to Dead. Set state of slot 5 at instr offset 0x92 to Dead. Set state of slot 6 at instr offset 0x92 to Dead. Set state of slot 7 at instr offset 0x92 to Dead. Set state of slot 4 at instr offset 0xac to Live. Set state of slot 5 at instr offset 0xac to Live. Set state of slot 6 at instr offset 0xac to Live. Set state of slot 7 at instr offset 0xac to Live. Set state of slot 4 at instr offset 0xae to Dead. Set state of slot 5 at instr offset 0xae to Dead. Set state of slot 6 at instr offset 0xae to Dead. Set state of slot 7 at instr offset 0xae to Dead. Defining 3 call sites: Offset 0x8e, size 4. Offset 0xac, size 2. Offset 0xf1, size 5. *************** Finishing PHASE Emit GC+EH tables Method code size: 247 Allocations for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool (MethodHash=c68acd7b) count: 2819, size: 199474, max = 3072 allocateMemory: 262144, nraUsed: 206312 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 6460 | 3.24% ASTNode | 26408 | 13.24% InstDesc | 7696 | 3.86% ImpStack | 384 | 0.19% BasicBlock | 3928 | 1.97% fgArgInfo | 648 | 0.32% fgArgInfoPtrArr | 72 | 0.04% FlowList | 480 | 0.24% TreeStatementList | 128 | 0.06% SiScope | 1480 | 0.74% DominatorMemory | 384 | 0.19% LSRA | 3552 | 1.78% LSRA_Interval | 2960 | 1.48% LSRA_RefPosition | 10816 | 5.42% Reachability | 16 | 0.01% SSA | 2360 | 1.18% ValueNumber | 20344 | 10.20% LvaTable | 2940 | 1.47% UnwindInfo | 0 | 0.00% hashBv | 320 | 0.16% bitset | 408 | 0.20% FixedBitVect | 40 | 0.02% Generic | 3312 | 1.66% LocalAddressVisitor | 512 | 0.26% FieldSeqStore | 176 | 0.09% ZeroOffsetFieldMap | 160 | 0.08% ArrayInfoMap | 272 | 0.14% MemoryPhiArg | 64 | 0.03% CSE | 2112 | 1.06% GC | 3011 | 1.51% CorTailCallInfo | 0 | 0.00% Inlining | 2752 | 1.38% ArrayStack | 0 | 0.00% DebugInfo | 896 | 0.45% DebugOnly | 86331 | 43.28% Codegen | 1184 | 0.59% LoopOpt | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 644 | 0.32% RangeCheck | 4488 | 2.25% CopyProp | 1488 | 0.75% SideEffects | 0 | 0.00% ObjectAllocator | 0 | 0.00% VariableLiveRanges | 0 | 0.00% ClassLayout | 112 | 0.06% TailMergeThrows | 0 | 0.00% EarlyProp | 0 | 0.00% ZeroInit | 136 | 0.07% ****** DONE compiling Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]],Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool ****** START compiling Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool (MethodHash=a679a79b) Generating code for Unix x64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false OPTIONS: optimized using profile data OPTIONS: Jit invoked for ngen IL to import: IL_0000 05 ldarg.3 IL_0001 28 bb 23 00 06 call 0x60023BB IL_0006 2c 07 brfalse.s 7 (IL_000f) IL_0008 17 ldc.i4.1 IL_0009 0a stloc.0 IL_000a 38 dd 00 00 00 br 221 (IL_00ec) IL_000f 17 ldc.i4.1 IL_0010 0b stloc.1 IL_0011 05 ldarg.3 IL_0012 28 d3 23 00 06 call 0x60023D3 IL_0017 2c 27 brfalse.s 39 (IL_0040) IL_0019 0e 04 ldarg.s 0x4 IL_001b 2c 21 brfalse.s 33 (IL_003e) IL_001d 0e 04 ldarg.s 0x4 IL_001f 04 ldarg.2 IL_0020 20 a4 7a 00 00 ldc.i4 0x7AA4 IL_0025 17 ldc.i4.1 IL_0026 8d 0e 00 00 01 newarr 0x100000E IL_002b 25 dup IL_002c 16 ldc.i4.0 IL_002d 05 ldarg.3 IL_002e a2 stelem.ref IL_002f 28 92 2a 00 06 call 0x6002A92 IL_0034 73 0b 17 00 06 newobj 0x600170B IL_0039 6f 44 0b 00 0a callvirt 0xA000B44 IL_003e 16 ldc.i4.0 IL_003f 0b stloc.1 IL_0040 04 ldarg.2 IL_0041 6f cb 12 00 06 callvirt 0x60012CB IL_0046 2c 0d brfalse.s 13 (IL_0055) IL_0048 04 ldarg.2 IL_0049 05 ldarg.3 IL_004a 0e 04 ldarg.s 0x4 IL_004c 28 20 17 00 06 call 0x6001720 IL_0051 2d 02 brtrue.s 2 (IL_0055) IL_0053 16 ldc.i4.0 IL_0054 0b stloc.1 IL_0055 04 ldarg.2 IL_0056 6f e6 12 00 06 callvirt 0x60012E6 IL_005b 2c 0d brfalse.s 13 (IL_006a) IL_005d 04 ldarg.2 IL_005e 05 ldarg.3 IL_005f 0e 04 ldarg.s 0x4 IL_0061 28 21 17 00 06 call 0x6001721 IL_0066 2d 02 brtrue.s 2 (IL_006a) IL_0068 16 ldc.i4.0 IL_0069 0b stloc.1 IL_006a 04 ldarg.2 IL_006b 6f e7 12 00 06 callvirt 0x60012E7 IL_0070 2c 10 brfalse.s 16 (IL_0082) IL_0072 02 ldarg.0 IL_0073 04 ldarg.2 IL_0074 05 ldarg.3 IL_0075 0e 04 ldarg.s 0x4 IL_0077 0e 05 ldarg.s 0x5 IL_0079 28 22 17 00 06 call 0x6001722 IL_007e 2d 02 brtrue.s 2 (IL_0082) IL_0080 16 ldc.i4.0 IL_0081 0b stloc.1 IL_0082 04 ldarg.2 IL_0083 0e 05 ldarg.s 0x5 IL_0085 6f ca 12 00 06 callvirt 0x60012CA IL_008a 0d stloc.3 IL_008b 12 03 ldloca.s 0x3 IL_008d 28 88 06 00 0a call 0xA000688 IL_0092 0c stloc.2 IL_0093 2b 4c br.s 76 (IL_00e1) IL_0095 12 02 ldloca.s 0x2 IL_0097 28 89 06 00 0a call 0xA000689 IL_009c 03 ldarg.1 IL_009d 6f 99 23 00 06 callvirt 0x6002399 IL_00a2 7b a8 07 00 04 ldfld 0x40007A8 IL_00a7 13 04 stloc.s 0x4 IL_00a9 05 ldarg.3 IL_00aa 11 04 ldloc.s 0x4 IL_00ac 0e 05 ldarg.s 0x5 IL_00ae 28 1f 17 00 06 call 0x600171F IL_00b3 2d 2c brtrue.s 44 (IL_00e1) IL_00b5 0e 04 ldarg.s 0x4 IL_00b7 2c 26 brfalse.s 38 (IL_00df) IL_00b9 0e 04 ldarg.s 0x4 IL_00bb 04 ldarg.2 IL_00bc 20 2c 7d 00 00 ldc.i4 0x7D2C IL_00c1 18 ldc.i4.2 IL_00c2 8d 0e 00 00 01 newarr 0x100000E IL_00c7 25 dup IL_00c8 16 ldc.i4.0 IL_00c9 05 ldarg.3 IL_00ca a2 stelem.ref IL_00cb 25 dup IL_00cc 17 ldc.i4.1 IL_00cd 11 04 ldloc.s 0x4 IL_00cf a2 stelem.ref IL_00d0 28 92 2a 00 06 call 0x6002A92 IL_00d5 73 0b 17 00 06 newobj 0x600170B IL_00da 6f 44 0b 00 0a callvirt 0xA000B44 IL_00df 16 ldc.i4.0 IL_00e0 0b stloc.1 IL_00e1 12 02 ldloca.s 0x2 IL_00e3 28 8a 06 00 0a call 0xA00068A IL_00e8 2d ab brtrue.s -85 (IL_0095) IL_00ea 07 ldloc.1 IL_00eb 0a stloc.0 IL_00ec 06 ldloc.0 IL_00ed 2a ret lvaSetClass: setting class for V00 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.VisualBasic.Symbol Arg #0 passed in register(s) rdi lvaSetClass: setting class for V01 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution Arg #1 passed in register(s) rsi lvaSetClass: setting class for V02 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol Arg #2 passed in register(s) rdx lvaSetClass: setting class for V03 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol Arg #3 passed in register(s) rcx lvaSetClass: setting class for V04 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo] Arg #4 passed in register(s) r8 Arg #5 passed in register(s) r9 lvaSetClass: setting class for V10 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol lvaGrabTemp returning 11 (V11 tmp0) (a long lifetime temp) called for OutgoingArgSpace. ; Initial local variable assignments ; ; V00 arg0 ref class-hnd ; V01 arg1 ref class-hnd ; V02 arg2 ref class-hnd ; V03 arg3 ref class-hnd ; V04 arg4 ref class-hnd ; V05 arg5 byref ; V06 loc0 bool ; V07 loc1 bool ; V08 loc2 struct ; V09 loc3 struct ; V10 loc4 ref class-hnd ; V11 OutArgs lclBlk "OutgoingArgSpace" *************** In compInitDebuggingInfo() for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 11 VarNum LVNum Name Beg End 0: 00h 00h V00 arg0 000h 0EEh 1: 01h 01h V01 arg1 000h 0EEh 2: 02h 02h V02 arg2 000h 0EEh 3: 03h 03h V03 arg3 000h 0EEh 4: 04h 04h V04 arg4 000h 0EEh 5: 05h 05h V05 arg5 000h 0EEh 6: 06h 06h V06 loc0 000h 0EEh 7: 07h 07h V07 loc1 000h 0EEh 8: 08h 08h V08 loc2 000h 0EEh 9: 09h 09h V09 loc3 000h 0EEh 10: 0Ah 0Ah V10 loc4 000h 0EEh info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool Marked V10 as a single def local Jump targets: IL_000f IL_003e IL_0040 IL_0055 IL_006a IL_0082 IL_0095 IL_00df IL_00e1 IL_00ec New Basic Block BB01 [0000] created. BB01 [000..008) New Basic Block BB02 [0001] created. BB02 [008..00F) New Basic Block BB03 [0002] created. BB03 [00F..019) New Basic Block BB04 [0003] created. BB04 [019..01D) New Basic Block BB05 [0004] created. BB05 [01D..03E) New Basic Block BB06 [0005] created. BB06 [03E..040) New Basic Block BB07 [0006] created. BB07 [040..048) New Basic Block BB08 [0007] created. BB08 [048..053) New Basic Block BB09 [0008] created. BB09 [053..055) New Basic Block BB10 [0009] created. BB10 [055..05D) New Basic Block BB11 [0010] created. BB11 [05D..068) New Basic Block BB12 [0011] created. BB12 [068..06A) New Basic Block BB13 [0012] created. BB13 [06A..072) New Basic Block BB14 [0013] created. BB14 [072..080) New Basic Block BB15 [0014] created. BB15 [080..082) New Basic Block BB16 [0015] created. BB16 [082..095) New Basic Block BB17 [0016] created. BB17 [095..0B5) New Basic Block BB18 [0017] created. BB18 [0B5..0B9) New Basic Block BB19 [0018] created. BB19 [0B9..0DF) New Basic Block BB20 [0019] created. BB20 [0DF..0E1) New Basic Block BB21 [0020] created. BB21 [0E1..0EA) New Basic Block BB22 [0021] created. BB22 [0EA..0EC) New Basic Block BB23 [0022] created. BB23 [0EC..0EE) INLINER: during 'prejit' result 'failed this callee' reason 'too many il bytes' for 'n/a' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' INLINER: Marking Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool as NOINLINE because of too many il bytes INLINER: during 'prejit' result 'failed this callee' reason 'too many il bytes' IL Code Size,Instr 238, 105, Basic Block count 23, Local Variable Num,Ref count 12, 47 for method Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool OPTIONS: opts.MinOpts() == false Basic block list for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) IBC BB02 [0001] 1 0 0 [008..00F)-> BB23 (always) rare IBC BB03 [0002] 1 20988. 20988 [00F..019)-> BB07 ( cond ) IBC BB04 [0003] 1 0 0 [019..01D)-> BB06 ( cond ) rare IBC BB05 [0004] 1 0 0 [01D..03E) rare IBC BB06 [0005] 2 0 0 [03E..040) rare IBC BB07 [0006] 2 20988. 20988 [040..048)-> BB10 ( cond ) IBC BB08 [0007] 1 131 131 [048..053)-> BB10 ( cond ) IBC BB09 [0008] 1 0 0 [053..055) rare IBC BB10 [0009] 3 20988. 20988 [055..05D)-> BB13 ( cond ) IBC BB11 [0010] 1 614 614 [05D..068)-> BB13 ( cond ) IBC BB12 [0011] 1 22 22 [068..06A) IBC BB13 [0012] 3 20988. 20988 [06A..072)-> BB16 ( cond ) IBC BB14 [0013] 1 87 87 [072..080)-> BB16 ( cond ) IBC BB15 [0014] 1 0 0 [080..082) rare IBC BB16 [0015] 3 20988. 20988 [082..095)-> BB21 (always) IBC BB17 [0016] 1 6120. 6120 [095..0B5)-> BB21 ( cond ) bwd bwd-target IBC BB18 [0017] 1 479 479 [0B5..0B9)-> BB20 ( cond ) bwd IBC BB19 [0018] 1 479 479 [0B9..0DF) bwd IBC BB20 [0019] 2 479 479 [0DF..0E1) bwd IBC BB21 [0020] 3 27108. 27108 [0E1..0EA)-> BB17 ( cond ) bwd IBC BB22 [0021] 1 20988. 20988 [0EA..0EC) IBC BB23 [0022] 2 20988. 20988 [0EC..0EE) (return) IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import *************** Starting PHASE Importation *************** In impImport() for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool impImportBlockPending for BB01 Importing BB01 (PC=000) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 0 (0x000) ldarg.3 [ 1] 1 (0x001) call 060023BB In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 STMT00000 (IL 0x000... ???) [000001] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.IsErrorType (exactContextHnd=0x00000000D1FFAB1E) [000000] ------------ arg0 \--* LCL_VAR ref V03 arg3 [ 1] 6 (0x006) brfalse.s STMT00001 (IL ???... ???) [000006] --C--------- * JTRUE void [000005] --C--------- \--* EQ int [000003] --C--------- +--* CAST int <- bool <- int [000002] --C--------- | \--* RET_EXPR int (inl return from call [000001]) [000004] ------------ \--* CNS_INT int 0 impImportBlockPending for BB02 impImportBlockPending for BB03 Importing BB03 (PC=015) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 15 (0x00f) ldc.i4.1 1 [ 1] 16 (0x010) stloc.1 STMT00002 (IL 0x00F... ???) [000009] -A---------- * ASG int [000008] D------N---- +--* LCL_VAR int V07 loc1 [000007] ------------ \--* CNS_INT int 1 [ 0] 17 (0x011) ldarg.3 [ 1] 18 (0x012) call 060023D3 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 STMT00003 (IL 0x011... ???) [000011] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.IsRestrictedType (exactContextHnd=0x00000000D1FFAB1E) [000010] ------------ arg0 \--* LCL_VAR ref V03 arg3 [ 1] 23 (0x017) brfalse.s STMT00004 (IL ???... ???) [000016] --C--------- * JTRUE void [000015] --C--------- \--* EQ int [000013] --C--------- +--* CAST int <- bool <- int [000012] --C--------- | \--* RET_EXPR int (inl return from call [000011]) [000014] ------------ \--* CNS_INT int 0 impImportBlockPending for BB04 impImportBlockPending for BB07 Importing BB07 (PC=064) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 64 (0x040) ldarg.2 [ 1] 65 (0x041) callvirt 060012CB In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is bool, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol (attrib 21000400) base method is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol::get_HasConstructorConstraint devirt to Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol::get_HasConstructorConstraint -- inexact or not final [000018] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] ------------ this in rdi \--* LCL_VAR ref V02 arg2 Class not final or exact, and method not final NOT Marking call [000018] as guarded devirtualization candidate -- disabled by jit config INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasConstructorConstraint():bool:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 1] 70 (0x046) brfalse.s STMT00005 (IL 0x040... ???) [000022] --C-G------- * JTRUE void [000021] --C-G------- \--* EQ int [000019] --C-G------- +--* CAST int <- bool <- int [000018] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000020] ------------ \--* CNS_INT int 0 impImportBlockPending for BB08 impImportBlockPending for BB10 Importing BB10 (PC=085) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 85 (0x055) ldarg.2 [ 1] 86 (0x056) callvirt 060012E6 In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is bool, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol (attrib 21000400) base method is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol::get_HasReferenceTypeConstraint devirt to Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol::get_HasReferenceTypeConstraint -- inexact or not final [000024] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] ------------ this in rdi \--* LCL_VAR ref V02 arg2 Class not final or exact, and method not final NOT Marking call [000024] as guarded devirtualization candidate -- disabled by jit config INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasReferenceTypeConstraint():bool:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 1] 91 (0x05b) brfalse.s STMT00006 (IL 0x055... ???) [000028] --C-G------- * JTRUE void [000027] --C-G------- \--* EQ int [000025] --C-G------- +--* CAST int <- bool <- int [000024] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000026] ------------ \--* CNS_INT int 0 impImportBlockPending for BB11 impImportBlockPending for BB13 Importing BB13 (PC=106) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 106 (0x06a) ldarg.2 [ 1] 107 (0x06b) callvirt 060012E7 In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is bool, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol (attrib 21000400) base method is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol::get_HasValueTypeConstraint devirt to Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol::get_HasValueTypeConstraint -- inexact or not final [000030] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] ------------ this in rdi \--* LCL_VAR ref V02 arg2 Class not final or exact, and method not final NOT Marking call [000030] as guarded devirtualization candidate -- disabled by jit config INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasValueTypeConstraint():bool:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 1] 112 (0x070) brfalse.s STMT00007 (IL 0x06A... ???) [000034] --C-G------- * JTRUE void [000033] --C-G------- \--* EQ int [000031] --C-G------- +--* CAST int <- bool <- int [000030] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000032] ------------ \--* CNS_INT int 0 impImportBlockPending for BB14 impImportBlockPending for BB16 Importing BB16 (PC=130) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 130 (0x082) ldarg.2 [ 1] 131 (0x083) ldarg.s 5 [ 2] 133 (0x085) callvirt 060012CA In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is struct, structSize is 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 1 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 STMT00008 (IL 0x082... ???) [000037] I-C-G------- * CALL r2r_ind struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics (exactContextHnd=0x00000000D1FFAB1E) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] ------------ arg1 \--* LCL_VAR byref V05 arg5 [ 1] 138 (0x08a) stloc.3 STMT00009 (IL ???... ???) [000042] -AC--------- * ASG ref [000041] ------------ +--* IND ref [000040] ------------ | \--* ADDR byref [000039] -------N---- | \--* LCL_VAR struct V09 loc3 [000038] --C--------- \--* RET_EXPR ref (inl return from call [000037]) [ 0] 139 (0x08b) ldloca.s 3 [ 1] 141 (0x08d) call 0A000688 In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16 **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1+Enumerator[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1+Enumerator[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 lvaGrabTemp returning 12 (V12 tmp1) called for Return value temp for multireg return. STMT00010 (IL 0x08B... ???) [000050] -AC-G------- * ASG struct (copy) [000048] D------N---- +--* LCL_VAR struct V12 tmp1 [000045] --C-G------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA [000044] ------------ this in rdi +--* ADDR byref [000043] -------N---- | \--* LCL_VAR struct V09 loc3 [000047] n----------- arg1 \--* IND long [000046] ------------ \--* CNS_INT(h) long 0xd1ffab1e class **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1+Enumerator[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 [ 1] 146 (0x092) stloc.2 STMT00011 (IL ???... ???) [000054] -A---------- * ASG struct (copy) [000052] D------N---- +--* LCL_VAR struct V08 loc2 [000051] -------N---- \--* LCL_VAR struct V12 tmp1 [ 0] 147 (0x093) br.s impImportBlockPending for BB21 Importing BB21 (PC=225) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 225 (0x0e1) ldloca.s 2 [ 1] 227 (0x0e3) call 0A00068A In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 [ 1] 232 (0x0e8) brtrue.s STMT00012 (IL 0x0E1... ???) [000063] --C-G------- * JTRUE void [000062] --C-G------- \--* NE int [000060] --C-G------- +--* CAST int <- bool <- int [000057] --C-G------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext [000056] ------------ this in rdi | +--* ADDR byref [000055] -------N---- | | \--* LCL_VAR struct V08 loc2 [000059] n----------- arg1 | \--* IND long [000058] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000061] ------------ \--* CNS_INT int 0 impImportBlockPending for BB22 impImportBlockPending for BB17 Importing BB17 (PC=149) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 149 (0x095) ldloca.s 2 [ 1] 151 (0x097) call 0A000689 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 [ 1] 156 (0x09c) ldarg.1 [ 2] 157 (0x09d) callvirt 06002399 In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is struct, structSize is 16 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is System.__Canon (attrib 00020000) base method is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol::InternalSubstituteTypeParameters --- no derived method, sorry INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol:InternalSubstituteTypeParameters(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution):Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeWithModifiers:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeWithModifiers), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: IntegerReference, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeWithModifiers), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: IntegerReference, byteSize: 8, byteOffset: 8 lvaGrabTemp returning 13 (V13 tmp2) called for Return value temp for multireg return. STMT00013 (IL 0x095... ???) [000073] -AC-G------- * ASG struct (copy) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 [000070] --C-G------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000066] --C-G------- this in rdi +--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current [000065] ------------ this in rdi | +--* ADDR byref [000064] -------N---- | | \--* LCL_VAR struct V08 loc2 [000068] n----------- arg1 | \--* IND long [000067] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000069] ------------ arg1 \--* LCL_VAR ref V01 arg1 **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeWithModifiers), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: IntegerReference, byteSize: 8, byteOffset: 8 [ 1] 162 (0x0a2) ldfld 040007A8 [ 1] 167 (0x0a7) stloc.s 4Querying runtime about current class of field Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeWithModifiers.Type (declared as Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol) Field's current class not available STMT00014 (IL ???... ???) [000078] -A---------- * ASG ref [000077] D------N---- +--* LCL_VAR ref V10 loc4 [000076] ------------ \--* FIELD ref Type [000075] ------------ \--* ADDR byref [000074] -------N---- \--* LCL_VAR struct V13 tmp2 [ 0] 169 (0x0a9) ldarg.3 [ 1] 170 (0x0aa) ldloc.s 4 [ 2] 172 (0x0ac) ldarg.s 5 [ 3] 174 (0x0ae) call 0600171F In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 STMT00015 (IL 0x0A9... ???) [000082] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesTypeConstraint (exactContextHnd=0x00000000D1FFAB1E) [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000080] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 [ 1] 179 (0x0b3) brtrue.s STMT00016 (IL ???... ???) [000087] --C--------- * JTRUE void [000086] --C--------- \--* NE int [000084] --C--------- +--* CAST int <- bool <- int [000083] --C--------- | \--* RET_EXPR int (inl return from call [000082]) [000085] ------------ \--* CNS_INT int 0 impImportBlockPending for BB18 impImportBlockPending for BB21 Importing BB18 (PC=181) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 181 (0x0b5) ldarg.s 4 [ 1] 183 (0x0b7) brfalse.s STMT00017 (IL 0x0B5... ???) [000091] ------------ * JTRUE void [000090] ------------ \--* EQ int [000088] ------------ +--* LCL_VAR ref V04 arg4 [000089] ------------ \--* CNS_INT ref null impImportBlockPending for BB19 impImportBlockPending for BB20 Importing BB20 (PC=223) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 223 (0x0df) ldc.i4.0 0 [ 1] 224 (0x0e0) stloc.1 STMT00018 (IL 0x0DF... ???) [000094] -A---------- * ASG int [000093] D------N---- +--* LCL_VAR int V07 loc1 [000092] ------------ \--* CNS_INT int 0 impImportBlockPending for BB21 Importing BB19 (PC=185) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 185 (0x0b9) ldarg.s 4 [ 1] 187 (0x0bb) ldarg.2 [ 2] 188 (0x0bc) ldc.i4 32044 [ 3] 193 (0x0c1) ldc.i4.2 2 [ 4] 194 (0x0c2) newarr 0100000E [ 4] 199 (0x0c7) dup lvaGrabTemp returning 14 (V14 tmp3) called for dup spill. STMT00019 (IL 0x0B9... ???) [000101] -ACXG------- * ASG ref [000100] D------N---- +--* LCL_VAR ref V14 tmp3 [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000098] ------------ arg0 \--* CNS_INT long 2 Marked V14 as a single def local lvaSetClass: setting class for V14 to (00000000D1FFAB1E) System.Object[] [exact] [ 5] 200 (0x0c8) ldc.i4.0 0 [ 6] 201 (0x0c9) ldarg.3 [ 7] 202 (0x0ca) stelem.ref stelem to (exact) object[]: skipping covariant store check STMT00020 (IL ???... ???) [000107] -A-XG------- * ASG ref [000106] ---XG--N---- +--* INDEX ref [000103] ------------ | +--* LCL_VAR ref V14 tmp3 [000104] ------------ | \--* CNS_INT int 0 [000105] ------------ \--* LCL_VAR ref V03 arg3 [ 4] 203 (0x0cb) dup [ 5] 204 (0x0cc) ldc.i4.1 1 [ 6] 205 (0x0cd) ldloc.s 4 [ 7] 207 (0x0cf) stelem.ref stelem to (exact) object[]: skipping covariant store check STMT00021 (IL ???... ???) [000112] -A-XG------- * ASG ref [000111] ---XG--N---- +--* INDEX ref [000108] ------------ | +--* LCL_VAR ref V14 tmp3 [000109] ------------ | \--* CNS_INT int 1 [000110] ------------ \--* LCL_VAR ref V10 loc4 [ 4] 208 (0x0d0) call 06002A92 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 STMT00022 (IL ???... ???) [000113] I-C-G------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.ErrorFactory.ErrorInfo (exactContextHnd=0x00000000D1FFAB1E) [000097] ------------ arg0 +--* CNS_INT int 0x7D2C [000102] ------------ arg1 \--* LCL_VAR ref V14 tmp3 [ 3] 213 (0x0d5) newobj lvaGrabTemp returning 15 (V15 tmp4) called for NewObj constructor temp. STMT00023 (IL ???... ???) [000117] IA---------- * ASG struct (init) [000115] D------N---- +--* LCL_VAR struct V15 tmp4 [000116] ------------ \--* CNS_INT int 0 0600170B In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 STMT00024 (IL ???... ???) [000120] I-C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor (exactContextHnd=0x00000000D1FFAB1E) [000119] ------------ this in rdi +--* ADDR byref [000118] -------N---- | \--* LCL_VAR struct V15 tmp4 [000096] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000114] --C--------- arg2 \--* RET_EXPR ref (inl return from call [000113]) [ 2] 218 (0x0da) callvirt 0A000B44 In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is void, structSize is 0 Calling impNormStructVal on: [000121] ------------ * LCL_VAR struct V15 tmp4 resulting tree: [000124] n----------- * OBJ struct [000123] ------------ \--* ADDR byref [000121] -------N---- \--* LCL_VAR struct V15 tmp4 impDevirtualizeCall: [R2R] base method not virtual, sorry INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo]:Add(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo):this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' STMT00025 (IL 0x0DA... ???) [000122] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000124] n----------- arg1 \--* OBJ struct [000123] ------------ \--* ADDR byref [000121] -------N---- \--* LCL_VAR struct V15 tmp4 impImportBlockPending for BB20 Importing BB22 (PC=234) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 234 (0x0ea) ldloc.1 [ 1] 235 (0x0eb) stloc.0 STMT00026 (IL 0x0EA... ???) [000127] -A---------- * ASG int [000126] D------N---- +--* LCL_VAR int V06 loc0 [000125] ------------ \--* LCL_VAR int V07 loc1 impImportBlockPending for BB23 Importing BB23 (PC=236) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 236 (0x0ec) ldloc.0 [ 1] 237 (0x0ed) ret STMT00027 (IL 0x0EC... ???) [000129] ------------ * RETURN int [000128] ------------ \--* LCL_VAR int V06 loc0 Importing BB14 (PC=114) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 114 (0x072) ldarg.0 [ 1] 115 (0x073) ldarg.2 [ 2] 116 (0x074) ldarg.3 [ 3] 117 (0x075) ldarg.s 4 [ 4] 119 (0x077) ldarg.s 5 [ 5] 121 (0x079) call 06001722 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesValueTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' INLINER: Marking Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesValueTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 126 (0x07e) brtrue.s STMT00028 (IL 0x072... ???) [000139] --C-G------- * JTRUE void [000138] --C-G------- \--* NE int [000136] --C-G------- +--* CAST int <- bool <- int [000135] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000131] ------------ arg1 | +--* LCL_VAR ref V02 arg2 [000132] ------------ arg2 | +--* LCL_VAR ref V03 arg3 [000133] ------------ arg3 | +--* LCL_VAR ref V04 arg4 [000134] ------------ arg4 | \--* LCL_VAR byref V05 arg5 [000137] ------------ \--* CNS_INT int 0 impImportBlockPending for BB15 impImportBlockPending for BB16 Importing BB15 (PC=128) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 128 (0x080) ldc.i4.0 0 [ 1] 129 (0x081) stloc.1 STMT00029 (IL 0x080... ???) [000142] -A---------- * ASG int [000141] D------N---- +--* LCL_VAR int V07 loc1 [000140] ------------ \--* CNS_INT int 0 impImportBlockPending for BB16 Importing BB11 (PC=093) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 93 (0x05d) ldarg.2 [ 1] 94 (0x05e) ldarg.3 [ 2] 95 (0x05f) ldarg.s 4 [ 3] 97 (0x061) call 06001721 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 STMT00030 (IL 0x05D... ???) [000146] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint (exactContextHnd=0x00000000D1FFAB1E) [000143] ------------ arg0 +--* LCL_VAR ref V02 arg2 [000144] ------------ arg1 +--* LCL_VAR ref V03 arg3 [000145] ------------ arg2 \--* LCL_VAR ref V04 arg4 [ 1] 102 (0x066) brtrue.s STMT00031 (IL ???... ???) [000151] --C--------- * JTRUE void [000150] --C--------- \--* NE int [000148] --C--------- +--* CAST int <- bool <- int [000147] --C--------- | \--* RET_EXPR int (inl return from call [000146]) [000149] ------------ \--* CNS_INT int 0 impImportBlockPending for BB12 impImportBlockPending for BB13 Importing BB12 (PC=104) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 104 (0x068) ldc.i4.0 0 [ 1] 105 (0x069) stloc.1 STMT00032 (IL 0x068... ???) [000154] -A---------- * ASG int [000153] D------N---- +--* LCL_VAR int V07 loc1 [000152] ------------ \--* CNS_INT int 0 impImportBlockPending for BB13 Importing BB08 (PC=072) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 72 (0x048) ldarg.2 [ 1] 73 (0x049) ldarg.3 [ 2] 74 (0x04a) ldarg.s 4 [ 3] 76 (0x04c) call 06001720 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesConstructorConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool' INLINER: Marking Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesConstructorConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' [ 1] 81 (0x051) brtrue.s STMT00033 (IL 0x048... ???) [000162] --C-G------- * JTRUE void [000161] --C-G------- \--* NE int [000159] --C-G------- +--* CAST int <- bool <- int [000158] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] ------------ arg0 | +--* LCL_VAR ref V02 arg2 [000156] ------------ arg1 | +--* LCL_VAR ref V03 arg3 [000157] ------------ arg2 | \--* LCL_VAR ref V04 arg4 [000160] ------------ \--* CNS_INT int 0 impImportBlockPending for BB09 impImportBlockPending for BB10 Importing BB09 (PC=083) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 83 (0x053) ldc.i4.0 0 [ 1] 84 (0x054) stloc.1 STMT00034 (IL 0x053... ???) [000165] -A---------- * ASG int [000164] D------N---- +--* LCL_VAR int V07 loc1 [000163] ------------ \--* CNS_INT int 0 impImportBlockPending for BB10 Importing BB04 (PC=025) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 25 (0x019) ldarg.s 4 [ 1] 27 (0x01b) brfalse.s STMT00035 (IL 0x019... ???) [000169] ------------ * JTRUE void [000168] ------------ \--* EQ int [000166] ------------ +--* LCL_VAR ref V04 arg4 [000167] ------------ \--* CNS_INT ref null impImportBlockPending for BB05 impImportBlockPending for BB06 Importing BB06 (PC=062) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 62 (0x03e) ldc.i4.0 0 [ 1] 63 (0x03f) stloc.1 STMT00036 (IL 0x03E... ???) [000172] -A---------- * ASG int [000171] D------N---- +--* LCL_VAR int V07 loc1 [000170] ------------ \--* CNS_INT int 0 impImportBlockPending for BB07 Importing BB05 (PC=029) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 29 (0x01d) ldarg.s 4 [ 1] 31 (0x01f) ldarg.2 [ 2] 32 (0x020) ldc.i4 31396 [ 3] 37 (0x025) ldc.i4.1 1 [ 4] 38 (0x026) newarr 0100000E [ 4] 43 (0x02b) dup lvaGrabTemp returning 16 (V16 tmp5) called for dup spill. STMT00037 (IL 0x01D... ???) [000179] -ACXG------- * ASG ref [000178] D------N---- +--* LCL_VAR ref V16 tmp5 [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000176] ------------ arg0 \--* CNS_INT long 1 Marked V16 as a single def local lvaSetClass: setting class for V16 to (00000000D1FFAB1E) System.Object[] [exact] [ 5] 44 (0x02c) ldc.i4.0 0 [ 6] 45 (0x02d) ldarg.3 [ 7] 46 (0x02e) stelem.ref stelem to (exact) object[]: skipping covariant store check STMT00038 (IL ???... ???) [000185] -A-XG------- * ASG ref [000184] ---XG--N---- +--* INDEX ref [000181] ------------ | +--* LCL_VAR ref V16 tmp5 [000182] ------------ | \--* CNS_INT int 0 [000183] ------------ \--* LCL_VAR ref V03 arg3 [ 4] 47 (0x02f) call 06002A92 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 STMT00039 (IL ???... ???) [000186] I-C-G------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.ErrorFactory.ErrorInfo (exactContextHnd=0x00000000D1FFAB1E) [000175] ------------ arg0 +--* CNS_INT int 0x7AA4 [000180] ------------ arg1 \--* LCL_VAR ref V16 tmp5 [ 3] 52 (0x034) newobj lvaGrabTemp returning 17 (V17 tmp6) called for NewObj constructor temp. Suppressing zero-init for V17 -- expect to zero in prolog 0600170B In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 STMT00040 (IL ???... ???) [000190] I-C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor (exactContextHnd=0x00000000D1FFAB1E) [000189] ------------ this in rdi +--* ADDR byref [000188] -------N---- | \--* LCL_VAR struct V17 tmp6 [000174] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000187] --C--------- arg2 \--* RET_EXPR ref (inl return from call [000186]) [ 2] 57 (0x039) callvirt 0A000B44 In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is void, structSize is 0 Calling impNormStructVal on: [000191] ------------ * LCL_VAR struct V17 tmp6 resulting tree: [000194] n----------- * OBJ struct [000193] ------------ \--* ADDR byref [000191] -------N---- \--* LCL_VAR struct V17 tmp6 impDevirtualizeCall: [R2R] base method not virtual, sorry INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo]:Add(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo):this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' STMT00041 (IL 0x039... ???) [000192] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000194] n----------- arg1 \--* OBJ struct [000193] ------------ \--* ADDR byref [000191] -------N---- \--* LCL_VAR struct V17 tmp6 impImportBlockPending for BB06 Importing BB02 (PC=008) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' [ 0] 8 (0x008) ldc.i4.1 1 [ 1] 9 (0x009) stloc.0 STMT00042 (IL 0x008... ???) [000197] -A---------- * ASG int [000196] D------N---- +--* LCL_VAR int V06 loc0 [000195] ------------ \--* CNS_INT int 1 [ 0] 10 (0x00a) br impImportBlockPending for BB23 *************** Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) i IBC BB02 [0001] 1 0 0 [008..00F)-> BB23 (always) i rare IBC BB03 [0002] 1 20988. 20988 [00F..019)-> BB07 ( cond ) i IBC BB04 [0003] 1 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 0 0 [01D..03E) i rare idxlen new[] IBC BB06 [0005] 2 0 0 [03E..040) i rare IBC BB07 [0006] 2 20988. 20988 [040..048)-> BB10 ( cond ) i IBC BB08 [0007] 1 131 131 [048..053)-> BB10 ( cond ) i IBC BB09 [0008] 1 0 0 [053..055) i rare IBC BB10 [0009] 3 20988. 20988 [055..05D)-> BB13 ( cond ) i IBC BB11 [0010] 1 614 614 [05D..068)-> BB13 ( cond ) i IBC BB12 [0011] 1 22 22 [068..06A) i IBC BB13 [0012] 3 20988. 20988 [06A..072)-> BB16 ( cond ) i IBC BB14 [0013] 1 87 87 [072..080)-> BB16 ( cond ) i IBC BB15 [0014] 1 0 0 [080..082) i rare IBC BB16 [0015] 3 20988. 20988 [082..095)-> BB21 (always) i IBC BB17 [0016] 1 6120. 6120 [095..0B5)-> BB21 ( cond ) i bwd bwd-target IBC BB18 [0017] 1 479 479 [0B5..0B9)-> BB20 ( cond ) i bwd IBC BB19 [0018] 1 479 479 [0B9..0DF) i idxlen new[] bwd IBC BB20 [0019] 2 479 479 [0DF..0E1) i bwd IBC BB21 [0020] 3 27108. 27108 [0E1..0EA)-> BB17 ( cond ) i bwd IBC BB22 [0021] 1 20988. 20988 [0EA..0EC) i IBC BB23 [0022] 2 20988. 20988 [0EC..0EE) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x006) [000001] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.IsErrorType (exactContextHnd=0x00000000D1FFAB1E) [000000] ------------ arg0 \--* LCL_VAR ref V03 arg3 ***** BB01 STMT00001 (IL ???... ???) [000006] --C--------- * JTRUE void [000005] --C--------- \--* EQ int [000003] --C--------- +--* CAST int <- bool <- int [000002] --C--------- | \--* RET_EXPR int (inl return from call [000001]) [000004] ------------ \--* CNS_INT int 0 ------------ BB02 [008..00F) -> BB23 (always), preds={} succs={BB23} ***** BB02 STMT00042 (IL 0x008...0x009) [000197] -A---------- * ASG int [000196] D------N---- +--* LCL_VAR int V06 loc0 [000195] ------------ \--* CNS_INT int 1 ------------ BB03 [00F..019) -> BB07 (cond), preds={} succs={BB04,BB07} ***** BB03 STMT00002 (IL 0x00F...0x010) [000009] -A---------- * ASG int [000008] D------N---- +--* LCL_VAR int V07 loc1 [000007] ------------ \--* CNS_INT int 1 ***** BB03 STMT00003 (IL 0x011...0x017) [000011] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.IsRestrictedType (exactContextHnd=0x00000000D1FFAB1E) [000010] ------------ arg0 \--* LCL_VAR ref V03 arg3 ***** BB03 STMT00004 (IL ???... ???) [000016] --C--------- * JTRUE void [000015] --C--------- \--* EQ int [000013] --C--------- +--* CAST int <- bool <- int [000012] --C--------- | \--* RET_EXPR int (inl return from call [000011]) [000014] ------------ \--* CNS_INT int 0 ------------ BB04 [019..01D) -> BB06 (cond), preds={} succs={BB05,BB06} ***** BB04 STMT00035 (IL 0x019...0x01B) [000169] ------------ * JTRUE void [000168] ------------ \--* EQ int [000166] ------------ +--* LCL_VAR ref V04 arg4 [000167] ------------ \--* CNS_INT ref null ------------ BB05 [01D..03E), preds={} succs={BB06} ***** BB05 STMT00037 (IL 0x01D...0x02E) [000179] -ACXG------- * ASG ref [000178] D------N---- +--* LCL_VAR ref V16 tmp5 [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000176] ------------ arg0 \--* CNS_INT long 1 ***** BB05 STMT00038 (IL ???... ???) [000185] -A-XG------- * ASG ref [000184] ---XG--N---- +--* INDEX ref [000181] ------------ | +--* LCL_VAR ref V16 tmp5 [000182] ------------ | \--* CNS_INT int 0 [000183] ------------ \--* LCL_VAR ref V03 arg3 ***** BB05 STMT00039 (IL ???...0x039) [000186] I-C-G------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.ErrorFactory.ErrorInfo (exactContextHnd=0x00000000D1FFAB1E) [000175] ------------ arg0 +--* CNS_INT int 0x7AA4 [000180] ------------ arg1 \--* LCL_VAR ref V16 tmp5 ***** BB05 STMT00040 (IL ???... ???) [000190] I-C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor (exactContextHnd=0x00000000D1FFAB1E) [000189] ------------ this in rdi +--* ADDR byref [000188] -------N---- | \--* LCL_VAR struct V17 tmp6 [000174] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000187] --C--------- arg2 \--* RET_EXPR ref (inl return from call [000186]) ***** BB05 STMT00041 (IL 0x039... ???) [000192] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000194] n----------- arg1 \--* OBJ struct [000193] ------------ \--* ADDR byref [000191] -------N---- \--* LCL_VAR struct V17 tmp6 ------------ BB06 [03E..040), preds={} succs={BB07} ***** BB06 STMT00036 (IL 0x03E...0x03F) [000172] -A---------- * ASG int [000171] D------N---- +--* LCL_VAR int V07 loc1 [000170] ------------ \--* CNS_INT int 0 ------------ BB07 [040..048) -> BB10 (cond), preds={} succs={BB08,BB10} ***** BB07 STMT00005 (IL 0x040...0x046) [000022] --C-G------- * JTRUE void [000021] --C-G------- \--* EQ int [000019] --C-G------- +--* CAST int <- bool <- int [000018] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000020] ------------ \--* CNS_INT int 0 ------------ BB08 [048..053) -> BB10 (cond), preds={} succs={BB09,BB10} ***** BB08 STMT00033 (IL 0x048...0x051) [000162] --C-G------- * JTRUE void [000161] --C-G------- \--* NE int [000159] --C-G------- +--* CAST int <- bool <- int [000158] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] ------------ arg0 | +--* LCL_VAR ref V02 arg2 [000156] ------------ arg1 | +--* LCL_VAR ref V03 arg3 [000157] ------------ arg2 | \--* LCL_VAR ref V04 arg4 [000160] ------------ \--* CNS_INT int 0 ------------ BB09 [053..055), preds={} succs={BB10} ***** BB09 STMT00034 (IL 0x053...0x054) [000165] -A---------- * ASG int [000164] D------N---- +--* LCL_VAR int V07 loc1 [000163] ------------ \--* CNS_INT int 0 ------------ BB10 [055..05D) -> BB13 (cond), preds={} succs={BB11,BB13} ***** BB10 STMT00006 (IL 0x055...0x05B) [000028] --C-G------- * JTRUE void [000027] --C-G------- \--* EQ int [000025] --C-G------- +--* CAST int <- bool <- int [000024] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000026] ------------ \--* CNS_INT int 0 ------------ BB11 [05D..068) -> BB13 (cond), preds={} succs={BB12,BB13} ***** BB11 STMT00030 (IL 0x05D...0x066) [000146] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint (exactContextHnd=0x00000000D1FFAB1E) [000143] ------------ arg0 +--* LCL_VAR ref V02 arg2 [000144] ------------ arg1 +--* LCL_VAR ref V03 arg3 [000145] ------------ arg2 \--* LCL_VAR ref V04 arg4 ***** BB11 STMT00031 (IL ???... ???) [000151] --C--------- * JTRUE void [000150] --C--------- \--* NE int [000148] --C--------- +--* CAST int <- bool <- int [000147] --C--------- | \--* RET_EXPR int (inl return from call [000146]) [000149] ------------ \--* CNS_INT int 0 ------------ BB12 [068..06A), preds={} succs={BB13} ***** BB12 STMT00032 (IL 0x068...0x069) [000154] -A---------- * ASG int [000153] D------N---- +--* LCL_VAR int V07 loc1 [000152] ------------ \--* CNS_INT int 0 ------------ BB13 [06A..072) -> BB16 (cond), preds={} succs={BB14,BB16} ***** BB13 STMT00007 (IL 0x06A...0x070) [000034] --C-G------- * JTRUE void [000033] --C-G------- \--* EQ int [000031] --C-G------- +--* CAST int <- bool <- int [000030] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000032] ------------ \--* CNS_INT int 0 ------------ BB14 [072..080) -> BB16 (cond), preds={} succs={BB15,BB16} ***** BB14 STMT00028 (IL 0x072...0x07E) [000139] --C-G------- * JTRUE void [000138] --C-G------- \--* NE int [000136] --C-G------- +--* CAST int <- bool <- int [000135] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000131] ------------ arg1 | +--* LCL_VAR ref V02 arg2 [000132] ------------ arg2 | +--* LCL_VAR ref V03 arg3 [000133] ------------ arg3 | +--* LCL_VAR ref V04 arg4 [000134] ------------ arg4 | \--* LCL_VAR byref V05 arg5 [000137] ------------ \--* CNS_INT int 0 ------------ BB15 [080..082), preds={} succs={BB16} ***** BB15 STMT00029 (IL 0x080...0x081) [000142] -A---------- * ASG int [000141] D------N---- +--* LCL_VAR int V07 loc1 [000140] ------------ \--* CNS_INT int 0 ------------ BB16 [082..095) -> BB21 (always), preds={} succs={BB21} ***** BB16 STMT00008 (IL 0x082...0x08A) [000037] I-C-G------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics (exactContextHnd=0x00000000D1FFAB1E) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] ------------ arg1 \--* LCL_VAR byref V05 arg5 ***** BB16 STMT00009 (IL ???... ???) [000042] -AC--------- * ASG ref [000041] ------------ +--* IND ref [000040] ------------ | \--* ADDR byref [000039] -------N---- | \--* LCL_VAR struct V09 loc3 [000038] --C--------- \--* RET_EXPR ref (inl return from call [000037]) ***** BB16 STMT00010 (IL 0x08B...0x092) [000050] -AC-G------- * ASG struct (copy) [000048] D------N---- +--* LCL_VAR struct V12 tmp1 [000045] --C-G------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA [000044] ------------ this in rdi +--* ADDR byref [000043] -------N---- | \--* LCL_VAR struct V09 loc3 [000047] n----------- arg1 \--* IND long [000046] ------------ \--* CNS_INT(h) long 0xd1ffab1e class ***** BB16 STMT00011 (IL ???... ???) [000054] -A---------- * ASG struct (copy) [000052] D------N---- +--* LCL_VAR struct V08 loc2 [000051] -------N---- \--* LCL_VAR struct V12 tmp1 ------------ BB17 [095..0B5) -> BB21 (cond), preds={} succs={BB18,BB21} ***** BB17 STMT00013 (IL 0x095...0x0A7) [000073] -AC-G------- * ASG struct (copy) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 [000070] --C-G------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000066] --C-G------- this in rdi +--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current [000065] ------------ this in rdi | +--* ADDR byref [000064] -------N---- | | \--* LCL_VAR struct V08 loc2 [000068] n----------- arg1 | \--* IND long [000067] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000069] ------------ arg1 \--* LCL_VAR ref V01 arg1 ***** BB17 STMT00014 (IL ???... ???) [000078] -A---------- * ASG ref [000077] D------N---- +--* LCL_VAR ref V10 loc4 [000076] ------------ \--* FIELD ref Type [000075] ------------ \--* ADDR byref [000074] -------N---- \--* LCL_VAR struct V13 tmp2 ***** BB17 STMT00015 (IL 0x0A9...0x0B3) [000082] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesTypeConstraint (exactContextHnd=0x00000000D1FFAB1E) [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000080] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 ***** BB17 STMT00016 (IL ???... ???) [000087] --C--------- * JTRUE void [000086] --C--------- \--* NE int [000084] --C--------- +--* CAST int <- bool <- int [000083] --C--------- | \--* RET_EXPR int (inl return from call [000082]) [000085] ------------ \--* CNS_INT int 0 ------------ BB18 [0B5..0B9) -> BB20 (cond), preds={} succs={BB19,BB20} ***** BB18 STMT00017 (IL 0x0B5...0x0B7) [000091] ------------ * JTRUE void [000090] ------------ \--* EQ int [000088] ------------ +--* LCL_VAR ref V04 arg4 [000089] ------------ \--* CNS_INT ref null ------------ BB19 [0B9..0DF), preds={} succs={BB20} ***** BB19 STMT00019 (IL 0x0B9...0x0CA) [000101] -ACXG------- * ASG ref [000100] D------N---- +--* LCL_VAR ref V14 tmp3 [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000098] ------------ arg0 \--* CNS_INT long 2 ***** BB19 STMT00020 (IL ???... ???) [000107] -A-XG------- * ASG ref [000106] ---XG--N---- +--* INDEX ref [000103] ------------ | +--* LCL_VAR ref V14 tmp3 [000104] ------------ | \--* CNS_INT int 0 [000105] ------------ \--* LCL_VAR ref V03 arg3 ***** BB19 STMT00021 (IL ???...0x0CF) [000112] -A-XG------- * ASG ref [000111] ---XG--N---- +--* INDEX ref [000108] ------------ | +--* LCL_VAR ref V14 tmp3 [000109] ------------ | \--* CNS_INT int 1 [000110] ------------ \--* LCL_VAR ref V10 loc4 ***** BB19 STMT00022 (IL ???...0x0DA) [000113] I-C-G------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.ErrorFactory.ErrorInfo (exactContextHnd=0x00000000D1FFAB1E) [000097] ------------ arg0 +--* CNS_INT int 0x7D2C [000102] ------------ arg1 \--* LCL_VAR ref V14 tmp3 ***** BB19 STMT00023 (IL ???... ???) [000117] IA---------- * ASG struct (init) [000115] D------N---- +--* LCL_VAR struct V15 tmp4 [000116] ------------ \--* CNS_INT int 0 ***** BB19 STMT00024 (IL ???... ???) [000120] I-C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor (exactContextHnd=0x00000000D1FFAB1E) [000119] ------------ this in rdi +--* ADDR byref [000118] -------N---- | \--* LCL_VAR struct V15 tmp4 [000096] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000114] --C--------- arg2 \--* RET_EXPR ref (inl return from call [000113]) ***** BB19 STMT00025 (IL 0x0DA... ???) [000122] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000124] n----------- arg1 \--* OBJ struct [000123] ------------ \--* ADDR byref [000121] -------N---- \--* LCL_VAR struct V15 tmp4 ------------ BB20 [0DF..0E1), preds={} succs={BB21} ***** BB20 STMT00018 (IL 0x0DF...0x0E0) [000094] -A---------- * ASG int [000093] D------N---- +--* LCL_VAR int V07 loc1 [000092] ------------ \--* CNS_INT int 0 ------------ BB21 [0E1..0EA) -> BB17 (cond), preds={} succs={BB22,BB17} ***** BB21 STMT00012 (IL 0x0E1...0x0E8) [000063] --C-G------- * JTRUE void [000062] --C-G------- \--* NE int [000060] --C-G------- +--* CAST int <- bool <- int [000057] --C-G------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext [000056] ------------ this in rdi | +--* ADDR byref [000055] -------N---- | | \--* LCL_VAR struct V08 loc2 [000059] n----------- arg1 | \--* IND long [000058] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000061] ------------ \--* CNS_INT int 0 ------------ BB22 [0EA..0EC), preds={} succs={BB23} ***** BB22 STMT00026 (IL 0x0EA...0x0EB) [000127] -A---------- * ASG int [000126] D------N---- +--* LCL_VAR int V06 loc0 [000125] ------------ \--* LCL_VAR int V07 loc1 ------------ BB23 [0EC..0EE) (return), preds={} succs={} ***** BB23 STMT00027 (IL 0x0EC...0x0ED) [000129] ------------ * RETURN int [000128] ------------ \--* LCL_VAR int V06 loc0 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 24, bitset array size: 1 (short) *************** In fgRemoveEmptyBlocks *************** Finishing PHASE Morph - Init *************** In fgDebugCheckBBlist *************** Starting PHASE Morph - Inlining Expanding INLINE_CANDIDATE in statement STMT00000 in BB01: STMT00000 (IL 0x000...0x006) [000001] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.IsErrorType (exactContextHnd=0x00000000D1FFAB1E) [000000] ------------ arg0 \--* LCL_VAR ref V03 arg3 Argument #0: is a local var [000000] ------------ * LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool : IL to import: IL_0000 02 ldarg.0 IL_0001 6f 00 2a 00 06 callvirt 0x6002A00 IL_0006 1a ldc.i4.4 IL_0007 fe 01 ceq IL_0009 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool Jump targets: none New Basic Block BB24 [0023] created. BB24 [000..00A) Basic block list for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB24 [0023] 1 1 [000..00A) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000001] Starting PHASE Pre-import *************** Inline @[000001] Finishing PHASE Pre-import *************** Inline @[000001] Starting PHASE Importation *************** In impImport() for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool impImportBlockPending for BB24 Importing BB24 (PC=000) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) callvirt 06002A00 In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is int, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol (attrib 21000400) base method is Microsoft.CodeAnalysis.VisualBasic.Symbol::get_Kind devirt to Microsoft.CodeAnalysis.VisualBasic.Symbol::get_Kind -- inexact or not final [000198] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi \--* LCL_VAR ref V03 arg3 Class not final or exact, and method not final NOT Marking call [000198] as guarded devirtualization candidate -- disabled by jit config INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbol:get_Kind():int:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 1] 6 (0x006) ldc.i4.4 4 [ 2] 7 (0x007) ceq [ 1] 9 (0x009) ret Inlinee Return expression (before normalization) => [000200] --C-G------- * EQ int [000198] --C-G------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi | \--* LCL_VAR ref V03 arg3 [000199] ------------ \--* CNS_INT int 4 Inlinee Return expression (after normalization) => [000200] --C-G------- * EQ int [000198] --C-G------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi | \--* LCL_VAR ref V03 arg3 [000199] ------------ \--* CNS_INT int 4 ** Note: inlinee IL was partially imported -- imported 0 of 10 bytes of method IL *************** Inline @[000001] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB24 [0023] 1 1 [000..00A) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB24 [000..00A) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000001] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000001] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000001] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000001] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000001] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000001] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000001] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000001] is [000200] --C-G------- * EQ int [000198] --C-G------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi | \--* LCL_VAR ref V03 arg3 [000199] ------------ \--* CNS_INT int 4 Successfully inlined Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool (10 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000002] with [000200] [000002] --C--------- * RET_EXPR int (inl return from call [000200]) Inserting the inline return expression [000200] --C-G------- * EQ int [000198] --C-G------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi | \--* LCL_VAR ref V03 arg3 [000199] ------------ \--* CNS_INT int 4 **** Late devirt opportunity [000198] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi \--* LCL_VAR ref V03 arg3 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol (attrib 21000400) base method is Microsoft.CodeAnalysis.VisualBasic.Symbol::get_Kind devirt to Microsoft.CodeAnalysis.VisualBasic.Symbol::get_Kind -- inexact or not final [000198] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi \--* LCL_VAR ref V03 arg3 Class not final or exact, and method not final No guarded devirt during late devirtualization Expanding INLINE_CANDIDATE in statement STMT00003 in BB03: STMT00003 (IL 0x011...0x017) [000011] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.IsRestrictedType (exactContextHnd=0x00000000D1FFAB1E) [000010] ------------ arg0 \--* LCL_VAR ref V03 arg3 Argument #0: is a local var [000010] ------------ * LCL_VAR ref V03 arg3 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsRestrictedType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsRestrictedType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool : IL to import: IL_0000 02 ldarg.0 IL_0001 6f 97 23 00 06 callvirt 0x6002397 IL_0006 28 17 20 00 06 call 0x6002017 IL_000b 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsRestrictedType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsRestrictedType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool Jump targets: none New Basic Block BB25 [0024] created. BB25 [000..00C) Basic block list for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsRestrictedType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB25 [0024] 1 1 [000..00C) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000011] Starting PHASE Pre-import *************** Inline @[000011] Finishing PHASE Pre-import *************** Inline @[000011] Starting PHASE Importation *************** In impImport() for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsRestrictedType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool impImportBlockPending for BB25 Importing BB25 (PC=000) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsRestrictedType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) callvirt 06002397 In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is byte, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol (attrib 21000400) base method is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol::get_SpecialType devirt to Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol::get_SpecialType -- inexact or not final [000202] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi \--* LCL_VAR ref V03 arg3 Class not final or exact, and method not final NOT Marking call [000202] as guarded devirtualization candidate -- disabled by jit config INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsRestrictedType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol:get_SpecialType():byte:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 1] 6 (0x006) call 06002017 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsRestrictedType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions:IsRestrictedType(byte):bool' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000205] --C-G------- * CAST int <- bool <- int [000204] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --C-G------- arg0 \--* CAST int <- byte <- int [000202] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi \--* LCL_VAR ref V03 arg3 Inlinee Return expression (after normalization) => [000205] --C-G------- * CAST int <- bool <- int [000204] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --C-G------- arg0 \--* CAST int <- byte <- int [000202] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi \--* LCL_VAR ref V03 arg3 ** Note: inlinee IL was partially imported -- imported 0 of 12 bytes of method IL *************** Inline @[000011] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB25 [0024] 1 1 [000..00C) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB25 [000..00C) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000011] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000011] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000011] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000011] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000011] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000011] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000011] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000011] is [000205] --C-G------- * CAST int <- bool <- int [000204] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --C-G------- arg0 \--* CAST int <- byte <- int [000202] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi \--* LCL_VAR ref V03 arg3 Successfully inlined Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsRestrictedType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool (12 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsRestrictedType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000012] with [000205] [000012] --C--------- * RET_EXPR int (inl return from call [000205]) Inserting the inline return expression [000205] --C-G------- * CAST int <- bool <- int [000204] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --C-G------- arg0 \--* CAST int <- byte <- int [000202] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi \--* LCL_VAR ref V03 arg3 **** Late devirt opportunity [000202] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi \--* LCL_VAR ref V03 arg3 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol (attrib 21000400) base method is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol::get_SpecialType devirt to Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol::get_SpecialType -- inexact or not final [000202] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi \--* LCL_VAR ref V03 arg3 Class not final or exact, and method not final No guarded devirt during late devirtualization Expanding INLINE_CANDIDATE in statement STMT00039 in BB05: STMT00039 (IL ???...0x039) [000186] I-C-G------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.ErrorFactory.ErrorInfo (exactContextHnd=0x00000000D1FFAB1E) [000175] ------------ arg0 +--* CNS_INT int 0x7AA4 [000180] ------------ arg1 \--* LCL_VAR ref V16 tmp5 Argument #0: is a constant [000175] ------------ * CNS_INT int 0x7AA4 Argument #1: is a local var [000180] ------------ * LCL_VAR ref V16 tmp5 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo : IL to import: IL_0000 7e b6 0e 00 04 ldsfld 0x4000EB6 IL_0005 02 ldarg.0 IL_0006 03 ldarg.1 IL_0007 73 af 09 00 0a newobj 0xA0009AF IL_000c 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo Jump targets: none New Basic Block BB26 [0025] created. BB26 [000..00D) Basic block list for 'Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB26 [0025] 1 1 [000..00D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000186] Starting PHASE Pre-import *************** Inline @[000186] Finishing PHASE Pre-import *************** Inline @[000186] Starting PHASE Importation *************** In impImport() for Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo impImportBlockPending for BB26 Importing BB26 (PC=000) of 'Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo' [ 0] 0 (0x000) ldsfld 04000EB6 [ 1] 5 (0x005) ldarg.0 [ 2] 6 (0x006) ldarg.1 [ 3] 7 (0x007) newobj lvaGrabTemp returning 18 (V18 tmp7) called for NewObj constructor temp. [000216] -A---------- * ASG ref [000215] D------N---- +--* LCL_VAR ref V18 tmp7 [000214] ------------ \--* ALLOCOBJ ref [000213] n----------- \--* IND long [000212] ------------ \--* CNS_INT(h) long 0xd1ffab1e token Marked V18 as a single def local lvaSetClass: setting class for V18 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.DiagnosticInfo [exact] 0A0009AF In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 [000210] --CXG------- arg1 +--* IND ref [000209] --CXG------- | \--* ADD byref [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000211] ------------ arg2 +--* CNS_INT int 0x7AA4 [000180] ------------ arg3 \--* LCL_VAR ref V16 tmp5 [ 1] 12 (0x00c) ret Inlinee Return expression (before normalization) => [000219] ------------ * LCL_VAR ref V18 tmp7 Inlinee Return expression (after normalization) => [000219] ------------ * LCL_VAR ref V18 tmp7 *************** Inline @[000186] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB26 [0025] 1 1 [000..00D) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB26 [000..00D) (return), preds={} succs={} ***** BB26 [000216] -A---------- * ASG ref [000215] D------N---- +--* LCL_VAR ref V18 tmp7 [000214] ------------ \--* ALLOCOBJ ref [000213] n----------- \--* IND long [000212] ------------ \--* CNS_INT(h) long 0xd1ffab1e token ***** BB26 [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 [000210] --CXG------- arg1 +--* IND ref [000209] --CXG------- | \--* ADD byref [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000211] ------------ arg2 +--* CNS_INT int 0x7AA4 [000180] ------------ arg3 \--* LCL_VAR ref V16 tmp5 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000186] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000186] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000186] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000186] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000186] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000186] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000186] ----------- Arguments setup: Inlinee method body: STMT00043 (IL ???... ???) [000216] -A---------- * ASG ref [000215] D------N---- +--* LCL_VAR ref V18 tmp7 [000214] ------------ \--* ALLOCOBJ ref [000213] n----------- \--* IND long [000212] ------------ \--* CNS_INT(h) long 0xd1ffab1e token STMT00044 (IL ???... ???) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 [000210] --CXG------- arg1 +--* IND ref [000209] --CXG------- | \--* ADD byref [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000211] ------------ arg2 +--* CNS_INT int 0x7AA4 [000180] ------------ arg3 \--* LCL_VAR ref V16 tmp5 fgInlineAppendStatements: no gc ref inline locals. INLINER: Updating optMethodFlags -- root:5 callee:2 new:7 Return expression for call at [000186] is [000219] ------------ * LCL_VAR ref V18 tmp7 Successfully inlined Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo (13 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00040 in BB05: STMT00040 (IL ???... ???) [000190] I-C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor (exactContextHnd=0x00000000D1FFAB1E) [000189] ------------ this in rdi +--* ADDR byref [000188] -------N---- | \--* LCL_VAR struct V17 tmp6 [000174] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000187] --C--------- arg2 \--* RET_EXPR ref (inl return from call [000219]) thisArg: is a constant is byref to a struct local [000189] ------------ * ADDR byref [000188] -------N---- \--* LCL_VAR struct V17 tmp6 Argument #1: is a local var [000174] ------------ * LCL_VAR ref V02 arg2 Argument #2: is a local var [000219] ------------ * LCL_VAR ref V18 tmp7 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this : IL to import: IL_0000 02 ldarg.0 IL_0001 fe 15 71 01 00 02 initobj 0x2000171 IL_0007 02 ldarg.0 IL_0008 03 ldarg.1 IL_0009 7d 19 05 00 04 stfld 0x4000519 IL_000e 02 ldarg.0 IL_000f 04 ldarg.2 IL_0010 7d 1b 05 00 04 stfld 0x400051B IL_0015 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this weight= 10 : state 3 [ ldarg.0 ] weight= 55 : state 180 [ initobj ] weight= 69 : state 226 [ ldarg.0 -> ldarg.1 -> stfld ] weight= 98 : state 228 [ ldarg.0 -> ldarg.2 -> stfld ] weight= 19 : state 42 [ ret ] multiplier in instance constructors increased to 1.5. Inline candidate is mostly loads and stores. Multiplier increased to 4.5. Inline candidate callsite is rare. Multiplier limited to 1.3. calleeNativeSizeEstimate=251 callsiteNativeSizeEstimate=145 benefit multiplier=1.3 threshold=188 Native estimate for function size exceeds threshold for inlining 25.1 > 18.8 (multiplier = 1.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000187] with [000219] [000187] --C--------- * RET_EXPR ref (inl return from call [000219]) Inserting the inline return expression [000219] ------------ * LCL_VAR ref V18 tmp7 **** Late devirt opportunity [000192] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000194] n----------- arg1 \--* OBJ struct [000193] ------------ \--* ADDR byref [000191] -------N---- \--* LCL_VAR struct V17 tmp6 impDevirtualizeCall: [R2R] base method not virtual, sorry **** Late devirt opportunity [000018] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] ------------ this in rdi \--* LCL_VAR ref V02 arg2 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol (attrib 21000400) base method is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol::get_HasConstructorConstraint devirt to Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol::get_HasConstructorConstraint -- inexact or not final [000018] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] ------------ this in rdi \--* LCL_VAR ref V02 arg2 Class not final or exact, and method not final No guarded devirt during late devirtualization **** Late devirt opportunity [000024] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] ------------ this in rdi \--* LCL_VAR ref V02 arg2 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol (attrib 21000400) base method is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol::get_HasReferenceTypeConstraint devirt to Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol::get_HasReferenceTypeConstraint -- inexact or not final [000024] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] ------------ this in rdi \--* LCL_VAR ref V02 arg2 Class not final or exact, and method not final No guarded devirt during late devirtualization Expanding INLINE_CANDIDATE in statement STMT00030 in BB11: STMT00030 (IL 0x05D...0x066) [000146] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint (exactContextHnd=0x00000000D1FFAB1E) [000143] ------------ arg0 +--* LCL_VAR ref V02 arg2 [000144] ------------ arg1 +--* LCL_VAR ref V03 arg3 [000145] ------------ arg2 \--* LCL_VAR ref V04 arg4 Argument #0: is a local var [000143] ------------ * LCL_VAR ref V02 arg2 Argument #1: is a local var [000144] ------------ * LCL_VAR ref V03 arg3 Argument #2: is a local var [000145] ------------ * LCL_VAR ref V04 arg4 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesReferenceTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesReferenceTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool : IL to import: IL_0000 03 ldarg.1 IL_0001 6f 91 23 00 06 callvirt 0x6002391 IL_0006 2d 2b brtrue.s 43 (IL_0033) IL_0008 04 ldarg.2 IL_0009 2c 24 brfalse.s 36 (IL_002f) IL_000b 04 ldarg.2 IL_000c 02 ldarg.0 IL_000d 20 6a 7d 00 00 ldc.i4 0x7D6A IL_0012 18 ldc.i4.2 IL_0013 8d 0e 00 00 01 newarr 0x100000E IL_0018 25 dup IL_0019 16 ldc.i4.0 IL_001a 03 ldarg.1 IL_001b a2 stelem.ref IL_001c 25 dup IL_001d 17 ldc.i4.1 IL_001e 02 ldarg.0 IL_001f a2 stelem.ref IL_0020 28 92 2a 00 06 call 0x6002A92 IL_0025 73 0b 17 00 06 newobj 0x600170B IL_002a 6f 44 0b 00 0a callvirt 0xA000B44 IL_002f 16 ldc.i4.0 IL_0030 0a stloc.0 IL_0031 2b 02 br.s 2 (IL_0035) IL_0033 17 ldc.i4.1 IL_0034 0a stloc.0 IL_0035 06 ldloc.0 IL_0036 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesReferenceTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesReferenceTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight= 25 : state 45 [ brtrue.s ] weight= 35 : state 5 [ ldarg.2 ] weight= 27 : state 44 [ brfalse.s ] weight= 35 : state 5 [ ldarg.2 ] weight= 10 : state 3 [ ldarg.0 ] weight= 38 : state 33 [ ldc.i4 ] weight= 34 : state 25 [ ldc.i4.2 ] weight=152 : state 118 [ newarr ] weight= 11 : state 38 [ dup ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 94 : state 139 [ stelem.ref ] weight= 11 : state 38 [ dup ] weight= 28 : state 24 [ ldc.i4.1 ] weight= 10 : state 3 [ ldarg.0 ] weight= 94 : state 139 [ stelem.ref ] weight= 79 : state 40 [ call ] weight=227 : state 103 [ newobj ] weight= 83 : state 99 [ callvirt ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 6 : state 11 [ stloc.0 ] weight= 44 : state 43 [ br.s ] weight= 28 : state 24 [ ldc.i4.1 ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 19 : state 42 [ ret ] Inline candidate has an arg that feeds a constant test. Multiplier increased to 1. Inline candidate callsite is warm. Multiplier increased to 3. calleeNativeSizeEstimate=1255 callsiteNativeSizeEstimate=145 benefit multiplier=3 threshold=435 Native estimate for function size exceeds threshold for inlining 125.5 > 43.5 (multiplier = 3) Inline expansion aborted, inline not profitable Inlining [000146] failed, so bashing STMT00030 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesReferenceTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000147] with [000146] [000147] --C--------- * RET_EXPR int (inl return from call [000146]) Inserting the inline return expression [000146] --C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] ------------ arg0 +--* LCL_VAR ref V02 arg2 [000144] ------------ arg1 +--* LCL_VAR ref V03 arg3 [000145] ------------ arg2 \--* LCL_VAR ref V04 arg4 **** Late devirt opportunity [000030] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] ------------ this in rdi \--* LCL_VAR ref V02 arg2 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol (attrib 21000400) base method is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol::get_HasValueTypeConstraint devirt to Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol::get_HasValueTypeConstraint -- inexact or not final [000030] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] ------------ this in rdi \--* LCL_VAR ref V02 arg2 Class not final or exact, and method not final No guarded devirt during late devirtualization Expanding INLINE_CANDIDATE in statement STMT00008 in BB16: STMT00008 (IL 0x082...0x08A) [000037] I-C-G------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics (exactContextHnd=0x00000000D1FFAB1E) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] ------------ arg1 \--* LCL_VAR byref V05 arg5 **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 1 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 thisArg: is a local var [000035] ------------ * LCL_VAR ref V02 arg2 Argument #1: is a local var [000036] ------------ * LCL_VAR byref V05 arg5 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:ConstraintTypesWithDefinitionUseSiteDiagnostics(byref):System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:ConstraintTypesWithDefinitionUseSiteDiagnostics(byref):System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]:this : IL to import: IL_0000 02 ldarg.0 IL_0001 6f c9 12 00 06 callvirt 0x60012C9 IL_0006 0a stloc.0 IL_0007 02 ldarg.0 IL_0008 03 ldarg.1 IL_0009 28 e4 23 00 06 call 0x60023E4 IL_000e 12 00 ldloca.s 0x0 IL_0010 28 88 06 00 0a call 0xA000688 IL_0015 0b stloc.1 IL_0016 2b 12 br.s 18 (IL_002a) IL_0018 12 01 ldloca.s 0x1 IL_001a 28 89 06 00 0a call 0xA000689 IL_001f 6f 81 23 00 06 callvirt 0x6002381 IL_0024 03 ldarg.1 IL_0025 28 e2 23 00 06 call 0x60023E2 IL_002a 12 01 ldloca.s 0x1 IL_002c 28 8a 06 00 0a call 0xA00068A IL_0031 2d e5 brtrue.s -27 (IL_0018) IL_0033 06 ldloc.0 IL_0034 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:ConstraintTypesWithDefinitionUseSiteDiagnostics(byref):System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]:this is 0x00000000D1FFAB1E. **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 1 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 1 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:ConstraintTypesWithDefinitionUseSiteDiagnostics(byref):System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]:this weight= 10 : state 3 [ ldarg.0 ] weight= 83 : state 99 [ callvirt ] weight= 6 : state 11 [ stloc.0 ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 79 : state 40 [ call ] weight= 61 : state 19 [ ldloca.s ] weight= 79 : state 40 [ call ] weight= 34 : state 12 [ stloc.1 ] weight= 44 : state 43 [ br.s ] weight= 61 : state 19 [ ldloca.s ] weight= 79 : state 40 [ call ] weight= 83 : state 99 [ callvirt ] weight= 16 : state 4 [ ldarg.1 ] weight= 79 : state 40 [ call ] weight= 61 : state 19 [ ldloca.s ] weight= 79 : state 40 [ call ] weight= 25 : state 45 [ brtrue.s ] weight= 12 : state 7 [ ldloc.0 ] weight= 19 : state 42 [ ret ] Inline candidate has an arg that feeds a constant test. Multiplier increased to 1. Inline candidate callsite is warm. Multiplier increased to 3. calleeNativeSizeEstimate=936 callsiteNativeSizeEstimate=115 benefit multiplier=3 threshold=345 Native estimate for function size exceeds threshold for inlining 93.6 > 34.5 (multiplier = 3) Inline expansion aborted, inline not profitable Inlining [000037] failed, so bashing STMT00008 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:ConstraintTypesWithDefinitionUseSiteDiagnostics(byref):System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]:this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000038] with [000037] [000038] --C--------- * RET_EXPR ref (inl return from call [000037]) Inserting the inline return expression [000037] --C-G------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] ------------ arg1 \--* LCL_VAR byref V05 arg5 **** Late devirt opportunity [000070] --C-G------- * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000066] --C-G------- this in rdi +--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current [000065] ------------ this in rdi | +--* ADDR byref [000064] -------N---- | | \--* LCL_VAR struct V08 loc2 [000068] n----------- arg1 | \--* IND long [000067] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000069] ------------ arg1 \--* LCL_VAR ref V01 arg1 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is System.__Canon (attrib 00020000) base method is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol::InternalSubstituteTypeParameters --- no derived method, sorry Querying runtime about current class of field Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeWithModifiers.Type (declared as Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00015 in BB17: STMT00015 (IL 0x0A9...0x0B3) [000082] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesTypeConstraint (exactContextHnd=0x00000000D1FFAB1E) [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000080] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 Argument #0: is a local var [000079] ------------ * LCL_VAR ref V03 arg3 Argument #1: is a local var [000080] ------------ * LCL_VAR ref V10 loc4 Argument #2: is a local var [000081] ------------ * LCL_VAR byref V05 arg5 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool : IL to import: IL_0000 03 ldarg.1 IL_0001 28 bb 23 00 06 call 0x60023BB IL_0006 2c 0b brfalse.s 11 (IL_0013) IL_0008 03 ldarg.1 IL_0009 04 ldarg.2 IL_000a 28 e2 23 00 06 call 0x60023E2 IL_000f 16 ldc.i4.0 IL_0010 0a stloc.0 IL_0011 2b 09 br.s 9 (IL_001c) IL_0013 02 ldarg.0 IL_0014 03 ldarg.1 IL_0015 04 ldarg.2 IL_0016 28 58 59 00 06 call 0x6005958 IL_001b 0a stloc.0 IL_001c 06 ldloc.0 IL_001d 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool weight= 16 : state 4 [ ldarg.1 ] weight= 79 : state 40 [ call ] weight= 27 : state 44 [ brfalse.s ] weight= 16 : state 4 [ ldarg.1 ] weight= 35 : state 5 [ ldarg.2 ] weight= 79 : state 40 [ call ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 6 : state 11 [ stloc.0 ] weight= 44 : state 43 [ br.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 35 : state 5 [ ldarg.2 ] weight= 79 : state 40 [ call ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 19 : state 42 [ ret ] Inline candidate has an arg that feeds a constant test. Multiplier increased to 1. Inline candidate callsite is in a loop. Multiplier increased to 4. calleeNativeSizeEstimate=496 callsiteNativeSizeEstimate=145 benefit multiplier=4 threshold=580 Native estimate for function size is within threshold for inlining 49.6 <= 58 (multiplier = 4) Jump targets: IL_0013 IL_001c New Basic Block BB27 [0026] created. BB27 [000..008) New Basic Block BB28 [0027] created. BB28 [008..013) New Basic Block BB29 [0028] created. BB29 [013..01C) New Basic Block BB30 [0029] created. BB30 [01C..01E) Basic block list for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB27 [0026] 1 1 [000..008)-> BB29 ( cond ) BB28 [0027] 1 1 [008..013)-> BB30 (always) BB29 [0028] 1 1 [013..01C) BB30 [0029] 2 1 [01C..01E) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000082] Starting PHASE Pre-import *************** Inline @[000082] Finishing PHASE Pre-import *************** Inline @[000082] Starting PHASE Importation *************** In impImport() for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool impImportBlockPending for BB27 Importing BB27 (PC=000) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool' [ 0] 0 (0x000) ldarg.1 [ 1] 1 (0x001) call 060023BB In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 [000223] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.IsErrorType (exactContextHnd=0x00000000D1FFAB1E) [000080] ------------ arg0 \--* LCL_VAR ref V10 loc4 [ 1] 6 (0x006) brfalse.s [000228] --C--------- * JTRUE void [000227] --C--------- \--* EQ int [000225] --C--------- +--* CAST int <- bool <- int [000224] --C--------- | \--* RET_EXPR int (inl return from call [000223]) [000226] ------------ \--* CNS_INT int 0 impImportBlockPending for BB28 impImportBlockPending for BB29 Importing BB29 (PC=019) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool' [ 0] 19 (0x013) ldarg.0 [ 1] 20 (0x014) ldarg.1 [ 2] 21 (0x015) ldarg.2 [ 3] 22 (0x016) call 06005958 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 [000230] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion (exactContextHnd=0x00000000D1FFAB1E) [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000229] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 [ 1] 27 (0x01b) stloc.0 lvaGrabTemp returning 19 (V19 tmp8) (a long lifetime temp) called for Inline stloc first use temp. [000234] -AC--------- * ASG bool [000233] D------N---- +--* LCL_VAR bool V19 tmp8 [000232] --C--------- \--* CAST int <- bool <- int [000231] --C--------- \--* RET_EXPR int (inl return from call [000230]) impImportBlockPending for BB30 Importing BB30 (PC=028) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool' [ 0] 28 (0x01c) ldloc.0 [ 1] 29 (0x01d) ret Inlinee Return expression (before normalization) => [000235] ------------ * LCL_VAR int V19 tmp8 Inlinee Return expression (after normalization) => [000236] ------------ * CAST int <- bool <- int [000235] ------------ \--* LCL_VAR int V19 tmp8 Importing BB28 (PC=008) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool' [ 0] 8 (0x008) ldarg.1 [ 1] 9 (0x009) ldarg.2 [ 2] 10 (0x00a) call 060023E2 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000239] I-C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics (exactContextHnd=0x00000000D1FFAB1E) [000237] ------------ arg0 +--* LCL_VAR ref V10 loc4 [000238] ------------ arg1 \--* LCL_VAR byref V05 arg5 [ 0] 15 (0x00f) ldc.i4.0 0 [ 1] 16 (0x010) stloc.0 [000242] -A---------- * ASG bool [000241] D------N---- +--* LCL_VAR bool V19 tmp8 [000240] ------------ \--* CNS_INT int 0 [ 0] 17 (0x011) br.s impImportBlockPending for BB30 ** Note: inlinee IL was partially imported -- imported 28 of 30 bytes of method IL *************** Inline @[000082] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB27 [0026] 1 1 [000..008)-> BB29 ( cond ) i BB28 [0027] 1 1 [008..013)-> BB30 (always) i BB29 [0028] 1 1 [013..01C) i BB30 [0029] 2 1 [01C..01E) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB27 [000..008) -> BB29 (cond), preds={} succs={BB28,BB29} ***** BB27 [000223] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.IsErrorType (exactContextHnd=0x00000000D1FFAB1E) [000080] ------------ arg0 \--* LCL_VAR ref V10 loc4 ***** BB27 [000228] --C--------- * JTRUE void [000227] --C--------- \--* EQ int [000225] --C--------- +--* CAST int <- bool <- int [000224] --C--------- | \--* RET_EXPR int (inl return from call [000223]) [000226] ------------ \--* CNS_INT int 0 ------------ BB28 [008..013) -> BB30 (always), preds={} succs={BB30} ***** BB28 [000239] I-C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics (exactContextHnd=0x00000000D1FFAB1E) [000237] ------------ arg0 +--* LCL_VAR ref V10 loc4 [000238] ------------ arg1 \--* LCL_VAR byref V05 arg5 ***** BB28 [000242] -A---------- * ASG bool [000241] D------N---- +--* LCL_VAR bool V19 tmp8 [000240] ------------ \--* CNS_INT int 0 ------------ BB29 [013..01C), preds={} succs={BB30} ***** BB29 [000230] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion (exactContextHnd=0x00000000D1FFAB1E) [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000229] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 ***** BB29 [000234] -AC--------- * ASG bool [000233] D------N---- +--* LCL_VAR bool V19 tmp8 [000232] --C--------- \--* CAST int <- bool <- int [000231] --C--------- \--* RET_EXPR int (inl return from call [000230]) ------------ BB30 [01C..01E) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000082] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000082] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000082] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000082] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000082] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000082] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000082] ----------- Arguments setup: Zero init inlinee locals: STMT00051 (IL 0x0A9... ???) [000245] -A---------- * ASG bool [000244] D------N---- +--* LCL_VAR bool V19 tmp8 [000243] ------------ \--* CNS_INT int 0 Inlinee method body:New Basic Block BB31 [0030] created. Convert bbJumpKind of BB30 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB27 [0026] 1 6120. 6120 [0A9..0AA)-> BB29 ( cond ) i bwd IBC BB28 [0027] 1 3060. [0A9..0AA)-> BB30 (always) i bwd BB29 [0028] 1 3060. [0A9..0AA) i bwd BB30 [0029] 2 6120. 6120 [0A9..0AA) i bwd IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB27 [0A9..0AA) -> BB29 (cond), preds={} succs={BB28,BB29} ***** BB27 STMT00045 (IL 0x0A9... ???) [000223] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.IsErrorType (exactContextHnd=0x00000000D1FFAB1E) [000080] ------------ arg0 \--* LCL_VAR ref V10 loc4 ***** BB27 STMT00046 (IL 0x0A9... ???) [000228] --C--------- * JTRUE void [000227] --C--------- \--* EQ int [000225] --C--------- +--* CAST int <- bool <- int [000224] --C--------- | \--* RET_EXPR int (inl return from call [000223]) [000226] ------------ \--* CNS_INT int 0 ------------ BB28 [0A9..0AA) -> BB30 (always), preds={} succs={BB30} ***** BB28 STMT00049 (IL 0x0A9... ???) [000239] I-C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics (exactContextHnd=0x00000000D1FFAB1E) [000237] ------------ arg0 +--* LCL_VAR ref V10 loc4 [000238] ------------ arg1 \--* LCL_VAR byref V05 arg5 ***** BB28 STMT00050 (IL 0x0A9... ???) [000242] -A---------- * ASG bool [000241] D------N---- +--* LCL_VAR bool V19 tmp8 [000240] ------------ \--* CNS_INT int 0 ------------ BB29 [0A9..0AA), preds={} succs={BB30} ***** BB29 STMT00047 (IL 0x0A9... ???) [000230] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion (exactContextHnd=0x00000000D1FFAB1E) [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000229] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 ***** BB29 STMT00048 (IL 0x0A9... ???) [000234] -AC--------- * ASG bool [000233] D------N---- +--* LCL_VAR bool V19 tmp8 [000232] --C--------- \--* CAST int <- bool <- int [000231] --C--------- \--* RET_EXPR int (inl return from call [000230]) ------------ BB30 [0A9..0AA), preds={} succs={BB31} ------------------------------------------------------------------------------------------------------------------- Return expression for call at [000082] is [000236] ------------ * CAST int <- bool <- int [000235] ------------ \--* LCL_VAR int V19 tmp8 Successfully inlined Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool (30 IL bytes) (depth 1) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool' INLINER: during 'fgInline' result 'success' reason 'profitable inline' Expanding INLINE_CANDIDATE in statement STMT00045 in BB27: STMT00045 (IL 0x0A9... ???) [000223] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.IsErrorType (exactContextHnd=0x00000000D1FFAB1E) [000080] ------------ arg0 \--* LCL_VAR ref V10 loc4 Argument #0: is a local var [000080] ------------ * LCL_VAR ref V10 loc4 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool : IL to import: IL_0000 02 ldarg.0 IL_0001 6f 00 2a 00 06 callvirt 0x6002A00 IL_0006 1a ldc.i4.4 IL_0007 fe 01 ceq IL_0009 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool Jump targets: none New Basic Block BB32 [0031] created. BB32 [000..00A) Basic block list for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB32 [0031] 1 1 [000..00A) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000223] Starting PHASE Pre-import *************** Inline @[000223] Finishing PHASE Pre-import *************** Inline @[000223] Starting PHASE Importation *************** In impImport() for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool impImportBlockPending for BB32 Importing BB32 (PC=000) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) callvirt 06002A00 In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is int, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol (attrib 21000400) base method is Microsoft.CodeAnalysis.VisualBasic.Symbol::get_Kind devirt to Microsoft.CodeAnalysis.VisualBasic.Symbol::get_Kind -- inexact or not final [000247] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi \--* LCL_VAR ref V10 loc4 Class not final or exact, and method not final NOT Marking call [000247] as guarded devirtualization candidate -- disabled by jit config INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbol:get_Kind():int:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 1] 6 (0x006) ldc.i4.4 4 [ 2] 7 (0x007) ceq [ 1] 9 (0x009) ret Inlinee Return expression (before normalization) => [000249] --C-G------- * EQ int [000247] --C-G------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi | \--* LCL_VAR ref V10 loc4 [000248] ------------ \--* CNS_INT int 4 Inlinee Return expression (after normalization) => [000249] --C-G------- * EQ int [000247] --C-G------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi | \--* LCL_VAR ref V10 loc4 [000248] ------------ \--* CNS_INT int 4 ** Note: inlinee IL was partially imported -- imported 0 of 10 bytes of method IL *************** Inline @[000223] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB32 [0031] 1 1 [000..00A) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB32 [000..00A) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000223] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000223] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000223] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000223] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000223] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000223] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000223] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000223] is [000249] --C-G------- * EQ int [000247] --C-G------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi | \--* LCL_VAR ref V10 loc4 [000248] ------------ \--* CNS_INT int 4 Successfully inlined Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool (10 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000224] with [000249] [000224] --C--------- * RET_EXPR int (inl return from call [000249]) Inserting the inline return expression [000249] --C-G------- * EQ int [000247] --C-G------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi | \--* LCL_VAR ref V10 loc4 [000248] ------------ \--* CNS_INT int 4 **** Late devirt opportunity [000247] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi \--* LCL_VAR ref V10 loc4 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol (attrib 21000400) base method is Microsoft.CodeAnalysis.VisualBasic.Symbol::get_Kind devirt to Microsoft.CodeAnalysis.VisualBasic.Symbol::get_Kind -- inexact or not final [000247] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi \--* LCL_VAR ref V10 loc4 Class not final or exact, and method not final No guarded devirt during late devirtualization Expanding INLINE_CANDIDATE in statement STMT00049 in BB28: STMT00049 (IL 0x0A9... ???) [000239] I-C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics (exactContextHnd=0x00000000D1FFAB1E) [000237] ------------ arg0 +--* LCL_VAR ref V10 loc4 [000238] ------------ arg1 \--* LCL_VAR byref V05 arg5 Argument #0: is a local var [000237] ------------ * LCL_VAR ref V10 loc4 Argument #1: is a local var [000238] ------------ * LCL_VAR byref V05 arg5 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:AddUseSiteDiagnostics(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:AddUseSiteDiagnostics(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref) : IL to import: IL_0000 02 ldarg.0 IL_0001 6f 3a 2a 00 06 callvirt 0x6002A3A IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 2c 14 brfalse.s 20 (IL_001e) IL_000a 03 ldarg.1 IL_000b 50 ldind.ref IL_000c 2d 07 brtrue.s 7 (IL_0015) IL_000e 03 ldarg.1 IL_000f 73 e1 0e 00 0a newobj 0xA000EE1 IL_0014 51 stind.ref IL_0015 03 ldarg.1 IL_0016 50 ldind.ref IL_0017 06 ldloc.0 IL_0018 6f e2 0e 00 0a callvirt 0xA000EE2 IL_001d 26 pop IL_001e 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:AddUseSiteDiagnostics(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:AddUseSiteDiagnostics(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref) weight= 10 : state 3 [ ldarg.0 ] weight= 83 : state 99 [ callvirt ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 27 : state 44 [ brfalse.s ] weight= 16 : state 4 [ ldarg.1 ] weight= 1 : state 68 [ ldind.ref ] weight= 25 : state 45 [ brtrue.s ] weight= 16 : state 4 [ ldarg.1 ] weight=227 : state 103 [ newobj ] weight= 60 : state 69 [ stind.ref ] weight= 16 : state 4 [ ldarg.1 ] weight= 1 : state 68 [ ldind.ref ] weight= 12 : state 7 [ ldloc.0 ] weight= 83 : state 99 [ callvirt ] weight=-24 : state 39 [ pop ] weight= 19 : state 42 [ ret ] Inline candidate has an arg that feeds a constant test. Multiplier increased to 1. Inline candidate callsite is in a loop. Multiplier increased to 4. calleeNativeSizeEstimate=592 callsiteNativeSizeEstimate=115 benefit multiplier=4 threshold=460 Native estimate for function size exceeds threshold for inlining 59.2 > 46 (multiplier = 4) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:AddUseSiteDiagnostics(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref)' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00047 in BB29: STMT00047 (IL 0x0A9... ???) [000230] I-C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion (exactContextHnd=0x00000000D1FFAB1E) [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000229] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 Argument #0: is a local var [000079] ------------ * LCL_VAR ref V03 arg3 Argument #1: is a local var [000229] ------------ * LCL_VAR ref V10 loc4 Argument #2: is a local var [000081] ------------ * LCL_VAR byref V05 arg5 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Conversions:HasWideningDirectCastConversionButNotEnumTypeConversion(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.VisualBasic.Conversions:HasWideningDirectCastConversionButNotEnumTypeConversion(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool : IL to import: IL_0000 02 ldarg.0 IL_0001 28 bb 23 00 06 call 0x60023BB IL_0006 2d 08 brtrue.s 8 (IL_0010) IL_0008 03 ldarg.1 IL_0009 28 bb 23 00 06 call 0x60023BB IL_000e 2c 0a brfalse.s 10 (IL_001a) IL_0010 02 ldarg.0 IL_0011 03 ldarg.1 IL_0012 28 c2 23 00 06 call 0x60023C2 IL_0017 0a stloc.0 IL_0018 2b 20 br.s 32 (IL_003a) IL_001a 02 ldarg.0 IL_001b 03 ldarg.1 IL_001c 04 ldarg.2 IL_001d 28 49 59 00 06 call 0x6005949 IL_0022 0b stloc.1 IL_0023 07 ldloc.1 IL_0024 28 7f 59 00 06 call 0x600597F IL_0029 2c 0d brfalse.s 13 (IL_0038) IL_002b 07 ldloc.1 IL_002c 20 00 20 00 00 ldc.i4 0x2000 IL_0031 5f and IL_0032 2d 04 brtrue.s 4 (IL_0038) IL_0034 17 ldc.i4.1 IL_0035 0a stloc.0 IL_0036 2b 02 br.s 2 (IL_003a) IL_0038 16 ldc.i4.0 IL_0039 0a stloc.0 IL_003a 06 ldloc.0 IL_003b 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Conversions:HasWideningDirectCastConversionButNotEnumTypeConversion(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.Conversions:HasWideningDirectCastConversionButNotEnumTypeConversion(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool weight= 10 : state 3 [ ldarg.0 ] weight= 79 : state 40 [ call ] weight= 25 : state 45 [ brtrue.s ] weight= 16 : state 4 [ ldarg.1 ] weight= 79 : state 40 [ call ] weight= 27 : state 44 [ brfalse.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 79 : state 40 [ call ] weight= 6 : state 11 [ stloc.0 ] weight= 44 : state 43 [ br.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 35 : state 5 [ ldarg.2 ] weight= 79 : state 40 [ call ] weight= -7 : state 200 [ stloc.1 -> ldloc.1 ] weight= 79 : state 40 [ call ] weight= 27 : state 44 [ brfalse.s ] weight= 9 : state 8 [ ldloc.1 ] weight= 38 : state 33 [ ldc.i4 ] weight= -5 : state 83 [ and ] weight= 25 : state 45 [ brtrue.s ] weight= 28 : state 24 [ ldc.i4.1 ] weight= 6 : state 11 [ stloc.0 ] weight= 44 : state 43 [ br.s ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 19 : state 42 [ ret ] Inline candidate has an arg that feeds a constant test. Multiplier increased to 1. Inline candidate callsite is in a loop. Multiplier increased to 4. calleeNativeSizeEstimate=829 callsiteNativeSizeEstimate=145 benefit multiplier=4 threshold=580 Native estimate for function size exceeds threshold for inlining 82.9 > 58 (multiplier = 4) Inline expansion aborted, inline not profitable Inlining [000230] failed, so bashing STMT00047 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Conversions:HasWideningDirectCastConversionButNotEnumTypeConversion(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000231] with [000230] [000231] --C--------- * RET_EXPR int (inl return from call [000230]) Inserting the inline return expression [000230] --C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000229] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 Replacing the return expression placeholder [000083] with [000236] [000083] --C--------- * RET_EXPR int (inl return from call [000236]) Inserting the inline return expression [000236] ------------ * CAST int <- bool <- int [000235] ------------ \--* LCL_VAR int V19 tmp8 Expanding INLINE_CANDIDATE in statement STMT00022 in BB19: STMT00022 (IL ???...0x0DA) [000113] I-C-G------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.ErrorFactory.ErrorInfo (exactContextHnd=0x00000000D1FFAB1E) [000097] ------------ arg0 +--* CNS_INT int 0x7D2C [000102] ------------ arg1 \--* LCL_VAR ref V14 tmp3 Argument #0: is a constant [000097] ------------ * CNS_INT int 0x7D2C Argument #1: is a local var [000102] ------------ * LCL_VAR ref V14 tmp3 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo : IL to import: IL_0000 7e b6 0e 00 04 ldsfld 0x4000EB6 IL_0005 02 ldarg.0 IL_0006 03 ldarg.1 IL_0007 73 af 09 00 0a newobj 0xA0009AF IL_000c 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo Jump targets: none New Basic Block BB33 [0032] created. BB33 [000..00D) Basic block list for 'Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB33 [0032] 1 1 [000..00D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000113] Starting PHASE Pre-import *************** Inline @[000113] Finishing PHASE Pre-import *************** Inline @[000113] Starting PHASE Importation *************** In impImport() for Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo impImportBlockPending for BB33 Importing BB33 (PC=000) of 'Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo' [ 0] 0 (0x000) ldsfld 04000EB6 [ 1] 5 (0x005) ldarg.0 [ 2] 6 (0x006) ldarg.1 [ 3] 7 (0x007) newobj lvaGrabTemp returning 20 (V20 tmp9) called for NewObj constructor temp. [000261] -A---------- * ASG ref [000260] D------N---- +--* LCL_VAR ref V20 tmp9 [000259] ------------ \--* ALLOCOBJ ref [000258] n----------- \--* IND long [000257] ------------ \--* CNS_INT(h) long 0xd1ffab1e token Marked V20 as a single def local lvaSetClass: setting class for V20 to (00000000D1FFAB1E) Microsoft.CodeAnalysis.DiagnosticInfo [exact] 0A0009AF In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 [000255] --CXG------- arg1 +--* IND ref [000254] --CXG------- | \--* ADD byref [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000256] ------------ arg2 +--* CNS_INT int 0x7D2C [000102] ------------ arg3 \--* LCL_VAR ref V14 tmp3 [ 1] 12 (0x00c) ret Inlinee Return expression (before normalization) => [000264] ------------ * LCL_VAR ref V20 tmp9 Inlinee Return expression (after normalization) => [000264] ------------ * LCL_VAR ref V20 tmp9 *************** Inline @[000113] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB33 [0032] 1 1 [000..00D) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB33 [000..00D) (return), preds={} succs={} ***** BB33 [000261] -A---------- * ASG ref [000260] D------N---- +--* LCL_VAR ref V20 tmp9 [000259] ------------ \--* ALLOCOBJ ref [000258] n----------- \--* IND long [000257] ------------ \--* CNS_INT(h) long 0xd1ffab1e token ***** BB33 [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 [000255] --CXG------- arg1 +--* IND ref [000254] --CXG------- | \--* ADD byref [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000256] ------------ arg2 +--* CNS_INT int 0x7D2C [000102] ------------ arg3 \--* LCL_VAR ref V14 tmp3 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000113] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000113] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000113] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000113] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000113] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000113] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000113] ----------- Arguments setup: Inlinee method body: STMT00052 (IL ???... ???) [000261] -A---------- * ASG ref [000260] D------N---- +--* LCL_VAR ref V20 tmp9 [000259] ------------ \--* ALLOCOBJ ref [000258] n----------- \--* IND long [000257] ------------ \--* CNS_INT(h) long 0xd1ffab1e token STMT00053 (IL ???... ???) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 [000255] --CXG------- arg1 +--* IND ref [000254] --CXG------- | \--* ADD byref [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000256] ------------ arg2 +--* CNS_INT int 0x7D2C [000102] ------------ arg3 \--* LCL_VAR ref V14 tmp3 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000113] is [000264] ------------ * LCL_VAR ref V20 tmp9 Successfully inlined Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo (13 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00024 in BB19: STMT00024 (IL ???... ???) [000120] I-C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor (exactContextHnd=0x00000000D1FFAB1E) [000119] ------------ this in rdi +--* ADDR byref [000118] -------N---- | \--* LCL_VAR struct V15 tmp4 [000096] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000114] --C--------- arg2 \--* RET_EXPR ref (inl return from call [000264]) thisArg: is a constant is byref to a struct local [000119] ------------ * ADDR byref [000118] -------N---- \--* LCL_VAR struct V15 tmp4 Argument #1: is a local var [000096] ------------ * LCL_VAR ref V02 arg2 Argument #2: is a local var [000264] ------------ * LCL_VAR ref V20 tmp9 INLINER: inlineInfo.tokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this : IL to import: IL_0000 02 ldarg.0 IL_0001 fe 15 71 01 00 02 initobj 0x2000171 IL_0007 02 ldarg.0 IL_0008 03 ldarg.1 IL_0009 7d 19 05 00 04 stfld 0x4000519 IL_000e 02 ldarg.0 IL_000f 04 ldarg.2 IL_0010 7d 1b 05 00 04 stfld 0x400051B IL_0015 2a ret INLINER impTokenLookupContextHandle for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this weight= 10 : state 3 [ ldarg.0 ] weight= 55 : state 180 [ initobj ] weight= 69 : state 226 [ ldarg.0 -> ldarg.1 -> stfld ] weight= 98 : state 228 [ ldarg.0 -> ldarg.2 -> stfld ] weight= 19 : state 42 [ ret ] multiplier in instance constructors increased to 1.5. Inline candidate is mostly loads and stores. Multiplier increased to 4.5. Inline candidate callsite is in a loop. Multiplier increased to 7.5. calleeNativeSizeEstimate=251 callsiteNativeSizeEstimate=145 benefit multiplier=7.5 threshold=1087 Native estimate for function size is within threshold for inlining 25.1 <= 108.7 (multiplier = 7.5) Jump targets: none New Basic Block BB34 [0033] created. BB34 [000..016) Basic block list for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB34 [0033] 1 1 [000..016) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000120] Starting PHASE Pre-import *************** Inline @[000120] Finishing PHASE Pre-import *************** Inline @[000120] Starting PHASE Importation *************** In impImport() for Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this impImportBlockPending for BB34 Importing BB34 (PC=000) of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) initobj 02000171 [000269] IA---------- * ASG struct (init) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 [000268] ------------ \--* CNS_INT int 0 [ 0] 7 (0x007) ldarg.0 [ 1] 8 (0x008) ldarg.1 [ 2] 9 (0x009) stfld 04000519 [000273] -A---------- * ASG ref [000272] -------N---- +--* FIELD ref TypeParameter [000270] ------------ | \--* ADDR byref [000271] -------N---- | \--* LCL_VAR struct V15 tmp4 [000096] ------------ \--* LCL_VAR ref V02 arg2 [ 0] 14 (0x00e) ldarg.0 [ 1] 15 (0x00f) ldarg.2 [ 2] 16 (0x010) stfld 0400051B [000277] -A---------- * ASG ref [000276] -------N---- +--* FIELD ref DiagnosticInfo [000274] ------------ | \--* ADDR byref [000275] -------N---- | \--* LCL_VAR struct V15 tmp4 [000264] ------------ \--* LCL_VAR ref V20 tmp9 [ 0] 21 (0x015) ret *************** Inline @[000120] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB34 [0033] 1 1 [000..016) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB34 [000..016) (return), preds={} succs={} ***** BB34 [000269] IA---------- * ASG struct (init) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 [000268] ------------ \--* CNS_INT int 0 ***** BB34 [000273] -A---------- * ASG ref [000272] -------N---- +--* FIELD ref TypeParameter [000270] ------------ | \--* ADDR byref [000271] -------N---- | \--* LCL_VAR struct V15 tmp4 [000096] ------------ \--* LCL_VAR ref V02 arg2 ***** BB34 [000277] -A---------- * ASG ref [000276] -------N---- +--* FIELD ref DiagnosticInfo [000274] ------------ | \--* ADDR byref [000275] -------N---- | \--* LCL_VAR struct V15 tmp4 [000264] ------------ \--* LCL_VAR ref V20 tmp9 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000120] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000120] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000120] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000120] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000120] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000120] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000120] ----------- Arguments setup: Inlinee method body: STMT00054 (IL ???... ???) [000269] IA---------- * ASG struct (init) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 [000268] ------------ \--* CNS_INT int 0 STMT00055 (IL ???... ???) [000273] -A---------- * ASG ref [000272] -------N---- +--* FIELD ref TypeParameter [000270] ------------ | \--* ADDR byref [000271] -------N---- | \--* LCL_VAR struct V15 tmp4 [000096] ------------ \--* LCL_VAR ref V02 arg2 STMT00056 (IL ???... ???) [000277] -A---------- * ASG ref [000276] -------N---- +--* FIELD ref DiagnosticInfo [000274] ------------ | \--* ADDR byref [000275] -------N---- | \--* LCL_VAR struct V15 tmp4 [000264] ------------ \--* LCL_VAR ref V20 tmp9 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this (22 IL bytes) (depth 1) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' calling 'Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this' INLINER: during 'fgInline' result 'success' reason 'profitable inline' **** Late devirt opportunity [000122] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000124] n----------- arg1 \--* OBJ struct [000123] ------------ \--* ADDR byref [000121] -------N---- \--* LCL_VAR struct V15 tmp4 impDevirtualizeCall: [R2R] base method not virtual, sorry **************** Inline Tree Inlines into 0600171A Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool [1 IL=0001 TR=000001 060023BB] [below ALWAYS_INLINE size] Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool [2 IL=0018 TR=000011 060023D3] [below ALWAYS_INLINE size] Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsRestrictedType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool [3 IL=0047 TR=000186 06002A92] [below ALWAYS_INLINE size] Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo [0 IL=0007 TR=000218 06000C32] [FAILED: noinline per VM] Microsoft.CodeAnalysis.DiagnosticInfo:.ctor(Microsoft.CodeAnalysis.CommonMessageProvider,int,System.Object[]):this [0 IL=0052 TR=000190 0600170B] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this [0 IL=0057 TR=000192 060015BF] [FAILED: target not direct] Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo]:Add(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo):this [0 IL=0065 TR=000018 060012CB] [FAILED: target not direct] Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasConstructorConstraint():bool:this [0 IL=0076 TR=000158 06001720] [FAILED: too many il bytes] Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesConstructorConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool [0 IL=0086 TR=000024 060012E6] [FAILED: target not direct] Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasReferenceTypeConstraint():bool:this [0 IL=0097 TR=000146 06001721] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesReferenceTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool [0 IL=0107 TR=000030 060012E7] [FAILED: target not direct] Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasValueTypeConstraint():bool:this [0 IL=0121 TR=000135 06001722] [FAILED: too many il bytes] Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesValueTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool [0 IL=0133 TR=000037 060012CA] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:ConstraintTypesWithDefinitionUseSiteDiagnostics(byref):System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]:this [0 IL=0141 TR=000045 060001BA] [FAILED: noinline per VM] System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:GetEnumerator():Enumerator[__Canon]:this [0 IL=0157 TR=000070 06002399] [FAILED: target not direct] Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol:InternalSubstituteTypeParameters(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution):Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeWithModifiers:this [0 IL=0151 TR=000066 060001FD] [FAILED: noinline per VM] Enumerator[__Canon][System.__Canon]:get_Current():System.__Canon:this [4 IL=0174 TR=000082 0600171F] [profitable inline] Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool [5 IL=0001 TR=000223 060023BB] [below ALWAYS_INLINE size] Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:IsErrorType(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol):bool [0 IL=0010 TR=000239 060023E2] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:AddUseSiteDiagnostics(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref) [0 IL=0022 TR=000230 06005958] [FAILED: unprofitable inline] Microsoft.CodeAnalysis.VisualBasic.Conversions:HasWideningDirectCastConversionButNotEnumTypeConversion(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool [6 IL=0208 TR=000113 06002A92] [below ALWAYS_INLINE size] Microsoft.CodeAnalysis.VisualBasic.ErrorFactory:ErrorInfo(int,System.Object[]):Microsoft.CodeAnalysis.DiagnosticInfo [0 IL=0007 TR=000263 06000C32] [FAILED: noinline per VM] Microsoft.CodeAnalysis.DiagnosticInfo:.ctor(Microsoft.CodeAnalysis.CommonMessageProvider,int,System.Object[]):this [7 IL=0213 TR=000120 0600170B] [profitable inline] Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this [0 IL=0218 TR=000122 060015BF] [FAILED: target not direct] Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo]:Add(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo):this [0 IL=0227 TR=000057 060001FE] [FAILED: noinline per VM] Enumerator[__Canon][System.__Canon]:MoveNext():bool:this Budget: initialTime=774, finalTime=828, initialBudget=7740, currentBudget=7740 Budget: initialSize=5557, finalSize=6014 *************** Finishing PHASE Morph - Inlining Trees after Morph - Inlining ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) i IBC BB02 [0001] 1 0 0 [008..00F)-> BB23 (always) i rare IBC BB03 [0002] 1 20988. 20988 [00F..019)-> BB07 ( cond ) i IBC BB04 [0003] 1 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 0 0 [01D..03E) i rare idxlen new[] newobj IBC BB06 [0005] 2 0 0 [03E..040) i rare IBC BB07 [0006] 2 20988. 20988 [040..048)-> BB10 ( cond ) i IBC BB08 [0007] 1 131 131 [048..053)-> BB10 ( cond ) i IBC BB09 [0008] 1 0 0 [053..055) i rare IBC BB10 [0009] 3 20988. 20988 [055..05D)-> BB13 ( cond ) i IBC BB11 [0010] 1 614 614 [05D..068)-> BB13 ( cond ) i IBC BB12 [0011] 1 22 22 [068..06A) i IBC BB13 [0012] 3 20988. 20988 [06A..072)-> BB16 ( cond ) i IBC BB14 [0013] 1 87 87 [072..080)-> BB16 ( cond ) i IBC BB15 [0014] 1 0 0 [080..082) i rare IBC BB16 [0015] 3 20988. 20988 [082..095)-> BB21 (always) i IBC BB17 [0016] 1 6120. 6120 [095..0B5) i bwd bwd-target IBC BB27 [0026] 1 6120. 6120 [0A9..0AA)-> BB29 ( cond ) i bwd IBC BB28 [0027] 1 3060. [0A9..0AA)-> BB30 (always) i bwd BB29 [0028] 1 3060. [0A9..0AA) i bwd BB30 [0029] 2 6120. 6120 [0A9..0AA) i bwd IBC BB31 [0030] 1 6120. 6120 [???..???)-> BB21 ( cond ) internal bwd IBC BB18 [0017] 1 479 479 [0B5..0B9)-> BB20 ( cond ) i bwd IBC BB19 [0018] 1 479 479 [0B9..0DF) i idxlen new[] newobj bwd IBC BB20 [0019] 2 479 479 [0DF..0E1) i bwd IBC BB21 [0020] 3 27108. 27108 [0E1..0EA)-> BB17 ( cond ) i bwd IBC BB22 [0021] 1 20988. 20988 [0EA..0EC) i IBC BB23 [0022] 2 20988. 20988 [0EC..0EE) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00001 (IL ???... ???) [000006] --C--------- * JTRUE void [000005] --C--------- \--* EQ int [000003] --C--------- +--* CAST int <- bool <- int [000200] --C-G------- | \--* EQ int [000198] --C-G------- | +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi | | \--* LCL_VAR ref V03 arg3 [000199] ------------ | \--* CNS_INT int 4 [000004] ------------ \--* CNS_INT int 0 ------------ BB02 [008..00F) -> BB23 (always), preds={} succs={BB23} ***** BB02 STMT00042 (IL 0x008...0x009) [000197] -A---------- * ASG int [000196] D------N---- +--* LCL_VAR int V06 loc0 [000195] ------------ \--* CNS_INT int 1 ------------ BB03 [00F..019) -> BB07 (cond), preds={} succs={BB04,BB07} ***** BB03 STMT00002 (IL 0x00F...0x010) [000009] -A---------- * ASG int [000008] D------N---- +--* LCL_VAR int V07 loc1 [000007] ------------ \--* CNS_INT int 1 ***** BB03 STMT00004 (IL ???... ???) [000016] --C--------- * JTRUE void [000015] --C--------- \--* EQ int [000013] --C--------- +--* CAST int <- bool <- int [000205] --C-G------- | \--* CAST int <- bool <- int [000204] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --C-G------- arg0 | \--* CAST int <- byte <- int [000202] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi | \--* LCL_VAR ref V03 arg3 [000014] ------------ \--* CNS_INT int 0 ------------ BB04 [019..01D) -> BB06 (cond), preds={} succs={BB05,BB06} ***** BB04 STMT00035 (IL 0x019...0x01B) [000169] ------------ * JTRUE void [000168] ------------ \--* EQ int [000166] ------------ +--* LCL_VAR ref V04 arg4 [000167] ------------ \--* CNS_INT ref null ------------ BB05 [01D..03E), preds={} succs={BB06} ***** BB05 STMT00037 (IL 0x01D...0x02E) [000179] -ACXG------- * ASG ref [000178] D------N---- +--* LCL_VAR ref V16 tmp5 [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000176] ------------ arg0 \--* CNS_INT long 1 ***** BB05 STMT00038 (IL ???... ???) [000185] -A-XG------- * ASG ref [000184] ---XG--N---- +--* INDEX ref [000181] ------------ | +--* LCL_VAR ref V16 tmp5 [000182] ------------ | \--* CNS_INT int 0 [000183] ------------ \--* LCL_VAR ref V03 arg3 ***** BB05 STMT00043 (IL ???... ???) [000216] -A---------- * ASG ref [000215] D------N---- +--* LCL_VAR ref V18 tmp7 [000214] ------------ \--* ALLOCOBJ ref [000213] n----------- \--* IND long [000212] ------------ \--* CNS_INT(h) long 0xd1ffab1e token ***** BB05 STMT00044 (IL ???... ???) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 [000210] --CXG------- arg1 +--* IND ref [000209] --CXG------- | \--* ADD byref [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000211] ------------ arg2 +--* CNS_INT int 0x7AA4 [000180] ------------ arg3 \--* LCL_VAR ref V16 tmp5 ***** BB05 STMT00040 (IL ???... ???) [000190] --C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor [000189] ------------ this in rdi +--* ADDR byref [000188] -------N---- | \--* LCL_VAR struct V17 tmp6 [000174] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000219] ------------ arg2 \--* LCL_VAR ref V18 tmp7 ***** BB05 STMT00041 (IL 0x039... ???) [000192] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000194] n----------- arg1 \--* OBJ struct [000193] ------------ \--* ADDR byref [000191] -------N---- \--* LCL_VAR struct V17 tmp6 ------------ BB06 [03E..040), preds={} succs={BB07} ***** BB06 STMT00036 (IL 0x03E...0x03F) [000172] -A---------- * ASG int [000171] D------N---- +--* LCL_VAR int V07 loc1 [000170] ------------ \--* CNS_INT int 0 ------------ BB07 [040..048) -> BB10 (cond), preds={} succs={BB08,BB10} ***** BB07 STMT00005 (IL 0x040...0x046) [000022] --C-G------- * JTRUE void [000021] --C-G------- \--* EQ int [000019] --C-G------- +--* CAST int <- bool <- int [000018] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000020] ------------ \--* CNS_INT int 0 ------------ BB08 [048..053) -> BB10 (cond), preds={} succs={BB09,BB10} ***** BB08 STMT00033 (IL 0x048...0x051) [000162] --C-G------- * JTRUE void [000161] --C-G------- \--* NE int [000159] --C-G------- +--* CAST int <- bool <- int [000158] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] ------------ arg0 | +--* LCL_VAR ref V02 arg2 [000156] ------------ arg1 | +--* LCL_VAR ref V03 arg3 [000157] ------------ arg2 | \--* LCL_VAR ref V04 arg4 [000160] ------------ \--* CNS_INT int 0 ------------ BB09 [053..055), preds={} succs={BB10} ***** BB09 STMT00034 (IL 0x053...0x054) [000165] -A---------- * ASG int [000164] D------N---- +--* LCL_VAR int V07 loc1 [000163] ------------ \--* CNS_INT int 0 ------------ BB10 [055..05D) -> BB13 (cond), preds={} succs={BB11,BB13} ***** BB10 STMT00006 (IL 0x055...0x05B) [000028] --C-G------- * JTRUE void [000027] --C-G------- \--* EQ int [000025] --C-G------- +--* CAST int <- bool <- int [000024] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000026] ------------ \--* CNS_INT int 0 ------------ BB11 [05D..068) -> BB13 (cond), preds={} succs={BB12,BB13} ***** BB11 STMT00031 (IL ???... ???) [000151] --C--------- * JTRUE void [000150] --C--------- \--* NE int [000148] --C--------- +--* CAST int <- bool <- int [000146] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] ------------ arg0 | +--* LCL_VAR ref V02 arg2 [000144] ------------ arg1 | +--* LCL_VAR ref V03 arg3 [000145] ------------ arg2 | \--* LCL_VAR ref V04 arg4 [000149] ------------ \--* CNS_INT int 0 ------------ BB12 [068..06A), preds={} succs={BB13} ***** BB12 STMT00032 (IL 0x068...0x069) [000154] -A---------- * ASG int [000153] D------N---- +--* LCL_VAR int V07 loc1 [000152] ------------ \--* CNS_INT int 0 ------------ BB13 [06A..072) -> BB16 (cond), preds={} succs={BB14,BB16} ***** BB13 STMT00007 (IL 0x06A...0x070) [000034] --C-G------- * JTRUE void [000033] --C-G------- \--* EQ int [000031] --C-G------- +--* CAST int <- bool <- int [000030] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000032] ------------ \--* CNS_INT int 0 ------------ BB14 [072..080) -> BB16 (cond), preds={} succs={BB15,BB16} ***** BB14 STMT00028 (IL 0x072...0x07E) [000139] --C-G------- * JTRUE void [000138] --C-G------- \--* NE int [000136] --C-G------- +--* CAST int <- bool <- int [000135] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000131] ------------ arg1 | +--* LCL_VAR ref V02 arg2 [000132] ------------ arg2 | +--* LCL_VAR ref V03 arg3 [000133] ------------ arg3 | +--* LCL_VAR ref V04 arg4 [000134] ------------ arg4 | \--* LCL_VAR byref V05 arg5 [000137] ------------ \--* CNS_INT int 0 ------------ BB15 [080..082), preds={} succs={BB16} ***** BB15 STMT00029 (IL 0x080...0x081) [000142] -A---------- * ASG int [000141] D------N---- +--* LCL_VAR int V07 loc1 [000140] ------------ \--* CNS_INT int 0 ------------ BB16 [082..095) -> BB21 (always), preds={} succs={BB21} ***** BB16 STMT00009 (IL ???... ???) [000042] -AC--------- * ASG ref [000041] ------------ +--* IND ref [000040] ------------ | \--* ADDR byref [000039] -------N---- | \--* LCL_VAR struct V09 loc3 [000037] --C-G------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] ------------ arg1 \--* LCL_VAR byref V05 arg5 ***** BB16 STMT00010 (IL 0x08B...0x092) [000050] -AC-G------- * ASG struct (copy) [000048] D------N---- +--* LCL_VAR struct V12 tmp1 [000045] --C-G------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA [000044] ------------ this in rdi +--* ADDR byref [000043] -------N---- | \--* LCL_VAR struct V09 loc3 [000047] n----------- arg1 \--* IND long [000046] ------------ \--* CNS_INT(h) long 0xd1ffab1e class ***** BB16 STMT00011 (IL ???... ???) [000054] -A---------- * ASG struct (copy) [000052] D------N---- +--* LCL_VAR struct V08 loc2 [000051] -------N---- \--* LCL_VAR struct V12 tmp1 ------------ BB17 [095..0B5), preds={} succs={BB27} ***** BB17 STMT00013 (IL 0x095...0x0A7) [000073] -AC-G------- * ASG struct (copy) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 [000070] --C-G------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000066] --C-G------- this in rdi +--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current [000065] ------------ this in rdi | +--* ADDR byref [000064] -------N---- | | \--* LCL_VAR struct V08 loc2 [000068] n----------- arg1 | \--* IND long [000067] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000069] ------------ arg1 \--* LCL_VAR ref V01 arg1 ***** BB17 STMT00014 (IL ???... ???) [000078] -A---------- * ASG ref [000077] D------N---- +--* LCL_VAR ref V10 loc4 [000076] ------------ \--* FIELD ref Type [000075] ------------ \--* ADDR byref [000074] -------N---- \--* LCL_VAR struct V13 tmp2 ***** BB17 STMT00051 (IL 0x0A9... ???) [000245] -A---------- * ASG bool [000244] D------N---- +--* LCL_VAR bool V19 tmp8 [000243] ------------ \--* CNS_INT int 0 ------------ BB27 [0A9..0AA) -> BB29 (cond), preds={} succs={BB28,BB29} ***** BB27 STMT00046 (IL 0x0A9... ???) [000228] --C--------- * JTRUE void [000227] --C--------- \--* EQ int [000225] --C--------- +--* CAST int <- bool <- int [000249] --C-G------- | \--* EQ int [000247] --C-G------- | +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi | | \--* LCL_VAR ref V10 loc4 [000248] ------------ | \--* CNS_INT int 4 [000226] ------------ \--* CNS_INT int 0 ------------ BB28 [0A9..0AA) -> BB30 (always), preds={} succs={BB30} ***** BB28 STMT00049 (IL 0x0A9... ???) [000239] --C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics [000237] ------------ arg0 +--* LCL_VAR ref V10 loc4 [000238] ------------ arg1 \--* LCL_VAR byref V05 arg5 ***** BB28 STMT00050 (IL 0x0A9... ???) [000242] -A---------- * ASG bool [000241] D------N---- +--* LCL_VAR bool V19 tmp8 [000240] ------------ \--* CNS_INT int 0 ------------ BB29 [0A9..0AA), preds={} succs={BB30} ***** BB29 STMT00048 (IL 0x0A9... ???) [000234] -AC--------- * ASG bool [000233] D------N---- +--* LCL_VAR bool V19 tmp8 [000232] --C--------- \--* CAST int <- bool <- int [000230] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000229] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 ------------ BB30 [0A9..0AA), preds={} succs={BB31} ------------ BB31 [???..???) -> BB21 (cond), preds={} succs={BB18,BB21} ***** BB31 STMT00016 (IL ???... ???) [000087] --C--------- * JTRUE void [000086] --C--------- \--* NE int [000084] --C--------- +--* CAST int <- bool <- int [000236] ------------ | \--* CAST int <- bool <- int [000235] ------------ | \--* LCL_VAR int V19 tmp8 [000085] ------------ \--* CNS_INT int 0 ------------ BB18 [0B5..0B9) -> BB20 (cond), preds={} succs={BB19,BB20} ***** BB18 STMT00017 (IL 0x0B5...0x0B7) [000091] ------------ * JTRUE void [000090] ------------ \--* EQ int [000088] ------------ +--* LCL_VAR ref V04 arg4 [000089] ------------ \--* CNS_INT ref null ------------ BB19 [0B9..0DF), preds={} succs={BB20} ***** BB19 STMT00019 (IL 0x0B9...0x0CA) [000101] -ACXG------- * ASG ref [000100] D------N---- +--* LCL_VAR ref V14 tmp3 [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000098] ------------ arg0 \--* CNS_INT long 2 ***** BB19 STMT00020 (IL ???... ???) [000107] -A-XG------- * ASG ref [000106] ---XG--N---- +--* INDEX ref [000103] ------------ | +--* LCL_VAR ref V14 tmp3 [000104] ------------ | \--* CNS_INT int 0 [000105] ------------ \--* LCL_VAR ref V03 arg3 ***** BB19 STMT00021 (IL ???...0x0CF) [000112] -A-XG------- * ASG ref [000111] ---XG--N---- +--* INDEX ref [000108] ------------ | +--* LCL_VAR ref V14 tmp3 [000109] ------------ | \--* CNS_INT int 1 [000110] ------------ \--* LCL_VAR ref V10 loc4 ***** BB19 STMT00052 (IL ???... ???) [000261] -A---------- * ASG ref [000260] D------N---- +--* LCL_VAR ref V20 tmp9 [000259] ------------ \--* ALLOCOBJ ref [000258] n----------- \--* IND long [000257] ------------ \--* CNS_INT(h) long 0xd1ffab1e token ***** BB19 STMT00053 (IL ???... ???) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 [000255] --CXG------- arg1 +--* IND ref [000254] --CXG------- | \--* ADD byref [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000256] ------------ arg2 +--* CNS_INT int 0x7D2C [000102] ------------ arg3 \--* LCL_VAR ref V14 tmp3 ***** BB19 STMT00023 (IL ???... ???) [000117] IA---------- * ASG struct (init) [000115] D------N---- +--* LCL_VAR struct V15 tmp4 [000116] ------------ \--* CNS_INT int 0 ***** BB19 STMT00054 (IL ???... ???) [000269] IA---------- * ASG struct (init) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 [000268] ------------ \--* CNS_INT int 0 ***** BB19 STMT00055 (IL ???... ???) [000273] -A---------- * ASG ref [000272] -------N---- +--* FIELD ref TypeParameter [000270] ------------ | \--* ADDR byref [000271] -------N---- | \--* LCL_VAR struct V15 tmp4 [000096] ------------ \--* LCL_VAR ref V02 arg2 ***** BB19 STMT00056 (IL ???... ???) [000277] -A---------- * ASG ref [000276] -------N---- +--* FIELD ref DiagnosticInfo [000274] ------------ | \--* ADDR byref [000275] -------N---- | \--* LCL_VAR struct V15 tmp4 [000264] ------------ \--* LCL_VAR ref V20 tmp9 ***** BB19 STMT00025 (IL 0x0DA... ???) [000122] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000124] n----------- arg1 \--* OBJ struct [000123] ------------ \--* ADDR byref [000121] -------N---- \--* LCL_VAR struct V15 tmp4 ------------ BB20 [0DF..0E1), preds={} succs={BB21} ***** BB20 STMT00018 (IL 0x0DF...0x0E0) [000094] -A---------- * ASG int [000093] D------N---- +--* LCL_VAR int V07 loc1 [000092] ------------ \--* CNS_INT int 0 ------------ BB21 [0E1..0EA) -> BB17 (cond), preds={} succs={BB22,BB17} ***** BB21 STMT00012 (IL 0x0E1...0x0E8) [000063] --C-G------- * JTRUE void [000062] --C-G------- \--* NE int [000060] --C-G------- +--* CAST int <- bool <- int [000057] --C-G------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext [000056] ------------ this in rdi | +--* ADDR byref [000055] -------N---- | | \--* LCL_VAR struct V08 loc2 [000059] n----------- arg1 | \--* IND long [000058] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000061] ------------ \--* CNS_INT int 0 ------------ BB22 [0EA..0EC), preds={} succs={BB23} ***** BB22 STMT00026 (IL 0x0EA...0x0EB) [000127] -A---------- * ASG int [000126] D------N---- +--* LCL_VAR int V06 loc0 [000125] ------------ \--* LCL_VAR int V07 loc1 ------------ BB23 [0EC..0EE) (return), preds={} succs={} ***** BB23 STMT00027 (IL 0x0EC...0x0ED) [000129] ------------ * RETURN int [000128] ------------ \--* LCL_VAR int V06 loc0 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Allocate Objects disabled, punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) i IBC BB02 [0001] 1 0 0 [008..00F)-> BB23 (always) i rare IBC BB03 [0002] 1 20988. 20988 [00F..019)-> BB07 ( cond ) i IBC BB04 [0003] 1 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 0 0 [01D..03E) i rare idxlen new[] newobj IBC BB06 [0005] 2 0 0 [03E..040) i rare IBC BB07 [0006] 2 20988. 20988 [040..048)-> BB10 ( cond ) i IBC BB08 [0007] 1 131 131 [048..053)-> BB10 ( cond ) i IBC BB09 [0008] 1 0 0 [053..055) i rare IBC BB10 [0009] 3 20988. 20988 [055..05D)-> BB13 ( cond ) i IBC BB11 [0010] 1 614 614 [05D..068)-> BB13 ( cond ) i IBC BB12 [0011] 1 22 22 [068..06A) i IBC BB13 [0012] 3 20988. 20988 [06A..072)-> BB16 ( cond ) i IBC BB14 [0013] 1 87 87 [072..080)-> BB16 ( cond ) i IBC BB15 [0014] 1 0 0 [080..082) i rare IBC BB16 [0015] 3 20988. 20988 [082..095)-> BB21 (always) i IBC BB17 [0016] 1 6120. 6120 [095..0B5) i bwd bwd-target IBC BB27 [0026] 1 6120. 6120 [0A9..0AA)-> BB29 ( cond ) i bwd IBC BB28 [0027] 1 3060. [0A9..0AA)-> BB30 (always) i bwd BB29 [0028] 1 3060. [0A9..0AA) i bwd BB30 [0029] 2 6120. 6120 [0A9..0AA) i bwd IBC BB31 [0030] 1 6120. 6120 [???..???)-> BB21 ( cond ) internal bwd IBC BB18 [0017] 1 479 479 [0B5..0B9)-> BB20 ( cond ) i bwd IBC BB19 [0018] 1 479 479 [0B9..0DF) i idxlen new[] newobj bwd IBC BB20 [0019] 2 479 479 [0DF..0E1) i bwd IBC BB21 [0020] 3 27108. 27108 [0E1..0EA)-> BB17 ( cond ) i bwd IBC BB22 [0021] 1 20988. 20988 [0EA..0EC) i IBC BB23 [0022] 2 20988. 20988 [0EC..0EE) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Compute preds Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) i IBC BB02 [0001] 1 0 0 [008..00F)-> BB23 (always) i rare IBC BB03 [0002] 1 20988. 20988 [00F..019)-> BB07 ( cond ) i IBC BB04 [0003] 1 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 0 0 [01D..03E) i rare idxlen new[] newobj IBC BB06 [0005] 2 0 0 [03E..040) i rare IBC BB07 [0006] 2 20988. 20988 [040..048)-> BB10 ( cond ) i IBC BB08 [0007] 1 131 131 [048..053)-> BB10 ( cond ) i IBC BB09 [0008] 1 0 0 [053..055) i rare IBC BB10 [0009] 3 20988. 20988 [055..05D)-> BB13 ( cond ) i IBC BB11 [0010] 1 614 614 [05D..068)-> BB13 ( cond ) i IBC BB12 [0011] 1 22 22 [068..06A) i IBC BB13 [0012] 3 20988. 20988 [06A..072)-> BB16 ( cond ) i IBC BB14 [0013] 1 87 87 [072..080)-> BB16 ( cond ) i IBC BB15 [0014] 1 0 0 [080..082) i rare IBC BB16 [0015] 3 20988. 20988 [082..095)-> BB21 (always) i IBC BB17 [0016] 1 6120. 6120 [095..0B5) i bwd bwd-target IBC BB27 [0026] 1 6120. 6120 [0A9..0AA)-> BB29 ( cond ) i bwd IBC BB28 [0027] 1 3060. [0A9..0AA)-> BB30 (always) i bwd BB29 [0028] 1 3060. [0A9..0AA) i bwd BB30 [0029] 2 6120. 6120 [0A9..0AA) i bwd IBC BB31 [0030] 1 6120. 6120 [???..???)-> BB21 ( cond ) internal bwd IBC BB18 [0017] 1 479 479 [0B5..0B9)-> BB20 ( cond ) i bwd IBC BB19 [0018] 1 479 479 [0B9..0DF) i idxlen new[] newobj bwd IBC BB20 [0019] 2 479 479 [0DF..0E1) i bwd IBC BB21 [0020] 3 27108. 27108 [0E1..0EA)-> BB17 ( cond ) i bwd IBC BB22 [0021] 1 20988. 20988 [0EA..0EC) i IBC BB23 [0022] 2 20988. 20988 [0EC..0EE) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB27 to BB18 Renumber BB28 to BB19 Renumber BB29 to BB20 Renumber BB30 to BB21 Renumber BB31 to BB22 Renumber BB18 to BB23 Renumber BB19 to BB24 Renumber BB20 to BB25 Renumber BB21 to BB26 Renumber BB22 to BB27 Renumber BB23 to BB28 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) i IBC BB02 [0001] 1 0 0 [008..00F)-> BB28 (always) i rare IBC BB03 [0002] 1 20988. 20988 [00F..019)-> BB07 ( cond ) i IBC BB04 [0003] 1 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 0 0 [01D..03E) i rare idxlen new[] newobj IBC BB06 [0005] 2 0 0 [03E..040) i rare IBC BB07 [0006] 2 20988. 20988 [040..048)-> BB10 ( cond ) i IBC BB08 [0007] 1 131 131 [048..053)-> BB10 ( cond ) i IBC BB09 [0008] 1 0 0 [053..055) i rare IBC BB10 [0009] 3 20988. 20988 [055..05D)-> BB13 ( cond ) i IBC BB11 [0010] 1 614 614 [05D..068)-> BB13 ( cond ) i IBC BB12 [0011] 1 22 22 [068..06A) i IBC BB13 [0012] 3 20988. 20988 [06A..072)-> BB16 ( cond ) i IBC BB14 [0013] 1 87 87 [072..080)-> BB16 ( cond ) i IBC BB15 [0014] 1 0 0 [080..082) i rare IBC BB16 [0015] 3 20988. 20988 [082..095)-> BB26 (always) i IBC BB17 [0016] 1 6120. 6120 [095..0B5) i bwd bwd-target IBC BB18 [0026] 1 6120. 6120 [0A9..0AA)-> BB20 ( cond ) i bwd IBC BB19 [0027] 1 3060. [0A9..0AA)-> BB21 (always) i bwd BB20 [0028] 1 3060. [0A9..0AA) i bwd BB21 [0029] 2 6120. 6120 [0A9..0AA) i bwd IBC BB22 [0030] 1 6120. 6120 [???..???)-> BB26 ( cond ) internal bwd IBC BB23 [0017] 1 479 479 [0B5..0B9)-> BB25 ( cond ) i bwd IBC BB24 [0018] 1 479 479 [0B9..0DF) i idxlen new[] newobj bwd IBC BB25 [0019] 2 479 479 [0DF..0E1) i bwd IBC BB26 [0020] 3 27108. 27108 [0E1..0EA)-> BB17 ( cond ) i bwd IBC BB27 [0021] 1 20988. 20988 [0EA..0EC) i IBC BB28 [0022] 2 20988. 20988 [0EC..0EE) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 2, # of blocks (including unused BB00): 29, bitset array size: 1 (short) *************** In fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) i IBC BB02 [0001] 1 0 0 [008..00F)-> BB28 (always) i rare IBC BB03 [0002] 1 20988. 20988 [00F..019)-> BB07 ( cond ) i IBC BB04 [0003] 1 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 0 0 [01D..03E) i rare idxlen new[] newobj IBC BB06 [0005] 2 0 0 [03E..040) i rare IBC BB07 [0006] 2 20988. 20988 [040..048)-> BB10 ( cond ) i IBC BB08 [0007] 1 131 131 [048..053)-> BB10 ( cond ) i IBC BB09 [0008] 1 0 0 [053..055) i rare IBC BB10 [0009] 3 20988. 20988 [055..05D)-> BB13 ( cond ) i IBC BB11 [0010] 1 614 614 [05D..068)-> BB13 ( cond ) i IBC BB12 [0011] 1 22 22 [068..06A) i IBC BB13 [0012] 3 20988. 20988 [06A..072)-> BB16 ( cond ) i IBC BB14 [0013] 1 87 87 [072..080)-> BB16 ( cond ) i IBC BB15 [0014] 1 0 0 [080..082) i rare IBC BB16 [0015] 3 20988. 20988 [082..095)-> BB26 (always) i IBC BB17 [0016] 1 6120. 6120 [095..0B5) i bwd bwd-target IBC BB18 [0026] 1 6120. 6120 [0A9..0AA)-> BB20 ( cond ) i bwd IBC BB19 [0027] 1 3060. [0A9..0AA)-> BB21 (always) i bwd BB20 [0028] 1 3060. [0A9..0AA) i bwd BB21 [0029] 2 6120. 6120 [0A9..0AA) i bwd IBC BB22 [0030] 1 6120. 6120 [???..???)-> BB26 ( cond ) internal bwd IBC BB23 [0017] 1 479 479 [0B5..0B9)-> BB25 ( cond ) i bwd IBC BB24 [0018] 1 479 479 [0B9..0DF) i idxlen new[] newobj bwd IBC BB25 [0019] 2 479 479 [0DF..0E1) i bwd IBC BB26 [0020] 3 27108. 27108 [0E1..0EA)-> BB17 ( cond ) i bwd IBC BB27 [0021] 1 20988. 20988 [0EA..0EC) i IBC BB28 [0022] 2 20988. 20988 [0EC..0EE) (return) i IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) i label target IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB28 (always) i rare IBC BB03 [0002] 1 BB01 20988. 20988 [00F..019)-> BB07 ( cond ) i label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040) i rare label target IBC BB07 [0006] 2 BB03,BB06 20988. 20988 [040..048)-> BB10 ( cond ) i label target IBC BB08 [0007] 1 BB07 131 131 [048..053)-> BB10 ( cond ) i IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 20988. 20988 [055..05D)-> BB13 ( cond ) i label target IBC BB11 [0010] 1 BB10 614 614 [05D..068)-> BB13 ( cond ) i IBC BB12 [0011] 1 BB11 22 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 20988. 20988 [06A..072)-> BB16 ( cond ) i label target IBC BB14 [0013] 1 BB13 87 87 [072..080)-> BB16 ( cond ) i IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 20988. 20988 [082..095)-> BB26 (always) i label target IBC BB17 [0016] 1 BB26 6120. 6120 [095..0B5) i label target bwd bwd-target IBC BB18 [0026] 1 BB17 6120. 6120 [0A9..0AA)-> BB20 ( cond ) i bwd IBC BB19 [0027] 1 BB18 3060. [0A9..0AA)-> BB21 (always) i bwd BB20 [0028] 1 BB18 3060. [0A9..0AA) i label target bwd BB21 [0029] 2 BB19,BB20 6120. 6120 [0A9..0AA) i label target bwd IBC BB22 [0030] 1 BB21 6120. 6120 [???..???)-> BB26 ( cond ) internal bwd IBC BB23 [0017] 1 BB22 479 479 [0B5..0B9)-> BB25 ( cond ) i bwd IBC BB24 [0018] 1 BB23 479 479 [0B9..0DF) i idxlen new[] newobj bwd IBC BB25 [0019] 2 BB23,BB24 479 479 [0DF..0E1) i label target bwd IBC BB26 [0020] 3 BB16,BB22,BB25 27108. 27108 [0E1..0EA)-> BB17 ( cond ) i label target bwd IBC BB27 [0021] 1 BB26 20988. 20988 [0EA..0EC) i IBC BB28 [0022] 2 BB02,BB27 20988. 20988 [0EC..0EE) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Compute preds *************** Starting PHASE Merge throw blocks *************** In fgTailMergeThrows Method does not have multiple noreturn calls. *************** Finishing PHASE Merge throw blocks [no changes] *************** Starting PHASE Update flow graph early pass *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) i label target IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB28 (always) i rare IBC BB03 [0002] 1 BB01 20988. 20988 [00F..019)-> BB07 ( cond ) i label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040) i rare label target IBC BB07 [0006] 2 BB03,BB06 20988. 20988 [040..048)-> BB10 ( cond ) i label target IBC BB08 [0007] 1 BB07 131 131 [048..053)-> BB10 ( cond ) i IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 20988. 20988 [055..05D)-> BB13 ( cond ) i label target IBC BB11 [0010] 1 BB10 614 614 [05D..068)-> BB13 ( cond ) i IBC BB12 [0011] 1 BB11 22 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 20988. 20988 [06A..072)-> BB16 ( cond ) i label target IBC BB14 [0013] 1 BB13 87 87 [072..080)-> BB16 ( cond ) i IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 20988. 20988 [082..095)-> BB26 (always) i label target IBC BB17 [0016] 1 BB26 6120. 6120 [095..0B5) i label target bwd bwd-target IBC BB18 [0026] 1 BB17 6120. 6120 [0A9..0AA)-> BB20 ( cond ) i bwd IBC BB19 [0027] 1 BB18 3060. [0A9..0AA)-> BB21 (always) i bwd BB20 [0028] 1 BB18 3060. [0A9..0AA) i label target bwd BB21 [0029] 2 BB19,BB20 6120. 6120 [0A9..0AA) i label target bwd IBC BB22 [0030] 1 BB21 6120. 6120 [???..???)-> BB26 ( cond ) internal bwd IBC BB23 [0017] 1 BB22 479 479 [0B5..0B9)-> BB25 ( cond ) i bwd IBC BB24 [0018] 1 BB23 479 479 [0B9..0DF) i idxlen new[] newobj bwd IBC BB25 [0019] 2 BB23,BB24 479 479 [0DF..0E1) i label target bwd IBC BB26 [0020] 3 BB16,BB22,BB25 27108. 27108 [0E1..0EA)-> BB17 ( cond ) i label target bwd IBC BB27 [0021] 1 BB26 20988. 20988 [0EA..0EC) i IBC BB28 [0022] 2 BB02,BB27 20988. 20988 [0EC..0EE) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB17 and BB18: *************** In fgDebugCheckBBlist Compacting blocks BB21 and BB22: *************** In fgDebugCheckBBlist After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) i label target IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB28 (always) i rare IBC BB03 [0002] 1 BB01 20988. 20988 [00F..019)-> BB07 ( cond ) i label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040) i rare label target IBC BB07 [0006] 2 BB03,BB06 20988. 20988 [040..048)-> BB10 ( cond ) i label target IBC BB08 [0007] 1 BB07 131 131 [048..053)-> BB10 ( cond ) i IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 20988. 20988 [055..05D)-> BB13 ( cond ) i label target IBC BB11 [0010] 1 BB10 614 614 [05D..068)-> BB13 ( cond ) i IBC BB12 [0011] 1 BB11 22 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 20988. 20988 [06A..072)-> BB16 ( cond ) i label target IBC BB14 [0013] 1 BB13 87 87 [072..080)-> BB16 ( cond ) i IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 20988. 20988 [082..095)-> BB26 (always) i label target IBC BB17 [0016] 1 BB26 6120. 6120 [095..0B5)-> BB20 ( cond ) i label target bwd bwd-target IBC BB19 [0027] 1 BB17 3060. [0A9..0AA)-> BB21 (always) i bwd BB20 [0028] 1 BB17 3060. [0A9..0AA) i label target bwd BB21 [0029] 2 BB19,BB20 6120. 6120 [0A9..0AA)-> BB26 ( cond ) i label target bwd IBC BB23 [0017] 1 BB21 479 479 [0B5..0B9)-> BB25 ( cond ) i bwd IBC BB24 [0018] 1 BB23 479 479 [0B9..0DF) i idxlen new[] newobj bwd IBC BB25 [0019] 2 BB23,BB24 479 479 [0DF..0E1) i label target bwd IBC BB26 [0020] 3 BB16,BB21,BB25 27108. 27108 [0E1..0EA)-> BB17 ( cond ) i label target bwd IBC BB27 [0021] 1 BB26 20988. 20988 [0EA..0EC) i IBC BB28 [0022] 2 BB02,BB27 20988. 20988 [0EC..0EE) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Update flow graph early pass *************** Starting PHASE Morph - Promote Structs *************** In fgPromoteStructs() lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 ref class-hnd ; V01 arg1 ref class-hnd ; V02 arg2 ref class-hnd ; V03 arg3 ref class-hnd ; V04 arg4 ref class-hnd ; V05 arg5 byref ; V06 loc0 bool ; V07 loc1 bool ; V08 loc2 struct ld-addr-op ; V09 loc3 struct ld-addr-op ; V10 loc4 ref class-hnd ; V11 OutArgs lclBlk "OutgoingArgSpace" ; V12 tmp1 struct multireg-ret "Return value temp for multireg return" ; V13 tmp2 struct multireg-ret "Return value temp for multireg return" ; V14 tmp3 ref class-hnd exact "dup spill" ; V15 tmp4 struct "NewObj constructor temp" ; V16 tmp5 ref class-hnd exact "dup spill" ; V17 tmp6 struct "NewObj constructor temp" ; V18 tmp7 ref class-hnd exact "NewObj constructor temp" ; V19 tmp8 bool "Inline stloc first use temp" ; V20 tmp9 ref class-hnd exact "NewObj constructor temp" Promoting struct local V08 (System.Collections.Immutable.ImmutableArray`1+Enumerator[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]): lvaGrabTemp returning 21 (V21 tmp10) (a long lifetime temp) called for field V08._array (fldOffset=0x0). lvaGrabTemp returning 22 (V22 tmp11) (a long lifetime temp) called for field V08._index (fldOffset=0x8). Promoting struct local V09 (System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]): lvaGrabTemp returning 23 (V23 tmp12) (a long lifetime temp) called for field V09.array (fldOffset=0x0). struct promotion of V12 is disabled because lvIsMultiRegRet struct promotion of V13 is disabled because lvIsMultiRegRet lvaTable after fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 ref class-hnd ; V01 arg1 ref class-hnd ; V02 arg2 ref class-hnd ; V03 arg3 ref class-hnd ; V04 arg4 ref class-hnd ; V05 arg5 byref ; V06 loc0 bool ; V07 loc1 bool ; V08 loc2 struct ld-addr-op ; V09 loc3 struct ld-addr-op ; V10 loc4 ref class-hnd ; V11 OutArgs lclBlk "OutgoingArgSpace" ; V12 tmp1 struct multireg-ret "Return value temp for multireg return" ; V13 tmp2 struct multireg-ret "Return value temp for multireg return" ; V14 tmp3 ref class-hnd exact "dup spill" ; V15 tmp4 struct "NewObj constructor temp" ; V16 tmp5 ref class-hnd exact "dup spill" ; V17 tmp6 struct "NewObj constructor temp" ; V18 tmp7 ref class-hnd exact "NewObj constructor temp" ; V19 tmp8 bool "Inline stloc first use temp" ; V20 tmp9 ref class-hnd exact "NewObj constructor temp" ; V21 tmp10 ref V08._array(offs=0x00) P-INDEP "field V08._array (fldOffset=0x0)" ; V22 tmp11 int V08._index(offs=0x08) P-INDEP "field V08._index (fldOffset=0x8)" ; V23 tmp12 ref V09.array(offs=0x00) P-INDEP "field V09.array (fldOffset=0x0)" *************** Finishing PHASE Morph - Promote Structs *************** Starting PHASE Morph - Structs/AddrExp *************** In fgMarkAddressExposedLocals() LocalAddressVisitor visiting statement: STMT00001 (IL ???... ???) [000006] --C--------- * JTRUE void [000005] --C--------- \--* EQ int [000003] --C--------- +--* CAST int <- bool <- int [000200] --C-G------- | \--* EQ int [000198] --C-G------- | +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi | | \--* LCL_VAR ref V03 arg3 [000199] ------------ | \--* CNS_INT int 4 [000004] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00042 (IL 0x008...0x009) [000197] -A---------- * ASG int [000196] D------N---- +--* LCL_VAR int V06 loc0 [000195] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00002 (IL 0x00F...0x010) [000009] -A---------- * ASG int [000008] D------N---- +--* LCL_VAR int V07 loc1 [000007] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00004 (IL ???... ???) [000016] --C--------- * JTRUE void [000015] --C--------- \--* EQ int [000013] --C--------- +--* CAST int <- bool <- int [000205] --C-G------- | \--* CAST int <- bool <- int [000204] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --C-G------- arg0 | \--* CAST int <- byte <- int [000202] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi | \--* LCL_VAR ref V03 arg3 [000014] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00035 (IL 0x019...0x01B) [000169] ------------ * JTRUE void [000168] ------------ \--* EQ int [000166] ------------ +--* LCL_VAR ref V04 arg4 [000167] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00037 (IL 0x01D...0x02E) [000179] -ACXG------- * ASG ref [000178] D------N---- +--* LCL_VAR ref V16 tmp5 [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000176] ------------ arg0 \--* CNS_INT long 1 LocalAddressVisitor visiting statement: STMT00038 (IL ???... ???) [000185] -A-XG------- * ASG ref [000184] ---XG--N---- +--* INDEX ref [000181] ------------ | +--* LCL_VAR ref V16 tmp5 [000182] ------------ | \--* CNS_INT int 0 [000183] ------------ \--* LCL_VAR ref V03 arg3 LocalAddressVisitor visiting statement: STMT00043 (IL ???... ???) [000216] -AC--------- * ASG ref [000215] D------N---- +--* LCL_VAR ref V18 tmp7 [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW LocalAddressVisitor visiting statement: STMT00044 (IL ???... ???) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 [000210] --CXG------- arg1 +--* IND ref [000209] --CXG------- | \--* ADD byref [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000211] ------------ arg2 +--* CNS_INT int 0x7AA4 [000180] ------------ arg3 \--* LCL_VAR ref V16 tmp5 LocalAddressVisitor visiting statement: STMT00040 (IL ???... ???) [000190] --C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor [000189] ------------ this in rdi +--* ADDR byref [000188] -------N---- | \--* LCL_VAR struct V17 tmp6 [000174] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000219] ------------ arg2 \--* LCL_VAR ref V18 tmp7 Local V17 should not be enregistered because: it is address exposed LocalAddressVisitor modified statement: STMT00040 (IL ???... ???) [000190] --C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 [000174] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000219] ------------ arg2 \--* LCL_VAR ref V18 tmp7 LocalAddressVisitor visiting statement: STMT00041 (IL 0x039... ???) [000192] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000194] n----------- arg1 \--* OBJ struct [000193] ------------ \--* ADDR byref [000191] -------N---- \--* LCL_VAR struct(AX) V17 tmp6 LocalAddressVisitor visiting statement: STMT00036 (IL 0x03E...0x03F) [000172] -A---------- * ASG int [000171] D------N---- +--* LCL_VAR int V07 loc1 [000170] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00005 (IL 0x040...0x046) [000022] --C-G------- * JTRUE void [000021] --C-G------- \--* EQ int [000019] --C-G------- +--* CAST int <- bool <- int [000018] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000020] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00033 (IL 0x048...0x051) [000162] --C-G------- * JTRUE void [000161] --C-G------- \--* NE int [000159] --C-G------- +--* CAST int <- bool <- int [000158] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] ------------ arg0 | +--* LCL_VAR ref V02 arg2 [000156] ------------ arg1 | +--* LCL_VAR ref V03 arg3 [000157] ------------ arg2 | \--* LCL_VAR ref V04 arg4 [000160] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00034 (IL 0x053...0x054) [000165] -A---------- * ASG int [000164] D------N---- +--* LCL_VAR int V07 loc1 [000163] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00006 (IL 0x055...0x05B) [000028] --C-G------- * JTRUE void [000027] --C-G------- \--* EQ int [000025] --C-G------- +--* CAST int <- bool <- int [000024] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000026] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00031 (IL ???... ???) [000151] --C--------- * JTRUE void [000150] --C--------- \--* NE int [000148] --C--------- +--* CAST int <- bool <- int [000146] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] ------------ arg0 | +--* LCL_VAR ref V02 arg2 [000144] ------------ arg1 | +--* LCL_VAR ref V03 arg3 [000145] ------------ arg2 | \--* LCL_VAR ref V04 arg4 [000149] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00032 (IL 0x068...0x069) [000154] -A---------- * ASG int [000153] D------N---- +--* LCL_VAR int V07 loc1 [000152] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00007 (IL 0x06A...0x070) [000034] --C-G------- * JTRUE void [000033] --C-G------- \--* EQ int [000031] --C-G------- +--* CAST int <- bool <- int [000030] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000032] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00028 (IL 0x072...0x07E) [000139] --C-G------- * JTRUE void [000138] --C-G------- \--* NE int [000136] --C-G------- +--* CAST int <- bool <- int [000135] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000131] ------------ arg1 | +--* LCL_VAR ref V02 arg2 [000132] ------------ arg2 | +--* LCL_VAR ref V03 arg3 [000133] ------------ arg3 | +--* LCL_VAR ref V04 arg4 [000134] ------------ arg4 | \--* LCL_VAR byref V05 arg5 [000137] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00029 (IL 0x080...0x081) [000142] -A---------- * ASG int [000141] D------N---- +--* LCL_VAR int V07 loc1 [000140] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00009 (IL ???... ???) [000042] -AC--------- * ASG ref [000041] ------------ +--* IND ref [000040] ------------ | \--* ADDR byref [000039] -------N---- | \--* LCL_VAR struct(P) V09 loc3 | \--* ref V09.array (offs=0x00) -> V23 tmp12 [000037] --C-G------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] ------------ arg1 \--* LCL_VAR byref V05 arg5 LocalAddressVisitor visiting statement: STMT00010 (IL 0x08B...0x092) [000050] -AC-G------- * ASG struct (copy) [000048] D------N---- +--* LCL_VAR struct V12 tmp1 [000045] --C-G------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA [000044] ------------ this in rdi +--* ADDR byref [000043] -------N---- | \--* LCL_VAR struct(P) V09 loc3 | \--* ref V09.array (offs=0x00) -> V23 tmp12 [000047] n----------- arg1 \--* IND long [000046] ------------ \--* CNS_INT(h) long 0xd1ffab1e class Local V23 should not be enregistered because: it is address exposed Local V09 should not be enregistered because: it is address exposed LocalAddressVisitor visiting statement: STMT00011 (IL ???... ???) [000054] -A---------- * ASG struct (copy) [000052] D------N---- +--* LCL_VAR struct(P) V08 loc2 +--* ref V08._array (offs=0x00) -> V21 tmp10 +--* int V08._index (offs=0x08) -> V22 tmp11 [000051] -------N---- \--* LCL_VAR struct V12 tmp1 LocalAddressVisitor visiting statement: STMT00013 (IL 0x095...0x0A7) [000073] -AC-G------- * ASG struct (copy) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 [000070] --C-G------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000066] --C-G------- this in rdi +--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current [000065] ------------ this in rdi | +--* ADDR byref [000064] -------N---- | | \--* LCL_VAR struct(P) V08 loc2 | | \--* ref V08._array (offs=0x00) -> V21 tmp10 | | \--* int V08._index (offs=0x08) -> V22 tmp11 [000068] n----------- arg1 | \--* IND long [000067] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000069] ------------ arg1 \--* LCL_VAR ref V01 arg1 Local V21 should not be enregistered because: it is address exposed Local V22 should not be enregistered because: it is address exposed Local V08 should not be enregistered because: it is address exposed LocalAddressVisitor visiting statement: STMT00014 (IL ???... ???) [000078] -A---------- * ASG ref [000077] D------N---- +--* LCL_VAR ref V10 loc4 [000076] ------------ \--* FIELD ref Type [000075] ------------ \--* ADDR byref [000074] -------N---- \--* LCL_VAR struct V13 tmp2 Local V13 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00014 (IL ???... ???) [000078] -A---------- * ASG ref [000077] D------N---- +--* LCL_VAR ref V10 loc4 [000076] ------------ \--* LCL_FLD ref V13 tmp2 [+0] Fseq[Type] LocalAddressVisitor visiting statement: STMT00051 (IL 0x0A9... ???) [000245] -A---------- * ASG bool [000244] D------N---- +--* LCL_VAR bool V19 tmp8 [000243] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00046 (IL 0x0A9... ???) [000228] --C--------- * JTRUE void [000227] --C--------- \--* EQ int [000225] --C--------- +--* CAST int <- bool <- int [000249] --C-G------- | \--* EQ int [000247] --C-G------- | +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi | | \--* LCL_VAR ref V10 loc4 [000248] ------------ | \--* CNS_INT int 4 [000226] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00049 (IL 0x0A9... ???) [000239] --C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics [000237] ------------ arg0 +--* LCL_VAR ref V10 loc4 [000238] ------------ arg1 \--* LCL_VAR byref V05 arg5 LocalAddressVisitor visiting statement: STMT00050 (IL 0x0A9... ???) [000242] -A---------- * ASG bool [000241] D------N---- +--* LCL_VAR bool V19 tmp8 [000240] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00048 (IL 0x0A9... ???) [000234] -AC--------- * ASG bool [000233] D------N---- +--* LCL_VAR bool V19 tmp8 [000232] --C--------- \--* CAST int <- bool <- int [000230] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000229] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 LocalAddressVisitor visiting statement: STMT00016 (IL ???... ???) [000087] --C--------- * JTRUE void [000086] --C--------- \--* NE int [000084] --C--------- +--* CAST int <- bool <- int [000236] ------------ | \--* CAST int <- bool <- int [000235] ------------ | \--* LCL_VAR int V19 tmp8 [000085] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00017 (IL 0x0B5...0x0B7) [000091] ------------ * JTRUE void [000090] ------------ \--* EQ int [000088] ------------ +--* LCL_VAR ref V04 arg4 [000089] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00019 (IL 0x0B9...0x0CA) [000101] -ACXG------- * ASG ref [000100] D------N---- +--* LCL_VAR ref V14 tmp3 [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000098] ------------ arg0 \--* CNS_INT long 2 LocalAddressVisitor visiting statement: STMT00020 (IL ???... ???) [000107] -A-XG------- * ASG ref [000106] ---XG--N---- +--* INDEX ref [000103] ------------ | +--* LCL_VAR ref V14 tmp3 [000104] ------------ | \--* CNS_INT int 0 [000105] ------------ \--* LCL_VAR ref V03 arg3 LocalAddressVisitor visiting statement: STMT00021 (IL ???...0x0CF) [000112] -A-XG------- * ASG ref [000111] ---XG--N---- +--* INDEX ref [000108] ------------ | +--* LCL_VAR ref V14 tmp3 [000109] ------------ | \--* CNS_INT int 1 [000110] ------------ \--* LCL_VAR ref V10 loc4 LocalAddressVisitor visiting statement: STMT00052 (IL ???... ???) [000261] -AC--------- * ASG ref [000260] D------N---- +--* LCL_VAR ref V20 tmp9 [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW LocalAddressVisitor visiting statement: STMT00053 (IL ???... ???) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 [000255] --CXG------- arg1 +--* IND ref [000254] --CXG------- | \--* ADD byref [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000256] ------------ arg2 +--* CNS_INT int 0x7D2C [000102] ------------ arg3 \--* LCL_VAR ref V14 tmp3 LocalAddressVisitor visiting statement: STMT00023 (IL ???... ???) [000117] IA---------- * ASG struct (init) [000115] D------N---- +--* LCL_VAR struct V15 tmp4 [000116] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00054 (IL ???... ???) [000269] IA---------- * ASG struct (init) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 [000268] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00055 (IL ???... ???) [000273] -A---------- * ASG ref [000272] -------N---- +--* FIELD ref TypeParameter [000270] ------------ | \--* ADDR byref [000271] -------N---- | \--* LCL_VAR struct V15 tmp4 [000096] ------------ \--* LCL_VAR ref V02 arg2 Local V15 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00055 (IL ???... ???) [000273] -A---------- * ASG ref [000272] U------N---- +--* LCL_FLD ref V15 tmp4 [+0] Fseq[TypeParameter] [000096] ------------ \--* LCL_VAR ref V02 arg2 LocalAddressVisitor visiting statement: STMT00056 (IL ???... ???) [000277] -A---------- * ASG ref [000276] -------N---- +--* FIELD ref DiagnosticInfo [000274] ------------ | \--* ADDR byref [000275] -------N---- | \--* LCL_VAR struct V15 tmp4 [000264] ------------ \--* LCL_VAR ref V20 tmp9 Local V15 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00056 (IL ???... ???) [000277] -A---------- * ASG ref [000276] U------N---- +--* LCL_FLD ref V15 tmp4 [+8] Fseq[DiagnosticInfo] [000264] ------------ \--* LCL_VAR ref V20 tmp9 LocalAddressVisitor visiting statement: STMT00025 (IL 0x0DA... ???) [000122] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000124] n----------- arg1 \--* OBJ struct [000123] ------------ \--* ADDR byref [000121] -------N---- \--* LCL_VAR struct V15 tmp4 LocalAddressVisitor visiting statement: STMT00018 (IL 0x0DF...0x0E0) [000094] -A---------- * ASG int [000093] D------N---- +--* LCL_VAR int V07 loc1 [000092] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00012 (IL 0x0E1...0x0E8) [000063] --C-G------- * JTRUE void [000062] --C-G------- \--* NE int [000060] --C-G------- +--* CAST int <- bool <- int [000057] --C-G------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext [000056] ------------ this in rdi | +--* ADDR byref [000055] -------N---- | | \--* LCL_VAR struct(AX)(P) V08 loc2 | | \--* ref V08._array (offs=0x00) -> V21 tmp10 | | \--* int V08._index (offs=0x08) -> V22 tmp11 [000059] n----------- arg1 | \--* IND long [000058] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000061] ------------ \--* CNS_INT int 0 Local V21 should not be enregistered because: it is address exposed Local V22 should not be enregistered because: it is address exposed Local V08 should not be enregistered because: it is address exposed LocalAddressVisitor visiting statement: STMT00026 (IL 0x0EA...0x0EB) [000127] -A---------- * ASG int [000126] D------N---- +--* LCL_VAR int V06 loc0 [000125] ------------ \--* LCL_VAR int V07 loc1 LocalAddressVisitor visiting statement: STMT00027 (IL 0x0EC...0x0ED) [000129] ------------ * RETURN int [000128] ------------ \--* LCL_VAR int V06 loc0 *************** Finishing PHASE Morph - Structs/AddrExp *************** Starting PHASE Morph - ByRefs *************** Finishing PHASE Morph - ByRefs *************** Starting PHASE Morph - Global *************** In fgMorphBlocks() Morphing BB01 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB01, STMT00001 (before) [000006] --C--------- * JTRUE void [000005] --C--------- \--* EQ int [000003] --C--------- +--* CAST int <- bool <- int [000200] --C-G------- | \--* EQ int [000198] --C-G------- | +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi | | \--* LCL_VAR ref V03 arg3 [000199] ------------ | \--* CNS_INT int 4 [000004] ------------ \--* CNS_INT int 0 fgMorphTree (before 0): [000006] --C--------- * JTRUE void [000005] --C--------- \--* EQ int [000003] --C--------- +--* CAST int <- bool <- int [000200] --C-G------- | \--* EQ int [000198] --C-G------- | +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi | | \--* LCL_VAR ref V03 arg3 [000199] ------------ | \--* CNS_INT int 4 [000004] ------------ \--* CNS_INT int 0 fgMorphTree (before 1): [000005] J-C----N---- * EQ int [000003] --C--------- +--* CAST int <- bool <- int [000200] --C-G------- | \--* EQ int [000198] --C-G------- | +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi | | \--* LCL_VAR ref V03 arg3 [000199] ------------ | \--* CNS_INT int 4 [000004] ------------ \--* CNS_INT int 0 fgMorphTree (before 2): [000003] --C--------- * CAST int <- bool <- int [000200] --C-G------- \--* EQ int [000198] --C-G------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi | \--* LCL_VAR ref V03 arg3 [000199] ------------ \--* CNS_INT int 4 fgMorphTree (before 3): [000200] --C-G------- * EQ int [000198] --C-G------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi | \--* LCL_VAR ref V03 arg3 [000199] ------------ \--* CNS_INT int 4 fgMorphTree (before 4): [000198] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] ------------ this in rdi \--* LCL_VAR ref V03 arg3 Initializing arg info for 198.CALL: ArgTable for 198.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 0.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 279.CNS_INT long, 1 reg: r11, align=1, isNonStandard] Morphing args for 198.CALL: fgMorphTree (before 5): [000000] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (after 5): [000000] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (before 6): [000279] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (after 6): [000279] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000000] -----+------ * LCL_VAR ref V03 arg3 Replaced with placeholder node: [000280] ----------L- * ARGPLACE ref Deferred argument ('r11'): [000279] -----+------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 Replaced with placeholder node: [000281] ----------L- * ARGPLACE long Shuffled argument table: rdi r11 ArgTable for 198.CALL after fgMorphArgs: fgArgTabEntry[arg 0 0.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 279.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 4): [000198] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] -----+------ this in rdi +--* LCL_VAR ref V03 arg3 [000279] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 GenTreeNode creates assertion: [000198] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind In BB01 New Local Constant Assertion: V03 != null index=#01, mask=0000000000000001 fgMorphTree (before 7): [000199] ------------ * CNS_INT int 4 fgMorphTree (after 7): [000199] ------------ * CNS_INT int 4 fgMorphTree (after 3): [000200] --CXG------- * EQ int [000198] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] -----+------ this in rdi | +--* LCL_VAR ref V03 arg3 [000279] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000199] -----+------ \--* CNS_INT int 4 fgMorphTree (after 2): [000200] --CXG+------ * EQ int [000198] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] -----+------ this in rdi | +--* LCL_VAR ref V03 arg3 [000279] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000199] -----+------ \--* CNS_INT int 4 fgMorphTree (before 8): [000004] ------------ * CNS_INT int 0 fgMorphTree (after 8): [000004] ------------ * CNS_INT int 0 fgMorphTree (after 1): [000200] J-CXG+-N---- * NE int [000198] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] -----+------ this in rdi | +--* LCL_VAR ref V03 arg3 [000279] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000199] -----+------ \--* CNS_INT int 4 fgMorphTree (after 0): [000006] --CXG------- * JTRUE void [000200] J-CXG+-N---- \--* NE int [000198] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] -----+------ this in rdi | +--* LCL_VAR ref V03 arg3 [000279] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000199] -----+------ \--* CNS_INT int 4 fgMorphTree BB01, STMT00001 (after) [000006] --CXG+------ * JTRUE void [000200] J-CXG+-N---- \--* NE int [000198] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] -----+------ this in rdi | +--* LCL_VAR ref V03 arg3 [000279] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000199] -----+------ \--* CNS_INT int 4 Morphing BB02 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB02, STMT00042 (before) [000197] -A---------- * ASG int [000196] D------N---- +--* LCL_VAR int V06 loc0 [000195] ------------ \--* CNS_INT int 1 fgMorphTree (before 9): [000197] -A---------- * ASG int [000196] D------N---- +--* LCL_VAR int V06 loc0 [000195] ------------ \--* CNS_INT int 1 fgMorphTree (before 10): [000196] D------N---- * LCL_VAR int V06 loc0 fgMorphTree (after 10): [000196] D------N---- * LCL_VAR int V06 loc0 fgMorphTree (before 11): [000282] ------------ * CAST int <- bool <- int [000195] ------------ \--* CNS_INT int 1 fgMorphTree (before 12): [000195] ------------ * CNS_INT int 1 fgMorphTree (after 12): [000195] ------------ * CNS_INT int 1 fgMorphTree (after 11): [000195] -----+------ * CNS_INT int 1 fgMorphTree (after 9): [000197] -A---------- * ASG int [000196] D----+-N---- +--* LCL_VAR int V06 loc0 [000195] -----+------ \--* CNS_INT int 1 GenTreeNode creates assertion: [000197] -A---------- * ASG int In BB02 New Local Constant Assertion: V06 == 1 index=#01, mask=0000000000000001 Morphing BB03 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB03, STMT00002 (before) [000009] -A---------- * ASG int [000008] D------N---- +--* LCL_VAR int V07 loc1 [000007] ------------ \--* CNS_INT int 1 fgMorphTree (before 13): [000009] -A---------- * ASG int [000008] D------N---- +--* LCL_VAR int V07 loc1 [000007] ------------ \--* CNS_INT int 1 fgMorphTree (before 14): [000008] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (after 14): [000008] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (before 15): [000283] ------------ * CAST int <- bool <- int [000007] ------------ \--* CNS_INT int 1 fgMorphTree (before 16): [000007] ------------ * CNS_INT int 1 fgMorphTree (after 16): [000007] ------------ * CNS_INT int 1 fgMorphTree (after 15): [000007] -----+------ * CNS_INT int 1 fgMorphTree (after 13): [000009] -A---------- * ASG int [000008] D----+-N---- +--* LCL_VAR int V07 loc1 [000007] -----+------ \--* CNS_INT int 1 GenTreeNode creates assertion: [000009] -A---------- * ASG int In BB03 New Local Constant Assertion: V07 == 1 index=#01, mask=0000000000000001 fgMorphTree BB03, STMT00004 (before) [000016] --C--------- * JTRUE void [000015] --C--------- \--* EQ int [000013] --C--------- +--* CAST int <- bool <- int [000205] --C-G------- | \--* CAST int <- bool <- int [000204] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --C-G------- arg0 | \--* CAST int <- byte <- int [000202] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi | \--* LCL_VAR ref V03 arg3 [000014] ------------ \--* CNS_INT int 0 fgMorphTree (before 17): [000016] --C--------- * JTRUE void [000015] --C--------- \--* EQ int [000013] --C--------- +--* CAST int <- bool <- int [000205] --C-G------- | \--* CAST int <- bool <- int [000204] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --C-G------- arg0 | \--* CAST int <- byte <- int [000202] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi | \--* LCL_VAR ref V03 arg3 [000014] ------------ \--* CNS_INT int 0 fgMorphTree (before 18): [000015] J-C----N---- * EQ int [000013] --C--------- +--* CAST int <- bool <- int [000205] --C-G------- | \--* CAST int <- bool <- int [000204] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --C-G------- arg0 | \--* CAST int <- byte <- int [000202] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi | \--* LCL_VAR ref V03 arg3 [000014] ------------ \--* CNS_INT int 0 fgMorphTree (before 19): [000013] --C--------- * CAST int <- bool <- int [000205] --C-G------- \--* CAST int <- bool <- int [000204] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --C-G------- arg0 \--* CAST int <- byte <- int [000202] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi \--* LCL_VAR ref V03 arg3 fgMorphTree (before 20): [000205] --C-G------- * CAST int <- bool <- int [000204] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --C-G------- arg0 \--* CAST int <- byte <- int [000202] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi \--* LCL_VAR ref V03 arg3 fgMorphTree (before 21): [000204] --C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --C-G------- arg0 \--* CAST int <- byte <- int [000202] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi \--* LCL_VAR ref V03 arg3 Initializing arg info for 204.CALL: ArgTable for 204.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 203.CAST int, 1 reg: rdi, align=1] Morphing args for 204.CALL: fgMorphTree (before 22): [000203] --C-G------- * CAST int <- byte <- int [000202] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi \--* LCL_VAR ref V03 arg3 fgMorphTree (before 23): [000202] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] ------------ this in rdi \--* LCL_VAR ref V03 arg3 Initializing arg info for 202.CALL: ArgTable for 202.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 10.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 284.CNS_INT long, 1 reg: r11, align=1, isNonStandard] Morphing args for 202.CALL: fgMorphTree (before 24): [000010] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (after 24): [000010] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (before 25): [000284] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (after 25): [000284] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000010] -----+------ * LCL_VAR ref V03 arg3 Replaced with placeholder node: [000285] ----------L- * ARGPLACE ref Deferred argument ('r11'): [000284] -----+------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 Replaced with placeholder node: [000286] ----------L- * ARGPLACE long Shuffled argument table: rdi r11 ArgTable for 202.CALL after fgMorphArgs: fgArgTabEntry[arg 0 10.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 284.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 23): [000202] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] -----+------ this in rdi +--* LCL_VAR ref V03 arg3 [000284] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 GenTreeNode creates assertion: [000202] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType In BB03 New Local Constant Assertion: V03 != null index=#02, mask=0000000000000002 fgMorphTree (after 22): [000203] --CXG------- * CAST int <- byte <- int [000202] --CXG+------ \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] -----+------ this in rdi +--* LCL_VAR ref V03 arg3 [000284] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000203] --CXG+------ * CAST int <- byte <- int [000202] --CXG+------ \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] -----+------ this in rdi +--* LCL_VAR ref V03 arg3 [000284] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 Replaced with placeholder node: [000287] ----------L- * ARGPLACE int Shuffled argument table: rdi ArgTable for 204.CALL after fgMorphArgs: fgArgTabEntry[arg 0 203.CAST int, 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree (after 21): [000204] --CXG------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --CXG+------ arg0 in rdi \--* CAST int <- byte <- int [000202] --CXG+------ \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] -----+------ this in rdi +--* LCL_VAR ref V03 arg3 [000284] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (after 20): [000205] --CXG------- * CAST int <- bool <- int [000204] --CXG+------ \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --CXG+------ arg0 in rdi \--* CAST int <- byte <- int [000202] --CXG+------ \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] -----+------ this in rdi +--* LCL_VAR ref V03 arg3 [000284] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (after 19): [000205] --CXG+------ * CAST int <- bool <- int [000204] --CXG+------ \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --CXG+------ arg0 in rdi \--* CAST int <- byte <- int [000202] --CXG+------ \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] -----+------ this in rdi +--* LCL_VAR ref V03 arg3 [000284] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (before 26): [000014] ------------ * CNS_INT int 0 fgMorphTree (after 26): [000014] ------------ * CNS_INT int 0 fgMorphTree (after 18): [000015] J-CXG--N---- * EQ int [000205] --CXG+------ +--* CAST int <- bool <- int [000204] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --CXG+------ arg0 in rdi | \--* CAST int <- byte <- int [000202] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] -----+------ this in rdi | +--* LCL_VAR ref V03 arg3 [000284] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000014] -----+------ \--* CNS_INT int 0 fgMorphTree (after 17): [000016] --CXG------- * JTRUE void [000015] J-CXG+-N---- \--* EQ int [000205] --CXG+------ +--* CAST int <- bool <- int [000204] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --CXG+------ arg0 in rdi | \--* CAST int <- byte <- int [000202] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] -----+------ this in rdi | +--* LCL_VAR ref V03 arg3 [000284] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000014] -----+------ \--* CNS_INT int 0 fgMorphTree BB03, STMT00004 (after) [000016] --CXG+------ * JTRUE void [000015] J-CXG+-N---- \--* EQ int [000205] --CXG+------ +--* CAST int <- bool <- int [000204] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --CXG+------ arg0 in rdi | \--* CAST int <- byte <- int [000202] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] -----+------ this in rdi | +--* LCL_VAR ref V03 arg3 [000284] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000014] -----+------ \--* CNS_INT int 0 Morphing BB04 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB04, STMT00035 (before) [000169] ------------ * JTRUE void [000168] ------------ \--* EQ int [000166] ------------ +--* LCL_VAR ref V04 arg4 [000167] ------------ \--* CNS_INT ref null fgMorphTree (before 27): [000169] ------------ * JTRUE void [000168] ------------ \--* EQ int [000166] ------------ +--* LCL_VAR ref V04 arg4 [000167] ------------ \--* CNS_INT ref null fgMorphTree (before 28): [000168] J------N---- * EQ int [000166] ------------ +--* LCL_VAR ref V04 arg4 [000167] ------------ \--* CNS_INT ref null fgMorphTree (before 29): [000166] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (after 29): [000166] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (before 30): [000167] ------------ * CNS_INT ref null fgMorphTree (after 30): [000167] ------------ * CNS_INT ref null fgMorphTree (after 28): [000168] J------N---- * EQ int [000166] -----+------ +--* LCL_VAR ref V04 arg4 [000167] -----+------ \--* CNS_INT ref null fgMorphTree (after 27): [000169] ------------ * JTRUE void [000168] J----+-N---- \--* EQ int [000166] -----+------ +--* LCL_VAR ref V04 arg4 [000167] -----+------ \--* CNS_INT ref null Morphing BB05 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB05, STMT00037 (before) [000179] -ACXG------- * ASG ref [000178] D------N---- +--* LCL_VAR ref V16 tmp5 [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000176] ------------ arg0 \--* CNS_INT long 1 fgMorphTree (before 31): [000179] -ACXG------- * ASG ref [000178] D------N---- +--* LCL_VAR ref V16 tmp5 [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000176] ------------ arg0 \--* CNS_INT long 1 fgMorphTree (before 32): [000178] D------N---- * LCL_VAR ref V16 tmp5 fgMorphTree (after 32): [000178] D------N---- * LCL_VAR ref V16 tmp5 fgMorphTree (before 33): [000177] --CXG------- * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000176] ------------ arg0 \--* CNS_INT long 1 Initializing arg info for 177.CALL: ArgTable for 177.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 176.CNS_INT long, 1 reg: rdi, align=1] Morphing args for 177.CALL: fgMorphTree (before 34): [000176] ------------ * CNS_INT long 1 fgMorphTree (after 34): [000176] ------------ * CNS_INT long 1 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000176] -----+------ * CNS_INT long 1 Replaced with placeholder node: [000288] ----------L- * ARGPLACE long Shuffled argument table: rdi ArgTable for 177.CALL after fgMorphArgs: fgArgTabEntry[arg 0 176.CNS_INT long, 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree (after 33): [000177] --CXG------- * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000176] -----+------ arg0 in rdi \--* CNS_INT long 1 fgMorphTree (after 31): [000179] -ACXG------- * ASG ref [000178] D----+-N---- +--* LCL_VAR ref V16 tmp5 [000177] --CXG+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000176] -----+------ arg0 in rdi \--* CNS_INT long 1 fgMorphTree BB05, STMT00037 (after) [000179] -ACXG+------ * ASG ref [000178] D----+-N---- +--* LCL_VAR ref V16 tmp5 [000177] --CXG+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000176] -----+------ arg0 in rdi \--* CNS_INT long 1 fgMorphTree BB05, STMT00038 (before) [000185] -A-XG------- * ASG ref [000184] ---XG--N---- +--* INDEX ref [000181] ------------ | +--* LCL_VAR ref V16 tmp5 [000182] ------------ | \--* CNS_INT int 0 [000183] ------------ \--* LCL_VAR ref V03 arg3 fgMorphTree (before 35): [000185] -A-XG------- * ASG ref [000184] ---XG--N---- +--* INDEX ref [000181] ------------ | +--* LCL_VAR ref V16 tmp5 [000182] ------------ | \--* CNS_INT int 0 [000183] ------------ \--* LCL_VAR ref V03 arg3 fgMorphTree (before 36): [000184] ---XG--N---- * INDEX ref [000181] ------------ +--* LCL_VAR ref V16 tmp5 [000182] ------------ \--* CNS_INT int 0 fgMorphTree (before 37): [000298] ---XG------- * COMMA ref [000292] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void [000182] ------------ | +--* CNS_INT int 0 [000291] ---X-------- | \--* ARR_LENGTH int [000181] ------------ | \--* LCL_VAR ref V16 tmp5 [000184] a--XG--N---- \--* IND ref [000297] ------------ \--* ADD byref [000289] ------------ +--* LCL_VAR ref V16 tmp5 [000296] ------------ \--* ADD long [000294] ------------ +--* MUL long [000290] ------------ | +--* CNS_INT long 0 [000293] -------N---- | \--* CNS_INT long 8 [000295] ------------ \--* CNS_INT long 16 fgMorphTree (before 38): [000292] ---X-------- * ARR_BOUNDS_CHECK_Rng void [000182] ------------ +--* CNS_INT int 0 [000291] ---X-------- \--* ARR_LENGTH int [000181] ------------ \--* LCL_VAR ref V16 tmp5 fgMorphTree (before 39): [000182] ------------ * CNS_INT int 0 fgMorphTree (after 39): [000182] ------------ * CNS_INT int 0 fgMorphTree (before 40): [000291] ---X-------- * ARR_LENGTH int [000181] ------------ \--* LCL_VAR ref V16 tmp5 fgMorphTree (before 41): [000181] ------------ * LCL_VAR ref V16 tmp5 fgMorphTree (after 41): [000181] ------------ * LCL_VAR ref V16 tmp5 fgMorphTree (after 40): [000291] ---X-------- * ARR_LENGTH int [000181] -----+------ \--* LCL_VAR ref V16 tmp5 GenTreeNode creates assertion: [000291] ---X-------- * ARR_LENGTH int In BB05 New Local Constant Assertion: V16 != null index=#01, mask=0000000000000001 fgMorphTree (after 38): [000292] ---X-------- * ARR_BOUNDS_CHECK_Rng void [000182] -----+------ +--* CNS_INT int 0 [000291] ---X-+------ \--* ARR_LENGTH int [000181] -----+------ \--* LCL_VAR ref V16 tmp5 fgMorphTree (before 42): [000184] a--XG--N---- * IND ref [000297] ------------ \--* ADD byref [000289] ------------ +--* LCL_VAR ref V16 tmp5 [000296] ------------ \--* ADD long [000294] ------------ +--* MUL long [000290] ------------ | +--* CNS_INT long 0 [000293] -------N---- | \--* CNS_INT long 8 [000295] ------------ \--* CNS_INT long 16 fgMorphTree (before 43): [000297] ------------ * ADD byref [000289] ------------ +--* LCL_VAR ref V16 tmp5 [000296] ------------ \--* ADD long [000294] ------------ +--* MUL long [000290] ------------ | +--* CNS_INT long 0 [000293] -------N---- | \--* CNS_INT long 8 [000295] ------------ \--* CNS_INT long 16 fgMorphTree (before 44): [000289] ------------ * LCL_VAR ref V16 tmp5 fgMorphTree (after 44): [000289] ------------ * LCL_VAR ref V16 tmp5 fgMorphTree (before 45): [000296] ------------ * ADD long [000294] ------------ +--* MUL long [000290] ------------ | +--* CNS_INT long 0 [000293] -------N---- | \--* CNS_INT long 8 [000295] ------------ \--* CNS_INT long 16 fgMorphTree (before 46): [000294] ------------ * MUL long [000290] ------------ +--* CNS_INT long 0 [000293] -------N---- \--* CNS_INT long 8 fgMorphTree (before 47): [000290] ------------ * CNS_INT long 0 fgMorphTree (after 47): [000290] ------------ * CNS_INT long 0 fgMorphTree (before 48): [000293] -------N---- * CNS_INT long 8 fgMorphTree (after 48): [000293] -------N---- * CNS_INT long 8 Folding long operator with constant nodes into a constant: [000294] ------------ * MUL long [000290] -----+------ +--* CNS_INT long 0 [000293] -----+-N---- \--* CNS_INT long 8 Bashed to long constant: [000294] ------------ * CNS_INT long 0 fgMorphTree (after 46): [000294] ------------ * CNS_INT long 0 fgMorphTree (before 49): [000295] ------------ * CNS_INT long 16 fgMorphTree (after 49): [000295] ------------ * CNS_INT long 16 Folding long operator with constant nodes into a constant: [000296] ------------ * ADD long [000294] -----+------ +--* CNS_INT long 0 [000295] -----+------ \--* CNS_INT long 16 Bashed to long constant: [000296] ------------ * CNS_INT long 16 fgMorphTree (after 45): [000296] ------------ * CNS_INT long 16 fgMorphTree (after 43): [000297] ------------ * ADD byref [000289] -----+------ +--* LCL_VAR ref V16 tmp5 [000296] -----+------ \--* CNS_INT long 16 fgMorphTree (after 42): [000184] a---G--N---- * IND ref [000297] -----+------ \--* ADD byref [000289] -----+------ +--* LCL_VAR ref V16 tmp5 [000296] -----+------ \--* CNS_INT long 16 fgMorphTree (after 37): [000298] ---XG------- * COMMA ref [000292] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000182] -----+------ | +--* CNS_INT int 0 [000291] ---X-+------ | \--* ARR_LENGTH int [000181] -----+------ | \--* LCL_VAR ref V16 tmp5 [000184] a---G+-N---- \--* IND ref [000297] -----+------ \--* ADD byref [000289] -----+------ +--* LCL_VAR ref V16 tmp5 [000296] -----+------ \--* CNS_INT long 16 fgMorphTree (after 36): [000298] ---XG+------ * COMMA ref [000292] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000182] -----+------ | +--* CNS_INT int 0 [000291] ---X-+------ | \--* ARR_LENGTH int [000181] -----+------ | \--* LCL_VAR ref V16 tmp5 [000184] a---G+-N---- \--* IND ref [000297] -----+------ \--* ADD byref [000289] -----+------ +--* LCL_VAR ref V16 tmp5 [000296] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree (before 50): [000183] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (after 50): [000183] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (after 35): [000185] -A-XG------- * ASG ref [000298] ---XG+-N---- +--* COMMA ref [000292] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000182] -----+------ | | +--* CNS_INT int 0 [000291] ---X-+------ | | \--* ARR_LENGTH int [000181] -----+------ | | \--* LCL_VAR ref V16 tmp5 [000184] a---G+-N---- | \--* IND ref [000297] -----+------ | \--* ADD byref [000289] -----+------ | +--* LCL_VAR ref V16 tmp5 [000296] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000183] -----+------ \--* LCL_VAR ref V03 arg3 fgMorphTree BB05, STMT00038 (after) [000185] -A-XG+------ * ASG ref [000298] ---XG+-N---- +--* COMMA ref [000292] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000182] -----+------ | | +--* CNS_INT int 0 [000291] ---X-+------ | | \--* ARR_LENGTH int [000181] -----+------ | | \--* LCL_VAR ref V16 tmp5 [000184] a---G+-N---- | \--* IND ref [000297] -----+------ | \--* ADD byref [000289] -----+------ | +--* LCL_VAR ref V16 tmp5 [000296] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000183] -----+------ \--* LCL_VAR ref V03 arg3 fgMorphTree BB05, STMT00043 (before) [000216] -AC--------- * ASG ref [000215] D------N---- +--* LCL_VAR ref V18 tmp7 [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW fgMorphTree (before 51): [000216] -AC--------- * ASG ref [000215] D------N---- +--* LCL_VAR ref V18 tmp7 [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW fgMorphTree (before 52): [000215] D------N---- * LCL_VAR ref V18 tmp7 fgMorphTree (after 52): [000215] D------N---- * LCL_VAR ref V18 tmp7 fgMorphTree (before 53): [000214] --C--------- * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW Initializing arg info for 214.CALL: ArgTable for 214.CALL after fgInitArgInfo: Morphing args for 214.CALL: argSlots=0, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 214.CALL after fgMorphArgs: fgMorphTree (after 53): [000214] --C--------- * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW fgMorphTree (after 51): [000216] -AC--------- * ASG ref [000215] D----+-N---- +--* LCL_VAR ref V18 tmp7 [000214] --C--+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW fgMorphTree BB05, STMT00044 (before) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 [000210] --CXG------- arg1 +--* IND ref [000209] --CXG------- | \--* ADD byref [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000211] ------------ arg2 +--* CNS_INT int 0x7AA4 [000180] ------------ arg3 \--* LCL_VAR ref V16 tmp5 fgMorphTree (before 54): [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 [000210] --CXG------- arg1 +--* IND ref [000209] --CXG------- | \--* ADD byref [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000211] ------------ arg2 +--* CNS_INT int 0x7AA4 [000180] ------------ arg3 \--* LCL_VAR ref V16 tmp5 Initializing arg info for 218.CALL: ArgTable for 218.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 217.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 210.IND ref, 1 reg: rsi, align=1] fgArgTabEntry[arg 2 211.CNS_INT int, 1 reg: rdx, align=1] fgArgTabEntry[arg 3 180.LCL_VAR ref, 1 reg: rcx, align=1] Morphing args for 218.CALL: fgMorphTree (before 55): [000217] ------------ * LCL_VAR ref V18 tmp7 fgMorphTree (after 55): [000217] ------------ * LCL_VAR ref V18 tmp7 fgMorphTree (before 56): [000210] --CXG------- * IND ref [000209] --CXG------- \--* ADD byref [000207] H-CXG------- +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] ------------ \--* CNS_INT int 0x418 Fseq[Instance] fgMorphTree (before 57): [000209] --CXG------- * ADD byref [000207] H-CXG------- +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] ------------ \--* CNS_INT int 0x418 Fseq[Instance] fgMorphTree (before 58): [000207] H-CXG------- * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE Initializing arg info for 207.CALL: ArgTable for 207.CALL after fgInitArgInfo: Morphing args for 207.CALL: argSlots=0, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 207.CALL after fgMorphArgs: fgMorphTree (after 58): [000207] H-CXG------- * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE fgMorphTree (before 59): [000208] ------------ * CNS_INT int 0x418 Fseq[Instance] fgMorphTree (after 59): [000208] ------------ * CNS_INT int 0x418 Fseq[Instance] fgMorphTree (after 57): [000209] --CXG------- * ADD byref [000207] H-CXG+------ +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] -----+------ \--* CNS_INT int 0x418 Fseq[Instance] fgMorphTree (after 56): [000210] --CXG------- * IND ref [000209] --CXG+------ \--* ADD byref [000207] H-CXG+------ +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] -----+------ \--* CNS_INT int 0x418 Fseq[Instance] fgMorphTree (before 60): [000211] ------------ * CNS_INT int 0x7AA4 fgMorphTree (after 60): [000211] ------------ * CNS_INT int 0x7AA4 fgMorphTree (before 61): [000180] ------------ * LCL_VAR ref V16 tmp5 fgMorphTree (after 61): [000180] ------------ * LCL_VAR ref V16 tmp5 argSlots=4, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Argument with 'side effect'... [000210] --CXG+------ * IND ref [000209] --CXG+------ \--* ADD byref [000207] H-CXG+------ +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] -----+------ \--* CNS_INT int 0x418 Fseq[Instance] lvaGrabTemp returning 24 (V24 tmp13) called for argument with side effect. Evaluate to a temp: [000300] -ACXG-----L- * ASG ref [000299] D------N---- +--* LCL_VAR ref V24 tmp13 [000210] --CXG+------ \--* IND ref [000209] --CXG+------ \--* ADD byref [000207] H-CXG+------ +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] -----+------ \--* CNS_INT int 0x418 Fseq[Instance] Deferred argument ('rdi'): [000217] -----+------ * LCL_VAR ref V18 tmp7 Replaced with placeholder node: [000302] ----------L- * ARGPLACE ref Deferred argument ('rcx'): [000180] -----+------ * LCL_VAR ref V16 tmp5 Replaced with placeholder node: [000303] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000211] -----+------ * CNS_INT int 0x7AA4 Replaced with placeholder node: [000304] ----------L- * ARGPLACE int Shuffled argument table: rsi rdi rcx rdx ArgTable for 218.CALL after fgMorphArgs: fgArgTabEntry[arg 1 301.LCL_VAR ref, 1 reg: rsi, align=1, lateArgInx=0, tmpNum=V24, isTmp, processed] fgArgTabEntry[arg 0 217.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 3 180.LCL_VAR ref, 1 reg: rcx, align=1, lateArgInx=2, processed] fgArgTabEntry[arg 2 211.CNS_INT int, 1 reg: rdx, align=1, lateArgInx=3, processed] fgMorphTree (after 54): [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000300] -ACXG-----L- arg1 SETUP +--* ASG ref [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 [000210] --CXG+------ | \--* IND ref [000209] --CXG+------ | \--* ADD byref [000207] H-CXG+------ | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] -----+------ | \--* CNS_INT int 0x418 Fseq[Instance] [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 [000217] -----+------ this in rdi +--* LCL_VAR ref V18 tmp7 [000180] -----+------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 [000211] -----+------ arg2 in rdx \--* CNS_INT int 0x7AA4 fgMorphTree BB05, STMT00044 (after) [000218] --CXG+------ * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000300] -ACXG-----L- arg1 SETUP +--* ASG ref [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 [000210] --CXG+------ | \--* IND ref [000209] --CXG+------ | \--* ADD byref [000207] H-CXG+------ | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] -----+------ | \--* CNS_INT int 0x418 Fseq[Instance] [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 [000217] -----+------ this in rdi +--* LCL_VAR ref V18 tmp7 [000180] -----+------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 [000211] -----+------ arg2 in rdx \--* CNS_INT int 0x7AA4 fgMorphTree BB05, STMT00040 (before) [000190] --C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 [000174] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000219] ------------ arg2 \--* LCL_VAR ref V18 tmp7 fgMorphTree (before 62): [000190] --C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 [000174] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000219] ------------ arg2 \--* LCL_VAR ref V18 tmp7 Initializing arg info for 190.CALL: ArgTable for 190.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 189.LCL_VAR_ADDR byref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 174.LCL_VAR ref, 1 reg: rsi, align=1] fgArgTabEntry[arg 2 219.LCL_VAR ref, 1 reg: rdx, align=1] Morphing args for 190.CALL: fgMorphTree (before 63): [000189] ------------ * LCL_VAR_ADDR byref V17 tmp6 fgMorphTree (after 63): [000189] ------------ * LCL_VAR_ADDR byref V17 tmp6 fgMorphTree (before 64): [000174] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (after 64): [000174] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (before 65): [000219] ------------ * LCL_VAR ref V18 tmp7 fgMorphTree (after 65): [000219] ------------ * LCL_VAR ref V18 tmp7 argSlots=3, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000189] -----+------ * LCL_VAR_ADDR byref V17 tmp6 Replaced with placeholder node: [000305] ----------L- * ARGPLACE byref Deferred argument ('rsi'): [000174] -----+------ * LCL_VAR ref V02 arg2 Replaced with placeholder node: [000306] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000219] -----+------ * LCL_VAR ref V18 tmp7 Replaced with placeholder node: [000307] ----------L- * ARGPLACE ref Shuffled argument table: rdi rsi rdx ArgTable for 190.CALL after fgMorphArgs: fgArgTabEntry[arg 0 189.LCL_VAR_ADDR byref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 174.LCL_VAR ref, 1 reg: rsi, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 2 219.LCL_VAR ref, 1 reg: rdx, align=1, lateArgInx=2, processed] fgMorphTree (after 62): [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor [000189] -----+------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 [000174] -----+------ arg1 in rsi +--* LCL_VAR ref V02 arg2 [000219] -----+------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 fgMorphTree BB05, STMT00040 (after) [000190] --CXG+------ * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor [000189] -----+------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 [000174] -----+------ arg1 in rsi +--* LCL_VAR ref V02 arg2 [000219] -----+------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 fgMorphTree BB05, STMT00041 (before) [000192] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000194] n----------- arg1 \--* OBJ struct [000193] ------------ \--* ADDR byref [000191] -------N---- \--* LCL_VAR struct(AX) V17 tmp6 fgMorphTree (before 66): [000192] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000194] n----------- arg1 \--* OBJ struct [000193] ------------ \--* ADDR byref [000191] -------N---- \--* LCL_VAR struct(AX) V17 tmp6 Initializing arg info for 192.CALL: **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo), ...) => passedInRegisters = false ArgTable for 192.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 173.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 308.CNS_INT long, 1 reg: r11, align=1, isNonStandard] fgArgTabEntry[arg 2 194.OBJ struct, numSlots=5, slotNum=0, align=1, isStruct] Morphing args for 192.CALL: fgMorphTree (before 67): [000173] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (after 67): [000173] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (before 68): [000308] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (after 68): [000308] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (before 69): [000194] n----------- * OBJ struct [000193] ------------ \--* ADDR byref [000191] -------N---- \--* LCL_VAR struct(AX) V17 tmp6 fgMorphTree (before 70): [000193] ------------ * ADDR byref [000191] -------N---- \--* LCL_VAR struct(AX) V17 tmp6 fgMorphTree (before 71): [000191] -------N---- * LCL_VAR struct(AX) V17 tmp6 fgMorphTree (after 71): [000191] ----G--N---- * LCL_VAR struct(AX) V17 tmp6 fgMorphTree (after 70): [000193] ------------ * ADDR byref [000191] ----G+-N---- \--* LCL_VAR struct(AX) V17 tmp6 fgMorphTree (after 69): [000194] n---G------- * OBJ struct [000193] -----+------ \--* ADDR byref [000191] ----G+-N---- \--* LCL_VAR struct(AX) V17 tmp6 argSlots=6, preallocatedArgCount=5, nextSlotNum=5, outgoingArgSpaceSize=40 Sorting the arguments: Deferred argument ('rdi'): [000173] -----+------ * LCL_VAR ref V04 arg4 Replaced with placeholder node: [000309] ----------L- * ARGPLACE ref Deferred argument ('r11'): [000308] -----+------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 Replaced with placeholder node: [000310] ----------L- * ARGPLACE long Shuffled argument table: rdi r11 Local V17 should not be enregistered because: it is a struct arg ArgTable for 192.CALL after fgMorphArgs: fgArgTabEntry[arg 2 194.OBJ struct, numSlots=5, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 0 173.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 308.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 66): [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct ( 3, 3) [000193] ------------ | \--* ADDR byref ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 [000173] -----+------ this in rdi +--* LCL_VAR ref V04 arg4 [000308] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 GenTreeNode creates assertion: [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add In BB05 New Local Constant Assertion: V04 != null index=#02, mask=0000000000000002 fgMorphTree BB05, STMT00041 (after) [000192] --CXG+------ * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct ( 3, 3) [000193] ------------ | \--* ADDR byref ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 [000173] -----+------ this in rdi +--* LCL_VAR ref V04 arg4 [000308] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 Morphing BB06 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB06, STMT00036 (before) [000172] -A---------- * ASG int [000171] D------N---- +--* LCL_VAR int V07 loc1 [000170] ------------ \--* CNS_INT int 0 fgMorphTree (before 72): [000172] -A---------- * ASG int [000171] D------N---- +--* LCL_VAR int V07 loc1 [000170] ------------ \--* CNS_INT int 0 fgMorphTree (before 73): [000171] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (after 73): [000171] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (before 74): [000311] ------------ * CAST int <- bool <- int [000170] ------------ \--* CNS_INT int 0 fgMorphTree (before 75): [000170] ------------ * CNS_INT int 0 fgMorphTree (after 75): [000170] ------------ * CNS_INT int 0 fgMorphTree (after 74): [000170] -----+------ * CNS_INT int 0 fgMorphTree (after 72): [000172] -A---------- * ASG int [000171] D----+-N---- +--* LCL_VAR int V07 loc1 [000170] -----+------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000172] -A---------- * ASG int In BB06 New Local Constant Assertion: V07 == 0 index=#01, mask=0000000000000001 Morphing BB07 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB07, STMT00005 (before) [000022] --C-G------- * JTRUE void [000021] --C-G------- \--* EQ int [000019] --C-G------- +--* CAST int <- bool <- int [000018] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000020] ------------ \--* CNS_INT int 0 fgMorphTree (before 76): [000022] --C-G------- * JTRUE void [000021] --C-G------- \--* EQ int [000019] --C-G------- +--* CAST int <- bool <- int [000018] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000020] ------------ \--* CNS_INT int 0 fgMorphTree (before 77): [000021] J-C-G--N---- * EQ int [000019] --C-G------- +--* CAST int <- bool <- int [000018] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000020] ------------ \--* CNS_INT int 0 fgMorphTree (before 78): [000019] --C-G------- * CAST int <- bool <- int [000018] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] ------------ this in rdi \--* LCL_VAR ref V02 arg2 fgMorphTree (before 79): [000018] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] ------------ this in rdi \--* LCL_VAR ref V02 arg2 Initializing arg info for 18.CALL: ArgTable for 18.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 17.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 312.CNS_INT long, 1 reg: r11, align=1, isNonStandard] Morphing args for 18.CALL: fgMorphTree (before 80): [000017] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (after 80): [000017] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (before 81): [000312] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (after 81): [000312] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000017] -----+------ * LCL_VAR ref V02 arg2 Replaced with placeholder node: [000313] ----------L- * ARGPLACE ref Deferred argument ('r11'): [000312] -----+------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 Replaced with placeholder node: [000314] ----------L- * ARGPLACE long Shuffled argument table: rdi r11 ArgTable for 18.CALL after fgMorphArgs: fgArgTabEntry[arg 0 17.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 312.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 79): [000018] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] -----+------ this in rdi +--* LCL_VAR ref V02 arg2 [000312] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 GenTreeNode creates assertion: [000018] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint In BB07 New Local Constant Assertion: V02 != null index=#01, mask=0000000000000001 fgMorphTree (after 78): [000019] --CXG------- * CAST int <- bool <- int [000018] --CXG+------ \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] -----+------ this in rdi +--* LCL_VAR ref V02 arg2 [000312] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (before 82): [000020] ------------ * CNS_INT int 0 fgMorphTree (after 82): [000020] ------------ * CNS_INT int 0 fgMorphTree (after 77): [000021] J-CXG--N---- * EQ int [000019] --CXG+------ +--* CAST int <- bool <- int [000018] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000312] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000020] -----+------ \--* CNS_INT int 0 fgMorphTree (after 76): [000022] --CXG------- * JTRUE void [000021] J-CXG+-N---- \--* EQ int [000019] --CXG+------ +--* CAST int <- bool <- int [000018] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000312] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000020] -----+------ \--* CNS_INT int 0 fgMorphTree BB07, STMT00005 (after) [000022] --CXG+------ * JTRUE void [000021] J-CXG+-N---- \--* EQ int [000019] --CXG+------ +--* CAST int <- bool <- int [000018] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000312] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000020] -----+------ \--* CNS_INT int 0 Morphing BB08 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB08, STMT00033 (before) [000162] --C-G------- * JTRUE void [000161] --C-G------- \--* NE int [000159] --C-G------- +--* CAST int <- bool <- int [000158] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] ------------ arg0 | +--* LCL_VAR ref V02 arg2 [000156] ------------ arg1 | +--* LCL_VAR ref V03 arg3 [000157] ------------ arg2 | \--* LCL_VAR ref V04 arg4 [000160] ------------ \--* CNS_INT int 0 fgMorphTree (before 83): [000162] --C-G------- * JTRUE void [000161] --C-G------- \--* NE int [000159] --C-G------- +--* CAST int <- bool <- int [000158] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] ------------ arg0 | +--* LCL_VAR ref V02 arg2 [000156] ------------ arg1 | +--* LCL_VAR ref V03 arg3 [000157] ------------ arg2 | \--* LCL_VAR ref V04 arg4 [000160] ------------ \--* CNS_INT int 0 fgMorphTree (before 84): [000161] J-C-G--N---- * NE int [000159] --C-G------- +--* CAST int <- bool <- int [000158] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] ------------ arg0 | +--* LCL_VAR ref V02 arg2 [000156] ------------ arg1 | +--* LCL_VAR ref V03 arg3 [000157] ------------ arg2 | \--* LCL_VAR ref V04 arg4 [000160] ------------ \--* CNS_INT int 0 fgMorphTree (before 85): [000159] --C-G------- * CAST int <- bool <- int [000158] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] ------------ arg0 +--* LCL_VAR ref V02 arg2 [000156] ------------ arg1 +--* LCL_VAR ref V03 arg3 [000157] ------------ arg2 \--* LCL_VAR ref V04 arg4 fgMorphTree (before 86): [000158] --C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] ------------ arg0 +--* LCL_VAR ref V02 arg2 [000156] ------------ arg1 +--* LCL_VAR ref V03 arg3 [000157] ------------ arg2 \--* LCL_VAR ref V04 arg4 Initializing arg info for 158.CALL: ArgTable for 158.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 155.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 156.LCL_VAR ref, 1 reg: rsi, align=1] fgArgTabEntry[arg 2 157.LCL_VAR ref, 1 reg: rdx, align=1] Morphing args for 158.CALL: fgMorphTree (before 87): [000155] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (after 87): [000155] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (before 88): [000156] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (after 88): [000156] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (before 89): [000157] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (after 89): [000157] ------------ * LCL_VAR ref V04 arg4 argSlots=3, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000155] -----+------ * LCL_VAR ref V02 arg2 Replaced with placeholder node: [000315] ----------L- * ARGPLACE ref Deferred argument ('rsi'): [000156] -----+------ * LCL_VAR ref V03 arg3 Replaced with placeholder node: [000316] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000157] -----+------ * LCL_VAR ref V04 arg4 Replaced with placeholder node: [000317] ----------L- * ARGPLACE ref Shuffled argument table: rdi rsi rdx ArgTable for 158.CALL after fgMorphArgs: fgArgTabEntry[arg 0 155.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 156.LCL_VAR ref, 1 reg: rsi, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 2 157.LCL_VAR ref, 1 reg: rdx, align=1, lateArgInx=2, processed] fgMorphTree (after 86): [000158] --CXG------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] -----+------ arg0 in rdi +--* LCL_VAR ref V02 arg2 [000156] -----+------ arg1 in rsi +--* LCL_VAR ref V03 arg3 [000157] -----+------ arg2 in rdx \--* LCL_VAR ref V04 arg4 fgMorphTree (after 85): [000159] --CXG------- * CAST int <- bool <- int [000158] --CXG+------ \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] -----+------ arg0 in rdi +--* LCL_VAR ref V02 arg2 [000156] -----+------ arg1 in rsi +--* LCL_VAR ref V03 arg3 [000157] -----+------ arg2 in rdx \--* LCL_VAR ref V04 arg4 fgMorphTree (before 90): [000160] ------------ * CNS_INT int 0 fgMorphTree (after 90): [000160] ------------ * CNS_INT int 0 fgMorphTree (after 84): [000161] J-CXG--N---- * NE int [000159] --CXG+------ +--* CAST int <- bool <- int [000158] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] -----+------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 [000156] -----+------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 [000157] -----+------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 [000160] -----+------ \--* CNS_INT int 0 fgMorphTree (after 83): [000162] --CXG------- * JTRUE void [000161] J-CXG+-N---- \--* NE int [000159] --CXG+------ +--* CAST int <- bool <- int [000158] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] -----+------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 [000156] -----+------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 [000157] -----+------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 [000160] -----+------ \--* CNS_INT int 0 fgMorphTree BB08, STMT00033 (after) [000162] --CXG+------ * JTRUE void [000161] J-CXG+-N---- \--* NE int [000159] --CXG+------ +--* CAST int <- bool <- int [000158] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] -----+------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 [000156] -----+------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 [000157] -----+------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 [000160] -----+------ \--* CNS_INT int 0 Morphing BB09 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB09, STMT00034 (before) [000165] -A---------- * ASG int [000164] D------N---- +--* LCL_VAR int V07 loc1 [000163] ------------ \--* CNS_INT int 0 fgMorphTree (before 91): [000165] -A---------- * ASG int [000164] D------N---- +--* LCL_VAR int V07 loc1 [000163] ------------ \--* CNS_INT int 0 fgMorphTree (before 92): [000164] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (after 92): [000164] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (before 93): [000318] ------------ * CAST int <- bool <- int [000163] ------------ \--* CNS_INT int 0 fgMorphTree (before 94): [000163] ------------ * CNS_INT int 0 fgMorphTree (after 94): [000163] ------------ * CNS_INT int 0 fgMorphTree (after 93): [000163] -----+------ * CNS_INT int 0 fgMorphTree (after 91): [000165] -A---------- * ASG int [000164] D----+-N---- +--* LCL_VAR int V07 loc1 [000163] -----+------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000165] -A---------- * ASG int In BB09 New Local Constant Assertion: V07 == 0 index=#01, mask=0000000000000001 Morphing BB10 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB10, STMT00006 (before) [000028] --C-G------- * JTRUE void [000027] --C-G------- \--* EQ int [000025] --C-G------- +--* CAST int <- bool <- int [000024] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000026] ------------ \--* CNS_INT int 0 fgMorphTree (before 95): [000028] --C-G------- * JTRUE void [000027] --C-G------- \--* EQ int [000025] --C-G------- +--* CAST int <- bool <- int [000024] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000026] ------------ \--* CNS_INT int 0 fgMorphTree (before 96): [000027] J-C-G--N---- * EQ int [000025] --C-G------- +--* CAST int <- bool <- int [000024] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000026] ------------ \--* CNS_INT int 0 fgMorphTree (before 97): [000025] --C-G------- * CAST int <- bool <- int [000024] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] ------------ this in rdi \--* LCL_VAR ref V02 arg2 fgMorphTree (before 98): [000024] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] ------------ this in rdi \--* LCL_VAR ref V02 arg2 Initializing arg info for 24.CALL: ArgTable for 24.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 23.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 319.CNS_INT long, 1 reg: r11, align=1, isNonStandard] Morphing args for 24.CALL: fgMorphTree (before 99): [000023] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (after 99): [000023] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (before 100): [000319] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (after 100): [000319] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000023] -----+------ * LCL_VAR ref V02 arg2 Replaced with placeholder node: [000320] ----------L- * ARGPLACE ref Deferred argument ('r11'): [000319] -----+------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 Replaced with placeholder node: [000321] ----------L- * ARGPLACE long Shuffled argument table: rdi r11 ArgTable for 24.CALL after fgMorphArgs: fgArgTabEntry[arg 0 23.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 319.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 98): [000024] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] -----+------ this in rdi +--* LCL_VAR ref V02 arg2 [000319] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 GenTreeNode creates assertion: [000024] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint In BB10 New Local Constant Assertion: V02 != null index=#01, mask=0000000000000001 fgMorphTree (after 97): [000025] --CXG------- * CAST int <- bool <- int [000024] --CXG+------ \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] -----+------ this in rdi +--* LCL_VAR ref V02 arg2 [000319] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (before 101): [000026] ------------ * CNS_INT int 0 fgMorphTree (after 101): [000026] ------------ * CNS_INT int 0 fgMorphTree (after 96): [000027] J-CXG--N---- * EQ int [000025] --CXG+------ +--* CAST int <- bool <- int [000024] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000319] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000026] -----+------ \--* CNS_INT int 0 fgMorphTree (after 95): [000028] --CXG------- * JTRUE void [000027] J-CXG+-N---- \--* EQ int [000025] --CXG+------ +--* CAST int <- bool <- int [000024] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000319] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000026] -----+------ \--* CNS_INT int 0 fgMorphTree BB10, STMT00006 (after) [000028] --CXG+------ * JTRUE void [000027] J-CXG+-N---- \--* EQ int [000025] --CXG+------ +--* CAST int <- bool <- int [000024] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000319] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000026] -----+------ \--* CNS_INT int 0 Morphing BB11 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB11, STMT00031 (before) [000151] --C--------- * JTRUE void [000150] --C--------- \--* NE int [000148] --C--------- +--* CAST int <- bool <- int [000146] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] ------------ arg0 | +--* LCL_VAR ref V02 arg2 [000144] ------------ arg1 | +--* LCL_VAR ref V03 arg3 [000145] ------------ arg2 | \--* LCL_VAR ref V04 arg4 [000149] ------------ \--* CNS_INT int 0 fgMorphTree (before 102): [000151] --C--------- * JTRUE void [000150] --C--------- \--* NE int [000148] --C--------- +--* CAST int <- bool <- int [000146] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] ------------ arg0 | +--* LCL_VAR ref V02 arg2 [000144] ------------ arg1 | +--* LCL_VAR ref V03 arg3 [000145] ------------ arg2 | \--* LCL_VAR ref V04 arg4 [000149] ------------ \--* CNS_INT int 0 fgMorphTree (before 103): [000150] J-C----N---- * NE int [000148] --C--------- +--* CAST int <- bool <- int [000146] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] ------------ arg0 | +--* LCL_VAR ref V02 arg2 [000144] ------------ arg1 | +--* LCL_VAR ref V03 arg3 [000145] ------------ arg2 | \--* LCL_VAR ref V04 arg4 [000149] ------------ \--* CNS_INT int 0 fgMorphTree (before 104): [000148] --C--------- * CAST int <- bool <- int [000146] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] ------------ arg0 +--* LCL_VAR ref V02 arg2 [000144] ------------ arg1 +--* LCL_VAR ref V03 arg3 [000145] ------------ arg2 \--* LCL_VAR ref V04 arg4 fgMorphTree (before 105): [000146] --C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] ------------ arg0 +--* LCL_VAR ref V02 arg2 [000144] ------------ arg1 +--* LCL_VAR ref V03 arg3 [000145] ------------ arg2 \--* LCL_VAR ref V04 arg4 Initializing arg info for 146.CALL: ArgTable for 146.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 143.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 144.LCL_VAR ref, 1 reg: rsi, align=1] fgArgTabEntry[arg 2 145.LCL_VAR ref, 1 reg: rdx, align=1] Morphing args for 146.CALL: fgMorphTree (before 106): [000143] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (after 106): [000143] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (before 107): [000144] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (after 107): [000144] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (before 108): [000145] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (after 108): [000145] ------------ * LCL_VAR ref V04 arg4 argSlots=3, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000143] -----+------ * LCL_VAR ref V02 arg2 Replaced with placeholder node: [000322] ----------L- * ARGPLACE ref Deferred argument ('rsi'): [000144] -----+------ * LCL_VAR ref V03 arg3 Replaced with placeholder node: [000323] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000145] -----+------ * LCL_VAR ref V04 arg4 Replaced with placeholder node: [000324] ----------L- * ARGPLACE ref Shuffled argument table: rdi rsi rdx ArgTable for 146.CALL after fgMorphArgs: fgArgTabEntry[arg 0 143.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 144.LCL_VAR ref, 1 reg: rsi, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 2 145.LCL_VAR ref, 1 reg: rdx, align=1, lateArgInx=2, processed] fgMorphTree (after 105): [000146] --CXG------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] -----+------ arg0 in rdi +--* LCL_VAR ref V02 arg2 [000144] -----+------ arg1 in rsi +--* LCL_VAR ref V03 arg3 [000145] -----+------ arg2 in rdx \--* LCL_VAR ref V04 arg4 fgMorphTree (after 104): [000148] --CXG------- * CAST int <- bool <- int [000146] --CXG+------ \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] -----+------ arg0 in rdi +--* LCL_VAR ref V02 arg2 [000144] -----+------ arg1 in rsi +--* LCL_VAR ref V03 arg3 [000145] -----+------ arg2 in rdx \--* LCL_VAR ref V04 arg4 fgMorphTree (before 109): [000149] ------------ * CNS_INT int 0 fgMorphTree (after 109): [000149] ------------ * CNS_INT int 0 fgMorphTree (after 103): [000150] J-CXG--N---- * NE int [000148] --CXG+------ +--* CAST int <- bool <- int [000146] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] -----+------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 [000144] -----+------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 [000145] -----+------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 [000149] -----+------ \--* CNS_INT int 0 fgMorphTree (after 102): [000151] --CXG------- * JTRUE void [000150] J-CXG+-N---- \--* NE int [000148] --CXG+------ +--* CAST int <- bool <- int [000146] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] -----+------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 [000144] -----+------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 [000145] -----+------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 [000149] -----+------ \--* CNS_INT int 0 fgMorphTree BB11, STMT00031 (after) [000151] --CXG+------ * JTRUE void [000150] J-CXG+-N---- \--* NE int [000148] --CXG+------ +--* CAST int <- bool <- int [000146] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] -----+------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 [000144] -----+------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 [000145] -----+------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 [000149] -----+------ \--* CNS_INT int 0 Morphing BB12 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB12, STMT00032 (before) [000154] -A---------- * ASG int [000153] D------N---- +--* LCL_VAR int V07 loc1 [000152] ------------ \--* CNS_INT int 0 fgMorphTree (before 110): [000154] -A---------- * ASG int [000153] D------N---- +--* LCL_VAR int V07 loc1 [000152] ------------ \--* CNS_INT int 0 fgMorphTree (before 111): [000153] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (after 111): [000153] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (before 112): [000325] ------------ * CAST int <- bool <- int [000152] ------------ \--* CNS_INT int 0 fgMorphTree (before 113): [000152] ------------ * CNS_INT int 0 fgMorphTree (after 113): [000152] ------------ * CNS_INT int 0 fgMorphTree (after 112): [000152] -----+------ * CNS_INT int 0 fgMorphTree (after 110): [000154] -A---------- * ASG int [000153] D----+-N---- +--* LCL_VAR int V07 loc1 [000152] -----+------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000154] -A---------- * ASG int In BB12 New Local Constant Assertion: V07 == 0 index=#01, mask=0000000000000001 Morphing BB13 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB13, STMT00007 (before) [000034] --C-G------- * JTRUE void [000033] --C-G------- \--* EQ int [000031] --C-G------- +--* CAST int <- bool <- int [000030] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000032] ------------ \--* CNS_INT int 0 fgMorphTree (before 114): [000034] --C-G------- * JTRUE void [000033] --C-G------- \--* EQ int [000031] --C-G------- +--* CAST int <- bool <- int [000030] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000032] ------------ \--* CNS_INT int 0 fgMorphTree (before 115): [000033] J-C-G--N---- * EQ int [000031] --C-G------- +--* CAST int <- bool <- int [000030] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] ------------ this in rdi | \--* LCL_VAR ref V02 arg2 [000032] ------------ \--* CNS_INT int 0 fgMorphTree (before 116): [000031] --C-G------- * CAST int <- bool <- int [000030] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] ------------ this in rdi \--* LCL_VAR ref V02 arg2 fgMorphTree (before 117): [000030] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] ------------ this in rdi \--* LCL_VAR ref V02 arg2 Initializing arg info for 30.CALL: ArgTable for 30.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 29.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 326.CNS_INT long, 1 reg: r11, align=1, isNonStandard] Morphing args for 30.CALL: fgMorphTree (before 118): [000029] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (after 118): [000029] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (before 119): [000326] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (after 119): [000326] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000029] -----+------ * LCL_VAR ref V02 arg2 Replaced with placeholder node: [000327] ----------L- * ARGPLACE ref Deferred argument ('r11'): [000326] -----+------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 Replaced with placeholder node: [000328] ----------L- * ARGPLACE long Shuffled argument table: rdi r11 ArgTable for 30.CALL after fgMorphArgs: fgArgTabEntry[arg 0 29.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 326.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 117): [000030] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] -----+------ this in rdi +--* LCL_VAR ref V02 arg2 [000326] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 GenTreeNode creates assertion: [000030] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint In BB13 New Local Constant Assertion: V02 != null index=#01, mask=0000000000000001 fgMorphTree (after 116): [000031] --CXG------- * CAST int <- bool <- int [000030] --CXG+------ \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] -----+------ this in rdi +--* LCL_VAR ref V02 arg2 [000326] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (before 120): [000032] ------------ * CNS_INT int 0 fgMorphTree (after 120): [000032] ------------ * CNS_INT int 0 fgMorphTree (after 115): [000033] J-CXG--N---- * EQ int [000031] --CXG+------ +--* CAST int <- bool <- int [000030] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000326] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000032] -----+------ \--* CNS_INT int 0 fgMorphTree (after 114): [000034] --CXG------- * JTRUE void [000033] J-CXG+-N---- \--* EQ int [000031] --CXG+------ +--* CAST int <- bool <- int [000030] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000326] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000032] -----+------ \--* CNS_INT int 0 fgMorphTree BB13, STMT00007 (after) [000034] --CXG+------ * JTRUE void [000033] J-CXG+-N---- \--* EQ int [000031] --CXG+------ +--* CAST int <- bool <- int [000030] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000326] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000032] -----+------ \--* CNS_INT int 0 Morphing BB14 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB14, STMT00028 (before) [000139] --C-G------- * JTRUE void [000138] --C-G------- \--* NE int [000136] --C-G------- +--* CAST int <- bool <- int [000135] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000131] ------------ arg1 | +--* LCL_VAR ref V02 arg2 [000132] ------------ arg2 | +--* LCL_VAR ref V03 arg3 [000133] ------------ arg3 | +--* LCL_VAR ref V04 arg4 [000134] ------------ arg4 | \--* LCL_VAR byref V05 arg5 [000137] ------------ \--* CNS_INT int 0 fgMorphTree (before 121): [000139] --C-G------- * JTRUE void [000138] --C-G------- \--* NE int [000136] --C-G------- +--* CAST int <- bool <- int [000135] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000131] ------------ arg1 | +--* LCL_VAR ref V02 arg2 [000132] ------------ arg2 | +--* LCL_VAR ref V03 arg3 [000133] ------------ arg3 | +--* LCL_VAR ref V04 arg4 [000134] ------------ arg4 | \--* LCL_VAR byref V05 arg5 [000137] ------------ \--* CNS_INT int 0 fgMorphTree (before 122): [000138] J-C-G--N---- * NE int [000136] --C-G------- +--* CAST int <- bool <- int [000135] --C-G------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] ------------ arg0 | +--* LCL_VAR ref V00 arg0 [000131] ------------ arg1 | +--* LCL_VAR ref V02 arg2 [000132] ------------ arg2 | +--* LCL_VAR ref V03 arg3 [000133] ------------ arg3 | +--* LCL_VAR ref V04 arg4 [000134] ------------ arg4 | \--* LCL_VAR byref V05 arg5 [000137] ------------ \--* CNS_INT int 0 fgMorphTree (before 123): [000136] --C-G------- * CAST int <- bool <- int [000135] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] ------------ arg0 +--* LCL_VAR ref V00 arg0 [000131] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000132] ------------ arg2 +--* LCL_VAR ref V03 arg3 [000133] ------------ arg3 +--* LCL_VAR ref V04 arg4 [000134] ------------ arg4 \--* LCL_VAR byref V05 arg5 fgMorphTree (before 124): [000135] --C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] ------------ arg0 +--* LCL_VAR ref V00 arg0 [000131] ------------ arg1 +--* LCL_VAR ref V02 arg2 [000132] ------------ arg2 +--* LCL_VAR ref V03 arg3 [000133] ------------ arg3 +--* LCL_VAR ref V04 arg4 [000134] ------------ arg4 \--* LCL_VAR byref V05 arg5 Initializing arg info for 135.CALL: ArgTable for 135.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 130.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 131.LCL_VAR ref, 1 reg: rsi, align=1] fgArgTabEntry[arg 2 132.LCL_VAR ref, 1 reg: rdx, align=1] fgArgTabEntry[arg 3 133.LCL_VAR ref, 1 reg: rcx, align=1] fgArgTabEntry[arg 4 134.LCL_VAR byref, 1 reg: r8, align=1] Morphing args for 135.CALL: fgMorphTree (before 125): [000130] ------------ * LCL_VAR ref V00 arg0 fgMorphTree (after 125): [000130] ------------ * LCL_VAR ref V00 arg0 fgMorphTree (before 126): [000131] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (after 126): [000131] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (before 127): [000132] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (after 127): [000132] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (before 128): [000133] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (after 128): [000133] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (before 129): [000134] ------------ * LCL_VAR byref V05 arg5 fgMorphTree (after 129): [000134] ------------ * LCL_VAR byref V05 arg5 argSlots=5, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000130] -----+------ * LCL_VAR ref V00 arg0 Replaced with placeholder node: [000329] ----------L- * ARGPLACE ref Deferred argument ('rsi'): [000131] -----+------ * LCL_VAR ref V02 arg2 Replaced with placeholder node: [000330] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000132] -----+------ * LCL_VAR ref V03 arg3 Replaced with placeholder node: [000331] ----------L- * ARGPLACE ref Deferred argument ('rcx'): [000133] -----+------ * LCL_VAR ref V04 arg4 Replaced with placeholder node: [000332] ----------L- * ARGPLACE ref Deferred argument ('r8'): [000134] -----+------ * LCL_VAR byref V05 arg5 Replaced with placeholder node: [000333] ----------L- * ARGPLACE byref Shuffled argument table: rdi rsi rdx rcx r8 ArgTable for 135.CALL after fgMorphArgs: fgArgTabEntry[arg 0 130.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 131.LCL_VAR ref, 1 reg: rsi, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 2 132.LCL_VAR ref, 1 reg: rdx, align=1, lateArgInx=2, processed] fgArgTabEntry[arg 3 133.LCL_VAR ref, 1 reg: rcx, align=1, lateArgInx=3, processed] fgArgTabEntry[arg 4 134.LCL_VAR byref, 1 reg: r8, align=1, lateArgInx=4, processed] fgMorphTree (after 124): [000135] --CXG------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] -----+------ arg0 in rdi +--* LCL_VAR ref V00 arg0 [000131] -----+------ arg1 in rsi +--* LCL_VAR ref V02 arg2 [000132] -----+------ arg2 in rdx +--* LCL_VAR ref V03 arg3 [000133] -----+------ arg3 in rcx +--* LCL_VAR ref V04 arg4 [000134] -----+------ arg4 in r8 \--* LCL_VAR byref V05 arg5 fgMorphTree (after 123): [000136] --CXG------- * CAST int <- bool <- int [000135] --CXG+------ \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] -----+------ arg0 in rdi +--* LCL_VAR ref V00 arg0 [000131] -----+------ arg1 in rsi +--* LCL_VAR ref V02 arg2 [000132] -----+------ arg2 in rdx +--* LCL_VAR ref V03 arg3 [000133] -----+------ arg3 in rcx +--* LCL_VAR ref V04 arg4 [000134] -----+------ arg4 in r8 \--* LCL_VAR byref V05 arg5 fgMorphTree (before 130): [000137] ------------ * CNS_INT int 0 fgMorphTree (after 130): [000137] ------------ * CNS_INT int 0 fgMorphTree (after 122): [000138] J-CXG--N---- * NE int [000136] --CXG+------ +--* CAST int <- bool <- int [000135] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] -----+------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 [000131] -----+------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 [000132] -----+------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 [000133] -----+------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 [000134] -----+------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 [000137] -----+------ \--* CNS_INT int 0 fgMorphTree (after 121): [000139] --CXG------- * JTRUE void [000138] J-CXG+-N---- \--* NE int [000136] --CXG+------ +--* CAST int <- bool <- int [000135] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] -----+------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 [000131] -----+------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 [000132] -----+------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 [000133] -----+------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 [000134] -----+------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 [000137] -----+------ \--* CNS_INT int 0 fgMorphTree BB14, STMT00028 (after) [000139] --CXG+------ * JTRUE void [000138] J-CXG+-N---- \--* NE int [000136] --CXG+------ +--* CAST int <- bool <- int [000135] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] -----+------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 [000131] -----+------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 [000132] -----+------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 [000133] -----+------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 [000134] -----+------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 [000137] -----+------ \--* CNS_INT int 0 Morphing BB15 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB15, STMT00029 (before) [000142] -A---------- * ASG int [000141] D------N---- +--* LCL_VAR int V07 loc1 [000140] ------------ \--* CNS_INT int 0 fgMorphTree (before 131): [000142] -A---------- * ASG int [000141] D------N---- +--* LCL_VAR int V07 loc1 [000140] ------------ \--* CNS_INT int 0 fgMorphTree (before 132): [000141] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (after 132): [000141] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (before 133): [000334] ------------ * CAST int <- bool <- int [000140] ------------ \--* CNS_INT int 0 fgMorphTree (before 134): [000140] ------------ * CNS_INT int 0 fgMorphTree (after 134): [000140] ------------ * CNS_INT int 0 fgMorphTree (after 133): [000140] -----+------ * CNS_INT int 0 fgMorphTree (after 131): [000142] -A---------- * ASG int [000141] D----+-N---- +--* LCL_VAR int V07 loc1 [000140] -----+------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000142] -A---------- * ASG int In BB15 New Local Constant Assertion: V07 == 0 index=#01, mask=0000000000000001 Morphing BB16 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB16, STMT00009 (before) [000042] -AC--------- * ASG ref [000041] ------------ +--* IND ref [000040] ------------ | \--* ADDR byref [000039] -------N---- | \--* LCL_VAR struct(AX)(P) V09 loc3 | \--* ref V09.array (offs=0x00) -> V23 tmp12 [000037] --C-G------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] ------------ arg1 \--* LCL_VAR byref V05 arg5 fgMorphTree (before 135): [000042] -AC--------- * ASG ref [000041] ------------ +--* IND ref [000040] ------------ | \--* ADDR byref [000039] -------N---- | \--* LCL_VAR struct(AX)(P) V09 loc3 | \--* ref V09.array (offs=0x00) -> V23 tmp12 [000037] --C-G------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] ------------ arg1 \--* LCL_VAR byref V05 arg5 fgMorphTree (before 136): [000041] -------N---- * IND ref [000040] ------------ \--* ADDR byref [000039] -------N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 fgMorphTree (before 137): [000040] ------------ * ADDR byref [000039] -------N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 fgMorphTree (before 138): [000039] -------N---- * LCL_VAR struct(AX)(P) V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 fgMorphTree (after 138): [000039] ----G--N---- * LCL_VAR struct(AX)(P) V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 fgMorphTree (after 137): [000040] ------------ * ADDR byref [000039] ----G+-N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 fgMorphTree (after 136): [000039] ----G+-N---- * LCL_VAR ref (AX) V23 tmp12 fgMorphTree (before 139): [000037] --C-G------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] ------------ arg1 \--* LCL_VAR byref V05 arg5 Initializing arg info for 37.CALL: ArgTable for 37.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 35.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 36.LCL_VAR byref, 1 reg: rsi, align=1] Morphing args for 37.CALL: fgMorphTree (before 140): [000035] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (after 140): [000035] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (before 141): [000036] ------------ * LCL_VAR byref V05 arg5 fgMorphTree (after 141): [000036] ------------ * LCL_VAR byref V05 arg5 argSlots=2, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000035] -----+------ * LCL_VAR ref V02 arg2 Replaced with placeholder node: [000335] ----------L- * ARGPLACE ref Deferred argument ('rsi'): [000036] -----+------ * LCL_VAR byref V05 arg5 Replaced with placeholder node: [000336] ----------L- * ARGPLACE byref Shuffled argument table: rdi rsi ArgTable for 37.CALL after fgMorphArgs: fgArgTabEntry[arg 0 35.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 36.LCL_VAR byref, 1 reg: rsi, align=1, lateArgInx=1, processed] fgMorphTree (after 139): [000037] --CXG------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics [000035] -----+------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] -----+------ arg1 in rsi \--* LCL_VAR byref V05 arg5 GenTreeNode creates assertion: [000037] --CXG------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics In BB16 New Local Constant Assertion: V02 != null index=#01, mask=0000000000000001 fgMorphTree (after 135): [000042] -ACXG------- * ASG ref [000039] D---G+-N---- +--* LCL_VAR ref (AX) V23 tmp12 [000037] --CXG+------ \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics [000035] -----+------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] -----+------ arg1 in rsi \--* LCL_VAR byref V05 arg5 fgMorphTree BB16, STMT00009 (after) [000042] -ACXG+------ * ASG ref [000039] D---G+-N---- +--* LCL_VAR ref (AX) V23 tmp12 [000037] --CXG+------ \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics [000035] -----+------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] -----+------ arg1 in rsi \--* LCL_VAR byref V05 arg5 fgMorphTree BB16, STMT00010 (before) [000050] -AC-G------- * ASG struct (copy) [000048] D------N---- +--* LCL_VAR struct V12 tmp1 [000045] --C-G------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA [000044] ------------ this in rdi +--* ADDR byref [000043] -------N---- | \--* LCL_VAR struct(AX)(P) V09 loc3 | \--* ref V09.array (offs=0x00) -> V23 tmp12 [000047] n----------- arg1 \--* IND long [000046] ------------ \--* CNS_INT(h) long 0xd1ffab1e class fgMorphTree (before 142): [000050] -AC-G------- * ASG struct (copy) [000048] D------N---- +--* LCL_VAR struct V12 tmp1 [000045] --C-G------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA [000044] ------------ this in rdi +--* ADDR byref [000043] -------N---- | \--* LCL_VAR struct(AX)(P) V09 loc3 | \--* ref V09.array (offs=0x00) -> V23 tmp12 [000047] n----------- arg1 \--* IND long [000046] ------------ \--* CNS_INT(h) long 0xd1ffab1e class fgMorphTree (before 143): [000048] D------N---- * LCL_VAR struct V12 tmp1 fgMorphTree (after 143): [000048] D------N---- * LCL_VAR struct V12 tmp1 fgMorphTree (before 144): [000045] --C-G------- * CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA [000044] ------------ this in rdi +--* ADDR byref [000043] -------N---- | \--* LCL_VAR struct(AX)(P) V09 loc3 | \--* ref V09.array (offs=0x00) -> V23 tmp12 [000047] n----------- arg1 \--* IND long [000046] ------------ \--* CNS_INT(h) long 0xd1ffab1e class **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (System.Collections.Immutable.ImmutableArray`1+Enumerator[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Initializing arg info for 45.CALL: ArgTable for 45.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 44.ADDR byref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 47.IND long, 1 reg: rsi, align=1] Morphing args for 45.CALL: fgMorphTree (before 145): [000044] ------------ * ADDR byref [000043] -------N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 fgMorphTree (before 146): [000043] -------N---- * LCL_VAR struct(AX)(P) V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 fgMorphTree (after 146): [000043] ----G--N---- * LCL_VAR struct(AX)(P) V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 fgMorphTree (after 145): [000044] ------------ * ADDR byref [000043] ----G+-N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 fgMorphTree (before 147): [000047] n----------- * IND long [000046] ------------ \--* CNS_INT(h) long 0xd1ffab1e class fgMorphTree (before 148): [000046] ------------ * CNS_INT(h) long 0xd1ffab1e class fgMorphTree (after 148): [000046] ------------ * CNS_INT(h) long 0xd1ffab1e class fgMorphTree (after 147): [000047] n----------- * IND long [000046] -----+------ \--* CNS_INT(h) long 0xd1ffab1e class argSlots=2, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rsi'): ( 5, 12) [000047] n----------- * IND long ( 3, 10) [000046] ------------ \--* CNS_INT(h) long 0xd1ffab1e class Replaced with placeholder node: [000337] ----------L- * ARGPLACE long Deferred argument ('rdi'): ( 3, 3) [000044] ------------ * ADDR byref ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 Replaced with placeholder node: [000338] ----------L- * ARGPLACE byref Shuffled argument table: rsi rdi ArgTable for 45.CALL after fgMorphArgs: fgArgTabEntry[arg 1 47.IND long, 1 reg: rsi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 0 44.ADDR byref, 1 reg: rdi, align=1, lateArgInx=1, processed] fgMorphTree (after 144): [000045] --CXG------- * CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 fgMorphCopyBlock: not morphing a multireg call return fgMorphTree (after 142): [000050] -ACXG------- * ASG struct (copy) [000048] D----+-N---- +--* LCL_VAR struct V12 tmp1 [000045] --CXG+------ \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 fgMorphTree BB16, STMT00010 (after) [000050] -ACXG+------ * ASG struct (copy) [000048] D----+-N---- +--* LCL_VAR struct V12 tmp1 [000045] --CXG+------ \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 fgMorphTree BB16, STMT00011 (before) [000054] -A---------- * ASG struct (copy) [000052] D------N---- +--* LCL_VAR struct(AX)(P) V08 loc2 +--* ref V08._array (offs=0x00) -> V21 tmp10 +--* int V08._index (offs=0x08) -> V22 tmp11 [000051] -------N---- \--* LCL_VAR struct V12 tmp1 fgMorphTree (before 149): [000054] -A---------- * ASG struct (copy) [000052] D------N---- +--* LCL_VAR struct(AX)(P) V08 loc2 +--* ref V08._array (offs=0x00) -> V21 tmp10 +--* int V08._index (offs=0x08) -> V22 tmp11 [000051] -------N---- \--* LCL_VAR struct V12 tmp1 fgMorphTree (before 150): [000052] D------N---- * LCL_VAR struct(AX)(P) V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (after 150): [000052] D---G--N---- * LCL_VAR struct(AX)(P) V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (before 151): [000051] -------N---- * LCL_VAR struct V12 tmp1 fgMorphTree (after 151): [000051] -------N---- * LCL_VAR struct V12 tmp1 fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000052] D---G+-N---- * LCL_VAR struct(AX)(P) V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 fgMorphBlkNode after: [000052] D---G+-N---- * LCL_VAR struct(AX)(P) V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 fgMorphBlkNode for src tree, before: [000051] -----+-N---- * LCL_VAR struct V12 tmp1 fgMorphBlkNode after: [000051] -----+-N---- * LCL_VAR struct V12 tmp1 block assignment to morph: [000054] -A--G------- * ASG struct (copy) [000052] D---G+-N---- +--* LCL_VAR struct(AX)(P) V08 loc2 +--* ref V08._array (offs=0x00) -> V21 tmp10 +--* int V08._index (offs=0x08) -> V22 tmp11 [000051] -----+-N---- \--* LCL_VAR struct V12 tmp1 (destDoFldAsg=true) using field by field assignments. Local V12 should not be enregistered because: written in a block op fgMorphTree (before 152): [000340] ------------ * ADDR byref [000341] -------N---- \--* LCL_VAR struct V12 tmp1 fgMorphTree (before 153): [000341] -------N---- * LCL_VAR struct V12 tmp1 fgMorphTree (after 153): [000341] -------N---- * LCL_VAR struct V12 tmp1 fgMorphTree (after 152): [000340] ------------ * ADDR byref [000341] -----+-N---- \--* LCL_VAR struct V12 tmp1 lvaGrabTemp returning 25 (V25 tmp14) called for BlockOp address local. Local V12 should not be enregistered because: it is address exposed fgAddFieldSeqForZeroOffset for Fseq[_array] addr (Before) [000345] ------------ LCL_VAR byref (After) [000345] ------------ LCL_VAR byref Zero Fseq[_array] fgMorphCopyBlock (after): [000355] -A-XG+------ * COMMA void [000348] -A-XG------- +--* COMMA void [000343] -A---------- | +--* ASG byref [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 [000340] -----+------ | | \--* ADDR byref [000341] -----+-N---- | | \--* LCL_VAR struct(AX) V12 tmp1 [000347] -A-XG------- | \--* ASG ref [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 [000346] ---X-------- | \--* IND ref [000345] ------------ | \--* LCL_VAR byref V25 tmp14 Zero Fseq[_array] [000354] -A-XG------- \--* ASG int [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 [000353] ---X-------- \--* IND int [000352] ------------ \--* ADD byref [000350] ------------ +--* LCL_VAR byref V25 tmp14 [000351] ------------ \--* CNS_INT long 8 Fseq[_index] fgMorphTree (after 149): [000355] -A-XG+------ * COMMA void [000348] -A-XG------- +--* COMMA void [000343] -A---------- | +--* ASG byref [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 [000340] -----+------ | | \--* ADDR byref [000341] -----+-N---- | | \--* LCL_VAR struct(AX) V12 tmp1 [000347] -A-XG------- | \--* ASG ref [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 [000346] ---X-------- | \--* IND ref [000345] ------------ | \--* LCL_VAR byref V25 tmp14 Zero Fseq[_array] [000354] -A-XG------- \--* ASG int [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 [000353] ---X-------- \--* IND int [000352] ------------ \--* ADD byref [000350] ------------ +--* LCL_VAR byref V25 tmp14 [000351] ------------ \--* CNS_INT long 8 Fseq[_index] fgMorphTree BB16, STMT00011 (after) [000355] -A-XG+------ * COMMA void [000348] -A-XG------- +--* COMMA void [000343] -A---------- | +--* ASG byref [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 [000340] -----+------ | | \--* ADDR byref [000341] -----+-N---- | | \--* LCL_VAR struct(AX) V12 tmp1 [000347] -A-XG------- | \--* ASG ref [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 [000346] ---X-------- | \--* IND ref [000345] ------------ | \--* LCL_VAR byref V25 tmp14 Zero Fseq[_array] [000354] -A-XG------- \--* ASG int [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 [000353] ---X-------- \--* IND int [000352] ------------ \--* ADD byref [000350] ------------ +--* LCL_VAR byref V25 tmp14 [000351] ------------ \--* CNS_INT long 8 Fseq[_index] Morphing BB17 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB17, STMT00013 (before) [000073] -AC-G------- * ASG struct (copy) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 [000070] --C-G------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000066] --C-G------- this in rdi +--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current [000065] ------------ this in rdi | +--* ADDR byref [000064] -------N---- | | \--* LCL_VAR struct(AX)(P) V08 loc2 | | \--* ref V08._array (offs=0x00) -> V21 tmp10 | | \--* int V08._index (offs=0x08) -> V22 tmp11 [000068] n----------- arg1 | \--* IND long [000067] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000069] ------------ arg1 \--* LCL_VAR ref V01 arg1 fgMorphTree (before 154): [000073] -AC-G------- * ASG struct (copy) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 [000070] --C-G------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000066] --C-G------- this in rdi +--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current [000065] ------------ this in rdi | +--* ADDR byref [000064] -------N---- | | \--* LCL_VAR struct(AX)(P) V08 loc2 | | \--* ref V08._array (offs=0x00) -> V21 tmp10 | | \--* int V08._index (offs=0x08) -> V22 tmp11 [000068] n----------- arg1 | \--* IND long [000067] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000069] ------------ arg1 \--* LCL_VAR ref V01 arg1 fgMorphTree (before 155): [000071] D------N---- * LCL_VAR struct V13 tmp2 fgMorphTree (after 155): [000071] D------N---- * LCL_VAR struct V13 tmp2 fgMorphTree (before 156): [000070] --C-G------- * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000066] --C-G------- this in rdi +--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current [000065] ------------ this in rdi | +--* ADDR byref [000064] -------N---- | | \--* LCL_VAR struct(AX)(P) V08 loc2 | | \--* ref V08._array (offs=0x00) -> V21 tmp10 | | \--* int V08._index (offs=0x08) -> V22 tmp11 [000068] n----------- arg1 | \--* IND long [000067] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000069] ------------ arg1 \--* LCL_VAR ref V01 arg1 **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeWithModifiers), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: IntegerReference, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: IntegerReference, byteSize: 8, byteOffset: 8 Initializing arg info for 70.CALL: ArgTable for 70.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 66.CALL ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 356.CNS_INT long, 1 reg: r11, align=1, isNonStandard] fgArgTabEntry[arg 2 69.LCL_VAR ref, 1 reg: rsi, align=1] Morphing args for 70.CALL: fgMorphTree (before 157): [000066] --C-G------- * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current [000065] ------------ this in rdi +--* ADDR byref [000064] -------N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 [000068] n----------- arg1 \--* IND long [000067] ------------ \--* CNS_INT(h) long 0xd1ffab1e class Initializing arg info for 66.CALL: ArgTable for 66.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 65.ADDR byref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 68.IND long, 1 reg: rsi, align=1] Morphing args for 66.CALL: fgMorphTree (before 158): [000065] ------------ * ADDR byref [000064] -------N---- \--* LCL_VAR struct(AX)(P) V08 loc2 \--* ref V08._array (offs=0x00) -> V21 tmp10 \--* int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (before 159): [000064] -------N---- * LCL_VAR struct(AX)(P) V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (after 159): [000064] ----G--N---- * LCL_VAR struct(AX)(P) V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (after 158): [000065] ------------ * ADDR byref [000064] ----G+-N---- \--* LCL_VAR struct(AX)(P) V08 loc2 \--* ref V08._array (offs=0x00) -> V21 tmp10 \--* int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (before 160): [000068] n----------- * IND long [000067] ------------ \--* CNS_INT(h) long 0xd1ffab1e class fgMorphTree (before 161): [000067] ------------ * CNS_INT(h) long 0xd1ffab1e class fgMorphTree (after 161): [000067] ------------ * CNS_INT(h) long 0xd1ffab1e class fgMorphTree (after 160): [000068] n----------- * IND long [000067] -----+------ \--* CNS_INT(h) long 0xd1ffab1e class argSlots=2, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rsi'): ( 5, 12) [000068] n----------- * IND long ( 3, 10) [000067] ------------ \--* CNS_INT(h) long 0xd1ffab1e class Replaced with placeholder node: [000357] ----------L- * ARGPLACE long Deferred argument ('rdi'): ( 3, 3) [000065] ------------ * ADDR byref ( 3, 2) [000064] ----G--N---- \--* LCL_VAR struct(AX)(P) V08 loc2 \--* ref V08._array (offs=0x00) -> V21 tmp10 \--* int V08._index (offs=0x08) -> V22 tmp11 Replaced with placeholder node: [000358] ----------L- * ARGPLACE byref Shuffled argument table: rsi rdi ArgTable for 66.CALL after fgMorphArgs: fgArgTabEntry[arg 1 68.IND long, 1 reg: rsi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 0 65.ADDR byref, 1 reg: rdi, align=1, lateArgInx=1, processed] fgMorphTree (after 157): [000066] --CXG------- * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current ( 5, 12) [000068] n----------- arg1 in rsi +--* IND long ( 3, 10) [000067] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000065] ------------ this in rdi \--* ADDR byref ( 3, 2) [000064] ----G--N---- \--* LCL_VAR struct(AX)(P) V08 loc2 \--* ref V08._array (offs=0x00) -> V21 tmp10 \--* int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (before 162): [000356] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (after 162): [000356] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (before 163): [000069] ------------ * LCL_VAR ref V01 arg1 fgMorphTree (after 163): [000069] ------------ * LCL_VAR ref V01 arg1 argSlots=2, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Argument with 'side effect'... [000066] --CXG+------ * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current ( 5, 12) [000068] n----------- arg1 in rsi +--* IND long ( 3, 10) [000067] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000065] ------------ this in rdi \--* ADDR byref ( 3, 2) [000064] ----G--N---- \--* LCL_VAR struct(AX)(P) V08 loc2 \--* ref V08._array (offs=0x00) -> V21 tmp10 \--* int V08._index (offs=0x08) -> V22 tmp11 lvaGrabTemp returning 26 (V26 tmp15) called for argument with side effect. Evaluate to a temp: [000360] -ACXG-----L- * ASG ref [000359] D------N---- +--* LCL_VAR ref V26 tmp15 [000066] --CXG+------ \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current ( 5, 12) [000068] n----------- arg1 in rsi +--* IND long ( 3, 10) [000067] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000065] ------------ this in rdi \--* ADDR byref ( 3, 2) [000064] ----G--N---- \--* LCL_VAR struct(AX)(P) V08 loc2 \--* ref V08._array (offs=0x00) -> V21 tmp10 \--* int V08._index (offs=0x08) -> V22 tmp11 Deferred argument ('rsi'): [000069] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000362] ----------L- * ARGPLACE ref Deferred argument ('r11'): [000356] -----+------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 Replaced with placeholder node: [000363] ----------L- * ARGPLACE long Shuffled argument table: rdi rsi r11 ArgTable for 70.CALL after fgMorphArgs: fgArgTabEntry[arg 0 361.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, tmpNum=V26, isTmp, processed] fgArgTabEntry[arg 2 69.LCL_VAR ref, 1 reg: rsi, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 1 356.CNS_INT long, 1 reg: r11, align=1, lateArgInx=2, processed, isNonStandard] fgMorphTree (after 156): [000070] --CXG------- * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000360] -ACXG-----L- this SETUP +--* ASG ref [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 [000066] --CXG+------ | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 [000069] -----+------ arg2 in rsi +--* LCL_VAR ref V01 arg1 [000356] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 GenTreeNode creates assertion: [000070] --CXG------- * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA In BB17 New Local Constant Assertion: V26 != null index=#01, mask=0000000000000001 fgMorphCopyBlock: not morphing a multireg call return fgMorphTree (after 154): [000073] -ACXG------- * ASG struct (copy) [000071] D----+-N---- +--* LCL_VAR struct V13 tmp2 [000070] --CXG+------ \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000360] -ACXG-----L- this SETUP +--* ASG ref [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 [000066] --CXG+------ | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 [000069] -----+------ arg2 in rsi +--* LCL_VAR ref V01 arg1 [000356] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree BB17, STMT00013 (after) [000073] -ACXG+------ * ASG struct (copy) [000071] D----+-N---- +--* LCL_VAR struct V13 tmp2 [000070] --CXG+------ \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000360] -ACXG-----L- this SETUP +--* ASG ref [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 [000066] --CXG+------ | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 [000069] -----+------ arg2 in rsi +--* LCL_VAR ref V01 arg1 [000356] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree BB17, STMT00014 (before) [000078] -A---------- * ASG ref [000077] D------N---- +--* LCL_VAR ref V10 loc4 [000076] ------------ \--* LCL_FLD ref V13 tmp2 [+0] Fseq[Type] fgMorphTree (before 164): [000078] -A---------- * ASG ref [000077] D------N---- +--* LCL_VAR ref V10 loc4 [000076] ------------ \--* LCL_FLD ref V13 tmp2 [+0] Fseq[Type] fgMorphTree (before 165): [000077] D------N---- * LCL_VAR ref V10 loc4 fgMorphTree (after 165): [000077] D------N---- * LCL_VAR ref V10 loc4 fgMorphTree (before 166): [000076] ------------ * LCL_FLD ref V13 tmp2 [+0] Fseq[Type] fgMorphTree (after 166): [000076] ------------ * LCL_FLD ref V13 tmp2 [+0] Fseq[Type] fgMorphTree (after 164): [000078] -A---------- * ASG ref [000077] D----+-N---- +--* LCL_VAR ref V10 loc4 [000076] -----+------ \--* LCL_FLD ref V13 tmp2 [+0] Fseq[Type] fgMorphTree BB17, STMT00051 (before) [000245] -A---------- * ASG bool [000244] D------N---- +--* LCL_VAR bool V19 tmp8 [000243] ------------ \--* CNS_INT int 0 fgMorphTree (before 167): [000245] -A---------- * ASG bool [000244] D------N---- +--* LCL_VAR bool V19 tmp8 [000243] ------------ \--* CNS_INT int 0 fgMorphTree (before 168): [000244] D------N---- * LCL_VAR int V19 tmp8 fgMorphTree (after 168): [000244] D------N---- * LCL_VAR int V19 tmp8 fgMorphTree (before 169): [000364] ------------ * CAST int <- bool <- int [000243] ------------ \--* CNS_INT int 0 fgMorphTree (before 170): [000243] ------------ * CNS_INT int 0 fgMorphTree (after 170): [000243] ------------ * CNS_INT int 0 fgMorphTree (after 169): [000243] -----+------ * CNS_INT int 0 fgMorphTree (after 167): [000245] -A---------- * ASG bool [000244] D----+-N---- +--* LCL_VAR int V19 tmp8 [000243] -----+------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000245] -A---------- * ASG bool In BB17 New Local Constant Assertion: V19 == 0 index=#02, mask=0000000000000002 fgMorphTree BB17, STMT00046 (before) [000228] --C--------- * JTRUE void [000227] --C--------- \--* EQ int [000225] --C--------- +--* CAST int <- bool <- int [000249] --C-G------- | \--* EQ int [000247] --C-G------- | +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi | | \--* LCL_VAR ref V10 loc4 [000248] ------------ | \--* CNS_INT int 4 [000226] ------------ \--* CNS_INT int 0 fgMorphTree (before 171): [000228] --C--------- * JTRUE void [000227] --C--------- \--* EQ int [000225] --C--------- +--* CAST int <- bool <- int [000249] --C-G------- | \--* EQ int [000247] --C-G------- | +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi | | \--* LCL_VAR ref V10 loc4 [000248] ------------ | \--* CNS_INT int 4 [000226] ------------ \--* CNS_INT int 0 fgMorphTree (before 172): [000227] J-C----N---- * EQ int [000225] --C--------- +--* CAST int <- bool <- int [000249] --C-G------- | \--* EQ int [000247] --C-G------- | +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi | | \--* LCL_VAR ref V10 loc4 [000248] ------------ | \--* CNS_INT int 4 [000226] ------------ \--* CNS_INT int 0 fgMorphTree (before 173): [000225] --C--------- * CAST int <- bool <- int [000249] --C-G------- \--* EQ int [000247] --C-G------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi | \--* LCL_VAR ref V10 loc4 [000248] ------------ \--* CNS_INT int 4 fgMorphTree (before 174): [000249] --C-G------- * EQ int [000247] --C-G------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi | \--* LCL_VAR ref V10 loc4 [000248] ------------ \--* CNS_INT int 4 fgMorphTree (before 175): [000247] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] ------------ this in rdi \--* LCL_VAR ref V10 loc4 Initializing arg info for 247.CALL: ArgTable for 247.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 80.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 365.CNS_INT long, 1 reg: r11, align=1, isNonStandard] Morphing args for 247.CALL: fgMorphTree (before 176): [000080] ------------ * LCL_VAR ref V10 loc4 fgMorphTree (after 176): [000080] ------------ * LCL_VAR ref V10 loc4 fgMorphTree (before 177): [000365] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (after 177): [000365] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000080] -----+------ * LCL_VAR ref V10 loc4 Replaced with placeholder node: [000366] ----------L- * ARGPLACE ref Deferred argument ('r11'): [000365] -----+------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 Replaced with placeholder node: [000367] ----------L- * ARGPLACE long Shuffled argument table: rdi r11 ArgTable for 247.CALL after fgMorphArgs: fgArgTabEntry[arg 0 80.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 365.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 175): [000247] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] -----+------ this in rdi +--* LCL_VAR ref V10 loc4 [000365] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 GenTreeNode creates assertion: [000247] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind In BB17 New Local Constant Assertion: V10 != null index=#03, mask=0000000000000004 fgMorphTree (before 178): [000248] ------------ * CNS_INT int 4 fgMorphTree (after 178): [000248] ------------ * CNS_INT int 4 fgMorphTree (after 174): [000249] --CXG------- * EQ int [000247] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] -----+------ this in rdi | +--* LCL_VAR ref V10 loc4 [000365] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000248] -----+------ \--* CNS_INT int 4 fgMorphTree (after 173): [000249] --CXG+------ * EQ int [000247] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] -----+------ this in rdi | +--* LCL_VAR ref V10 loc4 [000365] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000248] -----+------ \--* CNS_INT int 4 fgMorphTree (before 179): [000226] ------------ * CNS_INT int 0 fgMorphTree (after 179): [000226] ------------ * CNS_INT int 0 fgMorphTree (after 172): [000249] J-CXG+-N---- * NE int [000247] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] -----+------ this in rdi | +--* LCL_VAR ref V10 loc4 [000365] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000248] -----+------ \--* CNS_INT int 4 fgMorphTree (after 171): [000228] --CXG------- * JTRUE void [000249] J-CXG+-N---- \--* NE int [000247] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] -----+------ this in rdi | +--* LCL_VAR ref V10 loc4 [000365] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000248] -----+------ \--* CNS_INT int 4 fgMorphTree BB17, STMT00046 (after) [000228] --CXG+------ * JTRUE void [000249] J-CXG+-N---- \--* NE int [000247] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] -----+------ this in rdi | +--* LCL_VAR ref V10 loc4 [000365] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000248] -----+------ \--* CNS_INT int 4 Morphing BB19 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB19, STMT00049 (before) [000239] --C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics [000237] ------------ arg0 +--* LCL_VAR ref V10 loc4 [000238] ------------ arg1 \--* LCL_VAR byref V05 arg5 fgMorphTree (before 180): [000239] --C-G------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics [000237] ------------ arg0 +--* LCL_VAR ref V10 loc4 [000238] ------------ arg1 \--* LCL_VAR byref V05 arg5 Initializing arg info for 239.CALL: ArgTable for 239.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 237.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 238.LCL_VAR byref, 1 reg: rsi, align=1] Morphing args for 239.CALL: fgMorphTree (before 181): [000237] ------------ * LCL_VAR ref V10 loc4 fgMorphTree (after 181): [000237] ------------ * LCL_VAR ref V10 loc4 fgMorphTree (before 182): [000238] ------------ * LCL_VAR byref V05 arg5 fgMorphTree (after 182): [000238] ------------ * LCL_VAR byref V05 arg5 argSlots=2, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000237] -----+------ * LCL_VAR ref V10 loc4 Replaced with placeholder node: [000368] ----------L- * ARGPLACE ref Deferred argument ('rsi'): [000238] -----+------ * LCL_VAR byref V05 arg5 Replaced with placeholder node: [000369] ----------L- * ARGPLACE byref Shuffled argument table: rdi rsi ArgTable for 239.CALL after fgMorphArgs: fgArgTabEntry[arg 0 237.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 238.LCL_VAR byref, 1 reg: rsi, align=1, lateArgInx=1, processed] fgMorphTree (after 180): [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics [000237] -----+------ arg0 in rdi +--* LCL_VAR ref V10 loc4 [000238] -----+------ arg1 in rsi \--* LCL_VAR byref V05 arg5 fgMorphTree BB19, STMT00049 (after) [000239] --CXG+------ * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics [000237] -----+------ arg0 in rdi +--* LCL_VAR ref V10 loc4 [000238] -----+------ arg1 in rsi \--* LCL_VAR byref V05 arg5 fgMorphTree BB19, STMT00050 (before) [000242] -A---------- * ASG bool [000241] D------N---- +--* LCL_VAR bool V19 tmp8 [000240] ------------ \--* CNS_INT int 0 fgMorphTree (before 183): [000242] -A---------- * ASG bool [000241] D------N---- +--* LCL_VAR bool V19 tmp8 [000240] ------------ \--* CNS_INT int 0 fgMorphTree (before 184): [000241] D------N---- * LCL_VAR int V19 tmp8 fgMorphTree (after 184): [000241] D------N---- * LCL_VAR int V19 tmp8 fgMorphTree (before 185): [000370] ------------ * CAST int <- bool <- int [000240] ------------ \--* CNS_INT int 0 fgMorphTree (before 186): [000240] ------------ * CNS_INT int 0 fgMorphTree (after 186): [000240] ------------ * CNS_INT int 0 fgMorphTree (after 185): [000240] -----+------ * CNS_INT int 0 fgMorphTree (after 183): [000242] -A---------- * ASG bool [000241] D----+-N---- +--* LCL_VAR int V19 tmp8 [000240] -----+------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000242] -A---------- * ASG bool In BB19 New Local Constant Assertion: V19 == 0 index=#01, mask=0000000000000001 Morphing BB20 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB20, STMT00048 (before) [000234] -AC--------- * ASG bool [000233] D------N---- +--* LCL_VAR bool V19 tmp8 [000232] --C--------- \--* CAST int <- bool <- int [000230] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000229] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 fgMorphTree (before 187): [000234] -AC--------- * ASG bool [000233] D------N---- +--* LCL_VAR bool V19 tmp8 [000232] --C--------- \--* CAST int <- bool <- int [000230] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000229] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 fgMorphTree (before 188): [000233] D------N---- * LCL_VAR int V19 tmp8 fgMorphTree (after 188): [000233] D------N---- * LCL_VAR int V19 tmp8 fgMorphTree (before 189): [000232] --C--------- * CAST int <- bool <- int [000230] --C-G------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000229] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 fgMorphTree (before 190): [000230] --C-G------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] ------------ arg0 +--* LCL_VAR ref V03 arg3 [000229] ------------ arg1 +--* LCL_VAR ref V10 loc4 [000081] ------------ arg2 \--* LCL_VAR byref V05 arg5 Initializing arg info for 230.CALL: ArgTable for 230.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 79.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 229.LCL_VAR ref, 1 reg: rsi, align=1] fgArgTabEntry[arg 2 81.LCL_VAR byref, 1 reg: rdx, align=1] Morphing args for 230.CALL: fgMorphTree (before 191): [000079] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (after 191): [000079] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (before 192): [000229] ------------ * LCL_VAR ref V10 loc4 fgMorphTree (after 192): [000229] ------------ * LCL_VAR ref V10 loc4 fgMorphTree (before 193): [000081] ------------ * LCL_VAR byref V05 arg5 fgMorphTree (after 193): [000081] ------------ * LCL_VAR byref V05 arg5 argSlots=3, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000079] -----+------ * LCL_VAR ref V03 arg3 Replaced with placeholder node: [000371] ----------L- * ARGPLACE ref Deferred argument ('rsi'): [000229] -----+------ * LCL_VAR ref V10 loc4 Replaced with placeholder node: [000372] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000081] -----+------ * LCL_VAR byref V05 arg5 Replaced with placeholder node: [000373] ----------L- * ARGPLACE byref Shuffled argument table: rdi rsi rdx ArgTable for 230.CALL after fgMorphArgs: fgArgTabEntry[arg 0 79.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 229.LCL_VAR ref, 1 reg: rsi, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 2 81.LCL_VAR byref, 1 reg: rdx, align=1, lateArgInx=2, processed] fgMorphTree (after 190): [000230] --CXG------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] -----+------ arg0 in rdi +--* LCL_VAR ref V03 arg3 [000229] -----+------ arg1 in rsi +--* LCL_VAR ref V10 loc4 [000081] -----+------ arg2 in rdx \--* LCL_VAR byref V05 arg5 fgMorphTree (after 189): [000232] --CXG------- * CAST int <- bool <- int [000230] --CXG+------ \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] -----+------ arg0 in rdi +--* LCL_VAR ref V03 arg3 [000229] -----+------ arg1 in rsi +--* LCL_VAR ref V10 loc4 [000081] -----+------ arg2 in rdx \--* LCL_VAR byref V05 arg5 fgMorphTree (after 187): [000234] -ACXG------- * ASG bool [000233] D----+-N---- +--* LCL_VAR int V19 tmp8 [000232] --CXG+------ \--* CAST int <- bool <- int [000230] --CXG+------ \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] -----+------ arg0 in rdi +--* LCL_VAR ref V03 arg3 [000229] -----+------ arg1 in rsi +--* LCL_VAR ref V10 loc4 [000081] -----+------ arg2 in rdx \--* LCL_VAR byref V05 arg5 GenTreeNode creates assertion: [000234] -ACXG------- * ASG bool In BB20 New Local Subrange Assertion: V19 in [0..1] index=#01, mask=0000000000000001 fgMorphTree BB20, STMT00048 (after) [000234] -ACXG+------ * ASG bool [000233] D----+-N---- +--* LCL_VAR int V19 tmp8 [000232] --CXG+------ \--* CAST int <- bool <- int [000230] --CXG+------ \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] -----+------ arg0 in rdi +--* LCL_VAR ref V03 arg3 [000229] -----+------ arg1 in rsi +--* LCL_VAR ref V10 loc4 [000081] -----+------ arg2 in rdx \--* LCL_VAR byref V05 arg5 Morphing BB21 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB21, STMT00016 (before) [000087] --C--------- * JTRUE void [000086] --C--------- \--* NE int [000084] --C--------- +--* CAST int <- bool <- int [000236] ------------ | \--* CAST int <- bool <- int [000235] ------------ | \--* LCL_VAR int V19 tmp8 [000085] ------------ \--* CNS_INT int 0 fgMorphTree (before 194): [000087] --C--------- * JTRUE void [000086] --C--------- \--* NE int [000084] --C--------- +--* CAST int <- bool <- int [000236] ------------ | \--* CAST int <- bool <- int [000235] ------------ | \--* LCL_VAR int V19 tmp8 [000085] ------------ \--* CNS_INT int 0 fgMorphTree (before 195): [000086] J-C----N---- * NE int [000084] --C--------- +--* CAST int <- bool <- int [000236] ------------ | \--* CAST int <- bool <- int [000235] ------------ | \--* LCL_VAR int V19 tmp8 [000085] ------------ \--* CNS_INT int 0 fgMorphTree (before 196): [000084] --C--------- * CAST int <- bool <- int [000236] ------------ \--* CAST int <- bool <- int [000235] ------------ \--* LCL_VAR int V19 tmp8 fgMorphTree (before 197): [000236] ------------ * CAST int <- bool <- int [000235] ------------ \--* LCL_VAR int V19 tmp8 fgMorphTree (before 198): [000235] ------------ * LCL_VAR int V19 tmp8 fgMorphTree (after 198): [000235] ------------ * LCL_VAR int V19 tmp8 fgMorphTree (after 197): [000235] -----+------ * LCL_VAR int V19 tmp8 fgMorphTree (after 196): [000235] -----+------ * LCL_VAR int V19 tmp8 fgMorphTree (before 199): [000085] ------------ * CNS_INT int 0 fgMorphTree (after 199): [000085] ------------ * CNS_INT int 0 fgMorphTree (after 195): [000086] J------N---- * NE int [000235] -----+------ +--* LCL_VAR int V19 tmp8 [000085] -----+------ \--* CNS_INT int 0 fgMorphTree (after 194): [000087] ------------ * JTRUE void [000086] J----+-N---- \--* NE int [000235] -----+------ +--* LCL_VAR int V19 tmp8 [000085] -----+------ \--* CNS_INT int 0 fgMorphTree BB21, STMT00016 (after) [000087] -----+------ * JTRUE void [000086] J----+-N---- \--* NE int [000235] -----+------ +--* LCL_VAR int V19 tmp8 [000085] -----+------ \--* CNS_INT int 0 Morphing BB23 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB23, STMT00017 (before) [000091] ------------ * JTRUE void [000090] ------------ \--* EQ int [000088] ------------ +--* LCL_VAR ref V04 arg4 [000089] ------------ \--* CNS_INT ref null fgMorphTree (before 200): [000091] ------------ * JTRUE void [000090] ------------ \--* EQ int [000088] ------------ +--* LCL_VAR ref V04 arg4 [000089] ------------ \--* CNS_INT ref null fgMorphTree (before 201): [000090] J------N---- * EQ int [000088] ------------ +--* LCL_VAR ref V04 arg4 [000089] ------------ \--* CNS_INT ref null fgMorphTree (before 202): [000088] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (after 202): [000088] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (before 203): [000089] ------------ * CNS_INT ref null fgMorphTree (after 203): [000089] ------------ * CNS_INT ref null fgMorphTree (after 201): [000090] J------N---- * EQ int [000088] -----+------ +--* LCL_VAR ref V04 arg4 [000089] -----+------ \--* CNS_INT ref null fgMorphTree (after 200): [000091] ------------ * JTRUE void [000090] J----+-N---- \--* EQ int [000088] -----+------ +--* LCL_VAR ref V04 arg4 [000089] -----+------ \--* CNS_INT ref null Morphing BB24 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB24, STMT00019 (before) [000101] -ACXG------- * ASG ref [000100] D------N---- +--* LCL_VAR ref V14 tmp3 [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000098] ------------ arg0 \--* CNS_INT long 2 fgMorphTree (before 204): [000101] -ACXG------- * ASG ref [000100] D------N---- +--* LCL_VAR ref V14 tmp3 [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000098] ------------ arg0 \--* CNS_INT long 2 fgMorphTree (before 205): [000100] D------N---- * LCL_VAR ref V14 tmp3 fgMorphTree (after 205): [000100] D------N---- * LCL_VAR ref V14 tmp3 fgMorphTree (before 206): [000099] --CXG------- * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000098] ------------ arg0 \--* CNS_INT long 2 Initializing arg info for 99.CALL: ArgTable for 99.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 98.CNS_INT long, 1 reg: rdi, align=1] Morphing args for 99.CALL: fgMorphTree (before 207): [000098] ------------ * CNS_INT long 2 fgMorphTree (after 207): [000098] ------------ * CNS_INT long 2 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000098] -----+------ * CNS_INT long 2 Replaced with placeholder node: [000374] ----------L- * ARGPLACE long Shuffled argument table: rdi ArgTable for 99.CALL after fgMorphArgs: fgArgTabEntry[arg 0 98.CNS_INT long, 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree (after 206): [000099] --CXG------- * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000098] -----+------ arg0 in rdi \--* CNS_INT long 2 fgMorphTree (after 204): [000101] -ACXG------- * ASG ref [000100] D----+-N---- +--* LCL_VAR ref V14 tmp3 [000099] --CXG+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000098] -----+------ arg0 in rdi \--* CNS_INT long 2 fgMorphTree BB24, STMT00019 (after) [000101] -ACXG+------ * ASG ref [000100] D----+-N---- +--* LCL_VAR ref V14 tmp3 [000099] --CXG+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000098] -----+------ arg0 in rdi \--* CNS_INT long 2 fgMorphTree BB24, STMT00020 (before) [000107] -A-XG------- * ASG ref [000106] ---XG--N---- +--* INDEX ref [000103] ------------ | +--* LCL_VAR ref V14 tmp3 [000104] ------------ | \--* CNS_INT int 0 [000105] ------------ \--* LCL_VAR ref V03 arg3 fgMorphTree (before 208): [000107] -A-XG------- * ASG ref [000106] ---XG--N---- +--* INDEX ref [000103] ------------ | +--* LCL_VAR ref V14 tmp3 [000104] ------------ | \--* CNS_INT int 0 [000105] ------------ \--* LCL_VAR ref V03 arg3 fgMorphTree (before 209): [000106] ---XG--N---- * INDEX ref [000103] ------------ +--* LCL_VAR ref V14 tmp3 [000104] ------------ \--* CNS_INT int 0 fgMorphTree (before 210): [000384] ---XG------- * COMMA ref [000378] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void [000104] ------------ | +--* CNS_INT int 0 [000377] ---X-------- | \--* ARR_LENGTH int [000103] ------------ | \--* LCL_VAR ref V14 tmp3 [000106] a--XG--N---- \--* IND ref [000383] ------------ \--* ADD byref [000375] ------------ +--* LCL_VAR ref V14 tmp3 [000382] ------------ \--* ADD long [000380] ------------ +--* MUL long [000376] ------------ | +--* CNS_INT long 0 [000379] -------N---- | \--* CNS_INT long 8 [000381] ------------ \--* CNS_INT long 16 fgMorphTree (before 211): [000378] ---X-------- * ARR_BOUNDS_CHECK_Rng void [000104] ------------ +--* CNS_INT int 0 [000377] ---X-------- \--* ARR_LENGTH int [000103] ------------ \--* LCL_VAR ref V14 tmp3 fgMorphTree (before 212): [000104] ------------ * CNS_INT int 0 fgMorphTree (after 212): [000104] ------------ * CNS_INT int 0 fgMorphTree (before 213): [000377] ---X-------- * ARR_LENGTH int [000103] ------------ \--* LCL_VAR ref V14 tmp3 fgMorphTree (before 214): [000103] ------------ * LCL_VAR ref V14 tmp3 fgMorphTree (after 214): [000103] ------------ * LCL_VAR ref V14 tmp3 fgMorphTree (after 213): [000377] ---X-------- * ARR_LENGTH int [000103] -----+------ \--* LCL_VAR ref V14 tmp3 GenTreeNode creates assertion: [000377] ---X-------- * ARR_LENGTH int In BB24 New Local Constant Assertion: V14 != null index=#01, mask=0000000000000001 fgMorphTree (after 211): [000378] ---X-------- * ARR_BOUNDS_CHECK_Rng void [000104] -----+------ +--* CNS_INT int 0 [000377] ---X-+------ \--* ARR_LENGTH int [000103] -----+------ \--* LCL_VAR ref V14 tmp3 fgMorphTree (before 215): [000106] a--XG--N---- * IND ref [000383] ------------ \--* ADD byref [000375] ------------ +--* LCL_VAR ref V14 tmp3 [000382] ------------ \--* ADD long [000380] ------------ +--* MUL long [000376] ------------ | +--* CNS_INT long 0 [000379] -------N---- | \--* CNS_INT long 8 [000381] ------------ \--* CNS_INT long 16 fgMorphTree (before 216): [000383] ------------ * ADD byref [000375] ------------ +--* LCL_VAR ref V14 tmp3 [000382] ------------ \--* ADD long [000380] ------------ +--* MUL long [000376] ------------ | +--* CNS_INT long 0 [000379] -------N---- | \--* CNS_INT long 8 [000381] ------------ \--* CNS_INT long 16 fgMorphTree (before 217): [000375] ------------ * LCL_VAR ref V14 tmp3 fgMorphTree (after 217): [000375] ------------ * LCL_VAR ref V14 tmp3 fgMorphTree (before 218): [000382] ------------ * ADD long [000380] ------------ +--* MUL long [000376] ------------ | +--* CNS_INT long 0 [000379] -------N---- | \--* CNS_INT long 8 [000381] ------------ \--* CNS_INT long 16 fgMorphTree (before 219): [000380] ------------ * MUL long [000376] ------------ +--* CNS_INT long 0 [000379] -------N---- \--* CNS_INT long 8 fgMorphTree (before 220): [000376] ------------ * CNS_INT long 0 fgMorphTree (after 220): [000376] ------------ * CNS_INT long 0 fgMorphTree (before 221): [000379] -------N---- * CNS_INT long 8 fgMorphTree (after 221): [000379] -------N---- * CNS_INT long 8 Folding long operator with constant nodes into a constant: [000380] ------------ * MUL long [000376] -----+------ +--* CNS_INT long 0 [000379] -----+-N---- \--* CNS_INT long 8 Bashed to long constant: [000380] ------------ * CNS_INT long 0 fgMorphTree (after 219): [000380] ------------ * CNS_INT long 0 fgMorphTree (before 222): [000381] ------------ * CNS_INT long 16 fgMorphTree (after 222): [000381] ------------ * CNS_INT long 16 Folding long operator with constant nodes into a constant: [000382] ------------ * ADD long [000380] -----+------ +--* CNS_INT long 0 [000381] -----+------ \--* CNS_INT long 16 Bashed to long constant: [000382] ------------ * CNS_INT long 16 fgMorphTree (after 218): [000382] ------------ * CNS_INT long 16 fgMorphTree (after 216): [000383] ------------ * ADD byref [000375] -----+------ +--* LCL_VAR ref V14 tmp3 [000382] -----+------ \--* CNS_INT long 16 fgMorphTree (after 215): [000106] a---G--N---- * IND ref [000383] -----+------ \--* ADD byref [000375] -----+------ +--* LCL_VAR ref V14 tmp3 [000382] -----+------ \--* CNS_INT long 16 fgMorphTree (after 210): [000384] ---XG------- * COMMA ref [000378] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000104] -----+------ | +--* CNS_INT int 0 [000377] ---X-+------ | \--* ARR_LENGTH int [000103] -----+------ | \--* LCL_VAR ref V14 tmp3 [000106] a---G+-N---- \--* IND ref [000383] -----+------ \--* ADD byref [000375] -----+------ +--* LCL_VAR ref V14 tmp3 [000382] -----+------ \--* CNS_INT long 16 fgMorphTree (after 209): [000384] ---XG+------ * COMMA ref [000378] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000104] -----+------ | +--* CNS_INT int 0 [000377] ---X-+------ | \--* ARR_LENGTH int [000103] -----+------ | \--* LCL_VAR ref V14 tmp3 [000106] a---G+-N---- \--* IND ref [000383] -----+------ \--* ADD byref [000375] -----+------ +--* LCL_VAR ref V14 tmp3 [000382] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree (before 223): [000105] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (after 223): [000105] ------------ * LCL_VAR ref V03 arg3 fgMorphTree (after 208): [000107] -A-XG------- * ASG ref [000384] ---XG+-N---- +--* COMMA ref [000378] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000104] -----+------ | | +--* CNS_INT int 0 [000377] ---X-+------ | | \--* ARR_LENGTH int [000103] -----+------ | | \--* LCL_VAR ref V14 tmp3 [000106] a---G+-N---- | \--* IND ref [000383] -----+------ | \--* ADD byref [000375] -----+------ | +--* LCL_VAR ref V14 tmp3 [000382] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000105] -----+------ \--* LCL_VAR ref V03 arg3 fgMorphTree BB24, STMT00020 (after) [000107] -A-XG+------ * ASG ref [000384] ---XG+-N---- +--* COMMA ref [000378] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000104] -----+------ | | +--* CNS_INT int 0 [000377] ---X-+------ | | \--* ARR_LENGTH int [000103] -----+------ | | \--* LCL_VAR ref V14 tmp3 [000106] a---G+-N---- | \--* IND ref [000383] -----+------ | \--* ADD byref [000375] -----+------ | +--* LCL_VAR ref V14 tmp3 [000382] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000105] -----+------ \--* LCL_VAR ref V03 arg3 fgMorphTree BB24, STMT00021 (before) [000112] -A-XG------- * ASG ref [000111] ---XG--N---- +--* INDEX ref [000108] ------------ | +--* LCL_VAR ref V14 tmp3 [000109] ------------ | \--* CNS_INT int 1 [000110] ------------ \--* LCL_VAR ref V10 loc4 fgMorphTree (before 224): [000112] -A-XG------- * ASG ref [000111] ---XG--N---- +--* INDEX ref [000108] ------------ | +--* LCL_VAR ref V14 tmp3 [000109] ------------ | \--* CNS_INT int 1 [000110] ------------ \--* LCL_VAR ref V10 loc4 fgMorphTree (before 225): [000111] ---XG--N---- * INDEX ref [000108] ------------ +--* LCL_VAR ref V14 tmp3 [000109] ------------ \--* CNS_INT int 1 fgMorphTree (before 226): [000394] ---XG------- * COMMA ref [000388] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void [000109] ------------ | +--* CNS_INT int 1 [000387] ---X-------- | \--* ARR_LENGTH int [000108] ------------ | \--* LCL_VAR ref V14 tmp3 [000111] a--XG--N---- \--* IND ref [000393] ------------ \--* ADD byref [000385] ------------ +--* LCL_VAR ref V14 tmp3 [000392] ------------ \--* ADD long [000390] ------------ +--* MUL long [000386] ------------ | +--* CNS_INT long 1 [000389] -------N---- | \--* CNS_INT long 8 [000391] ------------ \--* CNS_INT long 16 fgMorphTree (before 227): [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void [000109] ------------ +--* CNS_INT int 1 [000387] ---X-------- \--* ARR_LENGTH int [000108] ------------ \--* LCL_VAR ref V14 tmp3 fgMorphTree (before 228): [000109] ------------ * CNS_INT int 1 fgMorphTree (after 228): [000109] ------------ * CNS_INT int 1 fgMorphTree (before 229): [000387] ---X-------- * ARR_LENGTH int [000108] ------------ \--* LCL_VAR ref V14 tmp3 fgMorphTree (before 230): [000108] ------------ * LCL_VAR ref V14 tmp3 fgMorphTree (after 230): [000108] ------------ * LCL_VAR ref V14 tmp3 fgMorphTree (after 229): [000387] ---X-------- * ARR_LENGTH int [000108] -----+------ \--* LCL_VAR ref V14 tmp3 fgMorphTree (after 227): [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void [000109] -----+------ +--* CNS_INT int 1 [000387] ---X-+------ \--* ARR_LENGTH int [000108] -----+------ \--* LCL_VAR ref V14 tmp3 fgMorphTree (before 231): [000111] a--XG--N---- * IND ref [000393] ------------ \--* ADD byref [000385] ------------ +--* LCL_VAR ref V14 tmp3 [000392] ------------ \--* ADD long [000390] ------------ +--* MUL long [000386] ------------ | +--* CNS_INT long 1 [000389] -------N---- | \--* CNS_INT long 8 [000391] ------------ \--* CNS_INT long 16 fgMorphTree (before 232): [000393] ------------ * ADD byref [000385] ------------ +--* LCL_VAR ref V14 tmp3 [000392] ------------ \--* ADD long [000390] ------------ +--* MUL long [000386] ------------ | +--* CNS_INT long 1 [000389] -------N---- | \--* CNS_INT long 8 [000391] ------------ \--* CNS_INT long 16 fgMorphTree (before 233): [000385] ------------ * LCL_VAR ref V14 tmp3 fgMorphTree (after 233): [000385] ------------ * LCL_VAR ref V14 tmp3 fgMorphTree (before 234): [000392] ------------ * ADD long [000390] ------------ +--* MUL long [000386] ------------ | +--* CNS_INT long 1 [000389] -------N---- | \--* CNS_INT long 8 [000391] ------------ \--* CNS_INT long 16 fgMorphTree (before 235): [000390] ------------ * MUL long [000386] ------------ +--* CNS_INT long 1 [000389] -------N---- \--* CNS_INT long 8 fgMorphTree (before 236): [000386] ------------ * CNS_INT long 1 fgMorphTree (after 236): [000386] ------------ * CNS_INT long 1 fgMorphTree (before 237): [000389] -------N---- * CNS_INT long 8 fgMorphTree (after 237): [000389] -------N---- * CNS_INT long 8 Folding long operator with constant nodes into a constant: [000390] ------------ * MUL long [000386] -----+------ +--* CNS_INT long 1 [000389] -----+-N---- \--* CNS_INT long 8 Bashed to long constant: [000390] ------------ * CNS_INT long 8 fgMorphTree (after 235): [000390] ------------ * CNS_INT long 8 fgMorphTree (before 238): [000391] ------------ * CNS_INT long 16 fgMorphTree (after 238): [000391] ------------ * CNS_INT long 16 Folding long operator with constant nodes into a constant: [000392] ------------ * ADD long [000390] -----+------ +--* CNS_INT long 8 [000391] -----+------ \--* CNS_INT long 16 Bashed to long constant: [000392] ------------ * CNS_INT long 24 fgMorphTree (after 234): [000392] ------------ * CNS_INT long 24 fgMorphTree (after 232): [000393] ------------ * ADD byref [000385] -----+------ +--* LCL_VAR ref V14 tmp3 [000392] -----+------ \--* CNS_INT long 24 fgMorphTree (after 231): [000111] a---G--N---- * IND ref [000393] -----+------ \--* ADD byref [000385] -----+------ +--* LCL_VAR ref V14 tmp3 [000392] -----+------ \--* CNS_INT long 24 fgMorphTree (after 226): [000394] ---XG------- * COMMA ref [000388] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000109] -----+------ | +--* CNS_INT int 1 [000387] ---X-+------ | \--* ARR_LENGTH int [000108] -----+------ | \--* LCL_VAR ref V14 tmp3 [000111] a---G+-N---- \--* IND ref [000393] -----+------ \--* ADD byref [000385] -----+------ +--* LCL_VAR ref V14 tmp3 [000392] -----+------ \--* CNS_INT long 24 fgMorphTree (after 225): [000394] ---XG+------ * COMMA ref [000388] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000109] -----+------ | +--* CNS_INT int 1 [000387] ---X-+------ | \--* ARR_LENGTH int [000108] -----+------ | \--* LCL_VAR ref V14 tmp3 [000111] a---G+-N---- \--* IND ref [000393] -----+------ \--* ADD byref [000385] -----+------ +--* LCL_VAR ref V14 tmp3 [000392] -----+------ \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] fgMorphTree (before 239): [000110] ------------ * LCL_VAR ref V10 loc4 fgMorphTree (after 239): [000110] ------------ * LCL_VAR ref V10 loc4 fgMorphTree (after 224): [000112] -A-XG------- * ASG ref [000394] ---XG+-N---- +--* COMMA ref [000388] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000109] -----+------ | | +--* CNS_INT int 1 [000387] ---X-+------ | | \--* ARR_LENGTH int [000108] -----+------ | | \--* LCL_VAR ref V14 tmp3 [000111] a---G+-N---- | \--* IND ref [000393] -----+------ | \--* ADD byref [000385] -----+------ | +--* LCL_VAR ref V14 tmp3 [000392] -----+------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] [000110] -----+------ \--* LCL_VAR ref V10 loc4 fgMorphTree BB24, STMT00021 (after) [000112] -A-XG+------ * ASG ref [000394] ---XG+-N---- +--* COMMA ref [000388] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000109] -----+------ | | +--* CNS_INT int 1 [000387] ---X-+------ | | \--* ARR_LENGTH int [000108] -----+------ | | \--* LCL_VAR ref V14 tmp3 [000111] a---G+-N---- | \--* IND ref [000393] -----+------ | \--* ADD byref [000385] -----+------ | +--* LCL_VAR ref V14 tmp3 [000392] -----+------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] [000110] -----+------ \--* LCL_VAR ref V10 loc4 fgMorphTree BB24, STMT00052 (before) [000261] -AC--------- * ASG ref [000260] D------N---- +--* LCL_VAR ref V20 tmp9 [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW fgMorphTree (before 240): [000261] -AC--------- * ASG ref [000260] D------N---- +--* LCL_VAR ref V20 tmp9 [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW fgMorphTree (before 241): [000260] D------N---- * LCL_VAR ref V20 tmp9 fgMorphTree (after 241): [000260] D------N---- * LCL_VAR ref V20 tmp9 fgMorphTree (before 242): [000259] --C--------- * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW Initializing arg info for 259.CALL: ArgTable for 259.CALL after fgInitArgInfo: Morphing args for 259.CALL: argSlots=0, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 259.CALL after fgMorphArgs: fgMorphTree (after 242): [000259] --C--------- * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW fgMorphTree (after 240): [000261] -AC--------- * ASG ref [000260] D----+-N---- +--* LCL_VAR ref V20 tmp9 [000259] --C--+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW fgMorphTree BB24, STMT00053 (before) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 [000255] --CXG------- arg1 +--* IND ref [000254] --CXG------- | \--* ADD byref [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000256] ------------ arg2 +--* CNS_INT int 0x7D2C [000102] ------------ arg3 \--* LCL_VAR ref V14 tmp3 fgMorphTree (before 243): [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 [000255] --CXG------- arg1 +--* IND ref [000254] --CXG------- | \--* ADD byref [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] [000256] ------------ arg2 +--* CNS_INT int 0x7D2C [000102] ------------ arg3 \--* LCL_VAR ref V14 tmp3 Initializing arg info for 263.CALL: ArgTable for 263.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 262.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 255.IND ref, 1 reg: rsi, align=1] fgArgTabEntry[arg 2 256.CNS_INT int, 1 reg: rdx, align=1] fgArgTabEntry[arg 3 102.LCL_VAR ref, 1 reg: rcx, align=1] Morphing args for 263.CALL: fgMorphTree (before 244): [000262] ------------ * LCL_VAR ref V20 tmp9 fgMorphTree (after 244): [000262] ------------ * LCL_VAR ref V20 tmp9 fgMorphTree (before 245): [000255] --CXG------- * IND ref [000254] --CXG------- \--* ADD byref [000252] H-CXG------- +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] ------------ \--* CNS_INT int 0x418 Fseq[Instance] fgMorphTree (before 246): [000254] --CXG------- * ADD byref [000252] H-CXG------- +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] ------------ \--* CNS_INT int 0x418 Fseq[Instance] fgMorphTree (before 247): [000252] H-CXG------- * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE Initializing arg info for 252.CALL: ArgTable for 252.CALL after fgInitArgInfo: Morphing args for 252.CALL: argSlots=0, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 252.CALL after fgMorphArgs: fgMorphTree (after 247): [000252] H-CXG------- * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE fgMorphTree (before 248): [000253] ------------ * CNS_INT int 0x418 Fseq[Instance] fgMorphTree (after 248): [000253] ------------ * CNS_INT int 0x418 Fseq[Instance] fgMorphTree (after 246): [000254] --CXG------- * ADD byref [000252] H-CXG+------ +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] -----+------ \--* CNS_INT int 0x418 Fseq[Instance] fgMorphTree (after 245): [000255] --CXG------- * IND ref [000254] --CXG+------ \--* ADD byref [000252] H-CXG+------ +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] -----+------ \--* CNS_INT int 0x418 Fseq[Instance] fgMorphTree (before 249): [000256] ------------ * CNS_INT int 0x7D2C fgMorphTree (after 249): [000256] ------------ * CNS_INT int 0x7D2C fgMorphTree (before 250): [000102] ------------ * LCL_VAR ref V14 tmp3 fgMorphTree (after 250): [000102] ------------ * LCL_VAR ref V14 tmp3 argSlots=4, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Argument with 'side effect'... [000255] --CXG+------ * IND ref [000254] --CXG+------ \--* ADD byref [000252] H-CXG+------ +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] -----+------ \--* CNS_INT int 0x418 Fseq[Instance] lvaGrabTemp returning 27 (V27 tmp16) called for argument with side effect. Evaluate to a temp: [000396] -ACXG-----L- * ASG ref [000395] D------N---- +--* LCL_VAR ref V27 tmp16 [000255] --CXG+------ \--* IND ref [000254] --CXG+------ \--* ADD byref [000252] H-CXG+------ +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] -----+------ \--* CNS_INT int 0x418 Fseq[Instance] Deferred argument ('rdi'): [000262] -----+------ * LCL_VAR ref V20 tmp9 Replaced with placeholder node: [000398] ----------L- * ARGPLACE ref Deferred argument ('rcx'): [000102] -----+------ * LCL_VAR ref V14 tmp3 Replaced with placeholder node: [000399] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000256] -----+------ * CNS_INT int 0x7D2C Replaced with placeholder node: [000400] ----------L- * ARGPLACE int Shuffled argument table: rsi rdi rcx rdx ArgTable for 263.CALL after fgMorphArgs: fgArgTabEntry[arg 1 397.LCL_VAR ref, 1 reg: rsi, align=1, lateArgInx=0, tmpNum=V27, isTmp, processed] fgArgTabEntry[arg 0 262.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 3 102.LCL_VAR ref, 1 reg: rcx, align=1, lateArgInx=2, processed] fgArgTabEntry[arg 2 256.CNS_INT int, 1 reg: rdx, align=1, lateArgInx=3, processed] fgMorphTree (after 243): [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000396] -ACXG-----L- arg1 SETUP +--* ASG ref [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 [000255] --CXG+------ | \--* IND ref [000254] --CXG+------ | \--* ADD byref [000252] H-CXG+------ | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] -----+------ | \--* CNS_INT int 0x418 Fseq[Instance] [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 [000262] -----+------ this in rdi +--* LCL_VAR ref V20 tmp9 [000102] -----+------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 [000256] -----+------ arg2 in rdx \--* CNS_INT int 0x7D2C fgMorphTree BB24, STMT00053 (after) [000263] --CXG+------ * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000396] -ACXG-----L- arg1 SETUP +--* ASG ref [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 [000255] --CXG+------ | \--* IND ref [000254] --CXG+------ | \--* ADD byref [000252] H-CXG+------ | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] -----+------ | \--* CNS_INT int 0x418 Fseq[Instance] [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 [000262] -----+------ this in rdi +--* LCL_VAR ref V20 tmp9 [000102] -----+------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 [000256] -----+------ arg2 in rdx \--* CNS_INT int 0x7D2C fgMorphTree BB24, STMT00023 (before) [000117] IA---------- * ASG struct (init) [000115] D------N---- +--* LCL_VAR struct V15 tmp4 [000116] ------------ \--* CNS_INT int 0 fgMorphTree (before 251): [000117] IA---------- * ASG struct (init) [000115] D------N---- +--* LCL_VAR struct V15 tmp4 [000116] ------------ \--* CNS_INT int 0 fgMorphTree (before 252): [000115] D------N---- * LCL_VAR struct V15 tmp4 fgMorphTree (after 252): [000115] D------N---- * LCL_VAR struct V15 tmp4 fgMorphTree (before 253): [000116] ------------ * CNS_INT int 0 fgMorphTree (after 253): [000116] ------------ * CNS_INT int 0 fgMorphBlkNode for dst tree, before: [000115] D----+-N---- * LCL_VAR struct V15 tmp4 fgMorphBlkNode after: [000115] D----+-N---- * LCL_VAR struct V15 tmp4 fgMorphInitBlock: Local V15 should not be enregistered because: written in a block op fgMorphTree (after 251): [000117] IA---------- * ASG struct (init) [000115] D----+-N---- +--* LCL_VAR struct V15 tmp4 [000116] -----+------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000117] IA---------- * ASG struct (init) In BB24 New Local Constant Assertion: V15 == 0 index=#02, mask=0000000000000002 fgMorphTree BB24, STMT00054 (before) [000269] IA---------- * ASG struct (init) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 [000268] ------------ \--* CNS_INT int 0 fgMorphTree (before 254): [000269] IA---------- * ASG struct (init) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 [000268] ------------ \--* CNS_INT int 0 fgMorphTree (before 255): [000267] D------N---- * LCL_VAR struct V15 tmp4 fgMorphTree (after 255): [000267] D------N---- * LCL_VAR struct V15 tmp4 fgMorphTree (before 256): [000268] ------------ * CNS_INT int 0 fgMorphTree (after 256): [000268] ------------ * CNS_INT int 0 fgMorphBlkNode for dst tree, before: [000267] D----+-N---- * LCL_VAR struct V15 tmp4 fgMorphBlkNode after: [000267] D----+-N---- * LCL_VAR struct V15 tmp4 fgMorphInitBlock: The assignment [000269] using V15 removes: Constant Assertion: V15 == 0 Local V15 should not be enregistered because: written in a block op fgMorphTree (after 254): [000269] IA---------- * ASG struct (init) [000267] D----+-N---- +--* LCL_VAR struct V15 tmp4 [000268] -----+------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000269] IA---------- * ASG struct (init) In BB24 New Local Constant Assertion: V15 == 0 index=#02, mask=0000000000000002 fgMorphTree BB24, STMT00055 (before) [000273] -A---------- * ASG ref [000272] U------N---- +--* LCL_FLD ref V15 tmp4 [+0] Fseq[TypeParameter] [000096] ------------ \--* LCL_VAR ref V02 arg2 fgMorphTree (before 257): [000273] -A---------- * ASG ref [000272] U------N---- +--* LCL_FLD ref V15 tmp4 [+0] Fseq[TypeParameter] [000096] ------------ \--* LCL_VAR ref V02 arg2 fgMorphTree (before 258): [000272] U------N---- * LCL_FLD ref V15 tmp4 [+0] Fseq[TypeParameter] fgMorphTree (after 258): [000272] U------N---- * LCL_FLD ref V15 tmp4 [+0] Fseq[TypeParameter] fgMorphTree (before 259): [000096] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (after 259): [000096] ------------ * LCL_VAR ref V02 arg2 fgMorphTree (after 257): [000273] -A---------- * ASG ref [000272] U----+-N---- +--* LCL_FLD ref V15 tmp4 [+0] Fseq[TypeParameter] [000096] -----+------ \--* LCL_VAR ref V02 arg2 The assignment [000273] using V15 removes: Constant Assertion: V15 == 0 fgMorphTree BB24, STMT00056 (before) [000277] -A---------- * ASG ref [000276] U------N---- +--* LCL_FLD ref V15 tmp4 [+8] Fseq[DiagnosticInfo] [000264] ------------ \--* LCL_VAR ref V20 tmp9 fgMorphTree (before 260): [000277] -A---------- * ASG ref [000276] U------N---- +--* LCL_FLD ref V15 tmp4 [+8] Fseq[DiagnosticInfo] [000264] ------------ \--* LCL_VAR ref V20 tmp9 fgMorphTree (before 261): [000276] U------N---- * LCL_FLD ref V15 tmp4 [+8] Fseq[DiagnosticInfo] fgMorphTree (after 261): [000276] U------N---- * LCL_FLD ref V15 tmp4 [+8] Fseq[DiagnosticInfo] fgMorphTree (before 262): [000264] ------------ * LCL_VAR ref V20 tmp9 fgMorphTree (after 262): [000264] ------------ * LCL_VAR ref V20 tmp9 fgMorphTree (after 260): [000277] -A---------- * ASG ref [000276] U----+-N---- +--* LCL_FLD ref V15 tmp4 [+8] Fseq[DiagnosticInfo] [000264] -----+------ \--* LCL_VAR ref V20 tmp9 fgMorphTree BB24, STMT00025 (before) [000122] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000124] n----------- arg1 \--* OBJ struct [000123] ------------ \--* ADDR byref [000121] -------N---- \--* LCL_VAR struct V15 tmp4 fgMorphTree (before 263): [000122] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 [000124] n----------- arg1 \--* OBJ struct [000123] ------------ \--* ADDR byref [000121] -------N---- \--* LCL_VAR struct V15 tmp4 Initializing arg info for 122.CALL: **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0xd1ffab1e (Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo), ...) => passedInRegisters = false ArgTable for 122.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 95.LCL_VAR ref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 401.CNS_INT long, 1 reg: r11, align=1, isNonStandard] fgArgTabEntry[arg 2 124.OBJ struct, numSlots=5, slotNum=0, align=1, isStruct] Morphing args for 122.CALL: fgMorphTree (before 264): [000095] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (after 264): [000095] ------------ * LCL_VAR ref V04 arg4 fgMorphTree (before 265): [000401] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (after 265): [000401] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 fgMorphTree (before 266): [000124] n----------- * OBJ struct [000123] ------------ \--* ADDR byref [000121] -------N---- \--* LCL_VAR struct V15 tmp4 fgMorphTree (before 267): [000123] ------------ * ADDR byref [000121] -------N---- \--* LCL_VAR struct V15 tmp4 fgMorphTree (before 268): [000121] -------N---- * LCL_VAR struct V15 tmp4 fgMorphTree (after 268): [000121] -------N---- * LCL_VAR struct V15 tmp4 fgMorphTree (after 267): [000123] ------------ * ADDR byref [000121] -----+-N---- \--* LCL_VAR struct V15 tmp4 fgMorphTree (after 266): [000124] n----------- * OBJ struct [000123] -----+------ \--* ADDR byref [000121] -----+-N---- \--* LCL_VAR struct V15 tmp4 argSlots=6, preallocatedArgCount=5, nextSlotNum=5, outgoingArgSpaceSize=40 Sorting the arguments: Deferred argument ('rdi'): [000095] -----+------ * LCL_VAR ref V04 arg4 Replaced with placeholder node: [000402] ----------L- * ARGPLACE ref Deferred argument ('r11'): [000401] -----+------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 Replaced with placeholder node: [000403] ----------L- * ARGPLACE long Shuffled argument table: rdi r11 Local V15 should not be enregistered because: it is a struct arg ArgTable for 122.CALL after fgMorphArgs: fgArgTabEntry[arg 2 124.OBJ struct, numSlots=5, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 0 95.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 401.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 263): [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct ( 3, 3) [000123] ------------ | \--* ADDR byref ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 [000095] -----+------ this in rdi +--* LCL_VAR ref V04 arg4 [000401] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 GenTreeNode creates assertion: [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add In BB24 New Local Constant Assertion: V04 != null index=#02, mask=0000000000000002 fgMorphTree BB24, STMT00025 (after) [000122] --CXG+------ * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct ( 3, 3) [000123] ------------ | \--* ADDR byref ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 [000095] -----+------ this in rdi +--* LCL_VAR ref V04 arg4 [000401] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 Morphing BB25 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB25, STMT00018 (before) [000094] -A---------- * ASG int [000093] D------N---- +--* LCL_VAR int V07 loc1 [000092] ------------ \--* CNS_INT int 0 fgMorphTree (before 269): [000094] -A---------- * ASG int [000093] D------N---- +--* LCL_VAR int V07 loc1 [000092] ------------ \--* CNS_INT int 0 fgMorphTree (before 270): [000093] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (after 270): [000093] D------N---- * LCL_VAR int V07 loc1 fgMorphTree (before 271): [000404] ------------ * CAST int <- bool <- int [000092] ------------ \--* CNS_INT int 0 fgMorphTree (before 272): [000092] ------------ * CNS_INT int 0 fgMorphTree (after 272): [000092] ------------ * CNS_INT int 0 fgMorphTree (after 271): [000092] -----+------ * CNS_INT int 0 fgMorphTree (after 269): [000094] -A---------- * ASG int [000093] D----+-N---- +--* LCL_VAR int V07 loc1 [000092] -----+------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000094] -A---------- * ASG int In BB25 New Local Constant Assertion: V07 == 0 index=#01, mask=0000000000000001 Morphing BB26 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB26, STMT00012 (before) [000063] --C-G------- * JTRUE void [000062] --C-G------- \--* NE int [000060] --C-G------- +--* CAST int <- bool <- int [000057] --C-G------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext [000056] ------------ this in rdi | +--* ADDR byref [000055] -------N---- | | \--* LCL_VAR struct(AX)(P) V08 loc2 | | \--* ref V08._array (offs=0x00) -> V21 tmp10 | | \--* int V08._index (offs=0x08) -> V22 tmp11 [000059] n----------- arg1 | \--* IND long [000058] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000061] ------------ \--* CNS_INT int 0 fgMorphTree (before 273): [000063] --C-G------- * JTRUE void [000062] --C-G------- \--* NE int [000060] --C-G------- +--* CAST int <- bool <- int [000057] --C-G------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext [000056] ------------ this in rdi | +--* ADDR byref [000055] -------N---- | | \--* LCL_VAR struct(AX)(P) V08 loc2 | | \--* ref V08._array (offs=0x00) -> V21 tmp10 | | \--* int V08._index (offs=0x08) -> V22 tmp11 [000059] n----------- arg1 | \--* IND long [000058] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000061] ------------ \--* CNS_INT int 0 fgMorphTree (before 274): [000062] J-C-G--N---- * NE int [000060] --C-G------- +--* CAST int <- bool <- int [000057] --C-G------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext [000056] ------------ this in rdi | +--* ADDR byref [000055] -------N---- | | \--* LCL_VAR struct(AX)(P) V08 loc2 | | \--* ref V08._array (offs=0x00) -> V21 tmp10 | | \--* int V08._index (offs=0x08) -> V22 tmp11 [000059] n----------- arg1 | \--* IND long [000058] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class [000061] ------------ \--* CNS_INT int 0 fgMorphTree (before 275): [000060] --C-G------- * CAST int <- bool <- int [000057] --C-G------- \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext [000056] ------------ this in rdi +--* ADDR byref [000055] -------N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 [000059] n----------- arg1 \--* IND long [000058] ------------ \--* CNS_INT(h) long 0xd1ffab1e class fgMorphTree (before 276): [000057] --C-G------- * CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext [000056] ------------ this in rdi +--* ADDR byref [000055] -------N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 [000059] n----------- arg1 \--* IND long [000058] ------------ \--* CNS_INT(h) long 0xd1ffab1e class Initializing arg info for 57.CALL: ArgTable for 57.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 56.ADDR byref, 1 reg: rdi, align=1] fgArgTabEntry[arg 1 59.IND long, 1 reg: rsi, align=1] Morphing args for 57.CALL: fgMorphTree (before 277): [000056] ------------ * ADDR byref [000055] -------N---- \--* LCL_VAR struct(AX)(P) V08 loc2 \--* ref V08._array (offs=0x00) -> V21 tmp10 \--* int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (before 278): [000055] -------N---- * LCL_VAR struct(AX)(P) V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (after 278): [000055] ----G--N---- * LCL_VAR struct(AX)(P) V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (after 277): [000056] ------------ * ADDR byref [000055] ----G+-N---- \--* LCL_VAR struct(AX)(P) V08 loc2 \--* ref V08._array (offs=0x00) -> V21 tmp10 \--* int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (before 279): [000059] n----------- * IND long [000058] ------------ \--* CNS_INT(h) long 0xd1ffab1e class fgMorphTree (before 280): [000058] ------------ * CNS_INT(h) long 0xd1ffab1e class fgMorphTree (after 280): [000058] ------------ * CNS_INT(h) long 0xd1ffab1e class fgMorphTree (after 279): [000059] n----------- * IND long [000058] -----+------ \--* CNS_INT(h) long 0xd1ffab1e class argSlots=2, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rsi'): ( 5, 12) [000059] n----------- * IND long ( 3, 10) [000058] ------------ \--* CNS_INT(h) long 0xd1ffab1e class Replaced with placeholder node: [000405] ----------L- * ARGPLACE long Deferred argument ('rdi'): ( 3, 3) [000056] ------------ * ADDR byref ( 3, 2) [000055] ----G--N---- \--* LCL_VAR struct(AX)(P) V08 loc2 \--* ref V08._array (offs=0x00) -> V21 tmp10 \--* int V08._index (offs=0x08) -> V22 tmp11 Replaced with placeholder node: [000406] ----------L- * ARGPLACE byref Shuffled argument table: rsi rdi ArgTable for 57.CALL after fgMorphArgs: fgArgTabEntry[arg 1 59.IND long, 1 reg: rsi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 0 56.ADDR byref, 1 reg: rdi, align=1, lateArgInx=1, processed] fgMorphTree (after 276): [000057] --CXG------- * CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext ( 5, 12) [000059] n----------- arg1 in rsi +--* IND long ( 3, 10) [000058] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000056] ------------ this in rdi \--* ADDR byref ( 3, 2) [000055] ----G--N---- \--* LCL_VAR struct(AX)(P) V08 loc2 \--* ref V08._array (offs=0x00) -> V21 tmp10 \--* int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (after 275): [000060] --CXG------- * CAST int <- bool <- int [000057] --CXG+------ \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext ( 5, 12) [000059] n----------- arg1 in rsi +--* IND long ( 3, 10) [000058] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000056] ------------ this in rdi \--* ADDR byref ( 3, 2) [000055] ----G--N---- \--* LCL_VAR struct(AX)(P) V08 loc2 \--* ref V08._array (offs=0x00) -> V21 tmp10 \--* int V08._index (offs=0x08) -> V22 tmp11 fgMorphTree (before 281): [000061] ------------ * CNS_INT int 0 fgMorphTree (after 281): [000061] ------------ * CNS_INT int 0 fgMorphTree (after 274): [000062] J-CXG--N---- * NE int [000060] --CXG+------ +--* CAST int <- bool <- int [000057] --CXG+------ | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 [000061] -----+------ \--* CNS_INT int 0 fgMorphTree (after 273): [000063] --CXG------- * JTRUE void [000062] J-CXG+-N---- \--* NE int [000060] --CXG+------ +--* CAST int <- bool <- int [000057] --CXG+------ | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 [000061] -----+------ \--* CNS_INT int 0 fgMorphTree BB26, STMT00012 (after) [000063] --CXG+------ * JTRUE void [000062] J-CXG+-N---- \--* NE int [000060] --CXG+------ +--* CAST int <- bool <- int [000057] --CXG+------ | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 [000061] -----+------ \--* CNS_INT int 0 Morphing BB27 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB27, STMT00026 (before) [000127] -A---------- * ASG int [000126] D------N---- +--* LCL_VAR int V06 loc0 [000125] ------------ \--* LCL_VAR int V07 loc1 fgMorphTree (before 282): [000127] -A---------- * ASG int [000126] D------N---- +--* LCL_VAR int V06 loc0 [000125] ------------ \--* LCL_VAR int V07 loc1 fgMorphTree (before 283): [000126] D------N---- * LCL_VAR int V06 loc0 fgMorphTree (after 283): [000126] D------N---- * LCL_VAR int V06 loc0 fgMorphTree (before 284): [000407] ------------ * CAST int <- bool <- int [000125] ------------ \--* LCL_VAR int V07 loc1 fgMorphTree (before 285): [000125] ------------ * LCL_VAR int V07 loc1 fgMorphTree (after 285): [000125] ------------ * LCL_VAR int V07 loc1 fgMorphTree (after 284): [000125] -----+------ * LCL_VAR int V07 loc1 fgMorphTree (after 282): [000127] -A---------- * ASG int [000126] D----+-N---- +--* LCL_VAR int V06 loc0 [000125] -----+------ \--* LCL_VAR int V07 loc1 GenTreeNode creates assertion: [000127] -A---------- * ASG int In BB27 New Local Copy Assertion: V06 == V07 index=#01, mask=0000000000000001 Morphing BB28 of 'Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool' fgMorphTree BB28, STMT00027 (before) [000129] ------------ * RETURN int [000128] ------------ \--* LCL_VAR int V06 loc0 fgMorphTree (before 286): [000129] ------------ * RETURN int [000128] ------------ \--* LCL_VAR int V06 loc0 fgMorphTree (before 287): [000128] ------------ * LCL_VAR int V06 loc0 fgMorphTree (after 287): [000128] ------------ * LCL_VAR int V06 loc0 fgMorphTree (after 286): [000129] ------------ * RETURN int [000128] -----+------ \--* LCL_VAR int V06 loc0 *************** Finishing PHASE Morph - Global Trees after Morph - Global ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) i label target gcsafe IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB28 (always) i rare IBC BB03 [0002] 1 BB01 20988. 20988 [00F..019)-> BB07 ( cond ) i label target gcsafe IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040) i rare label target IBC BB07 [0006] 2 BB03,BB06 20988. 20988 [040..048)-> BB10 ( cond ) i label target gcsafe IBC BB08 [0007] 1 BB07 131 131 [048..053)-> BB10 ( cond ) i gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 20988. 20988 [055..05D)-> BB13 ( cond ) i label target gcsafe IBC BB11 [0010] 1 BB10 614 614 [05D..068)-> BB13 ( cond ) i gcsafe IBC BB12 [0011] 1 BB11 22 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 20988. 20988 [06A..072)-> BB16 ( cond ) i label target gcsafe IBC BB14 [0013] 1 BB13 87 87 [072..080)-> BB16 ( cond ) i gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 20988. 20988 [082..095)-> BB26 (always) i label target gcsafe IBC BB17 [0016] 1 BB26 6120. 6120 [095..0B5)-> BB20 ( cond ) i label target gcsafe bwd bwd-target IBC BB19 [0027] 1 BB17 3060. [0A9..0AA)-> BB21 (always) i gcsafe bwd BB20 [0028] 1 BB17 3060. [0A9..0AA) i label target gcsafe bwd BB21 [0029] 2 BB19,BB20 6120. 6120 [0A9..0AA)-> BB26 ( cond ) i label target bwd IBC BB23 [0017] 1 BB21 479 479 [0B5..0B9)-> BB25 ( cond ) i bwd IBC BB24 [0018] 1 BB23 479 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB25 [0019] 2 BB23,BB24 479 479 [0DF..0E1) i label target bwd IBC BB26 [0020] 3 BB16,BB21,BB25 27108. 27108 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB27 [0021] 1 BB26 20988. 20988 [0EA..0EC) i IBC BB28 [0022] 2 BB02,BB27 20988. 20988 [0EC..0EE) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00001 (IL ???... ???) [000006] --CXG+------ * JTRUE void [000200] J-CXG+-N---- \--* NE int [000198] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] -----+------ this in rdi | +--* LCL_VAR ref V03 arg3 [000279] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000199] -----+------ \--* CNS_INT int 4 ------------ BB02 [008..00F) -> BB28 (always), preds={BB01} succs={BB28} ***** BB02 STMT00042 (IL 0x008...0x009) [000197] -A---+------ * ASG int [000196] D----+-N---- +--* LCL_VAR int V06 loc0 [000195] -----+------ \--* CNS_INT int 1 ------------ BB03 [00F..019) -> BB07 (cond), preds={BB01} succs={BB04,BB07} ***** BB03 STMT00002 (IL 0x00F...0x010) [000009] -A---+------ * ASG int [000008] D----+-N---- +--* LCL_VAR int V07 loc1 [000007] -----+------ \--* CNS_INT int 1 ***** BB03 STMT00004 (IL ???... ???) [000016] --CXG+------ * JTRUE void [000015] J-CXG+-N---- \--* EQ int [000205] --CXG+------ +--* CAST int <- bool <- int [000204] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --CXG+------ arg0 in rdi | \--* CAST int <- byte <- int [000202] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] -----+------ this in rdi | +--* LCL_VAR ref V03 arg3 [000284] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000014] -----+------ \--* CNS_INT int 0 ------------ BB04 [019..01D) -> BB06 (cond), preds={BB03} succs={BB05,BB06} ***** BB04 STMT00035 (IL 0x019...0x01B) [000169] -----+------ * JTRUE void [000168] J----+-N---- \--* EQ int [000166] -----+------ +--* LCL_VAR ref V04 arg4 [000167] -----+------ \--* CNS_INT ref null ------------ BB05 [01D..03E), preds={BB04} succs={BB06} ***** BB05 STMT00037 (IL 0x01D...0x02E) [000179] -ACXG+------ * ASG ref [000178] D----+-N---- +--* LCL_VAR ref V16 tmp5 [000177] --CXG+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000176] -----+------ arg0 in rdi \--* CNS_INT long 1 ***** BB05 STMT00038 (IL ???... ???) [000185] -A-XG+------ * ASG ref [000298] ---XG+-N---- +--* COMMA ref [000292] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000182] -----+------ | | +--* CNS_INT int 0 [000291] ---X-+------ | | \--* ARR_LENGTH int [000181] -----+------ | | \--* LCL_VAR ref V16 tmp5 [000184] a---G+-N---- | \--* IND ref [000297] -----+------ | \--* ADD byref [000289] -----+------ | +--* LCL_VAR ref V16 tmp5 [000296] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000183] -----+------ \--* LCL_VAR ref V03 arg3 ***** BB05 STMT00043 (IL ???... ???) [000216] -AC--+------ * ASG ref [000215] D----+-N---- +--* LCL_VAR ref V18 tmp7 [000214] --C--+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW ***** BB05 STMT00044 (IL ???... ???) [000218] --CXG+------ * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000300] -ACXG-----L- arg1 SETUP +--* ASG ref [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 [000210] --CXG+------ | \--* IND ref [000209] --CXG+------ | \--* ADD byref [000207] H-CXG+------ | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] -----+------ | \--* CNS_INT int 0x418 Fseq[Instance] [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 [000217] -----+------ this in rdi +--* LCL_VAR ref V18 tmp7 [000180] -----+------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 [000211] -----+------ arg2 in rdx \--* CNS_INT int 0x7AA4 ***** BB05 STMT00040 (IL ???... ???) [000190] --CXG+------ * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor [000189] -----+------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 [000174] -----+------ arg1 in rsi +--* LCL_VAR ref V02 arg2 [000219] -----+------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 ***** BB05 STMT00041 (IL 0x039... ???) [000192] --CXG+------ * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct ( 3, 3) [000193] ------------ | \--* ADDR byref ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 [000173] -----+------ this in rdi +--* LCL_VAR ref V04 arg4 [000308] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ------------ BB06 [03E..040), preds={BB04,BB05} succs={BB07} ***** BB06 STMT00036 (IL 0x03E...0x03F) [000172] -A---+------ * ASG int [000171] D----+-N---- +--* LCL_VAR int V07 loc1 [000170] -----+------ \--* CNS_INT int 0 ------------ BB07 [040..048) -> BB10 (cond), preds={BB03,BB06} succs={BB08,BB10} ***** BB07 STMT00005 (IL 0x040...0x046) [000022] --CXG+------ * JTRUE void [000021] J-CXG+-N---- \--* EQ int [000019] --CXG+------ +--* CAST int <- bool <- int [000018] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000312] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000020] -----+------ \--* CNS_INT int 0 ------------ BB08 [048..053) -> BB10 (cond), preds={BB07} succs={BB09,BB10} ***** BB08 STMT00033 (IL 0x048...0x051) [000162] --CXG+------ * JTRUE void [000161] J-CXG+-N---- \--* NE int [000159] --CXG+------ +--* CAST int <- bool <- int [000158] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] -----+------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 [000156] -----+------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 [000157] -----+------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 [000160] -----+------ \--* CNS_INT int 0 ------------ BB09 [053..055), preds={BB08} succs={BB10} ***** BB09 STMT00034 (IL 0x053...0x054) [000165] -A---+------ * ASG int [000164] D----+-N---- +--* LCL_VAR int V07 loc1 [000163] -----+------ \--* CNS_INT int 0 ------------ BB10 [055..05D) -> BB13 (cond), preds={BB07,BB08,BB09} succs={BB11,BB13} ***** BB10 STMT00006 (IL 0x055...0x05B) [000028] --CXG+------ * JTRUE void [000027] J-CXG+-N---- \--* EQ int [000025] --CXG+------ +--* CAST int <- bool <- int [000024] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000319] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000026] -----+------ \--* CNS_INT int 0 ------------ BB11 [05D..068) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ***** BB11 STMT00031 (IL ???... ???) [000151] --CXG+------ * JTRUE void [000150] J-CXG+-N---- \--* NE int [000148] --CXG+------ +--* CAST int <- bool <- int [000146] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] -----+------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 [000144] -----+------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 [000145] -----+------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 [000149] -----+------ \--* CNS_INT int 0 ------------ BB12 [068..06A), preds={BB11} succs={BB13} ***** BB12 STMT00032 (IL 0x068...0x069) [000154] -A---+------ * ASG int [000153] D----+-N---- +--* LCL_VAR int V07 loc1 [000152] -----+------ \--* CNS_INT int 0 ------------ BB13 [06A..072) -> BB16 (cond), preds={BB10,BB11,BB12} succs={BB14,BB16} ***** BB13 STMT00007 (IL 0x06A...0x070) [000034] --CXG+------ * JTRUE void [000033] J-CXG+-N---- \--* EQ int [000031] --CXG+------ +--* CAST int <- bool <- int [000030] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000326] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000032] -----+------ \--* CNS_INT int 0 ------------ BB14 [072..080) -> BB16 (cond), preds={BB13} succs={BB15,BB16} ***** BB14 STMT00028 (IL 0x072...0x07E) [000139] --CXG+------ * JTRUE void [000138] J-CXG+-N---- \--* NE int [000136] --CXG+------ +--* CAST int <- bool <- int [000135] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] -----+------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 [000131] -----+------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 [000132] -----+------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 [000133] -----+------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 [000134] -----+------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 [000137] -----+------ \--* CNS_INT int 0 ------------ BB15 [080..082), preds={BB14} succs={BB16} ***** BB15 STMT00029 (IL 0x080...0x081) [000142] -A---+------ * ASG int [000141] D----+-N---- +--* LCL_VAR int V07 loc1 [000140] -----+------ \--* CNS_INT int 0 ------------ BB16 [082..095) -> BB26 (always), preds={BB13,BB14,BB15} succs={BB26} ***** BB16 STMT00009 (IL ???... ???) [000042] -ACXG+------ * ASG ref [000039] D---G+-N---- +--* LCL_VAR ref (AX) V23 tmp12 [000037] --CXG+------ \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics [000035] -----+------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] -----+------ arg1 in rsi \--* LCL_VAR byref V05 arg5 ***** BB16 STMT00010 (IL 0x08B...0x092) [000050] -ACXG+------ * ASG struct (copy) [000048] D----+-N---- +--* LCL_VAR struct(AX) V12 tmp1 [000045] --CXG+------ \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 ***** BB16 STMT00011 (IL ???... ???) [000355] -A-XG+------ * COMMA void [000348] -A-XG------- +--* COMMA void [000343] -A---------- | +--* ASG byref [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 [000340] -----+------ | | \--* ADDR byref [000341] -----+-N---- | | \--* LCL_VAR struct(AX) V12 tmp1 [000347] -A-XG------- | \--* ASG ref [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 [000346] ---X-------- | \--* IND ref [000345] ------------ | \--* LCL_VAR byref V25 tmp14 Zero Fseq[_array] [000354] -A-XG------- \--* ASG int [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 [000353] ---X-------- \--* IND int [000352] ------------ \--* ADD byref [000350] ------------ +--* LCL_VAR byref V25 tmp14 [000351] ------------ \--* CNS_INT long 8 Fseq[_index] ------------ BB17 [095..0B5) -> BB20 (cond), preds={BB26} succs={BB19,BB20} ***** BB17 STMT00013 (IL 0x095...0x0A7) [000073] -ACXG+------ * ASG struct (copy) [000071] D----+-N---- +--* LCL_VAR struct V13 tmp2 [000070] --CXG+------ \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000360] -ACXG-----L- this SETUP +--* ASG ref [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 [000066] --CXG+------ | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 [000069] -----+------ arg2 in rsi +--* LCL_VAR ref V01 arg1 [000356] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ***** BB17 STMT00014 (IL ???... ???) [000078] -A---+------ * ASG ref [000077] D----+-N---- +--* LCL_VAR ref V10 loc4 [000076] -----+------ \--* LCL_FLD ref V13 tmp2 [+0] Fseq[Type] ***** BB17 STMT00051 (IL 0x0A9... ???) [000245] -A---+------ * ASG bool [000244] D----+-N---- +--* LCL_VAR int V19 tmp8 [000243] -----+------ \--* CNS_INT int 0 ***** BB17 STMT00046 (IL 0x0A9... ???) [000228] --CXG+------ * JTRUE void [000249] J-CXG+-N---- \--* NE int [000247] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] -----+------ this in rdi | +--* LCL_VAR ref V10 loc4 [000365] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000248] -----+------ \--* CNS_INT int 4 ------------ BB19 [0A9..0AA) -> BB21 (always), preds={BB17} succs={BB21} ***** BB19 STMT00049 (IL 0x0A9... ???) [000239] --CXG+------ * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics [000237] -----+------ arg0 in rdi +--* LCL_VAR ref V10 loc4 [000238] -----+------ arg1 in rsi \--* LCL_VAR byref V05 arg5 ***** BB19 STMT00050 (IL 0x0A9... ???) [000242] -A---+------ * ASG bool [000241] D----+-N---- +--* LCL_VAR int V19 tmp8 [000240] -----+------ \--* CNS_INT int 0 ------------ BB20 [0A9..0AA), preds={BB17} succs={BB21} ***** BB20 STMT00048 (IL 0x0A9... ???) [000234] -ACXG+------ * ASG bool [000233] D----+-N---- +--* LCL_VAR int V19 tmp8 [000232] --CXG+------ \--* CAST int <- bool <- int [000230] --CXG+------ \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] -----+------ arg0 in rdi +--* LCL_VAR ref V03 arg3 [000229] -----+------ arg1 in rsi +--* LCL_VAR ref V10 loc4 [000081] -----+------ arg2 in rdx \--* LCL_VAR byref V05 arg5 ------------ BB21 [0A9..0AA) -> BB26 (cond), preds={BB19,BB20} succs={BB23,BB26} ***** BB21 STMT00016 (IL ???... ???) [000087] -----+------ * JTRUE void [000086] J----+-N---- \--* NE int [000235] -----+------ +--* LCL_VAR int V19 tmp8 [000085] -----+------ \--* CNS_INT int 0 ------------ BB23 [0B5..0B9) -> BB25 (cond), preds={BB21} succs={BB24,BB25} ***** BB23 STMT00017 (IL 0x0B5...0x0B7) [000091] -----+------ * JTRUE void [000090] J----+-N---- \--* EQ int [000088] -----+------ +--* LCL_VAR ref V04 arg4 [000089] -----+------ \--* CNS_INT ref null ------------ BB24 [0B9..0DF), preds={BB23} succs={BB25} ***** BB24 STMT00019 (IL 0x0B9...0x0CA) [000101] -ACXG+------ * ASG ref [000100] D----+-N---- +--* LCL_VAR ref V14 tmp3 [000099] --CXG+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000098] -----+------ arg0 in rdi \--* CNS_INT long 2 ***** BB24 STMT00020 (IL ???... ???) [000107] -A-XG+------ * ASG ref [000384] ---XG+-N---- +--* COMMA ref [000378] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000104] -----+------ | | +--* CNS_INT int 0 [000377] ---X-+------ | | \--* ARR_LENGTH int [000103] -----+------ | | \--* LCL_VAR ref V14 tmp3 [000106] a---G+-N---- | \--* IND ref [000383] -----+------ | \--* ADD byref [000375] -----+------ | +--* LCL_VAR ref V14 tmp3 [000382] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000105] -----+------ \--* LCL_VAR ref V03 arg3 ***** BB24 STMT00021 (IL ???...0x0CF) [000112] -A-XG+------ * ASG ref [000394] ---XG+-N---- +--* COMMA ref [000388] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000109] -----+------ | | +--* CNS_INT int 1 [000387] ---X-+------ | | \--* ARR_LENGTH int [000108] -----+------ | | \--* LCL_VAR ref V14 tmp3 [000111] a---G+-N---- | \--* IND ref [000393] -----+------ | \--* ADD byref [000385] -----+------ | +--* LCL_VAR ref V14 tmp3 [000392] -----+------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] [000110] -----+------ \--* LCL_VAR ref V10 loc4 ***** BB24 STMT00052 (IL ???... ???) [000261] -AC--+------ * ASG ref [000260] D----+-N---- +--* LCL_VAR ref V20 tmp9 [000259] --C--+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW ***** BB24 STMT00053 (IL ???... ???) [000263] --CXG+------ * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000396] -ACXG-----L- arg1 SETUP +--* ASG ref [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 [000255] --CXG+------ | \--* IND ref [000254] --CXG+------ | \--* ADD byref [000252] H-CXG+------ | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] -----+------ | \--* CNS_INT int 0x418 Fseq[Instance] [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 [000262] -----+------ this in rdi +--* LCL_VAR ref V20 tmp9 [000102] -----+------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 [000256] -----+------ arg2 in rdx \--* CNS_INT int 0x7D2C ***** BB24 STMT00023 (IL ???... ???) [000117] IA---+------ * ASG struct (init) [000115] D----+-N---- +--* LCL_VAR struct V15 tmp4 [000116] -----+------ \--* CNS_INT int 0 ***** BB24 STMT00054 (IL ???... ???) [000269] IA---+------ * ASG struct (init) [000267] D----+-N---- +--* LCL_VAR struct V15 tmp4 [000268] -----+------ \--* CNS_INT int 0 ***** BB24 STMT00055 (IL ???... ???) [000273] -A---+------ * ASG ref [000272] U----+-N---- +--* LCL_FLD ref V15 tmp4 [+0] Fseq[TypeParameter] [000096] -----+------ \--* LCL_VAR ref V02 arg2 ***** BB24 STMT00056 (IL ???... ???) [000277] -A---+------ * ASG ref [000276] U----+-N---- +--* LCL_FLD ref V15 tmp4 [+8] Fseq[DiagnosticInfo] [000264] -----+------ \--* LCL_VAR ref V20 tmp9 ***** BB24 STMT00025 (IL 0x0DA... ???) [000122] --CXG+------ * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct ( 3, 3) [000123] ------------ | \--* ADDR byref ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 [000095] -----+------ this in rdi +--* LCL_VAR ref V04 arg4 [000401] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ------------ BB25 [0DF..0E1), preds={BB23,BB24} succs={BB26} ***** BB25 STMT00018 (IL 0x0DF...0x0E0) [000094] -A---+------ * ASG int [000093] D----+-N---- +--* LCL_VAR int V07 loc1 [000092] -----+------ \--* CNS_INT int 0 ------------ BB26 [0E1..0EA) -> BB17 (cond), preds={BB16,BB21,BB25} succs={BB27,BB17} ***** BB26 STMT00012 (IL 0x0E1...0x0E8) [000063] --CXG+------ * JTRUE void [000062] J-CXG+-N---- \--* NE int [000060] --CXG+------ +--* CAST int <- bool <- int [000057] --CXG+------ | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 [000061] -----+------ \--* CNS_INT int 0 ------------ BB27 [0EA..0EC), preds={BB26} succs={BB28} ***** BB27 STMT00026 (IL 0x0EA...0x0EB) [000127] -A---+------ * ASG int [000126] D----+-N---- +--* LCL_VAR int V06 loc0 [000125] -----+------ \--* LCL_VAR int V07 loc1 ------------ BB28 [0EC..0EE) (return), preds={BB02,BB27} succs={} ***** BB28 STMT00027 (IL 0x0EC...0x0ED) [000129] -----+------ * RETURN int [000128] -----+------ \--* LCL_VAR int V06 loc0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie *************** Starting PHASE Mark GC poll blocks *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) i label target gcsafe IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB28 (always) i rare IBC BB03 [0002] 1 BB01 20988. 20988 [00F..019)-> BB07 ( cond ) i label target gcsafe IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040) i rare label target IBC BB07 [0006] 2 BB03,BB06 20988. 20988 [040..048)-> BB10 ( cond ) i label target gcsafe IBC BB08 [0007] 1 BB07 131 131 [048..053)-> BB10 ( cond ) i gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 20988. 20988 [055..05D)-> BB13 ( cond ) i label target gcsafe IBC BB11 [0010] 1 BB10 614 614 [05D..068)-> BB13 ( cond ) i gcsafe IBC BB12 [0011] 1 BB11 22 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 20988. 20988 [06A..072)-> BB16 ( cond ) i label target gcsafe IBC BB14 [0013] 1 BB13 87 87 [072..080)-> BB16 ( cond ) i gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 20988. 20988 [082..095)-> BB26 (always) i label target gcsafe IBC BB17 [0016] 1 BB26 6120. 6120 [095..0B5)-> BB20 ( cond ) i label target gcsafe bwd bwd-target IBC BB19 [0027] 1 BB17 3060. [0A9..0AA)-> BB21 (always) i gcsafe bwd BB20 [0028] 1 BB17 3060. [0A9..0AA) i label target gcsafe bwd BB21 [0029] 2 BB19,BB20 6120. 6120 [0A9..0AA)-> BB26 ( cond ) i label target bwd IBC BB23 [0017] 1 BB21 479 479 [0B5..0B9)-> BB25 ( cond ) i bwd IBC BB24 [0018] 1 BB23 479 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB25 [0019] 2 BB23,BB24 479 479 [0DF..0E1) i label target bwd IBC BB26 [0020] 3 BB16,BB21,BB25 27108. 27108 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB27 [0021] 1 BB26 20988. 20988 [0EA..0EC) i IBC BB28 [0022] 2 BB02,BB27 20988. 20988 [0EC..0EE) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB19 to BB18 Renumber BB20 to BB19 Renumber BB21 to BB20 Renumber BB23 to BB21 Renumber BB24 to BB22 Renumber BB25 to BB23 Renumber BB26 to BB24 Renumber BB27 to BB25 Renumber BB28 to BB26 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 20988. 20988 [000..008)-> BB03 ( cond ) i label target gcsafe IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare IBC BB03 [0002] 1 BB01 20988. 20988 [00F..019)-> BB07 ( cond ) i label target gcsafe IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040) i rare label target IBC BB07 [0006] 2 BB03,BB06 20988. 20988 [040..048)-> BB10 ( cond ) i label target gcsafe IBC BB08 [0007] 1 BB07 131 131 [048..053)-> BB10 ( cond ) i gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 20988. 20988 [055..05D)-> BB13 ( cond ) i label target gcsafe IBC BB11 [0010] 1 BB10 614 614 [05D..068)-> BB13 ( cond ) i gcsafe IBC BB12 [0011] 1 BB11 22 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 20988. 20988 [06A..072)-> BB16 ( cond ) i label target gcsafe IBC BB14 [0013] 1 BB13 87 87 [072..080)-> BB16 ( cond ) i gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 20988. 20988 [082..095)-> BB24 (always) i label target gcsafe IBC BB17 [0016] 1 BB24 6120. 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 3060. [0A9..0AA)-> BB20 (always) i gcsafe bwd BB19 [0028] 1 BB17 3060. [0A9..0AA) i label target gcsafe bwd BB20 [0029] 2 BB18,BB19 6120. 6120 [0A9..0AA)-> BB24 ( cond ) i label target bwd IBC BB21 [0017] 1 BB20 479 479 [0B5..0B9)-> BB23 ( cond ) i bwd IBC BB22 [0018] 1 BB21 479 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 479 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB16,BB20,BB23 27108. 27108 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB25 [0021] 1 BB24 20988. 20988 [0EA..0EC) i IBC BB26 [0022] 2 BB02,BB25 20988. 20988 [0EC..0EE) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 3, # of blocks (including unused BB00): 27, bitset array size: 1 (short) *************** Finishing PHASE Mark GC poll blocks *************** Starting PHASE Compute edge weights (1, false) *************** In fgComputeBlockAndEdgeWeights() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 209.88 20988 [000..008)-> BB03 ( cond ) i label target gcsafe IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare IBC BB03 [0002] 1 BB01 209.88 20988 [00F..019)-> BB07 ( cond ) i label target gcsafe IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040) i rare label target IBC BB07 [0006] 2 BB03,BB06 209.88 20988 [040..048)-> BB10 ( cond ) i label target gcsafe IBC BB08 [0007] 1 BB07 1.31 131 [048..053)-> BB10 ( cond ) i gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 209.88 20988 [055..05D)-> BB13 ( cond ) i label target gcsafe IBC BB11 [0010] 1 BB10 6.14 614 [05D..068)-> BB13 ( cond ) i gcsafe IBC BB12 [0011] 1 BB11 0.22 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 209.88 20988 [06A..072)-> BB16 ( cond ) i label target gcsafe IBC BB14 [0013] 1 BB13 0.87 87 [072..080)-> BB16 ( cond ) i gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 209.88 20988 [082..095)-> BB24 (always) i label target gcsafe IBC BB17 [0016] 1 BB24 61.20 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 30.60 [0A9..0AA)-> BB20 (always) i gcsafe bwd BB19 [0028] 1 BB17 30.60 [0A9..0AA) i label target gcsafe bwd BB20 [0029] 2 BB18,BB19 61.20 6120 [0A9..0AA)-> BB24 ( cond ) i label target bwd IBC BB21 [0017] 1 BB20 4.79 479 [0B5..0B9)-> BB23 ( cond ) i bwd IBC BB22 [0018] 1 BB21 4.79 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 4.79 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB16,BB20,BB23 271.08 27108 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB25 [0021] 1 BB24 209.88 20988 [0EA..0EC) i IBC BB26 [0022] 2 BB02,BB25 209.88 20988 [0EC..0EE) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- We are using the Profile Weights and fgCalledCount is 20988. fgComputeEdgeWeights() was able to compute exact edge weights for all of the 38 edges, using 1 passes. Edge weights into BB02 :BB01 (0) Edge weights into BB03 :BB01 (20988) Edge weights into BB04 :BB03 (0) Edge weights into BB05 :BB04 (0) Edge weights into BB06 :BB04 (0), BB05 (0) Edge weights into BB07 :BB03 (20988), BB06 (0) Edge weights into BB08 :BB07 (131) Edge weights into BB09 :BB08 (0) Edge weights into BB10 :BB07 (20857), BB08 (131), BB09 (0) Edge weights into BB11 :BB10 (614) Edge weights into BB12 :BB11 (22) Edge weights into BB13 :BB10 (20374), BB11 (592), BB12 (22) Edge weights into BB14 :BB13 (87) Edge weights into BB15 :BB14 (0) Edge weights into BB16 :BB13 (20901), BB14 (87), BB15 (0) Edge weights into BB17 :BB24 (6120) Edge weights into BB18 :BB17 (3060) Edge weights into BB19 :BB17 (3060) Edge weights into BB20 :BB18 (3060), BB19 (3060) Edge weights into BB21 :BB20 (479) Edge weights into BB22 :BB21 (479) Edge weights into BB23 :BB21 (0), BB22 (479) Edge weights into BB24 :BB16 (20988), BB20 (5641), BB23 (479) Edge weights into BB25 :BB24 (20988) Edge weights into BB26 :BB02 (0), BB25 (20988) *************** Finishing PHASE Compute edge weights (1, false) *************** Starting PHASE Create EH funclets *************** In fgCreateFunclets() After fgCreateFunclets() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB03 ( cond ) i label target gcsafe IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB07 ( cond ) i label target gcsafe IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040) i rare label target IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB10 ( cond ) i label target gcsafe IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB13 ( cond ) i label target gcsafe IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB16 ( cond ) i label target gcsafe IBC BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB16 ( cond ) i gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 1 20988 [082..095)-> BB24 (always) i label target gcsafe IBC BB17 [0016] 1 BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB20 (always) i gcsafe bwd BB19 [0028] 1 BB17 0.15 [0A9..0AA) i label target gcsafe bwd BB20 [0029] 2 BB18,BB19 0.29 6120 [0A9..0AA)-> BB24 ( cond ) i label target bwd IBC BB21 [0017] 1 BB20 0.02 479 [0B5..0B9)-> BB23 ( cond ) i bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB16,BB20,BB23 1.29 27108 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB25 [0021] 1 BB24 1 20988 [0EA..0EC) i IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Create EH funclets *************** Starting PHASE Optimize layout *************** In optOptimizeLayout() *************** Exception Handling table is empty *************** In fgDebugCheckBBlist Duplication of loop condition [000062] is performed, because the cost of duplication (27) is less or equal than 32, loopIterations = 0.292, countOfHelpers = 0, validProfileWeights = true Duplicating loop condition in BB16 for loop (BB17 - BB24) Estimated code size expansion is 27 STMT00057 (IL 0x0E1... ???) [000419] --CXG------- * JTRUE void ( 25, 27) [000409] J-CXG--N---- \--* EQ int ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 fgComputeEdgeWeights() was able to compute exact edge weights for 35 of the 39 edges, using 2 passes. Edge weights into BB02 :BB01 (0) Edge weights into BB03 :BB01 (20988) Edge weights into BB04 :BB03 (0) Edge weights into BB05 :BB04 (0) Edge weights into BB06 :BB04 (0), BB05 (0) Edge weights into BB07 :BB03 (20988), BB06 (0) Edge weights into BB08 :BB07 (131) Edge weights into BB09 :BB08 (0) Edge weights into BB10 :BB07 (20857), BB08 (131), BB09 (0) Edge weights into BB11 :BB10 (614) Edge weights into BB12 :BB11 (22) Edge weights into BB13 :BB10 (20374), BB11 (592), BB12 (22) Edge weights into BB14 :BB13 (87) Edge weights into BB15 :BB14 (0) Edge weights into BB16 :BB13 (20901), BB14 (87), BB15 (0) Edge weights into BB17 :BB16 (0..6120), BB24 (0..6120) Edge weights into BB18 :BB17 (3060) Edge weights into BB19 :BB17 (3060) Edge weights into BB20 :BB18 (3060), BB19 (3060) Edge weights into BB21 :BB20 (479) Edge weights into BB22 :BB21 (479) Edge weights into BB23 :BB21 (0), BB22 (479) Edge weights into BB24 :BB20 (5641), BB23 (479) Edge weights into BB25 :BB16 (14868..20988), BB24 (0..6120) Edge weights into BB26 :BB02 (0), BB25 (20988) *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB03 ( cond ) i label target gcsafe IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB07 ( cond ) i label target gcsafe IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040) i rare label target IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB10 ( cond ) i label target gcsafe IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB13 ( cond ) i label target gcsafe IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB16 ( cond ) i label target gcsafe IBC BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB16 ( cond ) i gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 1 20988 [082..095)-> BB25 ( cond ) i label target gcsafe IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB20 (always) i gcsafe bwd BB19 [0028] 1 BB17 0.15 [0A9..0AA) i label target gcsafe bwd BB20 [0029] 2 BB18,BB19 0.29 6120 [0A9..0AA)-> BB24 ( cond ) i label target bwd IBC BB21 [0017] 1 BB20 0.02 479 [0B5..0B9)-> BB23 ( cond ) i bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 2 BB20,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB25 [0021] 2 BB16,BB24 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- New Basic Block BB27 [0034] created. fgOptimizeUncondBranchToSimpleCond(from BB18 to cond BB20), created new uncond BB27 expecting opts to key off V19, added cloned compare [000420] to BB18 Compacting blocks BB19 and BB20: *************** In fgDebugCheckBBlist After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB03 ( cond ) i label target gcsafe IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB07 ( cond ) i label target gcsafe IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040) i rare label target IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB10 ( cond ) i label target gcsafe IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB13 ( cond ) i label target gcsafe IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB16 ( cond ) i label target gcsafe IBC BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB16 ( cond ) i gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 1 20988 [082..095)-> BB25 ( cond ) i label target gcsafe IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB24 ( cond ) i label target gcsafe bwd IBC BB21 [0017] 2 BB19,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB25 [0021] 2 BB16,BB24 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB03 ( cond ) i label target gcsafe IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB07 ( cond ) i label target gcsafe IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040) i rare label target IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB10 ( cond ) i label target gcsafe IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB13 ( cond ) i label target gcsafe IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB16 ( cond ) i label target gcsafe IBC BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB16 ( cond ) i gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 1 20988 [082..095)-> BB25 ( cond ) i label target gcsafe IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB24 ( cond ) i label target gcsafe bwd IBC BB21 [0017] 2 BB19,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB25 [0021] 2 BB16,BB24 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB01 branch to BB03 because of IBC profile data Relocated rarely run block BB02 by reversing conditional jump at BB01 Relocated block [BB02..BB02] inserted after BB26 at the end of method After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB07 ( cond ) i label target gcsafe IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040) i rare label target IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB10 ( cond ) i label target gcsafe IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB13 ( cond ) i label target gcsafe IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB16 ( cond ) i label target gcsafe IBC BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB16 ( cond ) i gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 1 20988 [082..095)-> BB25 ( cond ) i label target gcsafe IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB24 ( cond ) i label target gcsafe bwd IBC BB21 [0017] 2 BB19,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB25 [0021] 2 BB16,BB24 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB03 branch to BB07 because of IBC profile data Relocated rarely run blocks (BB04 .. BB06) by reversing conditional jump at BB03 Relocated blocks [BB04..BB06] inserted after BB02 at the end of method Block BB06 ended with a BBJ_NONE, Changed to an unconditional jump to BB07 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB04 ( cond ) i label target gcsafe IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB10 ( cond ) i label target gcsafe IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055) i rare IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB13 ( cond ) i label target gcsafe IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB16 ( cond ) i label target gcsafe IBC BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB16 ( cond ) i gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 1 20988 [082..095)-> BB25 ( cond ) i label target gcsafe IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB24 ( cond ) i label target gcsafe bwd IBC BB21 [0017] 2 BB19,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB25 [0021] 2 BB16,BB24 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare label target IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040)-> BB07 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB07 branch to BB10 because of IBC profile data fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB10, jumpBlk=BB00, runRarely=false) Relocated uncommon blocks (BB08 .. BB09) by reversing conditional jump at BB07 Relocated blocks [BB08..BB09] inserted after BB27 Block BB09 ended with a BBJ_NONE, Changed to an unconditional jump to BB10 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB04 ( cond ) i label target gcsafe IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB08 ( cond ) i label target gcsafe IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB13 ( cond ) i label target gcsafe IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A) i IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB16 ( cond ) i label target gcsafe IBC BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB16 ( cond ) i gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 1 20988 [082..095)-> BB25 ( cond ) i label target gcsafe IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i label target gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055)-> BB10 (always) i rare IBC BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB24 ( cond ) i label target gcsafe bwd IBC BB21 [0017] 2 BB19,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB25 [0021] 2 BB16,BB24 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare label target IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040)-> BB07 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB10 branch to BB13 because of IBC profile data fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB13, jumpBlk=BB00, runRarely=false) Relocated uncommon blocks (BB11 .. BB12) by reversing conditional jump at BB10 Relocated blocks [BB11..BB12] inserted after BB27 Block BB12 ended with a BBJ_NONE, Changed to an unconditional jump to BB13 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB04 ( cond ) i label target gcsafe IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB08 ( cond ) i label target gcsafe IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB11 ( cond ) i label target gcsafe IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB16 ( cond ) i label target gcsafe IBC BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB16 ( cond ) i gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082) i rare IBC BB16 [0015] 3 BB13,BB14,BB15 1 20988 [082..095)-> BB25 ( cond ) i label target gcsafe IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i label target gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A)-> BB13 (always) i IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i label target gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055)-> BB10 (always) i rare IBC BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB24 ( cond ) i label target gcsafe bwd IBC BB21 [0017] 2 BB19,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB25 [0021] 2 BB16,BB24 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare label target IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040)-> BB07 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB13 branch to BB16 because of IBC profile data fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB16, jumpBlk=BB00, runRarely=false) Relocated uncommon blocks (BB14 .. BB15) by reversing conditional jump at BB13 Relocated blocks [BB14..BB15] inserted after BB27 Block BB15 ended with a BBJ_NONE, Changed to an unconditional jump to BB16 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB04 ( cond ) i label target gcsafe IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB08 ( cond ) i label target gcsafe IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB11 ( cond ) i label target gcsafe IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB14 ( cond ) i label target gcsafe IBC BB16 [0015] 3 BB13,BB14,BB15 1 20988 [082..095)-> BB25 ( cond ) i label target gcsafe IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB16 ( cond ) i label target gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082)-> BB16 (always) i rare IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i label target gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A)-> BB13 (always) i IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i label target gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055)-> BB10 (always) i rare IBC BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB24 ( cond ) i label target gcsafe bwd IBC BB21 [0017] 2 BB19,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB25 [0021] 2 BB16,BB24 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare label target IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040)-> BB07 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB16 branch to BB25 because of IBC profile data Relocated hot blocks (BB25 .. BB26) by reversing conditional jump at BB16 Relocated blocks [BB25..BB26] inserted after BB16 New Basic Block BB28 [0035] created. Added an unconditional jump to BB25 after block BB24 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB04 ( cond ) i label target gcsafe IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB08 ( cond ) i label target gcsafe IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB11 ( cond ) i label target gcsafe IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB14 ( cond ) i label target gcsafe IBC BB16 [0015] 3 BB13,BB14,BB15 1 20988 [082..095)-> BB17 ( cond ) i label target gcsafe IBC BB25 [0021] 2 BB16,BB28 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB16 ( cond ) i label target gcsafe IBC BB15 [0014] 1 BB14 0 0 [080..082)-> BB16 (always) i rare IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i label target gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A)-> BB13 (always) i IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i label target gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055)-> BB10 (always) i rare IBC BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB24 ( cond ) i label target gcsafe bwd IBC BB21 [0017] 2 BB19,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB28 [0035] 1 BB24 0.15 [???..???)-> BB25 (always) internal BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare label target IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040)-> BB07 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB14 branch to BB16 since it falls into a rarely run block Relocated rarely run block BB15 by reversing conditional jump at BB14 Relocated block [BB15..BB15] inserted after BB06 at the end of method New Basic Block BB29 [0036] created. Added an unconditional jump to BB16 after block BB14 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB04 ( cond ) i label target gcsafe IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB08 ( cond ) i label target gcsafe IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB11 ( cond ) i label target gcsafe IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB14 ( cond ) i label target gcsafe IBC BB16 [0015] 3 BB13,BB29,BB15 1 20988 [082..095)-> BB17 ( cond ) i label target gcsafe IBC BB25 [0021] 2 BB16,BB28 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB15 ( cond ) i label target gcsafe IBC BB29 [0036] 1 BB14 0.01 87 [???..???)-> BB16 (always) internal IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i label target gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A)-> BB13 (always) i IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i label target gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055)-> BB10 (always) i rare IBC BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB24 ( cond ) i label target gcsafe bwd IBC BB21 [0017] 2 BB19,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB28 [0035] 1 BB24 0.15 [???..???)-> BB25 (always) internal BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare label target IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040)-> BB07 (always) i rare label target IBC BB15 [0014] 1 BB14 0 0 [080..082)-> BB16 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Decided to straighten unconditional branch at block BB29 branch to BB19 because of IBC profile data Relocated hot block BB19 Relocated block [BB19..BB19] inserted after BB29 New Basic Block BB30 [0037] created. Added an unconditional jump to BB21 after block BB19 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB04 ( cond ) i label target gcsafe IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB08 ( cond ) i label target gcsafe IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB11 ( cond ) i label target gcsafe IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB14 ( cond ) i label target gcsafe IBC BB16 [0015] 3 BB13,BB29,BB15 1 20988 [082..095)-> BB17 ( cond ) i label target gcsafe IBC BB25 [0021] 2 BB16,BB28 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB15 ( cond ) i label target gcsafe IBC BB29 [0036] 1 BB14 0.01 87 [???..???)-> BB16 (always) internal IBC BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB24 ( cond ) i label target gcsafe bwd IBC BB30 [0037] 1 BB19 0.02 479 [???..???)-> BB21 (always) internal IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i label target gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A)-> BB13 (always) i IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i label target gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055)-> BB10 (always) i rare IBC BB21 [0017] 2 BB30,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i label target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1) i label target bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB28 [0035] 1 BB24 0.15 [???..???)-> BB25 (always) internal BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare label target IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040)-> BB07 (always) i rare label target IBC BB15 [0014] 1 BB14 0 0 [080..082)-> BB16 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB19 branch to BB24 because of IBC profile data Relocated hot blocks (BB24 .. BB28) by reversing conditional jump at BB19 Relocated blocks [BB24..BB28] inserted after BB19 Block BB23 ended with a BBJ_NONE, Changed to an unconditional jump to BB24 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB04 ( cond ) i label target gcsafe IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB08 ( cond ) i label target gcsafe IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB11 ( cond ) i label target gcsafe IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB14 ( cond ) i label target gcsafe IBC BB16 [0015] 3 BB13,BB29,BB15 1 20988 [082..095)-> BB17 ( cond ) i label target gcsafe IBC BB25 [0021] 2 BB16,BB28 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB15 ( cond ) i label target gcsafe IBC BB29 [0036] 1 BB14 0.01 87 [???..???)-> BB16 (always) internal IBC BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB30 ( cond ) i label target gcsafe bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB28 [0035] 1 BB24 0.15 [???..???)-> BB25 (always) internal BB30 [0037] 1 BB19 0.02 479 [???..???)-> BB21 (always) internal label target IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i label target gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A)-> BB13 (always) i IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i label target gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055)-> BB10 (always) i rare IBC BB21 [0017] 2 BB30,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i label target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1)-> BB24 (always) i label target bwd IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare label target IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040)-> BB07 (always) i rare label target IBC BB15 [0014] 1 BB14 0 0 [080..082)-> BB16 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Decided to straighten unconditional branch at block BB12 branch to BB21 because of IBC profile data Relocated hot blocks (BB21 .. BB23) Relocated blocks [BB21..BB23] inserted after BB12 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB04 ( cond ) i label target gcsafe IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB08 ( cond ) i label target gcsafe IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB11 ( cond ) i label target gcsafe IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB14 ( cond ) i label target gcsafe IBC BB16 [0015] 3 BB13,BB29,BB15 1 20988 [082..095)-> BB17 ( cond ) i label target gcsafe IBC BB25 [0021] 2 BB16,BB28 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB15 ( cond ) i label target gcsafe IBC BB29 [0036] 1 BB14 0.01 87 [???..???)-> BB16 (always) internal IBC BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB30 ( cond ) i label target gcsafe bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB28 [0035] 1 BB24 0.15 [???..???)-> BB25 (always) internal BB30 [0037] 1 BB19 0.02 479 [???..???)-> BB21 (always) internal label target IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i label target gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A)-> BB13 (always) i IBC BB21 [0017] 2 BB30,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i label target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1)-> BB24 (always) i label target bwd IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i label target gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055)-> BB10 (always) i rare IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare label target IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040)-> BB07 (always) i rare label target IBC BB15 [0014] 1 BB14 0 0 [080..082)-> BB16 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB04 ( cond ) i label target gcsafe IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB08 ( cond ) i label target gcsafe IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB11 ( cond ) i label target gcsafe IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB14 ( cond ) i label target gcsafe IBC BB16 [0015] 3 BB13,BB29,BB15 1 20988 [082..095)-> BB17 ( cond ) i label target gcsafe IBC BB25 [0021] 2 BB16,BB28 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB15 ( cond ) i label target gcsafe IBC BB29 [0036] 1 BB14 0.01 87 [???..???)-> BB16 (always) internal IBC BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB30 ( cond ) i label target gcsafe bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB28 [0035] 1 BB24 0.15 [???..???)-> BB25 (always) internal BB30 [0037] 1 BB19 0.02 479 [???..???)-> BB21 (always) internal label target IBC BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i label target gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A)-> BB13 (always) i IBC BB21 [0017] 2 BB30,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i label target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1)-> BB24 (always) i label target bwd IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i label target gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055)-> BB10 (always) i rare IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare label target IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040)-> BB07 (always) i rare label target IBC BB15 [0014] 1 BB14 0 0 [080..082)-> BB16 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- Optimizing a jump to an unconditional jump (BB19 -> BB30 -> BB21) fgRemoveBlock BB30 Removing unreachable BB30 After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB04 ( cond ) i label target gcsafe IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB08 ( cond ) i label target gcsafe IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB11 ( cond ) i label target gcsafe IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB14 ( cond ) i label target gcsafe IBC BB16 [0015] 3 BB13,BB29,BB15 1 20988 [082..095)-> BB17 ( cond ) i label target gcsafe IBC BB25 [0021] 2 BB16,BB28 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB15 ( cond ) i label target gcsafe IBC BB29 [0036] 1 BB14 0.01 87 [???..???)-> BB16 (always) internal IBC BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB21 ( cond ) i label target gcsafe bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB28 [0035] 1 BB24 0.15 [???..???)-> BB25 (always) internal BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i label target gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A)-> BB13 (always) i IBC BB21 [0017] 2 BB19,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i label target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1)-> BB24 (always) i label target bwd IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i label target gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055)-> BB10 (always) i rare IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare label target IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040)-> BB07 (always) i rare label target IBC BB15 [0014] 1 BB14 0 0 [080..082)-> BB16 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize layout *************** Starting PHASE Compute blocks reachability *************** In fgComputeReachability *************** In fgDebugCheckBBlist Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB02 ( cond ) i label target gcsafe IBC BB03 [0002] 1 BB01 1 20988 [00F..019)-> BB04 ( cond ) i label target gcsafe IBC BB07 [0006] 2 BB03,BB06 1 20988 [040..048)-> BB08 ( cond ) i label target gcsafe IBC BB10 [0009] 3 BB07,BB08,BB09 1 20988 [055..05D)-> BB11 ( cond ) i label target gcsafe IBC BB13 [0012] 3 BB10,BB11,BB12 1 20988 [06A..072)-> BB14 ( cond ) i label target gcsafe IBC BB16 [0015] 3 BB13,BB29,BB15 1 20988 [082..095)-> BB17 ( cond ) i label target gcsafe IBC BB25 [0021] 2 BB16,BB28 1 20988 [0EA..0EC) i label target IBC BB26 [0022] 2 BB02,BB25 1 20988 [0EC..0EE) (return) i label target IBC BB17 [0016] 2 BB16,BB24 0.29 6120 [095..0B5)-> BB19 ( cond ) i label target gcsafe bwd bwd-target IBC BB18 [0027] 1 BB17 0.15 [0A9..0AA)-> BB24 ( cond ) i gcsafe bwd BB27 [0034] 1 BB18 0.15 [???..???)-> BB21 (always) internal BB14 [0013] 1 BB13 0.01 87 [072..080)-> BB15 ( cond ) i label target gcsafe IBC BB29 [0036] 1 BB14 0.01 87 [???..???)-> BB16 (always) internal IBC BB19 [0028] 1 BB17 0.29 6120 [0A9..0AA)-> BB21 ( cond ) i label target gcsafe bwd IBC BB24 [0020] 3 BB18,BB19,BB23 0.29 6120 [0E1..0EA)-> BB17 ( cond ) i label target gcsafe bwd IBC BB28 [0035] 1 BB24 0.15 [???..???)-> BB25 (always) internal BB11 [0010] 1 BB10 0.03 614 [05D..068)-> BB13 ( cond ) i label target gcsafe IBC BB12 [0011] 1 BB11 0.01 22 [068..06A)-> BB13 (always) i IBC BB21 [0017] 2 BB19,BB27 0.02 479 [0B5..0B9)-> BB23 ( cond ) i label target bwd IBC BB22 [0018] 1 BB21 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB23 [0019] 2 BB21,BB22 0.02 479 [0DF..0E1)-> BB24 (always) i label target bwd IBC BB08 [0007] 1 BB07 0.01 131 [048..053)-> BB10 ( cond ) i label target gcsafe IBC BB09 [0008] 1 BB08 0 0 [053..055)-> BB10 (always) i rare IBC BB02 [0001] 1 BB01 0 0 [008..00F)-> BB26 (always) i rare label target IBC BB04 [0003] 1 BB03 0 0 [019..01D)-> BB06 ( cond ) i rare label target IBC BB05 [0004] 1 BB04 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB06 [0005] 2 BB04,BB05 0 0 [03E..040)-> BB07 (always) i rare label target IBC BB15 [0014] 1 BB14 0 0 [080..082)-> BB16 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB03 to BB02 Renumber BB07 to BB03 Renumber BB10 to BB04 Renumber BB13 to BB05 Renumber BB16 to BB06 Renumber BB25 to BB07 Renumber BB26 to BB08 Renumber BB17 to BB09 Renumber BB18 to BB10 Renumber BB27 to BB11 Renumber BB14 to BB12 Renumber BB29 to BB13 Renumber BB19 to BB14 Renumber BB24 to BB15 Renumber BB28 to BB16 Renumber BB11 to BB17 Renumber BB12 to BB18 Renumber BB21 to BB19 Renumber BB22 to BB20 Renumber BB23 to BB21 Renumber BB08 to BB22 Renumber BB09 to BB23 Renumber BB02 to BB24 Renumber BB04 to BB25 Renumber BB05 to BB26 Renumber BB06 to BB27 Renumber BB15 to BB28 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.15 [0A9..0AA)-> BB15 ( cond ) i gcsafe bwd BB11 [0034] 1 BB10 0.15 [???..???)-> BB19 (always) internal BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 3 BB10,BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i IBC BB19 [0017] 2 BB14,BB11 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 4, # of blocks (including unused BB00): 29, bitset array size: 1 (short) Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 BB03 : BB01 BB02 BB03 BB25 BB26 BB27 BB04 : BB01 BB02 BB03 BB04 BB22 BB23 BB25 BB26 BB27 BB05 : BB01 BB02 BB03 BB04 BB05 BB17 BB18 BB22 BB23 BB25 BB26 BB27 BB06 : BB01 BB02 BB03 BB04 BB05 BB06 BB12 BB13 BB17 BB18 BB22 BB23 BB25 BB26 BB27 BB28 BB07 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB25 BB26 BB27 BB28 BB08 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB09 : BB01 BB02 BB03 BB04 BB05 BB06 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB25 BB26 BB27 BB28 BB10 : BB01 BB02 BB03 BB04 BB05 BB06 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB25 BB26 BB27 BB28 BB11 : BB01 BB02 BB03 BB04 BB05 BB06 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB25 BB26 BB27 BB28 BB12 : BB01 BB02 BB03 BB04 BB05 BB12 BB17 BB18 BB22 BB23 BB25 BB26 BB27 BB13 : BB01 BB02 BB03 BB04 BB05 BB12 BB13 BB17 BB18 BB22 BB23 BB25 BB26 BB27 BB14 : BB01 BB02 BB03 BB04 BB05 BB06 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB25 BB26 BB27 BB28 BB15 : BB01 BB02 BB03 BB04 BB05 BB06 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB25 BB26 BB27 BB28 BB16 : BB01 BB02 BB03 BB04 BB05 BB06 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB25 BB26 BB27 BB28 BB17 : BB01 BB02 BB03 BB04 BB17 BB22 BB23 BB25 BB26 BB27 BB18 : BB01 BB02 BB03 BB04 BB17 BB18 BB22 BB23 BB25 BB26 BB27 BB19 : BB01 BB02 BB03 BB04 BB05 BB06 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB25 BB26 BB27 BB28 BB20 : BB01 BB02 BB03 BB04 BB05 BB06 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB25 BB26 BB27 BB28 BB21 : BB01 BB02 BB03 BB04 BB05 BB06 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB25 BB26 BB27 BB28 BB22 : BB01 BB02 BB03 BB22 BB25 BB26 BB27 BB23 : BB01 BB02 BB03 BB22 BB23 BB25 BB26 BB27 BB24 : BB01 BB24 BB25 : BB01 BB02 BB25 BB26 : BB01 BB02 BB25 BB26 BB27 : BB01 BB02 BB25 BB26 BB27 BB28 : BB01 BB02 BB03 BB04 BB05 BB12 BB17 BB18 BB22 BB23 BB25 BB26 BB27 BB28 After computing reachability: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.15 [0A9..0AA)-> BB15 ( cond ) i gcsafe bwd BB11 [0034] 1 BB10 0.15 [???..???)-> BB19 (always) internal gcsafe BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 3 BB10,BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB11 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeDoms *************** In fgDebugCheckBBlist Dominator computation start blocks (those blocks with no incoming edges): BB01 ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB01: BB01 BB02: BB02 BB01 BB03: BB03 BB02 BB01 BB04: BB04 BB03 BB02 BB01 BB05: BB05 BB04 BB03 BB02 BB01 BB06: BB06 BB05 BB04 BB03 BB02 BB01 BB07: BB07 BB06 BB05 BB04 BB03 BB02 BB01 BB09: BB09 BB06 BB05 BB04 BB03 BB02 BB01 BB10: BB10 BB09 BB06 BB05 BB04 BB03 BB02 BB01 BB11: BB11 BB10 BB09 BB06 BB05 BB04 BB03 BB02 BB01 BB14: BB14 BB09 BB06 BB05 BB04 BB03 BB02 BB01 BB15: BB15 BB09 BB06 BB05 BB04 BB03 BB02 BB01 BB16: BB16 BB15 BB09 BB06 BB05 BB04 BB03 BB02 BB01 BB19: BB19 BB09 BB06 BB05 BB04 BB03 BB02 BB01 BB20: BB20 BB19 BB09 BB06 BB05 BB04 BB03 BB02 BB01 BB21: BB21 BB19 BB09 BB06 BB05 BB04 BB03 BB02 BB01 BB12: BB12 BB05 BB04 BB03 BB02 BB01 BB13: BB13 BB12 BB05 BB04 BB03 BB02 BB01 BB28: BB28 BB12 BB05 BB04 BB03 BB02 BB01 BB17: BB17 BB04 BB03 BB02 BB01 BB18: BB18 BB17 BB04 BB03 BB02 BB01 BB22: BB22 BB03 BB02 BB01 BB23: BB23 BB22 BB03 BB02 BB01 BB25: BB25 BB02 BB01 BB26: BB26 BB25 BB02 BB01 BB27: BB27 BB25 BB02 BB01 BB24: BB24 BB01 BB08: BB08 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB24 BB08 BB02 BB02 : BB25 BB03 BB03 : BB22 BB04 BB04 : BB17 BB05 BB05 : BB12 BB06 BB06 : BB09 BB07 BB09 : BB19 BB15 BB14 BB10 BB10 : BB11 BB12 : BB28 BB13 BB15 : BB16 BB17 : BB18 BB19 : BB21 BB20 BB22 : BB23 BB25 : BB27 BB26 After numbering the dominator tree: BB01: pre=01, post=28 BB02: pre=04, post=27 BB03: pre=08, post=26 BB04: pre=11, post=25 BB05: pre=14, post=24 BB06: pre=18, post=23 BB07: pre=28, post=22 BB08: pre=03, post=02 BB09: pre=19, post=21 BB10: pre=26, post=20 BB11: pre=27, post=19 BB12: pre=15, post=12 BB13: pre=17, post=11 BB14: pre=25, post=18 BB15: pre=23, post=17 BB16: pre=24, post=16 BB17: pre=12, post=09 BB18: pre=13, post=08 BB19: pre=20, post=15 BB20: pre=22, post=14 BB21: pre=21, post=13 BB22: pre=09, post=07 BB23: pre=10, post=06 BB24: pre=02, post=01 BB25: pre=05, post=05 BB26: pre=07, post=04 BB27: pre=06, post=03 BB28: pre=16, post=10 *************** Finishing PHASE Compute blocks reachability *************** Starting PHASE Optimize loops *************** In optOptimizeLoops() *************** In fgDebugCheckBBlist *************** In optFindNaturalLoops() Marking a loop from BB09 to BB15 BB09(wt=0.29) BB10(wt=0.58) BB11(wt=0.58) BB14(wt=0.29) BB15(wt=0.29) Marking a loop from BB15 to BB21 BB15(wt=0.29) BB19(wt=0.02) BB20(wt=0.02) BB21(wt=0.02) Found a total of 2 loops. After loop weight marking: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB15 ( cond ) i gcsafe bwd BB11 [0034] 1 BB10 0.58 [???..???)-> BB19 (always) internal gcsafe BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 3 BB10,BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB11 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Optimize loops *************** Starting PHASE Clone loops *************** In optCloneLoops() *************** Finishing PHASE Clone loops *************** Starting PHASE Unroll loops *************** Finishing PHASE Unroll loops *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** *** marking local variables in block BB01 (weight=1 ) STMT00001 (IL ???... ???) [000006] --CXG+------ * JTRUE void [000200] J-CXG+-N---- \--* EQ int [000198] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000000] -----+------ this in rdi | +--* LCL_VAR ref V03 arg3 [000279] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000199] -----+------ \--* CNS_INT int 4 New refCnts for V03: refCnt = 1, refCntWtd = 1 *** marking local variables in block BB02 (weight=1 ) STMT00002 (IL 0x00F...0x010) [000009] -A---+------ * ASG int [000008] D----+-N---- +--* LCL_VAR int V07 loc1 [000007] -----+------ \--* CNS_INT int 1 New refCnts for V07: refCnt = 1, refCntWtd = 1 STMT00004 (IL ???... ???) [000016] --CXG+------ * JTRUE void [000015] J-CXG+-N---- \--* NE int [000205] --CXG+------ +--* CAST int <- bool <- int [000204] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType [000203] --CXG+------ arg0 in rdi | \--* CAST int <- byte <- int [000202] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType [000010] -----+------ this in rdi | +--* LCL_VAR ref V03 arg3 [000284] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000014] -----+------ \--* CNS_INT int 0 New refCnts for V03: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB03 (weight=1 ) STMT00005 (IL 0x040...0x046) [000022] --CXG+------ * JTRUE void [000021] J-CXG+-N---- \--* NE int [000019] --CXG+------ +--* CAST int <- bool <- int [000018] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint [000017] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000312] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000020] -----+------ \--* CNS_INT int 0 New refCnts for V02: refCnt = 1, refCntWtd = 1 *** marking local variables in block BB04 (weight=1 ) STMT00006 (IL 0x055...0x05B) [000028] --CXG+------ * JTRUE void [000027] J-CXG+-N---- \--* NE int [000025] --CXG+------ +--* CAST int <- bool <- int [000024] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint [000023] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000319] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000026] -----+------ \--* CNS_INT int 0 New refCnts for V02: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB05 (weight=1 ) STMT00007 (IL 0x06A...0x070) [000034] --CXG+------ * JTRUE void [000033] J-CXG+-N---- \--* NE int [000031] --CXG+------ +--* CAST int <- bool <- int [000030] --CXG+------ | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint [000029] -----+------ this in rdi | +--* LCL_VAR ref V02 arg2 [000326] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000032] -----+------ \--* CNS_INT int 0 New refCnts for V02: refCnt = 3, refCntWtd = 3 *** marking local variables in block BB06 (weight=1 ) STMT00009 (IL ???... ???) [000042] -ACXG+------ * ASG ref [000039] D---G+-N---- +--* LCL_VAR ref (AX) V23 tmp12 [000037] --CXG+------ \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics [000035] -----+------ this in rdi +--* LCL_VAR ref V02 arg2 [000036] -----+------ arg1 in rsi \--* LCL_VAR byref V05 arg5 New refCnts for V09: refCnt = 1, refCntWtd = 1 New refCnts for V23: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 4, refCntWtd = 4 New refCnts for V05: refCnt = 1, refCntWtd = 1 STMT00010 (IL 0x08B...0x092) [000050] -ACXG+------ * ASG struct (copy) [000048] D----+-N---- +--* LCL_VAR struct(AX) V12 tmp1 [000045] --CXG+------ \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 New refCnts for V12: refCnt = 1, refCntWtd = 2 New refCnts for V23: refCnt = 2, refCntWtd = 2 New refCnts for V09: refCnt = 2, refCntWtd = 2 STMT00011 (IL ???... ???) [000355] -A-XG+------ * COMMA void [000348] -A-XG------- +--* COMMA void [000343] -A---------- | +--* ASG byref [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 [000340] -----+------ | | \--* ADDR byref [000341] -----+-N---- | | \--* LCL_VAR struct(AX) V12 tmp1 [000347] -A-XG------- | \--* ASG ref [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 [000346] ---X-------- | \--* IND ref [000345] ------------ | \--* LCL_VAR byref V25 tmp14 Zero Fseq[_array] [000354] -A-XG------- \--* ASG int [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 [000353] ---X-------- \--* IND int [000352] ------------ \--* ADD byref [000350] ------------ +--* LCL_VAR byref V25 tmp14 [000351] ------------ \--* CNS_INT long 8 Fseq[_index] New refCnts for V25: refCnt = 1, refCntWtd = 2 New refCnts for V12: refCnt = 2, refCntWtd = 4 New refCnts for V08: refCnt = 1, refCntWtd = 1 New refCnts for V21: refCnt = 1, refCntWtd = 1 New refCnts for V25: refCnt = 2, refCntWtd = 4 New refCnts for V08: refCnt = 2, refCntWtd = 2 New refCnts for V22: refCnt = 1, refCntWtd = 1 New refCnts for V25: refCnt = 3, refCntWtd = 6 STMT00057 (IL 0x0E1... ???) [000419] --CXG------- * JTRUE void ( 25, 27) [000409] J-CXG--N---- \--* NE int ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 New refCnts for V21: refCnt = 2, refCntWtd = 2 New refCnts for V22: refCnt = 2, refCntWtd = 2 New refCnts for V08: refCnt = 3, refCntWtd = 3 *** marking local variables in block BB07 (weight=1 ) STMT00026 (IL 0x0EA...0x0EB) [000127] -A---+------ * ASG int [000126] D----+-N---- +--* LCL_VAR int V06 loc0 [000125] -----+------ \--* LCL_VAR int V07 loc1 New refCnts for V06: refCnt = 1, refCntWtd = 1 New refCnts for V07: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB08 (weight=1 ) STMT00027 (IL 0x0EC...0x0ED) [000129] -----+------ * RETURN int [000128] -----+------ \--* LCL_VAR int V06 loc0 New refCnts for V06: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB09 (weight=0.29) STMT00013 (IL 0x095...0x0A7) [000073] -ACXG+------ * ASG struct (copy) [000071] D----+-N---- +--* LCL_VAR struct V13 tmp2 [000070] --CXG+------ \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA [000360] -ACXG-----L- this SETUP +--* ASG ref [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 [000066] --CXG+------ | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 [000069] -----+------ arg2 in rsi +--* LCL_VAR ref V01 arg1 [000356] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 New refCnts for V13: refCnt = 1, refCntWtd = 0.58 New refCnts for V26: refCnt = 1, refCntWtd = 0.58 New refCnts for V21: refCnt = 3, refCntWtd = 2.29 New refCnts for V22: refCnt = 3, refCntWtd = 2.29 New refCnts for V08: refCnt = 4, refCntWtd = 3.29 New refCnts for V26: refCnt = 2, refCntWtd = 1.16 New refCnts for V01: refCnt = 1, refCntWtd = 0.29 STMT00014 (IL ???... ???) [000078] -A---+------ * ASG ref [000077] D----+-N---- +--* LCL_VAR ref V10 loc4 [000076] -----+------ \--* LCL_FLD ref V13 tmp2 [+0] Fseq[Type] New refCnts for V10: refCnt = 1, refCntWtd = 0.29 New refCnts for V13: refCnt = 2, refCntWtd = 1.16 STMT00051 (IL 0x0A9... ???) [000245] -A---+------ * ASG bool [000244] D----+-N---- +--* LCL_VAR int V19 tmp8 [000243] -----+------ \--* CNS_INT int 0 New refCnts for V19: refCnt = 1, refCntWtd = 0.29 STMT00046 (IL 0x0A9... ???) [000228] --CXG+------ * JTRUE void [000249] J-CXG+-N---- \--* NE int [000247] --CXG+------ +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind [000080] -----+------ this in rdi | +--* LCL_VAR ref V10 loc4 [000365] -----+------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 [000248] -----+------ \--* CNS_INT int 4 New refCnts for V10: refCnt = 2, refCntWtd = 0.58 *** marking local variables in block BB10 (weight=0.58) STMT00049 (IL 0x0A9... ???) [000239] --CXG+------ * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics [000237] -----+------ arg0 in rdi +--* LCL_VAR ref V10 loc4 [000238] -----+------ arg1 in rsi \--* LCL_VAR byref V05 arg5 New refCnts for V10: refCnt = 3, refCntWtd = 1.16 New refCnts for V05: refCnt = 2, refCntWtd = 1.58 STMT00050 (IL 0x0A9... ???) [000242] -A---+------ * ASG bool [000241] D----+-N---- +--* LCL_VAR int V19 tmp8 [000240] -----+------ \--* CNS_INT int 0 New refCnts for V19: refCnt = 2, refCntWtd = 0.87 STMT00058 (IL ???... ???) [000420] ------------ * JTRUE void [000421] J------N---- \--* NE int [000422] ------------ +--* LCL_VAR int V19 tmp8 [000423] ------------ \--* CNS_INT int 0 New refCnts for V19: refCnt = 3, refCntWtd = 1.45 *** marking local variables in block BB11 (weight=0.58) *** marking local variables in block BB12 (weight=0.01) STMT00028 (IL 0x072...0x07E) [000139] --CXG+------ * JTRUE void [000138] J-CXG+-N---- \--* EQ int [000136] --CXG+------ +--* CAST int <- bool <- int [000135] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint [000130] -----+------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 [000131] -----+------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 [000132] -----+------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 [000133] -----+------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 [000134] -----+------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 [000137] -----+------ \--* CNS_INT int 0 New refCnts for V00: refCnt = 1, refCntWtd = 0.01 New refCnts for V02: refCnt = 5, refCntWtd = 4.01 New refCnts for V03: refCnt = 3, refCntWtd = 2.01 New refCnts for V04: refCnt = 1, refCntWtd = 0.01 New refCnts for V05: refCnt = 3, refCntWtd = 1.59 *** marking local variables in block BB13 (weight=0.01) *** marking local variables in block BB14 (weight=0.29) STMT00048 (IL 0x0A9... ???) [000234] -ACXG+------ * ASG bool [000233] D----+-N---- +--* LCL_VAR int V19 tmp8 [000232] --CXG+------ \--* CAST int <- bool <- int [000230] --CXG+------ \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion [000079] -----+------ arg0 in rdi +--* LCL_VAR ref V03 arg3 [000229] -----+------ arg1 in rsi +--* LCL_VAR ref V10 loc4 [000081] -----+------ arg2 in rdx \--* LCL_VAR byref V05 arg5 New refCnts for V19: refCnt = 4, refCntWtd = 1.74 New refCnts for V03: refCnt = 4, refCntWtd = 2.30 New refCnts for V10: refCnt = 4, refCntWtd = 1.45 New refCnts for V05: refCnt = 4, refCntWtd = 1.88 STMT00016 (IL ???... ???) [000087] -----+------ * JTRUE void [000086] J----+-N---- \--* EQ int [000235] -----+------ +--* LCL_VAR int V19 tmp8 [000085] -----+------ \--* CNS_INT int 0 New refCnts for V19: refCnt = 5, refCntWtd = 2.03 *** marking local variables in block BB15 (weight=0.29) STMT00012 (IL 0x0E1...0x0E8) [000063] --CXG+------ * JTRUE void ( 25, 27) [000062] J-CXG--N---- \--* NE int ( 23, 25) [000060] --CXG------- +--* CAST int <- bool <- int ( 22, 23) [000057] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 ( 1, 1) [000061] ------------ \--* CNS_INT int 0 New refCnts for V21: refCnt = 4, refCntWtd = 2.58 New refCnts for V22: refCnt = 4, refCntWtd = 2.58 New refCnts for V08: refCnt = 5, refCntWtd = 3.58 *** marking local variables in block BB16 (weight=0.15) *** marking local variables in block BB17 (weight=0.03) STMT00031 (IL ???... ???) [000151] --CXG+------ * JTRUE void [000150] J-CXG+-N---- \--* NE int [000148] --CXG+------ +--* CAST int <- bool <- int [000146] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint [000143] -----+------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 [000144] -----+------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 [000145] -----+------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 [000149] -----+------ \--* CNS_INT int 0 New refCnts for V02: refCnt = 6, refCntWtd = 4.04 New refCnts for V03: refCnt = 5, refCntWtd = 2.33 New refCnts for V04: refCnt = 2, refCntWtd = 0.04 *** marking local variables in block BB18 (weight=0.01) STMT00032 (IL 0x068...0x069) [000154] -A---+------ * ASG int [000153] D----+-N---- +--* LCL_VAR int V07 loc1 [000152] -----+------ \--* CNS_INT int 0 New refCnts for V07: refCnt = 3, refCntWtd = 2.01 *** marking local variables in block BB19 (weight=0.02) STMT00017 (IL 0x0B5...0x0B7) [000091] -----+------ * JTRUE void [000090] J----+-N---- \--* EQ int [000088] -----+------ +--* LCL_VAR ref V04 arg4 [000089] -----+------ \--* CNS_INT ref null New refCnts for V04: refCnt = 3, refCntWtd = 0.06 *** marking local variables in block BB20 (weight=0.02) STMT00019 (IL 0x0B9...0x0CA) [000101] -ACXG+------ * ASG ref [000100] D----+-N---- +--* LCL_VAR ref V14 tmp3 [000099] --CXG+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000098] -----+------ arg0 in rdi \--* CNS_INT long 2 New refCnts for V14: refCnt = 1, refCntWtd = 0.04 STMT00020 (IL ???... ???) [000107] -A-XG+------ * ASG ref [000384] ---XG+-N---- +--* COMMA ref [000378] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000104] -----+------ | | +--* CNS_INT int 0 [000377] ---X-+------ | | \--* ARR_LENGTH int [000103] -----+------ | | \--* LCL_VAR ref V14 tmp3 [000106] a---G+-N---- | \--* IND ref [000383] -----+------ | \--* ADD byref [000375] -----+------ | +--* LCL_VAR ref V14 tmp3 [000382] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000105] -----+------ \--* LCL_VAR ref V03 arg3 New refCnts for V14: refCnt = 2, refCntWtd = 0.08 New refCnts for V14: refCnt = 3, refCntWtd = 0.12 New refCnts for V03: refCnt = 6, refCntWtd = 2.35 STMT00021 (IL ???...0x0CF) [000112] -A-XG+------ * ASG ref [000394] ---XG+-N---- +--* COMMA ref [000388] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000109] -----+------ | | +--* CNS_INT int 1 [000387] ---X-+------ | | \--* ARR_LENGTH int [000108] -----+------ | | \--* LCL_VAR ref V14 tmp3 [000111] a---G+-N---- | \--* IND ref [000393] -----+------ | \--* ADD byref [000385] -----+------ | +--* LCL_VAR ref V14 tmp3 [000392] -----+------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] [000110] -----+------ \--* LCL_VAR ref V10 loc4 New refCnts for V14: refCnt = 4, refCntWtd = 0.16 New refCnts for V14: refCnt = 5, refCntWtd = 0.20 New refCnts for V10: refCnt = 5, refCntWtd = 1.47 STMT00052 (IL ???... ???) [000261] -AC--+------ * ASG ref [000260] D----+-N---- +--* LCL_VAR ref V20 tmp9 [000259] --C--+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW New refCnts for V20: refCnt = 1, refCntWtd = 0.04 STMT00053 (IL ???... ???) [000263] --CXG+------ * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000396] -ACXG-----L- arg1 SETUP +--* ASG ref [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 [000255] --CXG+------ | \--* IND ref [000254] --CXG+------ | \--* ADD byref [000252] H-CXG+------ | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000253] -----+------ | \--* CNS_INT int 0x418 Fseq[Instance] [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 [000262] -----+------ this in rdi +--* LCL_VAR ref V20 tmp9 [000102] -----+------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 [000256] -----+------ arg2 in rdx \--* CNS_INT int 0x7D2C New refCnts for V27: refCnt = 1, refCntWtd = 0.04 New refCnts for V27: refCnt = 2, refCntWtd = 0.08 New refCnts for V20: refCnt = 2, refCntWtd = 0.08 New refCnts for V14: refCnt = 6, refCntWtd = 0.24 STMT00023 (IL ???... ???) [000117] IA---+------ * ASG struct (init) [000115] D----+-N---- +--* LCL_VAR struct V15 tmp4 [000116] -----+------ \--* CNS_INT int 0 New refCnts for V15: refCnt = 1, refCntWtd = 0.04 STMT00054 (IL ???... ???) [000269] IA---+------ * ASG struct (init) [000267] D----+-N---- +--* LCL_VAR struct V15 tmp4 [000268] -----+------ \--* CNS_INT int 0 New refCnts for V15: refCnt = 2, refCntWtd = 0.08 STMT00055 (IL ???... ???) [000273] -A---+------ * ASG ref [000272] U----+-N---- +--* LCL_FLD ref V15 tmp4 [+0] Fseq[TypeParameter] [000096] -----+------ \--* LCL_VAR ref V02 arg2 New refCnts for V15: refCnt = 3, refCntWtd = 0.12 New refCnts for V02: refCnt = 7, refCntWtd = 4.06 STMT00056 (IL ???... ???) [000277] -A---+------ * ASG ref [000276] U----+-N---- +--* LCL_FLD ref V15 tmp4 [+8] Fseq[DiagnosticInfo] [000264] -----+------ \--* LCL_VAR ref V20 tmp9 New refCnts for V15: refCnt = 4, refCntWtd = 0.16 New refCnts for V20: refCnt = 3, refCntWtd = 0.12 STMT00025 (IL 0x0DA... ???) [000122] --CXG+------ * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct ( 3, 3) [000123] ------------ | \--* ADDR byref ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 [000095] -----+------ this in rdi +--* LCL_VAR ref V04 arg4 [000401] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 New refCnts for V15: refCnt = 5, refCntWtd = 0.20 New refCnts for V04: refCnt = 4, refCntWtd = 0.08 *** marking local variables in block BB21 (weight=0.02) STMT00018 (IL 0x0DF...0x0E0) [000094] -A---+------ * ASG int [000093] D----+-N---- +--* LCL_VAR int V07 loc1 [000092] -----+------ \--* CNS_INT int 0 New refCnts for V07: refCnt = 4, refCntWtd = 2.03 *** marking local variables in block BB22 (weight=0.01) STMT00033 (IL 0x048...0x051) [000162] --CXG+------ * JTRUE void [000161] J-CXG+-N---- \--* NE int [000159] --CXG+------ +--* CAST int <- bool <- int [000158] --CXG+------ | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint [000155] -----+------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 [000156] -----+------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 [000157] -----+------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 [000160] -----+------ \--* CNS_INT int 0 New refCnts for V02: refCnt = 8, refCntWtd = 4.07 New refCnts for V03: refCnt = 7, refCntWtd = 2.36 New refCnts for V04: refCnt = 5, refCntWtd = 0.09 *** marking local variables in block BB23 (weight=0 ) STMT00034 (IL 0x053...0x054) [000165] -A---+------ * ASG int [000164] D----+-N---- +--* LCL_VAR int V07 loc1 [000163] -----+------ \--* CNS_INT int 0 New refCnts for V07: refCnt = 5, refCntWtd = 2.03 *** marking local variables in block BB24 (weight=0 ) STMT00042 (IL 0x008...0x009) [000197] -A---+------ * ASG int [000196] D----+-N---- +--* LCL_VAR int V06 loc0 [000195] -----+------ \--* CNS_INT int 1 New refCnts for V06: refCnt = 3, refCntWtd = 2 *** marking local variables in block BB25 (weight=0 ) STMT00035 (IL 0x019...0x01B) [000169] -----+------ * JTRUE void [000168] J----+-N---- \--* EQ int [000166] -----+------ +--* LCL_VAR ref V04 arg4 [000167] -----+------ \--* CNS_INT ref null New refCnts for V04: refCnt = 6, refCntWtd = 0.09 *** marking local variables in block BB26 (weight=0 ) STMT00037 (IL 0x01D...0x02E) [000179] -ACXG+------ * ASG ref [000178] D----+-N---- +--* LCL_VAR ref V16 tmp5 [000177] --CXG+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 [000176] -----+------ arg0 in rdi \--* CNS_INT long 1 New refCnts for V16: refCnt = 1, refCntWtd = 0 STMT00038 (IL ???... ???) [000185] -A-XG+------ * ASG ref [000298] ---XG+-N---- +--* COMMA ref [000292] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000182] -----+------ | | +--* CNS_INT int 0 [000291] ---X-+------ | | \--* ARR_LENGTH int [000181] -----+------ | | \--* LCL_VAR ref V16 tmp5 [000184] a---G+-N---- | \--* IND ref [000297] -----+------ | \--* ADD byref [000289] -----+------ | +--* LCL_VAR ref V16 tmp5 [000296] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000183] -----+------ \--* LCL_VAR ref V03 arg3 New refCnts for V16: refCnt = 2, refCntWtd = 0 New refCnts for V16: refCnt = 3, refCntWtd = 0 New refCnts for V03: refCnt = 8, refCntWtd = 2.36 STMT00043 (IL ???... ???) [000216] -AC--+------ * ASG ref [000215] D----+-N---- +--* LCL_VAR ref V18 tmp7 [000214] --C--+------ \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW New refCnts for V18: refCnt = 1, refCntWtd = 0 STMT00044 (IL ???... ???) [000218] --CXG+------ * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor [000300] -ACXG-----L- arg1 SETUP +--* ASG ref [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 [000210] --CXG+------ | \--* IND ref [000209] --CXG+------ | \--* ADD byref [000207] H-CXG+------ | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE [000208] -----+------ | \--* CNS_INT int 0x418 Fseq[Instance] [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 [000217] -----+------ this in rdi +--* LCL_VAR ref V18 tmp7 [000180] -----+------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 [000211] -----+------ arg2 in rdx \--* CNS_INT int 0x7AA4 New refCnts for V24: refCnt = 1, refCntWtd = 0 New refCnts for V24: refCnt = 2, refCntWtd = 0 New refCnts for V18: refCnt = 2, refCntWtd = 0 New refCnts for V16: refCnt = 4, refCntWtd = 0 STMT00040 (IL ???... ???) [000190] --CXG+------ * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor [000189] -----+------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 [000174] -----+------ arg1 in rsi +--* LCL_VAR ref V02 arg2 [000219] -----+------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 New refCnts for V17: refCnt = 1, refCntWtd = 0 New refCnts for V02: refCnt = 9, refCntWtd = 4.07 New refCnts for V18: refCnt = 3, refCntWtd = 0 STMT00041 (IL 0x039... ???) [000192] --CXG+------ * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct ( 3, 3) [000193] ------------ | \--* ADDR byref ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 [000173] -----+------ this in rdi +--* LCL_VAR ref V04 arg4 [000308] -----+------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 New refCnts for V17: refCnt = 2, refCntWtd = 0 New refCnts for V04: refCnt = 7, refCntWtd = 0.09 *** marking local variables in block BB27 (weight=0 ) STMT00036 (IL 0x03E...0x03F) [000172] -A---+------ * ASG int [000171] D----+-N---- +--* LCL_VAR int V07 loc1 [000170] -----+------ \--* CNS_INT int 0 New refCnts for V07: refCnt = 6, refCntWtd = 2.03 *** marking local variables in block BB28 (weight=0 ) STMT00029 (IL 0x080...0x081) [000142] -A---+------ * ASG int [000141] D----+-N---- +--* LCL_VAR int V07 loc1 [000140] -----+------ \--* CNS_INT int 0 New refCnts for V07: refCnt = 7, refCntWtd = 2.03 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 2, refCntWtd = 1.01 New refCnts for V00: refCnt = 3, refCntWtd = 2.01 New refCnts for V01: refCnt = 2, refCntWtd = 1.29 New refCnts for V01: refCnt = 3, refCntWtd = 2.29 New refCnts for V02: refCnt = 10, refCntWtd = 5.07 New refCnts for V02: refCnt = 11, refCntWtd = 6.07 New refCnts for V03: refCnt = 9, refCntWtd = 3.36 New refCnts for V03: refCnt = 10, refCntWtd = 4.36 New refCnts for V04: refCnt = 8, refCntWtd = 1.09 New refCnts for V04: refCnt = 9, refCntWtd = 2.09 New refCnts for V05: refCnt = 5, refCntWtd = 2.88 New refCnts for V05: refCnt = 6, refCntWtd = 3.88 *************** In optAddCopies() *************** Finishing PHASE Mark local vars *************** Starting PHASE Optimize bools *************** In optOptimizeBools() *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize bools *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order *************** Starting PHASE Set block order *************** In fgSetBlockOrder() fgMarkLoopHead: Checking loop head block BB09: this block will execute a call fgMarkLoopHead: Checking loop head block BB15: this block will execute a call The biggest BB has 17 tree nodes *************** Finishing PHASE Set block order Trees before Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB15 ( cond ) i gcsafe bwd BB11 [0034] 1 BB10 0.58 [???..???)-> BB19 (always) internal gcsafe BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 3 BB10,BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB11 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} ***** BB01 STMT00001 (IL ???... ???) N008 ( 28, 25) [000006] --CXG------- * JTRUE void N007 ( 26, 23) [000200] J-CXG--N---- \--* EQ int N005 ( 24, 21) [000198] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind N003 ( 1, 1) [000000] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 N004 ( 3, 10) [000279] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N006 ( 1, 1) [000199] ------------ \--* CNS_INT int 4 ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} ***** BB02 STMT00002 (IL 0x00F...0x010) N003 ( 5, 4) [000009] -A------R--- * ASG int N002 ( 3, 2) [000008] D------N---- +--* LCL_VAR int V07 loc1 N001 ( 1, 1) [000007] ------------ \--* CNS_INT int 1 ***** BB02 STMT00004 (IL ???... ???) N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} ***** BB03 STMT00005 (IL 0x040...0x046) N009 ( 29, 27) [000022] --CXG------- * JTRUE void N008 ( 27, 25) [000021] J-CXG--N---- \--* NE int N006 ( 25, 23) [000019] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000018] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint N003 ( 1, 1) [000017] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 N004 ( 3, 10) [000312] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000020] ------------ \--* CNS_INT int 0 ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} ***** BB04 STMT00006 (IL 0x055...0x05B) N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} ***** BB05 STMT00007 (IL 0x06A...0x070) N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} ***** BB06 STMT00009 (IL ???... ???) N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 ***** BB06 STMT00010 (IL 0x08B...0x092) N009 ( 26, 26) [000050] -ACXG---R--- * ASG struct (copy) N008 ( 3, 2) [000048] D------N---- +--* LCL_VAR struct(AX) V12 tmp1 N007 ( 22, 23) [000045] --CXG------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA N004 ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long N003 ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref N005 ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 ***** BB06 STMT00011 (IL ???... ???) N016 ( 18, 15) [000355] -A-XG------- * COMMA void N009 ( 10, 8) [000348] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref N001 ( 3, 2) [000341] -------N---- | | \--* LCL_VAR struct(AX) V12 tmp1 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 Zero Fseq[_array] N015 ( 8, 7) [000354] -A-XG---R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] ---X-------- \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] ***** BB06 STMT00057 (IL 0x0E1... ???) N011 ( 27, 29) [000419] --CXG------- * JTRUE void N010 ( 25, 27) [000409] J-CXG--N---- \--* NE int N008 ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int N007 ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext N004 ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref N005 ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N009 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} ***** BB07 STMT00026 (IL 0x0EA...0x0EB) N003 ( 7, 5) [000127] -A------R--- * ASG int N002 ( 3, 2) [000126] D------N---- +--* LCL_VAR int V06 loc0 N001 ( 3, 2) [000125] ------------ \--* LCL_VAR int V07 loc1 ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} ***** BB08 STMT00027 (IL 0x0EC...0x0ED) N002 ( 4, 3) [000129] ------------ * RETURN int N001 ( 3, 2) [000128] ------------ \--* LCL_VAR int V06 loc0 ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} ***** BB09 STMT00013 (IL 0x095...0x0A7) N017 ( 59, 54) [000073] -ACXG---R--- * ASG struct (copy) N016 ( 3, 2) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 N015 ( 55, 51) [000070] --CXG------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA N009 ( 26, 26) [000360] -ACXG---R-L- this SETUP +--* ASG ref N008 ( 3, 2) [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 N007 ( 22, 23) [000066] --CXG------- | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current N004 ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref N005 ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N012 ( 3, 2) [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 N013 ( 3, 2) [000069] ------------ arg2 in rsi +--* LCL_VAR ref V01 arg1 N014 ( 3, 10) [000356] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ***** BB09 STMT00014 (IL ???... ???) N003 ( 7, 7) [000078] -A------R--- * ASG ref N002 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V10 loc4 N001 ( 3, 4) [000076] ------------ \--* LCL_FLD ref V13 tmp2 [+0] Fseq[Type] ***** BB09 STMT00051 (IL 0x0A9... ???) N003 ( 5, 4) [000245] -A------R--- * ASG bool N002 ( 3, 2) [000244] D------N---- +--* LCL_VAR int V19 tmp8 N001 ( 1, 1) [000243] ------------ \--* CNS_INT int 0 ***** BB09 STMT00046 (IL 0x0A9... ???) N008 ( 30, 26) [000228] --CXG------- * JTRUE void N007 ( 28, 24) [000249] J-CXG--N---- \--* NE int N005 ( 26, 22) [000247] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind N003 ( 3, 2) [000080] ------------ this in rdi | +--* LCL_VAR ref V10 loc4 N004 ( 3, 10) [000365] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N006 ( 1, 1) [000248] ------------ \--* CNS_INT int 4 ------------ BB10 [0A9..0AA) -> BB15 (cond), preds={BB09} succs={BB11,BB15} ***** BB10 STMT00049 (IL 0x0A9... ???) N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics N003 ( 3, 2) [000237] ------------ arg0 in rdi +--* LCL_VAR ref V10 loc4 N004 ( 1, 1) [000238] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 ***** BB10 STMT00050 (IL 0x0A9... ???) N003 ( 5, 4) [000242] -A------R--- * ASG bool N002 ( 3, 2) [000241] D------N---- +--* LCL_VAR int V19 tmp8 N001 ( 1, 1) [000240] ------------ \--* CNS_INT int 0 ***** BB10 STMT00058 (IL ???... ???) N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] J------N---- \--* NE int N001 ( 3, 2) [000422] ------------ +--* LCL_VAR int V19 tmp8 N002 ( 1, 1) [000423] ------------ \--* CNS_INT int 0 ------------ BB11 [???..???) -> BB19 (always), preds={BB10} succs={BB19} ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} ***** BB12 STMT00028 (IL 0x072...0x07E) N015 ( 28, 23) [000139] --CXG------- * JTRUE void N014 ( 26, 21) [000138] J-CXG--N---- \--* EQ int N012 ( 24, 19) [000136] --CXG------- +--* CAST int <- bool <- int N011 ( 23, 17) [000135] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint N006 ( 3, 2) [000130] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 N007 ( 1, 1) [000131] ------------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 N008 ( 1, 1) [000132] ------------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 N009 ( 3, 2) [000133] ------------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 N010 ( 1, 1) [000134] ------------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 N013 ( 1, 1) [000137] ------------ \--* CNS_INT int 0 ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} ***** BB14 STMT00048 (IL 0x0A9... ???) N010 ( 24, 17) [000234] -ACXG---R--- * ASG bool N009 ( 3, 2) [000233] D------N---- +--* LCL_VAR int V19 tmp8 N008 ( 20, 14) [000232] --CXG------- \--* CAST int <- bool <- int N007 ( 19, 12) [000230] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion N004 ( 1, 1) [000079] ------------ arg0 in rdi +--* LCL_VAR ref V03 arg3 N005 ( 3, 2) [000229] ------------ arg1 in rsi +--* LCL_VAR ref V10 loc4 N006 ( 1, 1) [000081] ------------ arg2 in rdx \--* LCL_VAR byref V05 arg5 ***** BB14 STMT00016 (IL ???... ???) N004 ( 7, 6) [000087] ------------ * JTRUE void N003 ( 5, 4) [000086] J------N---- \--* EQ int N001 ( 3, 2) [000235] ------------ +--* LCL_VAR int V19 tmp8 N002 ( 1, 1) [000085] ------------ \--* CNS_INT int 0 ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB10,BB14,BB21} succs={BB16,BB09} ***** BB15 STMT00012 (IL 0x0E1...0x0E8) N011 ( 27, 29) [000063] --CXG------- * JTRUE void N010 ( 25, 27) [000062] J-CXG--N---- \--* NE int N008 ( 23, 25) [000060] --CXG------- +--* CAST int <- bool <- int N007 ( 22, 23) [000057] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext N004 ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref N005 ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N009 ( 1, 1) [000061] ------------ \--* CNS_INT int 0 ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} ***** BB17 STMT00031 (IL ???... ???) N011 ( 24, 18) [000151] --CXG------- * JTRUE void N010 ( 22, 16) [000150] J-CXG--N---- \--* NE int N008 ( 20, 14) [000148] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000146] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint N004 ( 1, 1) [000143] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 N005 ( 1, 1) [000144] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 N006 ( 3, 2) [000145] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 N009 ( 1, 1) [000149] ------------ \--* CNS_INT int 0 ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} ***** BB18 STMT00032 (IL 0x068...0x069) N003 ( 5, 4) [000154] -A------R--- * ASG int N002 ( 3, 2) [000153] D------N---- +--* LCL_VAR int V07 loc1 N001 ( 1, 1) [000152] ------------ \--* CNS_INT int 0 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB11} succs={BB20,BB21} ***** BB19 STMT00017 (IL 0x0B5...0x0B7) N004 ( 7, 6) [000091] ------------ * JTRUE void N003 ( 5, 4) [000090] J------N---- \--* EQ int N001 ( 3, 2) [000088] ------------ +--* LCL_VAR ref V04 arg4 N002 ( 1, 1) [000089] ------------ \--* CNS_INT ref null ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} ***** BB20 STMT00019 (IL 0x0B9...0x0CA) N005 ( 19, 10) [000101] -ACXG---R--- * ASG ref N004 ( 3, 2) [000100] D------N---- +--* LCL_VAR ref V14 tmp3 N003 ( 15, 7) [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 N002 ( 1, 1) [000098] ------------ arg0 in rdi \--* CNS_INT long 2 ***** BB20 STMT00020 (IL ???... ???) N011 ( 18, 19) [000107] -A-XG------- * ASG ref N009 ( 16, 17) [000384] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000378] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 N003 ( 5, 4) [000377] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000103] ------------ | | \--* LCL_VAR ref V14 tmp3 N008 ( 6, 5) [000106] a---G--N---- | \--* IND ref N007 ( 4, 3) [000383] -------N---- | \--* ADD byref N005 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 N006 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N010 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 ***** BB20 STMT00021 (IL ???...0x0CF) N011 ( 20, 20) [000112] -A-XG------- * ASG ref N009 ( 16, 17) [000394] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 N003 ( 5, 4) [000387] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000108] ------------ | | \--* LCL_VAR ref V14 tmp3 N008 ( 6, 5) [000111] a---G--N---- | \--* IND ref N007 ( 4, 3) [000393] -------N---- | \--* ADD byref N005 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 N006 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] N010 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 ***** BB20 STMT00052 (IL ???... ???) N003 ( 18, 8) [000261] -AC-----R--- * ASG ref N002 ( 3, 2) [000260] D------N---- +--* LCL_VAR ref V20 tmp9 N001 ( 14, 5) [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW ***** BB20 STMT00053 (IL ???... ???) N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor N007 ( 21, 14) [000396] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 N005 ( 17, 11) [000255] --CXG------- | \--* IND ref N004 ( 15, 9) [000254] --CXG--N---- | \--* ADD byref N002 ( 14, 5) [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE N003 ( 1, 4) [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] N010 ( 3, 2) [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 N011 ( 3, 2) [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 N012 ( 3, 2) [000102] ------------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 N013 ( 1, 4) [000256] ------------ arg2 in rdx \--* CNS_INT int 0x7D2C ***** BB20 STMT00023 (IL ???... ???) N003 ( 5, 4) [000117] IA------R--- * ASG struct (init) N002 ( 3, 2) [000115] D------N---- +--* LCL_VAR struct V15 tmp4 N001 ( 1, 1) [000116] ------------ \--* CNS_INT int 0 ***** BB20 STMT00054 (IL ???... ???) N003 ( 5, 4) [000269] IA------R--- * ASG struct (init) N002 ( 3, 2) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 N001 ( 1, 1) [000268] ------------ \--* CNS_INT int 0 ***** BB20 STMT00055 (IL ???... ???) N003 ( 5, 6) [000273] -A------R--- * ASG ref N002 ( 3, 4) [000272] U------N---- +--* LCL_FLD ref V15 tmp4 [+0] Fseq[TypeParameter] N001 ( 1, 1) [000096] ------------ \--* LCL_VAR ref V02 arg2 ***** BB20 STMT00056 (IL ???... ???) N003 ( 7, 7) [000277] -A------R--- * ASG ref N002 ( 3, 4) [000276] U------N---- +--* LCL_FLD ref V15 tmp4 [+8] Fseq[DiagnosticInfo] N001 ( 3, 2) [000264] ------------ \--* LCL_VAR ref V20 tmp9 ***** BB20 STMT00025 (IL 0x0DA... ???) N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000123] ------------ | \--* ADDR byref N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} ***** BB21 STMT00018 (IL 0x0DF...0x0E0) N003 ( 5, 4) [000094] -A------R--- * ASG int N002 ( 3, 2) [000093] D------N---- +--* LCL_VAR int V07 loc1 N001 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} ***** BB22 STMT00033 (IL 0x048...0x051) N011 ( 24, 18) [000162] --CXG------- * JTRUE void N010 ( 22, 16) [000161] J-CXG--N---- \--* NE int N008 ( 20, 14) [000159] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000158] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint N004 ( 1, 1) [000155] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 N005 ( 1, 1) [000156] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 N006 ( 3, 2) [000157] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 N009 ( 1, 1) [000160] ------------ \--* CNS_INT int 0 ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} ***** BB23 STMT00034 (IL 0x053...0x054) N003 ( 5, 4) [000165] -A------R--- * ASG int N002 ( 3, 2) [000164] D------N---- +--* LCL_VAR int V07 loc1 N001 ( 1, 1) [000163] ------------ \--* CNS_INT int 0 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} ***** BB24 STMT00042 (IL 0x008...0x009) N003 ( 5, 4) [000197] -A------R--- * ASG int N002 ( 3, 2) [000196] D------N---- +--* LCL_VAR int V06 loc0 N001 ( 1, 1) [000195] ------------ \--* CNS_INT int 1 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} ***** BB25 STMT00035 (IL 0x019...0x01B) N004 ( 7, 6) [000169] ------------ * JTRUE void N003 ( 5, 4) [000168] J------N---- \--* EQ int N001 ( 3, 2) [000166] ------------ +--* LCL_VAR ref V04 arg4 N002 ( 1, 1) [000167] ------------ \--* CNS_INT ref null ------------ BB26 [01D..03E), preds={BB25} succs={BB27} ***** BB26 STMT00037 (IL 0x01D...0x02E) N005 ( 19, 10) [000179] -ACXG---R--- * ASG ref N004 ( 3, 2) [000178] D------N---- +--* LCL_VAR ref V16 tmp5 N003 ( 15, 7) [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 N002 ( 1, 1) [000176] ------------ arg0 in rdi \--* CNS_INT long 1 ***** BB26 STMT00038 (IL ???... ???) N011 ( 18, 19) [000185] -A-XG------- * ASG ref N009 ( 16, 17) [000298] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000292] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000182] ------------ | | +--* CNS_INT int 0 N003 ( 5, 4) [000291] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000181] ------------ | | \--* LCL_VAR ref V16 tmp5 N008 ( 6, 5) [000184] a---G--N---- | \--* IND ref N007 ( 4, 3) [000297] -------N---- | \--* ADD byref N005 ( 3, 2) [000289] ------------ | +--* LCL_VAR ref V16 tmp5 N006 ( 1, 1) [000296] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N010 ( 1, 1) [000183] ------------ \--* LCL_VAR ref V03 arg3 ***** BB26 STMT00043 (IL ???... ???) N003 ( 18, 8) [000216] -AC-----R--- * ASG ref N002 ( 3, 2) [000215] D------N---- +--* LCL_VAR ref V18 tmp7 N001 ( 14, 5) [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW ***** BB26 STMT00044 (IL ???... ???) N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor N007 ( 21, 14) [000300] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 N005 ( 17, 11) [000210] --CXG------- | \--* IND ref N004 ( 15, 9) [000209] --CXG--N---- | \--* ADD byref N002 ( 14, 5) [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE N003 ( 1, 4) [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] N010 ( 3, 2) [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 N011 ( 3, 2) [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 N012 ( 3, 2) [000180] ------------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 N013 ( 1, 4) [000211] ------------ arg2 in rdx \--* CNS_INT int 0x7AA4 ***** BB26 STMT00040 (IL ???... ???) N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor N004 ( 3, 3) [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 N005 ( 1, 1) [000174] ------------ arg1 in rsi +--* LCL_VAR ref V02 arg2 N006 ( 3, 2) [000219] ------------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 ***** BB26 STMT00041 (IL 0x039... ???) N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} ***** BB27 STMT00036 (IL 0x03E...0x03F) N003 ( 5, 4) [000172] -A------R--- * ASG int N002 ( 3, 2) [000171] D------N---- +--* LCL_VAR int V07 loc1 N001 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} ***** BB28 STMT00029 (IL 0x080...0x081) N003 ( 5, 4) [000142] -A------R--- * ASG int N002 ( 3, 2) [000141] D------N---- +--* LCL_VAR int V07 loc1 N001 ( 1, 1) [000140] ------------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Build SSA representation *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 29. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB15 ( cond ) i gcsafe bwd BB11 [0034] 1 BB10 0.58 [???..???)-> BB19 (always) internal gcsafe BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 3 BB10,BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB11 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB24 BB08 BB02 BB02 : BB25 BB03 BB03 : BB22 BB04 BB04 : BB17 BB05 BB05 : BB12 BB06 BB06 : BB09 BB07 BB09 : BB19 BB15 BB14 BB10 BB10 : BB11 BB12 : BB28 BB13 BB15 : BB16 BB17 : BB18 BB19 : BB21 BB20 BB22 : BB23 BB25 : BB27 BB26 *************** In fgLocalVarLiveness() In fgLocalVarLivenessInit Local V13 should not be enregistered because: it is a struct Local V15 should not be enregistered because: it is a struct Tracked variable (20 out of 28) table: V02 arg2 [ ref]: refCnt = 11, refCntWtd = 6.07 V03 arg3 [ ref]: refCnt = 10, refCntWtd = 4.36 V25 tmp14 [ byref]: refCnt = 3, refCntWtd = 6 V05 arg5 [ byref]: refCnt = 6, refCntWtd = 3.88 V01 arg1 [ ref]: refCnt = 3, refCntWtd = 2.29 V04 arg4 [ ref]: refCnt = 9, refCntWtd = 2.09 V00 arg0 [ ref]: refCnt = 3, refCntWtd = 2.01 V07 loc1 [ bool]: refCnt = 7, refCntWtd = 2.03 V19 tmp8 [ bool]: refCnt = 5, refCntWtd = 2.03 V06 loc0 [ bool]: refCnt = 3, refCntWtd = 2 V10 loc4 [ ref]: refCnt = 5, refCntWtd = 1.47 V26 tmp15 [ ref]: refCnt = 2, refCntWtd = 1.16 V13 tmp2 [struct]: refCnt = 2, refCntWtd = 1.16 V14 tmp3 [ ref]: refCnt = 6, refCntWtd = 0.24 V15 tmp4 [struct]: refCnt = 5, refCntWtd = 0.20 V20 tmp9 [ ref]: refCnt = 3, refCntWtd = 0.12 V27 tmp16 [ ref]: refCnt = 2, refCntWtd = 0.08 V16 tmp5 [ ref]: refCnt = 4, refCntWtd = 0 V18 tmp7 [ ref]: refCnt = 3, refCntWtd = 0 V24 tmp13 [ ref]: refCnt = 2, refCntWtd = 0 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V03} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB02 USE(1)={V03 } + ByrefExposed + GcHeap DEF(1)={ V07} + ByrefExposed* + GcHeap* BB03 USE(1)={V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB04 USE(1)={V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB05 USE(1)={V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB06 USE(2)={V02 V05} + ByrefExposed + GcHeap DEF(1)={ V25 } + ByrefExposed* + GcHeap* BB07 USE(1)={V07 } DEF(1)={ V06} BB08 USE(1)={V06} DEF(0)={ } BB09 USE(1)={V01 } + ByrefExposed + GcHeap DEF(4)={ V19 V10 V26 V13} + ByrefExposed* + GcHeap* BB10 USE(2)={V05 V10} + ByrefExposed + GcHeap DEF(1)={ V19 } + ByrefExposed* + GcHeap* BB11 USE(0)={} DEF(0)={} BB12 USE(5)={V02 V03 V05 V04 V00} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB13 USE(0)={} DEF(0)={} BB14 USE(3)={V03 V05 V10} + ByrefExposed + GcHeap DEF(1)={ V19 } + ByrefExposed* + GcHeap* BB15 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB16 USE(0)={} DEF(0)={} BB17 USE(3)={V02 V03 V04} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB18 USE(0)={ } DEF(1)={V07} BB19 USE(1)={V04} DEF(0)={ } BB20 USE(4)={V02 V03 V04 V10 } + ByrefExposed + GcHeap DEF(4)={ V14 V15 V20 V27} + ByrefExposed* + GcHeap* BB21 USE(0)={ } DEF(1)={V07} BB22 USE(3)={V02 V03 V04} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB23 USE(0)={ } DEF(1)={V07} BB24 USE(0)={ } DEF(1)={V06} BB25 USE(1)={V04} DEF(0)={ } BB26 USE(3)={V02 V03 V04 } + ByrefExposed + GcHeap DEF(3)={ V16 V18 V24} + ByrefExposed* + GcHeap* BB27 USE(0)={ } DEF(1)={V07} BB28 USE(0)={ } DEF(1)={V07} ** Memory liveness computed, GcHeap states and ByrefExposed states diverge *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap BB02 IN (6)={V02 V03 V05 V01 V04 V00 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB03 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB04 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB05 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB06 IN (6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap BB07 IN (1)={V07 } OUT(1)={ V06} BB08 IN (1)={V06} OUT(0)={ } BB09 IN (6)={V02 V03 V05 V01 V04 V07 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V07 V10} + ByrefExposed + GcHeap BB10 IN (7)={V02 V03 V05 V01 V04 V07 V10} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V07 V10} + ByrefExposed + GcHeap BB11 IN (6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap BB12 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap BB13 IN (6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap BB14 IN (7)={V02 V03 V05 V01 V04 V07 V10} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V07 V10} + ByrefExposed + GcHeap BB15 IN (6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap BB16 IN (1)={V07} OUT(1)={V07} BB17 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB18 IN (6)={V02 V03 V05 V01 V04 V00 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB19 IN (6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap BB20 IN (6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap OUT(5)={V02 V03 V05 V01 V04 } + ByrefExposed + GcHeap BB21 IN (5)={V02 V03 V05 V01 V04 } + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap BB22 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB23 IN (6)={V02 V03 V05 V01 V04 V00 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB24 IN (0)={ } OUT(1)={V06} BB25 IN (6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap BB26 IN (6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap BB27 IN (6)={V02 V03 V05 V01 V04 V00 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB28 IN (5)={V02 V03 V05 V01 V04 } + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap top level assign removing stmt with no side effects Removing statement STMT00051 (IL 0x0A9... ???) N003 ( 5, 4) [000245] -A------R--- * ASG bool N002 ( 3, 2) [000244] D------N---- +--* LCL_VAR int V19 tmp8 N001 ( 1, 1) [000243] ------------ \--* CNS_INT int 0 in BB09 as useless: top level assign removing stmt with no side effects Removing statement STMT00023 (IL ???... ???) N003 ( 5, 4) [000117] IA------R--- * ASG struct (init) N002 ( 3, 2) [000115] D------N---- +--* LCL_VAR struct V15 tmp4 N001 ( 1, 1) [000116] ------------ \--* CNS_INT int 0 in BB20 as useless: *************** In SsaBuilder::InsertPhiFunctions() Inserting phi functions: Added PHI definition for V06 at start of BB08. Inserting phi definition for ByrefExposed at start of BB09. Inserting phi definition for GcHeap at start of BB09. Added PHI definition for V07 at start of BB15. Added PHI definition for V07 at start of BB07. Added PHI definition for V07 at start of BB09. Inserting phi definition for ByrefExposed at start of BB21. Inserting phi definition for GcHeap at start of BB21. Inserting phi definition for ByrefExposed at start of BB15. Inserting phi definition for GcHeap at start of BB15. Inserting phi definition for ByrefExposed at start of BB19. Inserting phi definition for GcHeap at start of BB19. Added PHI definition for V07 at start of BB06. Inserting phi definition for ByrefExposed at start of BB06. Inserting phi definition for GcHeap at start of BB06. Added PHI definition for V07 at start of BB05. Inserting phi definition for ByrefExposed at start of BB05. Inserting phi definition for GcHeap at start of BB05. Added PHI definition for V07 at start of BB04. Inserting phi definition for ByrefExposed at start of BB04. Inserting phi definition for GcHeap at start of BB04. Added PHI definition for V07 at start of BB03. Inserting phi definition for ByrefExposed at start of BB27. Inserting phi definition for GcHeap at start of BB27. Inserting phi definition for ByrefExposed at start of BB03. Inserting phi definition for GcHeap at start of BB03. *************** In SsaBuilder::RenameVariables() After fgSsaBuild: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB15 ( cond ) i gcsafe bwd BB11 [0034] 1 BB10 0.58 [???..???)-> BB19 (always) internal gcsafe BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 3 BB10,BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB11 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} ***** BB01 STMT00001 (IL ???... ???) N008 ( 28, 25) [000006] --CXG------- * JTRUE void N007 ( 26, 23) [000200] J-CXG--N---- \--* EQ int N005 ( 24, 21) [000198] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind N003 ( 1, 1) [000000] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 N004 ( 3, 10) [000279] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N006 ( 1, 1) [000199] ------------ \--* CNS_INT int 4 ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} ***** BB02 STMT00002 (IL 0x00F...0x010) N003 ( 5, 4) [000009] -A------R--- * ASG int N002 ( 3, 2) [000008] D------N---- +--* LCL_VAR int V07 loc1 d:2 N001 ( 1, 1) [000007] ------------ \--* CNS_INT int 1 ***** BB02 STMT00004 (IL ???... ???) N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} ***** BB03 STMT00066 (IL ???... ???) N005 ( 0, 0) [000447] -A------R--- * ASG bool N004 ( 0, 0) [000445] D------N---- +--* LCL_VAR bool V07 loc1 d:4 N003 ( 0, 0) [000446] ------------ \--* PHI bool N001 ( 0, 0) [000450] ------------ pred BB27 +--* PHI_ARG bool V07 loc1 u:3 N002 ( 0, 0) [000449] ------------ pred BB02 \--* PHI_ARG bool V07 loc1 u:2 ***** BB03 STMT00005 (IL 0x040...0x046) N009 ( 29, 27) [000022] --CXG------- * JTRUE void N008 ( 27, 25) [000021] J-CXG--N---- \--* NE int N006 ( 25, 23) [000019] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000018] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint N003 ( 1, 1) [000017] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 N004 ( 3, 10) [000312] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000020] ------------ \--* CNS_INT int 0 ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} ***** BB04 STMT00065 (IL ???... ???) N005 ( 0, 0) [000444] -A------R--- * ASG bool N004 ( 0, 0) [000442] D------N---- +--* LCL_VAR bool V07 loc1 d:6 N003 ( 0, 0) [000443] ------------ \--* PHI bool N001 ( 0, 0) [000452] ------------ pred BB23 +--* PHI_ARG bool V07 loc1 u:5 N002 ( 0, 0) [000451] ------------ pred BB03 \--* PHI_ARG bool V07 loc1 u:4 ***** BB04 STMT00006 (IL 0x055...0x05B) N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} ***** BB05 STMT00064 (IL ???... ???) N005 ( 0, 0) [000441] -A------R--- * ASG bool N004 ( 0, 0) [000439] D------N---- +--* LCL_VAR bool V07 loc1 d:8 N003 ( 0, 0) [000440] ------------ \--* PHI bool N001 ( 0, 0) [000454] ------------ pred BB18 +--* PHI_ARG bool V07 loc1 u:7 N002 ( 0, 0) [000453] ------------ pred BB04 \--* PHI_ARG bool V07 loc1 u:6 ***** BB05 STMT00007 (IL 0x06A...0x070) N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} ***** BB06 STMT00063 (IL ???... ???) N005 ( 0, 0) [000438] -A------R--- * ASG bool N004 ( 0, 0) [000436] D------N---- +--* LCL_VAR bool V07 loc1 d:10 N003 ( 0, 0) [000437] ------------ \--* PHI bool N001 ( 0, 0) [000456] ------------ pred BB28 +--* PHI_ARG bool V07 loc1 u:9 N002 ( 0, 0) [000455] ------------ pred BB05 \--* PHI_ARG bool V07 loc1 u:8 ***** BB06 STMT00009 (IL ???... ???) N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 ***** BB06 STMT00010 (IL 0x08B...0x092) N009 ( 26, 26) [000050] -ACXG---R--- * ASG struct (copy) N008 ( 3, 2) [000048] D------N---- +--* LCL_VAR struct(AX) V12 tmp1 N007 ( 22, 23) [000045] --CXG------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA N004 ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long N003 ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref N005 ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 ***** BB06 STMT00011 (IL ???... ???) N016 ( 18, 15) [000355] -A-XG------- * COMMA void N009 ( 10, 8) [000348] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref N001 ( 3, 2) [000341] -------N---- | | \--* LCL_VAR struct(AX) V12 tmp1 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] N015 ( 8, 7) [000354] -A-XG---R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] ---X-------- \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] ***** BB06 STMT00057 (IL 0x0E1... ???) N011 ( 27, 29) [000419] --CXG------- * JTRUE void N010 ( 25, 27) [000409] J-CXG--N---- \--* NE int N008 ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int N007 ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext N004 ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref N005 ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N009 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} ***** BB07 STMT00061 (IL ???... ???) N005 ( 0, 0) [000432] -A------R--- * ASG bool N004 ( 0, 0) [000430] D------N---- +--* LCL_VAR bool V07 loc1 d:14 N003 ( 0, 0) [000431] ------------ \--* PHI bool N001 ( 0, 0) [000461] ------------ pred BB16 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 ***** BB07 STMT00026 (IL 0x0EA...0x0EB) N003 ( 7, 5) [000127] -A------R--- * ASG int N002 ( 3, 2) [000126] D------N---- +--* LCL_VAR int V06 loc0 d:4 N001 ( 3, 2) [000125] ------------ \--* LCL_VAR int V07 loc1 u:14 (last use) ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} ***** BB08 STMT00059 (IL ???... ???) N005 ( 0, 0) [000426] -A------R--- * ASG bool N004 ( 0, 0) [000424] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000425] ------------ \--* PHI bool N001 ( 0, 0) [000463] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:4 N002 ( 0, 0) [000448] ------------ pred BB24 \--* PHI_ARG bool V06 loc0 u:2 ***** BB08 STMT00027 (IL 0x0EC...0x0ED) N002 ( 4, 3) [000129] ------------ * RETURN int N001 ( 3, 2) [000128] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} ***** BB09 STMT00062 (IL ???... ???) N005 ( 0, 0) [000435] -A------R--- * ASG bool N004 ( 0, 0) [000433] D------N---- +--* LCL_VAR bool V07 loc1 d:11 N003 ( 0, 0) [000434] ------------ \--* PHI bool N001 ( 0, 0) [000460] ------------ pred BB15 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 ***** BB09 STMT00013 (IL 0x095...0x0A7) N017 ( 59, 54) [000073] -ACXG---R--- * ASG struct (copy) N016 ( 3, 2) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 d:2 N015 ( 55, 51) [000070] --CXG------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA N009 ( 26, 26) [000360] -ACXG---R-L- this SETUP +--* ASG ref N008 ( 3, 2) [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 d:2 N007 ( 22, 23) [000066] --CXG------- | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current N004 ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref N005 ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N012 ( 3, 2) [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 u:2 (last use) N013 ( 3, 2) [000069] ------------ arg2 in rsi +--* LCL_VAR ref V01 arg1 u:1 N014 ( 3, 10) [000356] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ***** BB09 STMT00014 (IL ???... ???) N003 ( 7, 7) [000078] -A------R--- * ASG ref N002 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N001 ( 3, 4) [000076] ------------ \--* LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) ***** BB09 STMT00046 (IL 0x0A9... ???) N008 ( 30, 26) [000228] --CXG------- * JTRUE void N007 ( 28, 24) [000249] J-CXG--N---- \--* NE int N005 ( 26, 22) [000247] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind N003 ( 3, 2) [000080] ------------ this in rdi | +--* LCL_VAR ref V10 loc4 u:2 N004 ( 3, 10) [000365] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N006 ( 1, 1) [000248] ------------ \--* CNS_INT int 4 ------------ BB10 [0A9..0AA) -> BB15 (cond), preds={BB09} succs={BB11,BB15} ***** BB10 STMT00049 (IL 0x0A9... ???) N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics N003 ( 3, 2) [000237] ------------ arg0 in rdi +--* LCL_VAR ref V10 loc4 u:2 N004 ( 1, 1) [000238] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 ***** BB10 STMT00050 (IL 0x0A9... ???) N003 ( 5, 4) [000242] -A------R--- * ASG bool N002 ( 3, 2) [000241] D------N---- +--* LCL_VAR int V19 tmp8 d:3 N001 ( 1, 1) [000240] ------------ \--* CNS_INT int 0 ***** BB10 STMT00058 (IL ???... ???) N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] J------N---- \--* NE int N001 ( 3, 2) [000422] ------------ +--* LCL_VAR int V19 tmp8 u:3 (last use) N002 ( 1, 1) [000423] ------------ \--* CNS_INT int 0 ------------ BB11 [???..???) -> BB19 (always), preds={BB10} succs={BB19} ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} ***** BB12 STMT00028 (IL 0x072...0x07E) N015 ( 28, 23) [000139] --CXG------- * JTRUE void N014 ( 26, 21) [000138] J-CXG--N---- \--* EQ int N012 ( 24, 19) [000136] --CXG------- +--* CAST int <- bool <- int N011 ( 23, 17) [000135] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint N006 ( 3, 2) [000130] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 (last use) N007 ( 1, 1) [000131] ------------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 u:1 N008 ( 1, 1) [000132] ------------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 u:1 N009 ( 3, 2) [000133] ------------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 u:1 N010 ( 1, 1) [000134] ------------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 u:1 N013 ( 1, 1) [000137] ------------ \--* CNS_INT int 0 ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} ***** BB14 STMT00048 (IL 0x0A9... ???) N010 ( 24, 17) [000234] -ACXG---R--- * ASG bool N009 ( 3, 2) [000233] D------N---- +--* LCL_VAR int V19 tmp8 d:2 N008 ( 20, 14) [000232] --CXG------- \--* CAST int <- bool <- int N007 ( 19, 12) [000230] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion N004 ( 1, 1) [000079] ------------ arg0 in rdi +--* LCL_VAR ref V03 arg3 u:1 N005 ( 3, 2) [000229] ------------ arg1 in rsi +--* LCL_VAR ref V10 loc4 u:2 N006 ( 1, 1) [000081] ------------ arg2 in rdx \--* LCL_VAR byref V05 arg5 u:1 ***** BB14 STMT00016 (IL ???... ???) N004 ( 7, 6) [000087] ------------ * JTRUE void N003 ( 5, 4) [000086] J------N---- \--* EQ int N001 ( 3, 2) [000235] ------------ +--* LCL_VAR int V19 tmp8 u:2 (last use) N002 ( 1, 1) [000085] ------------ \--* CNS_INT int 0 ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB10,BB14,BB21} succs={BB16,BB09} ***** BB15 STMT00060 (IL ???... ???) N005 ( 0, 0) [000429] -A------R--- * ASG bool N004 ( 0, 0) [000427] D------N---- +--* LCL_VAR bool V07 loc1 d:13 N003 ( 0, 0) [000428] ------------ \--* PHI bool N001 ( 0, 0) [000462] ------------ pred BB14 +--* PHI_ARG bool V07 loc1 u:11 N002 ( 0, 0) [000459] ------------ pred BB21 \--* PHI_ARG bool V07 loc1 u:12 ***** BB15 STMT00012 (IL 0x0E1...0x0E8) N011 ( 27, 29) [000063] --CXG------- * JTRUE void N010 ( 25, 27) [000062] J-CXG--N---- \--* NE int N008 ( 23, 25) [000060] --CXG------- +--* CAST int <- bool <- int N007 ( 22, 23) [000057] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext N004 ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref N005 ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N009 ( 1, 1) [000061] ------------ \--* CNS_INT int 0 ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} ***** BB17 STMT00031 (IL ???... ???) N011 ( 24, 18) [000151] --CXG------- * JTRUE void N010 ( 22, 16) [000150] J-CXG--N---- \--* NE int N008 ( 20, 14) [000148] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000146] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint N004 ( 1, 1) [000143] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 N005 ( 1, 1) [000144] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 N006 ( 3, 2) [000145] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 N009 ( 1, 1) [000149] ------------ \--* CNS_INT int 0 ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} ***** BB18 STMT00032 (IL 0x068...0x069) N003 ( 5, 4) [000154] -A------R--- * ASG int N002 ( 3, 2) [000153] D------N---- +--* LCL_VAR int V07 loc1 d:7 N001 ( 1, 1) [000152] ------------ \--* CNS_INT int 0 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB11} succs={BB20,BB21} ***** BB19 STMT00017 (IL 0x0B5...0x0B7) N004 ( 7, 6) [000091] ------------ * JTRUE void N003 ( 5, 4) [000090] J------N---- \--* EQ int N001 ( 3, 2) [000088] ------------ +--* LCL_VAR ref V04 arg4 u:1 N002 ( 1, 1) [000089] ------------ \--* CNS_INT ref null ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} ***** BB20 STMT00019 (IL 0x0B9...0x0CA) N005 ( 19, 10) [000101] -ACXG---R--- * ASG ref N004 ( 3, 2) [000100] D------N---- +--* LCL_VAR ref V14 tmp3 d:2 N003 ( 15, 7) [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 N002 ( 1, 1) [000098] ------------ arg0 in rdi \--* CNS_INT long 2 ***** BB20 STMT00020 (IL ???... ???) N011 ( 18, 19) [000107] -A-XG------- * ASG ref N009 ( 16, 17) [000384] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000378] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 N003 ( 5, 4) [000377] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000103] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 N008 ( 6, 5) [000106] a---G--N---- | \--* IND ref N007 ( 4, 3) [000383] -------N---- | \--* ADD byref N005 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 N006 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N010 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 ***** BB20 STMT00021 (IL ???...0x0CF) N011 ( 20, 20) [000112] -A-XG------- * ASG ref N009 ( 16, 17) [000394] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 N003 ( 5, 4) [000387] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000108] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 N008 ( 6, 5) [000111] a---G--N---- | \--* IND ref N007 ( 4, 3) [000393] -------N---- | \--* ADD byref N005 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 N006 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] N010 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) ***** BB20 STMT00052 (IL ???... ???) N003 ( 18, 8) [000261] -AC-----R--- * ASG ref N002 ( 3, 2) [000260] D------N---- +--* LCL_VAR ref V20 tmp9 d:2 N001 ( 14, 5) [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW ***** BB20 STMT00053 (IL ???... ???) N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor N007 ( 21, 14) [000396] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 d:2 N005 ( 17, 11) [000255] --CXG------- | \--* IND ref N004 ( 15, 9) [000254] --CXG--N---- | \--* ADD byref N002 ( 14, 5) [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE N003 ( 1, 4) [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] N010 ( 3, 2) [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 u:2 N012 ( 3, 2) [000102] ------------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 u:2 (last use) N013 ( 1, 4) [000256] ------------ arg2 in rdx \--* CNS_INT int 0x7D2C ***** BB20 STMT00054 (IL ???... ???) N003 ( 5, 4) [000269] IA------R--- * ASG struct (init) N002 ( 3, 2) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 d:2 N001 ( 1, 1) [000268] ------------ \--* CNS_INT int 0 ***** BB20 STMT00055 (IL ???... ???) N003 ( 5, 6) [000273] -A------R--- * ASG ref N002 ( 3, 4) [000272] U------N---- +--* LCL_FLD ref V15 tmp4 ud:2->3[+0] Fseq[TypeParameter] N001 ( 1, 1) [000096] ------------ \--* LCL_VAR ref V02 arg2 u:1 ***** BB20 STMT00056 (IL ???... ???) N003 ( 7, 7) [000277] -A------R--- * ASG ref N002 ( 3, 4) [000276] U------N---- +--* LCL_FLD ref V15 tmp4 ud:3->4[+8] Fseq[DiagnosticInfo] N001 ( 3, 2) [000264] ------------ \--* LCL_VAR ref V20 tmp9 u:2 (last use) ***** BB20 STMT00025 (IL 0x0DA... ???) N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000123] ------------ | \--* ADDR byref N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} ***** BB21 STMT00018 (IL 0x0DF...0x0E0) N003 ( 5, 4) [000094] -A------R--- * ASG int N002 ( 3, 2) [000093] D------N---- +--* LCL_VAR int V07 loc1 d:12 N001 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} ***** BB22 STMT00033 (IL 0x048...0x051) N011 ( 24, 18) [000162] --CXG------- * JTRUE void N010 ( 22, 16) [000161] J-CXG--N---- \--* NE int N008 ( 20, 14) [000159] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000158] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint N004 ( 1, 1) [000155] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 N005 ( 1, 1) [000156] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 N006 ( 3, 2) [000157] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 N009 ( 1, 1) [000160] ------------ \--* CNS_INT int 0 ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} ***** BB23 STMT00034 (IL 0x053...0x054) N003 ( 5, 4) [000165] -A------R--- * ASG int N002 ( 3, 2) [000164] D------N---- +--* LCL_VAR int V07 loc1 d:5 N001 ( 1, 1) [000163] ------------ \--* CNS_INT int 0 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} ***** BB24 STMT00042 (IL 0x008...0x009) N003 ( 5, 4) [000197] -A------R--- * ASG int N002 ( 3, 2) [000196] D------N---- +--* LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000195] ------------ \--* CNS_INT int 1 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} ***** BB25 STMT00035 (IL 0x019...0x01B) N004 ( 7, 6) [000169] ------------ * JTRUE void N003 ( 5, 4) [000168] J------N---- \--* EQ int N001 ( 3, 2) [000166] ------------ +--* LCL_VAR ref V04 arg4 u:1 N002 ( 1, 1) [000167] ------------ \--* CNS_INT ref null ------------ BB26 [01D..03E), preds={BB25} succs={BB27} ***** BB26 STMT00037 (IL 0x01D...0x02E) N005 ( 19, 10) [000179] -ACXG---R--- * ASG ref N004 ( 3, 2) [000178] D------N---- +--* LCL_VAR ref V16 tmp5 d:2 N003 ( 15, 7) [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 N002 ( 1, 1) [000176] ------------ arg0 in rdi \--* CNS_INT long 1 ***** BB26 STMT00038 (IL ???... ???) N011 ( 18, 19) [000185] -A-XG------- * ASG ref N009 ( 16, 17) [000298] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000292] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000182] ------------ | | +--* CNS_INT int 0 N003 ( 5, 4) [000291] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000181] ------------ | | \--* LCL_VAR ref V16 tmp5 u:2 N008 ( 6, 5) [000184] a---G--N---- | \--* IND ref N007 ( 4, 3) [000297] -------N---- | \--* ADD byref N005 ( 3, 2) [000289] ------------ | +--* LCL_VAR ref V16 tmp5 u:2 N006 ( 1, 1) [000296] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N010 ( 1, 1) [000183] ------------ \--* LCL_VAR ref V03 arg3 u:1 ***** BB26 STMT00043 (IL ???... ???) N003 ( 18, 8) [000216] -AC-----R--- * ASG ref N002 ( 3, 2) [000215] D------N---- +--* LCL_VAR ref V18 tmp7 d:2 N001 ( 14, 5) [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW ***** BB26 STMT00044 (IL ???... ???) N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor N007 ( 21, 14) [000300] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 d:2 N005 ( 17, 11) [000210] --CXG------- | \--* IND ref N004 ( 15, 9) [000209] --CXG--N---- | \--* ADD byref N002 ( 14, 5) [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE N003 ( 1, 4) [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] N010 ( 3, 2) [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 u:2 N012 ( 3, 2) [000180] ------------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 u:2 (last use) N013 ( 1, 4) [000211] ------------ arg2 in rdx \--* CNS_INT int 0x7AA4 ***** BB26 STMT00040 (IL ???... ???) N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor N004 ( 3, 3) [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 N005 ( 1, 1) [000174] ------------ arg1 in rsi +--* LCL_VAR ref V02 arg2 u:1 N006 ( 3, 2) [000219] ------------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 u:2 (last use) ***** BB26 STMT00041 (IL 0x039... ???) N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} ***** BB27 STMT00036 (IL 0x03E...0x03F) N003 ( 5, 4) [000172] -A------R--- * ASG int N002 ( 3, 2) [000171] D------N---- +--* LCL_VAR int V07 loc1 d:3 N001 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} ***** BB28 STMT00029 (IL 0x080...0x081) N003 ( 5, 4) [000142] -A------R--- * ASG int N002 ( 3, 2) [000141] D------N---- +--* LCL_VAR int V07 loc1 d:9 N001 ( 1, 1) [000140] ------------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Build SSA representation Trees after Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB15 ( cond ) i gcsafe bwd BB11 [0034] 1 BB10 0.58 [???..???)-> BB19 (always) internal gcsafe BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 3 BB10,BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB11 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} ***** BB01 STMT00001 (IL ???... ???) N008 ( 28, 25) [000006] --CXG------- * JTRUE void N007 ( 26, 23) [000200] J-CXG--N---- \--* EQ int N005 ( 24, 21) [000198] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind N003 ( 1, 1) [000000] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 N004 ( 3, 10) [000279] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N006 ( 1, 1) [000199] ------------ \--* CNS_INT int 4 ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} ***** BB02 STMT00002 (IL 0x00F...0x010) N003 ( 5, 4) [000009] -A------R--- * ASG int N002 ( 3, 2) [000008] D------N---- +--* LCL_VAR int V07 loc1 d:2 N001 ( 1, 1) [000007] ------------ \--* CNS_INT int 1 ***** BB02 STMT00004 (IL ???... ???) N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} ***** BB03 STMT00066 (IL ???... ???) N005 ( 0, 0) [000447] -A------R--- * ASG bool N004 ( 0, 0) [000445] D------N---- +--* LCL_VAR bool V07 loc1 d:4 N003 ( 0, 0) [000446] ------------ \--* PHI bool N001 ( 0, 0) [000450] ------------ pred BB27 +--* PHI_ARG bool V07 loc1 u:3 N002 ( 0, 0) [000449] ------------ pred BB02 \--* PHI_ARG bool V07 loc1 u:2 ***** BB03 STMT00005 (IL 0x040...0x046) N009 ( 29, 27) [000022] --CXG------- * JTRUE void N008 ( 27, 25) [000021] J-CXG--N---- \--* NE int N006 ( 25, 23) [000019] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000018] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint N003 ( 1, 1) [000017] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 N004 ( 3, 10) [000312] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000020] ------------ \--* CNS_INT int 0 ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} ***** BB04 STMT00065 (IL ???... ???) N005 ( 0, 0) [000444] -A------R--- * ASG bool N004 ( 0, 0) [000442] D------N---- +--* LCL_VAR bool V07 loc1 d:6 N003 ( 0, 0) [000443] ------------ \--* PHI bool N001 ( 0, 0) [000452] ------------ pred BB23 +--* PHI_ARG bool V07 loc1 u:5 N002 ( 0, 0) [000451] ------------ pred BB03 \--* PHI_ARG bool V07 loc1 u:4 ***** BB04 STMT00006 (IL 0x055...0x05B) N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} ***** BB05 STMT00064 (IL ???... ???) N005 ( 0, 0) [000441] -A------R--- * ASG bool N004 ( 0, 0) [000439] D------N---- +--* LCL_VAR bool V07 loc1 d:8 N003 ( 0, 0) [000440] ------------ \--* PHI bool N001 ( 0, 0) [000454] ------------ pred BB18 +--* PHI_ARG bool V07 loc1 u:7 N002 ( 0, 0) [000453] ------------ pred BB04 \--* PHI_ARG bool V07 loc1 u:6 ***** BB05 STMT00007 (IL 0x06A...0x070) N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} ***** BB06 STMT00063 (IL ???... ???) N005 ( 0, 0) [000438] -A------R--- * ASG bool N004 ( 0, 0) [000436] D------N---- +--* LCL_VAR bool V07 loc1 d:10 N003 ( 0, 0) [000437] ------------ \--* PHI bool N001 ( 0, 0) [000456] ------------ pred BB28 +--* PHI_ARG bool V07 loc1 u:9 N002 ( 0, 0) [000455] ------------ pred BB05 \--* PHI_ARG bool V07 loc1 u:8 ***** BB06 STMT00009 (IL ???... ???) N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 ***** BB06 STMT00010 (IL 0x08B...0x092) N009 ( 26, 26) [000050] -ACXG---R--- * ASG struct (copy) N008 ( 3, 2) [000048] D------N---- +--* LCL_VAR struct(AX) V12 tmp1 N007 ( 22, 23) [000045] --CXG------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA N004 ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long N003 ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref N005 ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 ***** BB06 STMT00011 (IL ???... ???) N016 ( 18, 15) [000355] -A-XG------- * COMMA void N009 ( 10, 8) [000348] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref N001 ( 3, 2) [000341] -------N---- | | \--* LCL_VAR struct(AX) V12 tmp1 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] N015 ( 8, 7) [000354] -A-XG---R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] ---X-------- \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] ***** BB06 STMT00057 (IL 0x0E1... ???) N011 ( 27, 29) [000419] --CXG------- * JTRUE void N010 ( 25, 27) [000409] J-CXG--N---- \--* NE int N008 ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int N007 ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext N004 ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref N005 ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N009 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} ***** BB07 STMT00061 (IL ???... ???) N005 ( 0, 0) [000432] -A------R--- * ASG bool N004 ( 0, 0) [000430] D------N---- +--* LCL_VAR bool V07 loc1 d:14 N003 ( 0, 0) [000431] ------------ \--* PHI bool N001 ( 0, 0) [000461] ------------ pred BB16 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 ***** BB07 STMT00026 (IL 0x0EA...0x0EB) N003 ( 7, 5) [000127] -A------R--- * ASG int N002 ( 3, 2) [000126] D------N---- +--* LCL_VAR int V06 loc0 d:4 N001 ( 3, 2) [000125] ------------ \--* LCL_VAR int V07 loc1 u:14 (last use) ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} ***** BB08 STMT00059 (IL ???... ???) N005 ( 0, 0) [000426] -A------R--- * ASG bool N004 ( 0, 0) [000424] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000425] ------------ \--* PHI bool N001 ( 0, 0) [000463] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:4 N002 ( 0, 0) [000448] ------------ pred BB24 \--* PHI_ARG bool V06 loc0 u:2 ***** BB08 STMT00027 (IL 0x0EC...0x0ED) N002 ( 4, 3) [000129] ------------ * RETURN int N001 ( 3, 2) [000128] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} ***** BB09 STMT00062 (IL ???... ???) N005 ( 0, 0) [000435] -A------R--- * ASG bool N004 ( 0, 0) [000433] D------N---- +--* LCL_VAR bool V07 loc1 d:11 N003 ( 0, 0) [000434] ------------ \--* PHI bool N001 ( 0, 0) [000460] ------------ pred BB15 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 ***** BB09 STMT00013 (IL 0x095...0x0A7) N017 ( 59, 54) [000073] -ACXG---R--- * ASG struct (copy) N016 ( 3, 2) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 d:2 N015 ( 55, 51) [000070] --CXG------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA N009 ( 26, 26) [000360] -ACXG---R-L- this SETUP +--* ASG ref N008 ( 3, 2) [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 d:2 N007 ( 22, 23) [000066] --CXG------- | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current N004 ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref N005 ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N012 ( 3, 2) [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 u:2 (last use) N013 ( 3, 2) [000069] ------------ arg2 in rsi +--* LCL_VAR ref V01 arg1 u:1 N014 ( 3, 10) [000356] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ***** BB09 STMT00014 (IL ???... ???) N003 ( 7, 7) [000078] -A------R--- * ASG ref N002 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N001 ( 3, 4) [000076] ------------ \--* LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) ***** BB09 STMT00046 (IL 0x0A9... ???) N008 ( 30, 26) [000228] --CXG------- * JTRUE void N007 ( 28, 24) [000249] J-CXG--N---- \--* NE int N005 ( 26, 22) [000247] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind N003 ( 3, 2) [000080] ------------ this in rdi | +--* LCL_VAR ref V10 loc4 u:2 N004 ( 3, 10) [000365] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N006 ( 1, 1) [000248] ------------ \--* CNS_INT int 4 ------------ BB10 [0A9..0AA) -> BB15 (cond), preds={BB09} succs={BB11,BB15} ***** BB10 STMT00049 (IL 0x0A9... ???) N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics N003 ( 3, 2) [000237] ------------ arg0 in rdi +--* LCL_VAR ref V10 loc4 u:2 N004 ( 1, 1) [000238] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 ***** BB10 STMT00050 (IL 0x0A9... ???) N003 ( 5, 4) [000242] -A------R--- * ASG bool N002 ( 3, 2) [000241] D------N---- +--* LCL_VAR int V19 tmp8 d:3 N001 ( 1, 1) [000240] ------------ \--* CNS_INT int 0 ***** BB10 STMT00058 (IL ???... ???) N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] J------N---- \--* NE int N001 ( 3, 2) [000422] ------------ +--* LCL_VAR int V19 tmp8 u:3 (last use) N002 ( 1, 1) [000423] ------------ \--* CNS_INT int 0 ------------ BB11 [???..???) -> BB19 (always), preds={BB10} succs={BB19} ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} ***** BB12 STMT00028 (IL 0x072...0x07E) N015 ( 28, 23) [000139] --CXG------- * JTRUE void N014 ( 26, 21) [000138] J-CXG--N---- \--* EQ int N012 ( 24, 19) [000136] --CXG------- +--* CAST int <- bool <- int N011 ( 23, 17) [000135] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint N006 ( 3, 2) [000130] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 (last use) N007 ( 1, 1) [000131] ------------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 u:1 N008 ( 1, 1) [000132] ------------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 u:1 N009 ( 3, 2) [000133] ------------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 u:1 N010 ( 1, 1) [000134] ------------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 u:1 N013 ( 1, 1) [000137] ------------ \--* CNS_INT int 0 ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} ***** BB14 STMT00048 (IL 0x0A9... ???) N010 ( 24, 17) [000234] -ACXG---R--- * ASG bool N009 ( 3, 2) [000233] D------N---- +--* LCL_VAR int V19 tmp8 d:2 N008 ( 20, 14) [000232] --CXG------- \--* CAST int <- bool <- int N007 ( 19, 12) [000230] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion N004 ( 1, 1) [000079] ------------ arg0 in rdi +--* LCL_VAR ref V03 arg3 u:1 N005 ( 3, 2) [000229] ------------ arg1 in rsi +--* LCL_VAR ref V10 loc4 u:2 N006 ( 1, 1) [000081] ------------ arg2 in rdx \--* LCL_VAR byref V05 arg5 u:1 ***** BB14 STMT00016 (IL ???... ???) N004 ( 7, 6) [000087] ------------ * JTRUE void N003 ( 5, 4) [000086] J------N---- \--* EQ int N001 ( 3, 2) [000235] ------------ +--* LCL_VAR int V19 tmp8 u:2 (last use) N002 ( 1, 1) [000085] ------------ \--* CNS_INT int 0 ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB10,BB14,BB21} succs={BB16,BB09} ***** BB15 STMT00060 (IL ???... ???) N005 ( 0, 0) [000429] -A------R--- * ASG bool N004 ( 0, 0) [000427] D------N---- +--* LCL_VAR bool V07 loc1 d:13 N003 ( 0, 0) [000428] ------------ \--* PHI bool N001 ( 0, 0) [000462] ------------ pred BB14 +--* PHI_ARG bool V07 loc1 u:11 N002 ( 0, 0) [000459] ------------ pred BB21 \--* PHI_ARG bool V07 loc1 u:12 ***** BB15 STMT00012 (IL 0x0E1...0x0E8) N011 ( 27, 29) [000063] --CXG------- * JTRUE void N010 ( 25, 27) [000062] J-CXG--N---- \--* NE int N008 ( 23, 25) [000060] --CXG------- +--* CAST int <- bool <- int N007 ( 22, 23) [000057] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext N004 ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref N005 ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N009 ( 1, 1) [000061] ------------ \--* CNS_INT int 0 ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} ***** BB17 STMT00031 (IL ???... ???) N011 ( 24, 18) [000151] --CXG------- * JTRUE void N010 ( 22, 16) [000150] J-CXG--N---- \--* NE int N008 ( 20, 14) [000148] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000146] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint N004 ( 1, 1) [000143] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 N005 ( 1, 1) [000144] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 N006 ( 3, 2) [000145] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 N009 ( 1, 1) [000149] ------------ \--* CNS_INT int 0 ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} ***** BB18 STMT00032 (IL 0x068...0x069) N003 ( 5, 4) [000154] -A------R--- * ASG int N002 ( 3, 2) [000153] D------N---- +--* LCL_VAR int V07 loc1 d:7 N001 ( 1, 1) [000152] ------------ \--* CNS_INT int 0 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB11} succs={BB20,BB21} ***** BB19 STMT00017 (IL 0x0B5...0x0B7) N004 ( 7, 6) [000091] ------------ * JTRUE void N003 ( 5, 4) [000090] J------N---- \--* EQ int N001 ( 3, 2) [000088] ------------ +--* LCL_VAR ref V04 arg4 u:1 N002 ( 1, 1) [000089] ------------ \--* CNS_INT ref null ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} ***** BB20 STMT00019 (IL 0x0B9...0x0CA) N005 ( 19, 10) [000101] -ACXG---R--- * ASG ref N004 ( 3, 2) [000100] D------N---- +--* LCL_VAR ref V14 tmp3 d:2 N003 ( 15, 7) [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 N002 ( 1, 1) [000098] ------------ arg0 in rdi \--* CNS_INT long 2 ***** BB20 STMT00020 (IL ???... ???) N011 ( 18, 19) [000107] -A-XG------- * ASG ref N009 ( 16, 17) [000384] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000378] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 N003 ( 5, 4) [000377] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000103] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 N008 ( 6, 5) [000106] a---G--N---- | \--* IND ref N007 ( 4, 3) [000383] -------N---- | \--* ADD byref N005 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 N006 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N010 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 ***** BB20 STMT00021 (IL ???...0x0CF) N011 ( 20, 20) [000112] -A-XG------- * ASG ref N009 ( 16, 17) [000394] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 N003 ( 5, 4) [000387] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000108] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 N008 ( 6, 5) [000111] a---G--N---- | \--* IND ref N007 ( 4, 3) [000393] -------N---- | \--* ADD byref N005 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 N006 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] N010 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) ***** BB20 STMT00052 (IL ???... ???) N003 ( 18, 8) [000261] -AC-----R--- * ASG ref N002 ( 3, 2) [000260] D------N---- +--* LCL_VAR ref V20 tmp9 d:2 N001 ( 14, 5) [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW ***** BB20 STMT00053 (IL ???... ???) N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor N007 ( 21, 14) [000396] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 d:2 N005 ( 17, 11) [000255] --CXG------- | \--* IND ref N004 ( 15, 9) [000254] --CXG--N---- | \--* ADD byref N002 ( 14, 5) [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE N003 ( 1, 4) [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] N010 ( 3, 2) [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 u:2 N012 ( 3, 2) [000102] ------------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 u:2 (last use) N013 ( 1, 4) [000256] ------------ arg2 in rdx \--* CNS_INT int 0x7D2C ***** BB20 STMT00054 (IL ???... ???) N003 ( 5, 4) [000269] IA------R--- * ASG struct (init) N002 ( 3, 2) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 d:2 N001 ( 1, 1) [000268] ------------ \--* CNS_INT int 0 ***** BB20 STMT00055 (IL ???... ???) N003 ( 5, 6) [000273] -A------R--- * ASG ref N002 ( 3, 4) [000272] U------N---- +--* LCL_FLD ref V15 tmp4 ud:2->3[+0] Fseq[TypeParameter] N001 ( 1, 1) [000096] ------------ \--* LCL_VAR ref V02 arg2 u:1 ***** BB20 STMT00056 (IL ???... ???) N003 ( 7, 7) [000277] -A------R--- * ASG ref N002 ( 3, 4) [000276] U------N---- +--* LCL_FLD ref V15 tmp4 ud:3->4[+8] Fseq[DiagnosticInfo] N001 ( 3, 2) [000264] ------------ \--* LCL_VAR ref V20 tmp9 u:2 (last use) ***** BB20 STMT00025 (IL 0x0DA... ???) N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000123] ------------ | \--* ADDR byref N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} ***** BB21 STMT00018 (IL 0x0DF...0x0E0) N003 ( 5, 4) [000094] -A------R--- * ASG int N002 ( 3, 2) [000093] D------N---- +--* LCL_VAR int V07 loc1 d:12 N001 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} ***** BB22 STMT00033 (IL 0x048...0x051) N011 ( 24, 18) [000162] --CXG------- * JTRUE void N010 ( 22, 16) [000161] J-CXG--N---- \--* NE int N008 ( 20, 14) [000159] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000158] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint N004 ( 1, 1) [000155] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 N005 ( 1, 1) [000156] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 N006 ( 3, 2) [000157] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 N009 ( 1, 1) [000160] ------------ \--* CNS_INT int 0 ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} ***** BB23 STMT00034 (IL 0x053...0x054) N003 ( 5, 4) [000165] -A------R--- * ASG int N002 ( 3, 2) [000164] D------N---- +--* LCL_VAR int V07 loc1 d:5 N001 ( 1, 1) [000163] ------------ \--* CNS_INT int 0 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} ***** BB24 STMT00042 (IL 0x008...0x009) N003 ( 5, 4) [000197] -A------R--- * ASG int N002 ( 3, 2) [000196] D------N---- +--* LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000195] ------------ \--* CNS_INT int 1 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} ***** BB25 STMT00035 (IL 0x019...0x01B) N004 ( 7, 6) [000169] ------------ * JTRUE void N003 ( 5, 4) [000168] J------N---- \--* EQ int N001 ( 3, 2) [000166] ------------ +--* LCL_VAR ref V04 arg4 u:1 N002 ( 1, 1) [000167] ------------ \--* CNS_INT ref null ------------ BB26 [01D..03E), preds={BB25} succs={BB27} ***** BB26 STMT00037 (IL 0x01D...0x02E) N005 ( 19, 10) [000179] -ACXG---R--- * ASG ref N004 ( 3, 2) [000178] D------N---- +--* LCL_VAR ref V16 tmp5 d:2 N003 ( 15, 7) [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 N002 ( 1, 1) [000176] ------------ arg0 in rdi \--* CNS_INT long 1 ***** BB26 STMT00038 (IL ???... ???) N011 ( 18, 19) [000185] -A-XG------- * ASG ref N009 ( 16, 17) [000298] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000292] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000182] ------------ | | +--* CNS_INT int 0 N003 ( 5, 4) [000291] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000181] ------------ | | \--* LCL_VAR ref V16 tmp5 u:2 N008 ( 6, 5) [000184] a---G--N---- | \--* IND ref N007 ( 4, 3) [000297] -------N---- | \--* ADD byref N005 ( 3, 2) [000289] ------------ | +--* LCL_VAR ref V16 tmp5 u:2 N006 ( 1, 1) [000296] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N010 ( 1, 1) [000183] ------------ \--* LCL_VAR ref V03 arg3 u:1 ***** BB26 STMT00043 (IL ???... ???) N003 ( 18, 8) [000216] -AC-----R--- * ASG ref N002 ( 3, 2) [000215] D------N---- +--* LCL_VAR ref V18 tmp7 d:2 N001 ( 14, 5) [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW ***** BB26 STMT00044 (IL ???... ???) N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor N007 ( 21, 14) [000300] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 d:2 N005 ( 17, 11) [000210] --CXG------- | \--* IND ref N004 ( 15, 9) [000209] --CXG--N---- | \--* ADD byref N002 ( 14, 5) [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE N003 ( 1, 4) [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] N010 ( 3, 2) [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 u:2 N012 ( 3, 2) [000180] ------------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 u:2 (last use) N013 ( 1, 4) [000211] ------------ arg2 in rdx \--* CNS_INT int 0x7AA4 ***** BB26 STMT00040 (IL ???... ???) N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor N004 ( 3, 3) [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 N005 ( 1, 1) [000174] ------------ arg1 in rsi +--* LCL_VAR ref V02 arg2 u:1 N006 ( 3, 2) [000219] ------------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 u:2 (last use) ***** BB26 STMT00041 (IL 0x039... ???) N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} ***** BB27 STMT00036 (IL 0x03E...0x03F) N003 ( 5, 4) [000172] -A------R--- * ASG int N002 ( 3, 2) [000171] D------N---- +--* LCL_VAR int V07 loc1 d:3 N001 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} ***** BB28 STMT00029 (IL 0x080...0x081) N003 ( 5, 4) [000142] -A------R--- * ASG int N002 ( 3, 2) [000141] D------N---- +--* LCL_VAR int V07 loc1 d:9 N001 ( 1, 1) [000140] ------------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Redundant zero Inits *************** In optRemoveRedundantZeroInits() *************** Finishing PHASE Redundant zero Inits *************** Starting PHASE Early Value Propagation *************** In optEarlyProp() After optEarlyProp: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB15 ( cond ) i gcsafe bwd BB11 [0034] 1 BB10 0.58 [???..???)-> BB19 (always) internal gcsafe BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 3 BB10,BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB11 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} ***** BB01 STMT00001 (IL ???... ???) N008 ( 28, 25) [000006] --CXG------- * JTRUE void N007 ( 26, 23) [000200] J-CXG--N---- \--* EQ int N005 ( 24, 21) [000198] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind N003 ( 1, 1) [000000] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 N004 ( 3, 10) [000279] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N006 ( 1, 1) [000199] ------------ \--* CNS_INT int 4 ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} ***** BB02 STMT00002 (IL 0x00F...0x010) N003 ( 5, 4) [000009] -A------R--- * ASG int N002 ( 3, 2) [000008] D------N---- +--* LCL_VAR int V07 loc1 d:2 N001 ( 1, 1) [000007] ------------ \--* CNS_INT int 1 ***** BB02 STMT00004 (IL ???... ???) N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} ***** BB03 STMT00066 (IL ???... ???) N005 ( 0, 0) [000447] -A------R--- * ASG bool N004 ( 0, 0) [000445] D------N---- +--* LCL_VAR bool V07 loc1 d:4 N003 ( 0, 0) [000446] ------------ \--* PHI bool N001 ( 0, 0) [000450] ------------ pred BB27 +--* PHI_ARG bool V07 loc1 u:3 N002 ( 0, 0) [000449] ------------ pred BB02 \--* PHI_ARG bool V07 loc1 u:2 ***** BB03 STMT00005 (IL 0x040...0x046) N009 ( 29, 27) [000022] --CXG------- * JTRUE void N008 ( 27, 25) [000021] J-CXG--N---- \--* NE int N006 ( 25, 23) [000019] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000018] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint N003 ( 1, 1) [000017] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 N004 ( 3, 10) [000312] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000020] ------------ \--* CNS_INT int 0 ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} ***** BB04 STMT00065 (IL ???... ???) N005 ( 0, 0) [000444] -A------R--- * ASG bool N004 ( 0, 0) [000442] D------N---- +--* LCL_VAR bool V07 loc1 d:6 N003 ( 0, 0) [000443] ------------ \--* PHI bool N001 ( 0, 0) [000452] ------------ pred BB23 +--* PHI_ARG bool V07 loc1 u:5 N002 ( 0, 0) [000451] ------------ pred BB03 \--* PHI_ARG bool V07 loc1 u:4 ***** BB04 STMT00006 (IL 0x055...0x05B) N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} ***** BB05 STMT00064 (IL ???... ???) N005 ( 0, 0) [000441] -A------R--- * ASG bool N004 ( 0, 0) [000439] D------N---- +--* LCL_VAR bool V07 loc1 d:8 N003 ( 0, 0) [000440] ------------ \--* PHI bool N001 ( 0, 0) [000454] ------------ pred BB18 +--* PHI_ARG bool V07 loc1 u:7 N002 ( 0, 0) [000453] ------------ pred BB04 \--* PHI_ARG bool V07 loc1 u:6 ***** BB05 STMT00007 (IL 0x06A...0x070) N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} ***** BB06 STMT00063 (IL ???... ???) N005 ( 0, 0) [000438] -A------R--- * ASG bool N004 ( 0, 0) [000436] D------N---- +--* LCL_VAR bool V07 loc1 d:10 N003 ( 0, 0) [000437] ------------ \--* PHI bool N001 ( 0, 0) [000456] ------------ pred BB28 +--* PHI_ARG bool V07 loc1 u:9 N002 ( 0, 0) [000455] ------------ pred BB05 \--* PHI_ARG bool V07 loc1 u:8 ***** BB06 STMT00009 (IL ???... ???) N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 ***** BB06 STMT00010 (IL 0x08B...0x092) N009 ( 26, 26) [000050] -ACXG---R--- * ASG struct (copy) N008 ( 3, 2) [000048] D------N---- +--* LCL_VAR struct(AX) V12 tmp1 N007 ( 22, 23) [000045] --CXG------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA N004 ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long N003 ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref N005 ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 ***** BB06 STMT00011 (IL ???... ???) N016 ( 18, 15) [000355] -A-XG------- * COMMA void N009 ( 10, 8) [000348] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref N001 ( 3, 2) [000341] -------N---- | | \--* LCL_VAR struct(AX) V12 tmp1 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] N015 ( 8, 7) [000354] -A-XG---R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] ---X-------- \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] ***** BB06 STMT00057 (IL 0x0E1... ???) N011 ( 27, 29) [000419] --CXG------- * JTRUE void N010 ( 25, 27) [000409] J-CXG--N---- \--* NE int N008 ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int N007 ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext N004 ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref N005 ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N009 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} ***** BB07 STMT00061 (IL ???... ???) N005 ( 0, 0) [000432] -A------R--- * ASG bool N004 ( 0, 0) [000430] D------N---- +--* LCL_VAR bool V07 loc1 d:14 N003 ( 0, 0) [000431] ------------ \--* PHI bool N001 ( 0, 0) [000461] ------------ pred BB16 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 ***** BB07 STMT00026 (IL 0x0EA...0x0EB) N003 ( 7, 5) [000127] -A------R--- * ASG int N002 ( 3, 2) [000126] D------N---- +--* LCL_VAR int V06 loc0 d:4 N001 ( 3, 2) [000125] ------------ \--* LCL_VAR int V07 loc1 u:14 (last use) ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} ***** BB08 STMT00059 (IL ???... ???) N005 ( 0, 0) [000426] -A------R--- * ASG bool N004 ( 0, 0) [000424] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000425] ------------ \--* PHI bool N001 ( 0, 0) [000463] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:4 N002 ( 0, 0) [000448] ------------ pred BB24 \--* PHI_ARG bool V06 loc0 u:2 ***** BB08 STMT00027 (IL 0x0EC...0x0ED) N002 ( 4, 3) [000129] ------------ * RETURN int N001 ( 3, 2) [000128] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} ***** BB09 STMT00062 (IL ???... ???) N005 ( 0, 0) [000435] -A------R--- * ASG bool N004 ( 0, 0) [000433] D------N---- +--* LCL_VAR bool V07 loc1 d:11 N003 ( 0, 0) [000434] ------------ \--* PHI bool N001 ( 0, 0) [000460] ------------ pred BB15 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 ***** BB09 STMT00013 (IL 0x095...0x0A7) N017 ( 59, 54) [000073] -ACXG---R--- * ASG struct (copy) N016 ( 3, 2) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 d:2 N015 ( 55, 51) [000070] --CXG------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA N009 ( 26, 26) [000360] -ACXG---R-L- this SETUP +--* ASG ref N008 ( 3, 2) [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 d:2 N007 ( 22, 23) [000066] --CXG------- | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current N004 ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref N005 ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N012 ( 3, 2) [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 u:2 (last use) N013 ( 3, 2) [000069] ------------ arg2 in rsi +--* LCL_VAR ref V01 arg1 u:1 N014 ( 3, 10) [000356] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ***** BB09 STMT00014 (IL ???... ???) N003 ( 7, 7) [000078] -A------R--- * ASG ref N002 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N001 ( 3, 4) [000076] ------------ \--* LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) ***** BB09 STMT00046 (IL 0x0A9... ???) N008 ( 30, 26) [000228] --CXG------- * JTRUE void N007 ( 28, 24) [000249] J-CXG--N---- \--* NE int N005 ( 26, 22) [000247] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind N003 ( 3, 2) [000080] ------------ this in rdi | +--* LCL_VAR ref V10 loc4 u:2 N004 ( 3, 10) [000365] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N006 ( 1, 1) [000248] ------------ \--* CNS_INT int 4 ------------ BB10 [0A9..0AA) -> BB15 (cond), preds={BB09} succs={BB11,BB15} ***** BB10 STMT00049 (IL 0x0A9... ???) N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics N003 ( 3, 2) [000237] ------------ arg0 in rdi +--* LCL_VAR ref V10 loc4 u:2 N004 ( 1, 1) [000238] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 ***** BB10 STMT00050 (IL 0x0A9... ???) N003 ( 5, 4) [000242] -A------R--- * ASG bool N002 ( 3, 2) [000241] D------N---- +--* LCL_VAR int V19 tmp8 d:3 N001 ( 1, 1) [000240] ------------ \--* CNS_INT int 0 ***** BB10 STMT00058 (IL ???... ???) N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] J------N---- \--* NE int N001 ( 3, 2) [000422] ------------ +--* LCL_VAR int V19 tmp8 u:3 (last use) N002 ( 1, 1) [000423] ------------ \--* CNS_INT int 0 ------------ BB11 [???..???) -> BB19 (always), preds={BB10} succs={BB19} ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} ***** BB12 STMT00028 (IL 0x072...0x07E) N015 ( 28, 23) [000139] --CXG------- * JTRUE void N014 ( 26, 21) [000138] J-CXG--N---- \--* EQ int N012 ( 24, 19) [000136] --CXG------- +--* CAST int <- bool <- int N011 ( 23, 17) [000135] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint N006 ( 3, 2) [000130] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 (last use) N007 ( 1, 1) [000131] ------------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 u:1 N008 ( 1, 1) [000132] ------------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 u:1 N009 ( 3, 2) [000133] ------------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 u:1 N010 ( 1, 1) [000134] ------------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 u:1 N013 ( 1, 1) [000137] ------------ \--* CNS_INT int 0 ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} ***** BB14 STMT00048 (IL 0x0A9... ???) N010 ( 24, 17) [000234] -ACXG---R--- * ASG bool N009 ( 3, 2) [000233] D------N---- +--* LCL_VAR int V19 tmp8 d:2 N008 ( 20, 14) [000232] --CXG------- \--* CAST int <- bool <- int N007 ( 19, 12) [000230] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion N004 ( 1, 1) [000079] ------------ arg0 in rdi +--* LCL_VAR ref V03 arg3 u:1 N005 ( 3, 2) [000229] ------------ arg1 in rsi +--* LCL_VAR ref V10 loc4 u:2 N006 ( 1, 1) [000081] ------------ arg2 in rdx \--* LCL_VAR byref V05 arg5 u:1 ***** BB14 STMT00016 (IL ???... ???) N004 ( 7, 6) [000087] ------------ * JTRUE void N003 ( 5, 4) [000086] J------N---- \--* EQ int N001 ( 3, 2) [000235] ------------ +--* LCL_VAR int V19 tmp8 u:2 (last use) N002 ( 1, 1) [000085] ------------ \--* CNS_INT int 0 ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB10,BB14,BB21} succs={BB16,BB09} ***** BB15 STMT00060 (IL ???... ???) N005 ( 0, 0) [000429] -A------R--- * ASG bool N004 ( 0, 0) [000427] D------N---- +--* LCL_VAR bool V07 loc1 d:13 N003 ( 0, 0) [000428] ------------ \--* PHI bool N001 ( 0, 0) [000462] ------------ pred BB14 +--* PHI_ARG bool V07 loc1 u:11 N002 ( 0, 0) [000459] ------------ pred BB21 \--* PHI_ARG bool V07 loc1 u:12 ***** BB15 STMT00012 (IL 0x0E1...0x0E8) N011 ( 27, 29) [000063] --CXG------- * JTRUE void N010 ( 25, 27) [000062] J-CXG--N---- \--* NE int N008 ( 23, 25) [000060] --CXG------- +--* CAST int <- bool <- int N007 ( 22, 23) [000057] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext N004 ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref N005 ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N009 ( 1, 1) [000061] ------------ \--* CNS_INT int 0 ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} ***** BB17 STMT00031 (IL ???... ???) N011 ( 24, 18) [000151] --CXG------- * JTRUE void N010 ( 22, 16) [000150] J-CXG--N---- \--* NE int N008 ( 20, 14) [000148] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000146] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint N004 ( 1, 1) [000143] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 N005 ( 1, 1) [000144] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 N006 ( 3, 2) [000145] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 N009 ( 1, 1) [000149] ------------ \--* CNS_INT int 0 ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} ***** BB18 STMT00032 (IL 0x068...0x069) N003 ( 5, 4) [000154] -A------R--- * ASG int N002 ( 3, 2) [000153] D------N---- +--* LCL_VAR int V07 loc1 d:7 N001 ( 1, 1) [000152] ------------ \--* CNS_INT int 0 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB11} succs={BB20,BB21} ***** BB19 STMT00017 (IL 0x0B5...0x0B7) N004 ( 7, 6) [000091] ------------ * JTRUE void N003 ( 5, 4) [000090] J------N---- \--* EQ int N001 ( 3, 2) [000088] ------------ +--* LCL_VAR ref V04 arg4 u:1 N002 ( 1, 1) [000089] ------------ \--* CNS_INT ref null ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} ***** BB20 STMT00019 (IL 0x0B9...0x0CA) N005 ( 19, 10) [000101] -ACXG---R--- * ASG ref N004 ( 3, 2) [000100] D------N---- +--* LCL_VAR ref V14 tmp3 d:2 N003 ( 15, 7) [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 N002 ( 1, 1) [000098] ------------ arg0 in rdi \--* CNS_INT long 2 ***** BB20 STMT00020 (IL ???... ???) N011 ( 18, 19) [000107] -A-XG------- * ASG ref N009 ( 16, 17) [000384] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000378] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 N003 ( 5, 4) [000377] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000103] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 N008 ( 6, 5) [000106] a---G--N---- | \--* IND ref N007 ( 4, 3) [000383] -------N---- | \--* ADD byref N005 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 N006 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N010 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 ***** BB20 STMT00021 (IL ???...0x0CF) N011 ( 20, 20) [000112] -A-XG------- * ASG ref N009 ( 16, 17) [000394] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 N003 ( 5, 4) [000387] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000108] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 N008 ( 6, 5) [000111] a---G--N---- | \--* IND ref N007 ( 4, 3) [000393] -------N---- | \--* ADD byref N005 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 N006 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] N010 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) ***** BB20 STMT00052 (IL ???... ???) N003 ( 18, 8) [000261] -AC-----R--- * ASG ref N002 ( 3, 2) [000260] D------N---- +--* LCL_VAR ref V20 tmp9 d:2 N001 ( 14, 5) [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW ***** BB20 STMT00053 (IL ???... ???) N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor N007 ( 21, 14) [000396] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 d:2 N005 ( 17, 11) [000255] --CXG------- | \--* IND ref N004 ( 15, 9) [000254] --CXG--N---- | \--* ADD byref N002 ( 14, 5) [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE N003 ( 1, 4) [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] N010 ( 3, 2) [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 u:2 N012 ( 3, 2) [000102] ------------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 u:2 (last use) N013 ( 1, 4) [000256] ------------ arg2 in rdx \--* CNS_INT int 0x7D2C ***** BB20 STMT00054 (IL ???... ???) N003 ( 5, 4) [000269] IA------R--- * ASG struct (init) N002 ( 3, 2) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 d:2 N001 ( 1, 1) [000268] ------------ \--* CNS_INT int 0 ***** BB20 STMT00055 (IL ???... ???) N003 ( 5, 6) [000273] -A------R--- * ASG ref N002 ( 3, 4) [000272] U------N---- +--* LCL_FLD ref V15 tmp4 ud:2->3[+0] Fseq[TypeParameter] N001 ( 1, 1) [000096] ------------ \--* LCL_VAR ref V02 arg2 u:1 ***** BB20 STMT00056 (IL ???... ???) N003 ( 7, 7) [000277] -A------R--- * ASG ref N002 ( 3, 4) [000276] U------N---- +--* LCL_FLD ref V15 tmp4 ud:3->4[+8] Fseq[DiagnosticInfo] N001 ( 3, 2) [000264] ------------ \--* LCL_VAR ref V20 tmp9 u:2 (last use) ***** BB20 STMT00025 (IL 0x0DA... ???) N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000123] ------------ | \--* ADDR byref N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} ***** BB21 STMT00018 (IL 0x0DF...0x0E0) N003 ( 5, 4) [000094] -A------R--- * ASG int N002 ( 3, 2) [000093] D------N---- +--* LCL_VAR int V07 loc1 d:12 N001 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} ***** BB22 STMT00033 (IL 0x048...0x051) N011 ( 24, 18) [000162] --CXG------- * JTRUE void N010 ( 22, 16) [000161] J-CXG--N---- \--* NE int N008 ( 20, 14) [000159] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000158] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint N004 ( 1, 1) [000155] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 N005 ( 1, 1) [000156] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 N006 ( 3, 2) [000157] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 N009 ( 1, 1) [000160] ------------ \--* CNS_INT int 0 ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} ***** BB23 STMT00034 (IL 0x053...0x054) N003 ( 5, 4) [000165] -A------R--- * ASG int N002 ( 3, 2) [000164] D------N---- +--* LCL_VAR int V07 loc1 d:5 N001 ( 1, 1) [000163] ------------ \--* CNS_INT int 0 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} ***** BB24 STMT00042 (IL 0x008...0x009) N003 ( 5, 4) [000197] -A------R--- * ASG int N002 ( 3, 2) [000196] D------N---- +--* LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000195] ------------ \--* CNS_INT int 1 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} ***** BB25 STMT00035 (IL 0x019...0x01B) N004 ( 7, 6) [000169] ------------ * JTRUE void N003 ( 5, 4) [000168] J------N---- \--* EQ int N001 ( 3, 2) [000166] ------------ +--* LCL_VAR ref V04 arg4 u:1 N002 ( 1, 1) [000167] ------------ \--* CNS_INT ref null ------------ BB26 [01D..03E), preds={BB25} succs={BB27} ***** BB26 STMT00037 (IL 0x01D...0x02E) N005 ( 19, 10) [000179] -ACXG---R--- * ASG ref N004 ( 3, 2) [000178] D------N---- +--* LCL_VAR ref V16 tmp5 d:2 N003 ( 15, 7) [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 N002 ( 1, 1) [000176] ------------ arg0 in rdi \--* CNS_INT long 1 ***** BB26 STMT00038 (IL ???... ???) N011 ( 18, 19) [000185] -A-XG------- * ASG ref N009 ( 16, 17) [000298] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000292] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000182] ------------ | | +--* CNS_INT int 0 N003 ( 5, 4) [000291] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000181] ------------ | | \--* LCL_VAR ref V16 tmp5 u:2 N008 ( 6, 5) [000184] a---G--N---- | \--* IND ref N007 ( 4, 3) [000297] -------N---- | \--* ADD byref N005 ( 3, 2) [000289] ------------ | +--* LCL_VAR ref V16 tmp5 u:2 N006 ( 1, 1) [000296] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N010 ( 1, 1) [000183] ------------ \--* LCL_VAR ref V03 arg3 u:1 ***** BB26 STMT00043 (IL ???... ???) N003 ( 18, 8) [000216] -AC-----R--- * ASG ref N002 ( 3, 2) [000215] D------N---- +--* LCL_VAR ref V18 tmp7 d:2 N001 ( 14, 5) [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW ***** BB26 STMT00044 (IL ???... ???) N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor N007 ( 21, 14) [000300] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 d:2 N005 ( 17, 11) [000210] --CXG------- | \--* IND ref N004 ( 15, 9) [000209] --CXG--N---- | \--* ADD byref N002 ( 14, 5) [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE N003 ( 1, 4) [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] N010 ( 3, 2) [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 u:2 N012 ( 3, 2) [000180] ------------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 u:2 (last use) N013 ( 1, 4) [000211] ------------ arg2 in rdx \--* CNS_INT int 0x7AA4 ***** BB26 STMT00040 (IL ???... ???) N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor N004 ( 3, 3) [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 N005 ( 1, 1) [000174] ------------ arg1 in rsi +--* LCL_VAR ref V02 arg2 u:1 N006 ( 3, 2) [000219] ------------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 u:2 (last use) ***** BB26 STMT00041 (IL 0x039... ???) N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} ***** BB27 STMT00036 (IL 0x03E...0x03F) N003 ( 5, 4) [000172] -A------R--- * ASG int N002 ( 3, 2) [000171] D------N---- +--* LCL_VAR int V07 loc1 d:3 N001 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} ***** BB28 STMT00029 (IL 0x080...0x081) N003 ( 5, 4) [000142] -A------R--- * ASG int N002 ( 3, 2) [000141] D------N---- +--* LCL_VAR int V07 loc1 d:9 N001 ( 1, 1) [000140] ------------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Early Value Propagation *************** Starting PHASE Do value numbering *************** In fgValueNumber() Memory Initial Value in BB01 is: $85 The SSA definition for ByrefExposed (#1) at start of BB01 is $85 {InitVal($46)} The SSA definition for GcHeap (#1) at start of BB01 is $85 {InitVal($46)} ***** BB01, STMT00001(before) N008 ( 28, 25) [000006] --CXG------- * JTRUE void N007 ( 26, 23) [000200] J-CXG--N---- \--* EQ int N005 ( 24, 21) [000198] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind N003 ( 1, 1) [000000] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 N004 ( 3, 10) [000279] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N006 ( 1, 1) [000199] ------------ \--* CNS_INT int 4 N001 [000280] ARGPLACE => $140 {140} N002 [000281] ARGPLACE => $180 {180} N003 [000000] LCL_VAR V03 arg3 u:1 => $83 {InitVal($43)} N004 [000279] CNS_INT(h) 0xd1ffab1e ftn => $1c0 {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000281] updated to $83 {InitVal($43)} fgCurMemoryVN[GcHeap] assigned for CALL at [000198] to VN: $141. N005 [000198] CALLV stub => $200 {200} N006 [000199] CNS_INT 4 => $44 {IntCns 4} N007 [000200] EQ => $280 {EQ($200, $44)} ***** BB01, STMT00001(after) N008 ( 28, 25) [000006] --CXG------- * JTRUE void N007 ( 26, 23) [000200] J-CXG--N---- \--* EQ int $280 N005 ( 24, 21) [000198] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 N003 ( 1, 1) [000000] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N004 ( 3, 10) [000279] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 N006 ( 1, 1) [000199] ------------ \--* CNS_INT int 4 $44 finish(BB01). Succ(BB02). Not yet completed. All preds complete, adding to allDone. Succ(BB24). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#2) at start of BB24 is $240 {240} The SSA definition for GcHeap (#3) at start of BB24 is $141 {141} ***** BB24, STMT00042(before) N003 ( 5, 4) [000197] -A------R--- * ASG int N002 ( 3, 2) [000196] D------N---- +--* LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000195] ------------ \--* CNS_INT int 1 N001 [000195] CNS_INT 1 => $41 {IntCns 1} N002 [000196] LCL_VAR V06 loc0 d:2 => $41 {IntCns 1} N003 [000197] ASG => $41 {IntCns 1} ***** BB24, STMT00042(after) N003 ( 5, 4) [000197] -A------R--- * ASG int $41 N002 ( 3, 2) [000196] D------N---- +--* LCL_VAR int V06 loc0 d:2 $41 N001 ( 1, 1) [000195] ------------ \--* CNS_INT int 1 $41 finish(BB24). Succ(BB08). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#2) at start of BB02 is $240 {240} The SSA definition for GcHeap (#3) at start of BB02 is $141 {141} ***** BB02, STMT00002(before) N003 ( 5, 4) [000009] -A------R--- * ASG int N002 ( 3, 2) [000008] D------N---- +--* LCL_VAR int V07 loc1 d:2 N001 ( 1, 1) [000007] ------------ \--* CNS_INT int 1 N001 [000007] CNS_INT 1 => $41 {IntCns 1} N002 [000008] LCL_VAR V07 loc1 d:2 => $41 {IntCns 1} N003 [000009] ASG => $41 {IntCns 1} ***** BB02, STMT00002(after) N003 ( 5, 4) [000009] -A------R--- * ASG int $41 N002 ( 3, 2) [000008] D------N---- +--* LCL_VAR int V07 loc1 d:2 $41 N001 ( 1, 1) [000007] ------------ \--* CNS_INT int 1 $41 --------- ***** BB02, STMT00004(before) N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 N001 [000287] ARGPLACE => $203 {203} N002 [000285] ARGPLACE => $142 {142} N003 [000286] ARGPLACE => $181 {181} N004 [000010] LCL_VAR V03 arg3 u:1 => $83 {InitVal($43)} N005 [000284] CNS_INT(h) 0xd1ffab1e ftn => $1c1 {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000286] updated to $83 {InitVal($43)} fgCurMemoryVN[GcHeap] assigned for CALL at [000202] to VN: $143. N006 [000202] CALLV stub => $204 {204} VNForCastOper(byte) is $47 N007 [000203] CAST => $281 {Cast($204, $47)} VN of ARGPLACE tree [000287] updated to $281 {Cast($204, $47)} fgCurMemoryVN[GcHeap] assigned for CALL at [000204] to VN: $144. N008 [000204] CALL r2r_ind => $205 {205} VNForCastOper(bool) is $44 N009 [000205] CAST => $282 {Cast($205, $44)} N010 [000014] CNS_INT 0 => $40 {IntCns 0} N011 [000015] NE => $283 {NE($282, $40)} ***** BB02, STMT00004(after) N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int $283 N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 finish(BB02). Succ(BB03). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB25). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#4) at start of BB25 is $242 {242} The SSA definition for GcHeap (#5) at start of BB25 is $144 {144} ***** BB25, STMT00035(before) N004 ( 7, 6) [000169] ------------ * JTRUE void N003 ( 5, 4) [000168] J------N---- \--* EQ int N001 ( 3, 2) [000166] ------------ +--* LCL_VAR ref V04 arg4 u:1 N002 ( 1, 1) [000167] ------------ \--* CNS_INT ref null N001 [000166] LCL_VAR V04 arg4 u:1 => $84 {InitVal($44)} N002 [000167] CNS_INT null => $VN.Null N003 [000168] EQ => $284 {EQ($84, $0)} ***** BB25, STMT00035(after) N004 ( 7, 6) [000169] ------------ * JTRUE void N003 ( 5, 4) [000168] J------N---- \--* EQ int $284 N001 ( 3, 2) [000166] ------------ +--* LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000167] ------------ \--* CNS_INT ref null $VN.Null finish(BB25). Succ(BB26). Not yet completed. All preds complete, adding to allDone. Succ(BB27). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB26 is $242 {242} The SSA definition for GcHeap (#5) at start of BB26 is $144 {144} ***** BB26, STMT00037(before) N005 ( 19, 10) [000179] -ACXG---R--- * ASG ref N004 ( 3, 2) [000178] D------N---- +--* LCL_VAR ref V16 tmp5 d:2 N003 ( 15, 7) [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 N002 ( 1, 1) [000176] ------------ arg0 in rdi \--* CNS_INT long 1 N001 [000288] ARGPLACE => $182 {182} N002 [000176] CNS_INT 1 => $2c0 {LngCns: 1} VN of ARGPLACE tree [000288] updated to $2c0 {LngCns: 1} N003 [000177] CALL help r2r_ind => $342 {norm=$380 {JitReadyToRunNewArr($1c2, $2c0, $145)}, exc=$341 {NewArrOverflowExc($2c0)}} N004 [000178] LCL_VAR V16 tmp5 d:2 => $380 {JitReadyToRunNewArr($1c2, $2c0, $145)} N005 [000179] ASG => $342 {norm=$380 {JitReadyToRunNewArr($1c2, $2c0, $145)}, exc=$341 {NewArrOverflowExc($2c0)}} ***** BB26, STMT00037(after) N005 ( 19, 10) [000179] -ACXG---R--- * ASG ref $342 N004 ( 3, 2) [000178] D------N---- +--* LCL_VAR ref V16 tmp5 d:2 $380 N003 ( 15, 7) [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 N002 ( 1, 1) [000176] ------------ arg0 in rdi \--* CNS_INT long 1 $2c0 --------- ***** BB26, STMT00038(before) N011 ( 18, 19) [000185] -A-XG------- * ASG ref N009 ( 16, 17) [000298] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000292] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000182] ------------ | | +--* CNS_INT int 0 N003 ( 5, 4) [000291] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000181] ------------ | | \--* LCL_VAR ref V16 tmp5 u:2 N008 ( 6, 5) [000184] a---G--N---- | \--* IND ref N007 ( 4, 3) [000297] -------N---- | \--* ADD byref N005 ( 3, 2) [000289] ------------ | +--* LCL_VAR ref V16 tmp5 u:2 N006 ( 1, 1) [000296] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N010 ( 1, 1) [000183] ------------ \--* LCL_VAR ref V03 arg3 u:1 N001 [000182] CNS_INT 0 => $40 {IntCns 0} N002 [000181] LCL_VAR V16 tmp5 u:2 => $380 {JitReadyToRunNewArr($1c2, $2c0, $145)} N003 [000291] ARR_LENGTH => $285 {norm=$3c0 {ARR_LENGTH($380)}, exc=$343 {NullPtrExc($380)}} N004 [000292] ARR_BOUNDS_CHECK_Rng => $348 {norm=$3 {3}, exc=$347( {NullPtrExc($380)}, {IndexOutOfRangeExc($40, $3c0)})} N005 [000289] LCL_VAR V16 tmp5 u:2 => $380 {JitReadyToRunNewArr($1c2, $2c0, $145)} N006 [000296] CNS_INT 16 Fseq[#FirstElem] => $2c1 {LngCns: 16} N007 [000297] ADD => $400 {ADD($2c1, $380)} VNForHandle(arrElemType: ref) is $1c3 Relabeled IND_ARR_INDEX address node [000297] with l:$440: {PtrToArrElem($1c3, $380, $2c2, $0)} N009 [000298] COMMA => $348 {norm=$3 {3}, exc=$347( {NullPtrExc($380)}, {IndexOutOfRangeExc($40, $3c0)})} N010 [000183] LCL_VAR V03 arg3 u:1 => $83 {InitVal($43)} Tree [000185] assigns to an array element: VNForMapSelect($144, $1c3):ref returns $349 {$144[$1c3]} VNForMapSelect($349, $380):ref returns $34a {$349[$380]} VNForMapSelect($34a, $2c2):ref returns $34b {$34a[$2c2]} VNForMapStore($34a, $2c2, $83):ref returns $381 {$34a[$2c2 := $83]} VNForMapStore($349, $380, $381):ref returns $382 {$349[$380 := $381]} hAtArrType $349 is MapSelect(curGcHeap($144), ref[]). hAtArrTypeAtArr $34a is MapSelect(hAtArrType($349), arr=$380) hAtArrTypeAtArrAtInx $34b is MapSelect(hAtArrTypeAtArr($34a), inx=$2c2):ref newValAtInd $83 is {InitVal($43)} newValAtArr $381 is {$34a[$2c2 := $83]} newValAtArrType $382 is {$349[$380 := $381]} VNForMapStore($144, $1c3, $382):ref returns $383 {$144[$1c3 := $382]} fgCurMemoryVN[GcHeap] assigned for ArrIndexAssign (case 1) at [000185] to VN: $383. N011 [000185] ASG => $VN.Void ***** BB26, STMT00038(after) N011 ( 18, 19) [000185] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000298] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000292] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $348 N001 ( 1, 1) [000182] ------------ | | +--* CNS_INT int 0 $40 N003 ( 5, 4) [000291] ---X-------- | | \--* ARR_LENGTH int $285 N002 ( 3, 2) [000181] ------------ | | \--* LCL_VAR ref V16 tmp5 u:2 $380 N008 ( 6, 5) [000184] a---G--N---- | \--* IND ref $83 N007 ( 4, 3) [000297] -------N---- | \--* ADD byref $440 N005 ( 3, 2) [000289] ------------ | +--* LCL_VAR ref V16 tmp5 u:2 $380 N006 ( 1, 1) [000296] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N010 ( 1, 1) [000183] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 --------- ***** BB26, STMT00043(before) N003 ( 18, 8) [000216] -AC-----R--- * ASG ref N002 ( 3, 2) [000215] D------N---- +--* LCL_VAR ref V18 tmp7 d:2 N001 ( 14, 5) [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW N001 [000214] CALL help r2r_ind => $34c {JitReadyToRunNew($1c4, $147)} N002 [000215] LCL_VAR V18 tmp7 d:2 => $34c {JitReadyToRunNew($1c4, $147)} N003 [000216] ASG => $34c {JitReadyToRunNew($1c4, $147)} ***** BB26, STMT00043(after) N003 ( 18, 8) [000216] -AC-----R--- * ASG ref $34c N002 ( 3, 2) [000215] D------N---- +--* LCL_VAR ref V18 tmp7 d:2 $34c N001 ( 14, 5) [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c --------- ***** BB26, STMT00044(before) N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor N007 ( 21, 14) [000300] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 d:2 N005 ( 17, 11) [000210] --CXG------- | \--* IND ref N004 ( 15, 9) [000209] --CXG--N---- | \--* ADD byref N002 ( 14, 5) [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE N003 ( 1, 4) [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] N010 ( 3, 2) [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 u:2 N012 ( 3, 2) [000180] ------------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 u:2 (last use) N013 ( 1, 4) [000211] ------------ arg2 in rdx \--* CNS_INT int 0x7AA4 N001 [000302] ARGPLACE => $149 {149} N002 [000207] CALL help r2r_ind => $401 {norm=$c1 {ReadyToRunStaticBase($1c5)}, exc=$340 {HelperMultipleExc()}} N003 [000208] CNS_INT 0x418 Fseq[Instance] => $48 {IntCns 0x418} N004 [000209] ADD => $403 {norm=$402 {ADD($48, $c1)}, exc=$340 {HelperMultipleExc()}} VNApplySelectors: VNForHandle(Instance) is $1c6, fieldType is ref AX2: $1c6 != $1c3 ==> select([$383]store($144, $1c3, $382), $1c6) ==> select($144, $1c6). VNForMapSelect($383, $1c6):ref returns $34d {$144[$1c6]} VNForMapSelect($34d, $c1):ref returns $34e {$34d[$c1]} N005 [000210] IND => N006 [000299] LCL_VAR V24 tmp13 d:2 => N007 [000300] ASG => N008 [000304] ARGPLACE => $206 {206} N009 [000303] ARGPLACE => $14c {14c} N010 [000301] LCL_VAR V24 tmp13 u:2 (last use) => N011 [000217] LCL_VAR V18 tmp7 u:2 => $34c {JitReadyToRunNew($1c4, $147)} N012 [000180] LCL_VAR V16 tmp5 u:2 (last use) => $380 {JitReadyToRunNewArr($1c2, $2c0, $145)} N013 [000211] CNS_INT 0x7AA4 => $49 {IntCns 0x7AA4} VN of ARGPLACE tree [000304] updated to VN of ARGPLACE tree [000303] updated to $49 {IntCns 0x7AA4} fgCurMemoryVN[GcHeap] assigned for CALL at [000218] to VN: $14d. N014 [000218] CALL r2r_ind => $VN.Void ***** BB26, STMT00044(after) N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N007 ( 21, 14) [000300] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 d:2 N005 ( 17, 11) [000210] --CXG------- | \--* IND ref N004 ( 15, 9) [000209] --CXG--N---- | \--* ADD byref $403 N002 ( 14, 5) [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] $48 N010 ( 3, 2) [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 u:2 $34c N012 ( 3, 2) [000180] ------------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 u:2 (last use) $380 N013 ( 1, 4) [000211] ------------ arg2 in rdx \--* CNS_INT int 0x7AA4 $49 --------- ***** BB26, STMT00040(before) N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor N004 ( 3, 3) [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 N005 ( 1, 1) [000174] ------------ arg1 in rsi +--* LCL_VAR ref V02 arg2 u:1 N006 ( 3, 2) [000219] ------------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 u:2 (last use) N001 [000305] ARGPLACE => $480 {480} N002 [000306] ARGPLACE => $14e {14e} N003 [000307] ARGPLACE => $14f {14f} N004 [000189] LCL_VAR_ADDR V17 tmp6 => $481 {481} N005 [000174] LCL_VAR V02 arg2 u:1 => $82 {InitVal($42)} N006 [000219] LCL_VAR V18 tmp7 u:2 (last use) => $34c {JitReadyToRunNew($1c4, $147)} VN of ARGPLACE tree [000306] updated to $481 {481} VN of ARGPLACE tree [000307] updated to $82 {InitVal($42)} fgCurMemoryVN[GcHeap] assigned for CALL at [000190] to VN: $150. N007 [000190] CALL r2r_ind => $VN.Void ***** BB26, STMT00040(after) N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void N004 ( 3, 3) [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 $481 N005 ( 1, 1) [000174] ------------ arg1 in rsi +--* LCL_VAR ref V02 arg2 u:1 $82 N006 ( 3, 2) [000219] ------------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 u:2 (last use) $34c --------- ***** BB26, STMT00041(before) N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N001 [000309] ARGPLACE => $151 {151} N002 [000310] ARGPLACE => $183 {183} N003 [000191] LCL_VAR V17 tmp6 => $4c0 {ByrefExposedLoad($4b, $404, $245)} N004 [000193] ADDR => $482 {482} N005 [000194] OBJ => N006 [000173] LCL_VAR V04 arg4 u:1 => $84 {InitVal($44)} N007 [000308] CNS_INT(h) 0xd1ffab1e ftn => $1c7 {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000310] updated to $84 {InitVal($44)} fgCurMemoryVN[GcHeap] assigned for CALL at [000192] to VN: $152. N008 [000192] CALLV stub => $VN.Void ***** BB26, STMT00041(after) N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 $4c0 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 finish(BB26). Succ(BB27). Not yet completed. All preds complete, adding to allDone. Building phi application: $4c = SSA# 8. Building phi application: $44 = SSA# 4. Building phi application: $355 = phi($44, $4c). The SSA definition for ByrefExposed (#6) at start of BB27 is $356 {PhiMemoryDef($1c8, $355)} Building phi application: $4d = SSA# 9. Building phi application: $45 = SSA# 5. Building phi application: $357 = phi($45, $4d). The SSA definition for GcHeap (#7) at start of BB27 is $358 {PhiMemoryDef($1c8, $357)} ***** BB27, STMT00036(before) N003 ( 5, 4) [000172] -A------R--- * ASG int N002 ( 3, 2) [000171] D------N---- +--* LCL_VAR int V07 loc1 d:3 N001 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 N001 [000170] CNS_INT 0 => $40 {IntCns 0} N002 [000171] LCL_VAR V07 loc1 d:3 => $40 {IntCns 0} N003 [000172] ASG => $40 {IntCns 0} ***** BB27, STMT00036(after) N003 ( 5, 4) [000172] -A------R--- * ASG int $40 N002 ( 3, 2) [000171] D------N---- +--* LCL_VAR int V07 loc1 d:3 $40 N001 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 $40 finish(BB27). Succ(BB03). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 7/4 to $580 {PhiDef($7, $4, $540)} . Building phi application: $47 = SSA# 6. Building phi application: $44 = SSA# 4. Building phi application: $359 = phi($44, $47). The SSA definition for ByrefExposed (#10) at start of BB03 is $35a {PhiMemoryDef($1c9, $359)} Building phi application: $4e = SSA# 7. Building phi application: $45 = SSA# 5. Building phi application: $35b = phi($45, $4e). The SSA definition for GcHeap (#11) at start of BB03 is $35c {PhiMemoryDef($1c9, $35b)} ***** BB03, STMT00005(before) N009 ( 29, 27) [000022] --CXG------- * JTRUE void N008 ( 27, 25) [000021] J-CXG--N---- \--* NE int N006 ( 25, 23) [000019] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000018] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint N003 ( 1, 1) [000017] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 N004 ( 3, 10) [000312] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000020] ------------ \--* CNS_INT int 0 N001 [000313] ARGPLACE => $153 {153} N002 [000314] ARGPLACE => $184 {184} N003 [000017] LCL_VAR V02 arg2 u:1 => $82 {InitVal($42)} N004 [000312] CNS_INT(h) 0xd1ffab1e ftn => $1ca {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000314] updated to $82 {InitVal($42)} fgCurMemoryVN[GcHeap] assigned for CALL at [000018] to VN: $154. N005 [000018] CALLV stub => $208 {208} VNForCastOper(bool) is $44 N006 [000019] CAST => $286 {Cast($208, $44)} N007 [000020] CNS_INT 0 => $40 {IntCns 0} N008 [000021] NE => $287 {NE($286, $40)} ***** BB03, STMT00005(after) N009 ( 29, 27) [000022] --CXG------- * JTRUE void N008 ( 27, 25) [000021] J-CXG--N---- \--* NE int $287 N006 ( 25, 23) [000019] --CXG------- +--* CAST int <- bool <- int $286 N005 ( 24, 21) [000018] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 N003 ( 1, 1) [000017] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000312] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca N007 ( 1, 1) [000020] ------------ \--* CNS_INT int 0 $40 finish(BB03). Succ(BB04). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB22). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#12) at start of BB22 is $247 {247} The SSA definition for GcHeap (#13) at start of BB22 is $154 {154} ***** BB22, STMT00033(before) N011 ( 24, 18) [000162] --CXG------- * JTRUE void N010 ( 22, 16) [000161] J-CXG--N---- \--* NE int N008 ( 20, 14) [000159] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000158] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint N004 ( 1, 1) [000155] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 N005 ( 1, 1) [000156] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 N006 ( 3, 2) [000157] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 N009 ( 1, 1) [000160] ------------ \--* CNS_INT int 0 N001 [000315] ARGPLACE => $155 {155} N002 [000316] ARGPLACE => $156 {156} N003 [000317] ARGPLACE => $157 {157} N004 [000155] LCL_VAR V02 arg2 u:1 => $82 {InitVal($42)} N005 [000156] LCL_VAR V03 arg3 u:1 => $83 {InitVal($43)} N006 [000157] LCL_VAR V04 arg4 u:1 => $84 {InitVal($44)} VN of ARGPLACE tree [000315] updated to $82 {InitVal($42)} VN of ARGPLACE tree [000316] updated to $83 {InitVal($43)} VN of ARGPLACE tree [000317] updated to $84 {InitVal($44)} fgCurMemoryVN[GcHeap] assigned for CALL at [000158] to VN: $158. N007 [000158] CALL r2r_ind => $209 {209} VNForCastOper(bool) is $44 N008 [000159] CAST => $288 {Cast($209, $44)} N009 [000160] CNS_INT 0 => $40 {IntCns 0} N010 [000161] NE => $289 {NE($288, $40)} ***** BB22, STMT00033(after) N011 ( 24, 18) [000162] --CXG------- * JTRUE void N010 ( 22, 16) [000161] J-CXG--N---- \--* NE int $289 N008 ( 20, 14) [000159] --CXG------- +--* CAST int <- bool <- int $288 N007 ( 19, 12) [000158] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 N004 ( 1, 1) [000155] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000156] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000157] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 $84 N009 ( 1, 1) [000160] ------------ \--* CNS_INT int 0 $40 finish(BB22). Succ(BB23). Not yet completed. All preds complete, adding to allDone. Succ(BB04). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#14) at start of BB23 is $248 {248} The SSA definition for GcHeap (#15) at start of BB23 is $158 {158} ***** BB23, STMT00034(before) N003 ( 5, 4) [000165] -A------R--- * ASG int N002 ( 3, 2) [000164] D------N---- +--* LCL_VAR int V07 loc1 d:5 N001 ( 1, 1) [000163] ------------ \--* CNS_INT int 0 N001 [000163] CNS_INT 0 => $40 {IntCns 0} N002 [000164] LCL_VAR V07 loc1 d:5 => $40 {IntCns 0} N003 [000165] ASG => $40 {IntCns 0} ***** BB23, STMT00034(after) N003 ( 5, 4) [000165] -A------R--- * ASG int $40 N002 ( 3, 2) [000164] D------N---- +--* LCL_VAR int V07 loc1 d:5 $40 N001 ( 1, 1) [000163] ------------ \--* CNS_INT int 0 $40 finish(BB23). Succ(BB04). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 7/6 to $581 {PhiDef($7, $6, $541)} . Building phi application: $4f = SSA# 14. Building phi application: $50 = SSA# 12. Building phi application: $35d = phi($50, $4f). The SSA definition for ByrefExposed (#16) at start of BB04 is $35e {PhiMemoryDef($1cb, $35d)} Building phi application: $4b = SSA# 15. Building phi application: $51 = SSA# 13. Building phi application: $35f = phi($51, $4b). The SSA definition for GcHeap (#17) at start of BB04 is $360 {PhiMemoryDef($1cb, $35f)} ***** BB04, STMT00006(before) N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 N001 [000320] ARGPLACE => $159 {159} N002 [000321] ARGPLACE => $185 {185} N003 [000023] LCL_VAR V02 arg2 u:1 => $82 {InitVal($42)} N004 [000319] CNS_INT(h) 0xd1ffab1e ftn => $1cc {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000321] updated to $82 {InitVal($42)} fgCurMemoryVN[GcHeap] assigned for CALL at [000024] to VN: $15a. N005 [000024] CALLV stub => $20b {20b} VNForCastOper(bool) is $44 N006 [000025] CAST => $28a {Cast($20b, $44)} N007 [000026] CNS_INT 0 => $40 {IntCns 0} N008 [000027] NE => $28b {NE($28a, $40)} ***** BB04, STMT00006(after) N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int $28b N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 $40 finish(BB04). Succ(BB05). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB17). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#18) at start of BB17 is $249 {249} The SSA definition for GcHeap (#19) at start of BB17 is $15a {15a} ***** BB17, STMT00031(before) N011 ( 24, 18) [000151] --CXG------- * JTRUE void N010 ( 22, 16) [000150] J-CXG--N---- \--* NE int N008 ( 20, 14) [000148] --CXG------- +--* CAST int <- bool <- int N007 ( 19, 12) [000146] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint N004 ( 1, 1) [000143] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 N005 ( 1, 1) [000144] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 N006 ( 3, 2) [000145] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 N009 ( 1, 1) [000149] ------------ \--* CNS_INT int 0 N001 [000322] ARGPLACE => $15b {15b} N002 [000323] ARGPLACE => $15c {15c} N003 [000324] ARGPLACE => $15d {15d} N004 [000143] LCL_VAR V02 arg2 u:1 => $82 {InitVal($42)} N005 [000144] LCL_VAR V03 arg3 u:1 => $83 {InitVal($43)} N006 [000145] LCL_VAR V04 arg4 u:1 => $84 {InitVal($44)} VN of ARGPLACE tree [000322] updated to $82 {InitVal($42)} VN of ARGPLACE tree [000323] updated to $83 {InitVal($43)} VN of ARGPLACE tree [000324] updated to $84 {InitVal($44)} fgCurMemoryVN[GcHeap] assigned for CALL at [000146] to VN: $15e. N007 [000146] CALL r2r_ind => $20c {20c} VNForCastOper(bool) is $44 N008 [000148] CAST => $28c {Cast($20c, $44)} N009 [000149] CNS_INT 0 => $40 {IntCns 0} N010 [000150] NE => $28d {NE($28c, $40)} ***** BB17, STMT00031(after) N011 ( 24, 18) [000151] --CXG------- * JTRUE void N010 ( 22, 16) [000150] J-CXG--N---- \--* NE int $28d N008 ( 20, 14) [000148] --CXG------- +--* CAST int <- bool <- int $28c N007 ( 19, 12) [000146] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c N004 ( 1, 1) [000143] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000144] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000145] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 $84 N009 ( 1, 1) [000149] ------------ \--* CNS_INT int 0 $40 finish(BB17). Succ(BB18). Not yet completed. All preds complete, adding to allDone. Succ(BB05). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#20) at start of BB18 is $24a {24a} The SSA definition for GcHeap (#21) at start of BB18 is $15e {15e} ***** BB18, STMT00032(before) N003 ( 5, 4) [000154] -A------R--- * ASG int N002 ( 3, 2) [000153] D------N---- +--* LCL_VAR int V07 loc1 d:7 N001 ( 1, 1) [000152] ------------ \--* CNS_INT int 0 N001 [000152] CNS_INT 0 => $40 {IntCns 0} N002 [000153] LCL_VAR V07 loc1 d:7 => $40 {IntCns 0} N003 [000154] ASG => $40 {IntCns 0} ***** BB18, STMT00032(after) N003 ( 5, 4) [000154] -A------R--- * ASG int $40 N002 ( 3, 2) [000153] D------N---- +--* LCL_VAR int V07 loc1 d:7 $40 N001 ( 1, 1) [000152] ------------ \--* CNS_INT int 0 $40 finish(BB18). Succ(BB05). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 7/8 to $582 {PhiDef($7, $8, $542)} . Building phi application: $52 = SSA# 20. Building phi application: $53 = SSA# 18. Building phi application: $361 = phi($53, $52). The SSA definition for ByrefExposed (#22) at start of BB05 is $362 {PhiMemoryDef($1cd, $361)} Building phi application: $54 = SSA# 21. Building phi application: $55 = SSA# 19. Building phi application: $363 = phi($55, $54). The SSA definition for GcHeap (#23) at start of BB05 is $364 {PhiMemoryDef($1cd, $363)} ***** BB05, STMT00007(before) N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 N001 [000327] ARGPLACE => $15f {15f} N002 [000328] ARGPLACE => $186 {186} N003 [000029] LCL_VAR V02 arg2 u:1 => $82 {InitVal($42)} N004 [000326] CNS_INT(h) 0xd1ffab1e ftn => $1ce {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000328] updated to $82 {InitVal($42)} fgCurMemoryVN[GcHeap] assigned for CALL at [000030] to VN: $160. N005 [000030] CALLV stub => $20e {20e} VNForCastOper(bool) is $44 N006 [000031] CAST => $28e {Cast($20e, $44)} N007 [000032] CNS_INT 0 => $40 {IntCns 0} N008 [000033] NE => $28f {NE($28e, $40)} ***** BB05, STMT00007(after) N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int $28f N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 $40 finish(BB05). Succ(BB06). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB12). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#24) at start of BB12 is $24b {24b} The SSA definition for GcHeap (#25) at start of BB12 is $160 {160} ***** BB12, STMT00028(before) N015 ( 28, 23) [000139] --CXG------- * JTRUE void N014 ( 26, 21) [000138] J-CXG--N---- \--* EQ int N012 ( 24, 19) [000136] --CXG------- +--* CAST int <- bool <- int N011 ( 23, 17) [000135] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint N006 ( 3, 2) [000130] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 (last use) N007 ( 1, 1) [000131] ------------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 u:1 N008 ( 1, 1) [000132] ------------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 u:1 N009 ( 3, 2) [000133] ------------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 u:1 N010 ( 1, 1) [000134] ------------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 u:1 N013 ( 1, 1) [000137] ------------ \--* CNS_INT int 0 N001 [000329] ARGPLACE => $161 {161} N002 [000330] ARGPLACE => $162 {162} N003 [000331] ARGPLACE => $163 {163} N004 [000332] ARGPLACE => $164 {164} N005 [000333] ARGPLACE => $483 {483} N006 [000130] LCL_VAR V00 arg0 u:1 (last use) => $80 {InitVal($40)} N007 [000131] LCL_VAR V02 arg2 u:1 => $82 {InitVal($42)} N008 [000132] LCL_VAR V03 arg3 u:1 => $83 {InitVal($43)} N009 [000133] LCL_VAR V04 arg4 u:1 => $84 {InitVal($44)} N010 [000134] LCL_VAR V05 arg5 u:1 => $c0 {InitVal($45)} VN of ARGPLACE tree [000329] updated to $80 {InitVal($40)} VN of ARGPLACE tree [000330] updated to $82 {InitVal($42)} VN of ARGPLACE tree [000331] updated to $83 {InitVal($43)} VN of ARGPLACE tree [000332] updated to $84 {InitVal($44)} VN of ARGPLACE tree [000333] updated to $c0 {InitVal($45)} fgCurMemoryVN[GcHeap] assigned for CALL at [000135] to VN: $165. N011 [000135] CALL r2r_ind => $20f {20f} VNForCastOper(bool) is $44 N012 [000136] CAST => $290 {Cast($20f, $44)} N013 [000137] CNS_INT 0 => $40 {IntCns 0} N014 [000138] EQ => $291 {EQ($290, $40)} ***** BB12, STMT00028(after) N015 ( 28, 23) [000139] --CXG------- * JTRUE void N014 ( 26, 21) [000138] J-CXG--N---- \--* EQ int $291 N012 ( 24, 19) [000136] --CXG------- +--* CAST int <- bool <- int $290 N011 ( 23, 17) [000135] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f N006 ( 3, 2) [000130] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 (last use) $80 N007 ( 1, 1) [000131] ------------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 u:1 $82 N008 ( 1, 1) [000132] ------------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 u:1 $83 N009 ( 3, 2) [000133] ------------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 u:1 $84 N010 ( 1, 1) [000134] ------------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 u:1 $c0 N013 ( 1, 1) [000137] ------------ \--* CNS_INT int 0 $40 finish(BB12). Succ(BB13). Not yet completed. All preds complete, adding to allDone. Succ(BB28). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#26) at start of BB28 is $24c {24c} The SSA definition for GcHeap (#27) at start of BB28 is $165 {165} ***** BB28, STMT00029(before) N003 ( 5, 4) [000142] -A------R--- * ASG int N002 ( 3, 2) [000141] D------N---- +--* LCL_VAR int V07 loc1 d:9 N001 ( 1, 1) [000140] ------------ \--* CNS_INT int 0 N001 [000140] CNS_INT 0 => $40 {IntCns 0} N002 [000141] LCL_VAR V07 loc1 d:9 => $40 {IntCns 0} N003 [000142] ASG => $40 {IntCns 0} ***** BB28, STMT00029(after) N003 ( 5, 4) [000142] -A------R--- * ASG int $40 N002 ( 3, 2) [000141] D------N---- +--* LCL_VAR int V07 loc1 d:9 $40 N001 ( 1, 1) [000140] ------------ \--* CNS_INT int 0 $40 finish(BB28). Succ(BB06). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#26) at start of BB13 is $24c {24c} The SSA definition for GcHeap (#27) at start of BB13 is $165 {165} finish(BB13). Succ(BB06). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 7/10 to $583 {PhiDef($7, $a, $543)} . Building phi application: $56 = SSA# 26. Building phi application: $57 = SSA# 24. Building phi application: $365 = phi($57, $56). The SSA definition for ByrefExposed (#28) at start of BB06 is $366 {PhiMemoryDef($1cf, $365)} Building phi application: $58 = SSA# 27. Building phi application: $59 = SSA# 25. Building phi application: $367 = phi($59, $58). The SSA definition for GcHeap (#29) at start of BB06 is $368 {PhiMemoryDef($1cf, $367)} ***** BB06, STMT00009(before) N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 N001 [000335] ARGPLACE => $166 {166} N002 [000336] ARGPLACE => $484 {484} N003 [000035] LCL_VAR V02 arg2 u:1 => $82 {InitVal($42)} N004 [000036] LCL_VAR V05 arg5 u:1 => $c0 {InitVal($45)} VN of ARGPLACE tree [000336] updated to $82 {InitVal($42)} fgCurMemoryVN[GcHeap] assigned for CALL at [000037] to VN: $168. N005 [000037] CALL r2r_ind => $167 {167} fgCurMemoryVN[ByrefExposed] assigned for local assign at [000042] to VN: $24e. N007 [000042] ASG => $167 {167} ***** BB06, STMT00009(after) N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref $167 N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 --------- ***** BB06, STMT00010(before) N009 ( 26, 26) [000050] -ACXG---R--- * ASG struct (copy) N008 ( 3, 2) [000048] D------N---- +--* LCL_VAR struct(AX) V12 tmp1 N007 ( 22, 23) [000045] --CXG------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA N004 ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long N003 ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref N005 ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 N001 [000338] ARGPLACE => $485 {485} N002 [000337] ARGPLACE => $187 {187} N003 [000046] CNS_INT(h) 0xd1ffab1e class => $1d0 {Hnd const: 0x00000000D1FFAB1E} N004 [000047] IND => N005 [000043] LCL_VAR V09 loc3 ref V09.array (offs=0x00) -> V23 tmp12 => $4c2 {ByrefExposedLoad($4b, $405, $24e)} N006 [000044] ADDR => $486 {486} VN of ARGPLACE tree [000337] updated to $486 {486} fgCurMemoryVN[GcHeap] assigned for CALL at [000045] to VN: $169. N007 [000045] CALL r2r_ind => $501 {501} fgCurMemoryVN[ByrefExposed] assigned for COPYBLK - address-exposed local at [000050] to VN: $250. N009 [000050] ASG => $VN.Void ***** BB06, STMT00010(after) N009 ( 26, 26) [000050] -ACXG---R--- * ASG struct (copy) $VN.Void N008 ( 3, 2) [000048] D------N---- +--* LCL_VAR struct(AX) V12 tmp1 N007 ( 22, 23) [000045] --CXG------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 N004 ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long N003 ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class $1d0 N006 ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref $486 N005 ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 $4c2 --------- ***** BB06, STMT00011(before) N016 ( 18, 15) [000355] -A-XG------- * COMMA void N009 ( 10, 8) [000348] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref N001 ( 3, 2) [000341] -------N---- | | \--* LCL_VAR struct(AX) V12 tmp1 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] N015 ( 8, 7) [000354] -A-XG---R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] ---X-------- \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] N001 [000341] LCL_VAR V12 tmp1 => $4c3 {ByrefExposedLoad($4b, $406, $250)} N002 [000340] ADDR => $487 {487} N003 [000342] LCL_VAR V25 tmp14 d:2 => $487 {487} N004 [000343] ASG => $487 {487} N005 [000345] LCL_VAR V25 tmp14 u:2 => $487 {487} N006 [000346] IND => fgCurMemoryVN[ByrefExposed] assigned for local assign at [000347] to VN: $251. N008 [000347] ASG => N009 [000348] COMMA => N010 [000350] LCL_VAR V25 tmp14 u:2 (last use) => $487 {487} N011 [000351] CNS_INT 8 Fseq[_index] => $2c3 {LngCns: 8} N012 [000352] ADD => $407 {ADD($2c3, $487)} N013 [000353] IND => fgCurMemoryVN[ByrefExposed] assigned for local assign at [000354] to VN: $252. N015 [000354] ASG => N016 [000355] COMMA => ***** BB06, STMT00011(after) N016 ( 18, 15) [000355] -A-XG------- * COMMA void N009 ( 10, 8) [000348] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref $487 N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref $487 N001 ( 3, 2) [000341] -------N---- | | \--* LCL_VAR struct(AX) V12 tmp1 $4c3 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 N015 ( 8, 7) [000354] -A-XG---R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] ---X-------- \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 --------- ***** BB06, STMT00057(before) N011 ( 27, 29) [000419] --CXG------- * JTRUE void N010 ( 25, 27) [000409] J-CXG--N---- \--* NE int N008 ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int N007 ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext N004 ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref N005 ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N009 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 N001 [000412] ARGPLACE => $489 {489} N002 [000413] ARGPLACE => $189 {189} N003 [000415] CNS_INT(h) 0xd1ffab1e class => $1d1 {Hnd const: 0x00000000D1FFAB1E} N004 [000414] IND => N005 [000417] LCL_VAR V08 loc2 ref V08._array (offs=0x00) -> V21 tmp10 int V08._index (offs=0x08) -> V22 tmp11 => $4c4 {ByrefExposedLoad($4b, $408, $252)} N006 [000416] ADDR => $48a {48a} VN of ARGPLACE tree [000413] updated to $48a {48a} fgCurMemoryVN[GcHeap] assigned for CALL at [000411] to VN: $16b. N007 [000411] CALL r2r_ind => $212 {212} VNForCastOper(bool) is $44 N008 [000410] CAST => $294 {Cast($212, $44)} N009 [000418] CNS_INT 0 => $40 {IntCns 0} N010 [000409] NE => $295 {NE($294, $40)} ***** BB06, STMT00057(after) N011 ( 27, 29) [000419] --CXG------- * JTRUE void N010 ( 25, 27) [000409] J-CXG--N---- \--* NE int $295 N008 ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int $294 N007 ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $212 N004 ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref $48a N005 ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c4 N009 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 $40 finish(BB06). Succ(BB07). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB09). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. SSA PHI definition: set VN of local 7/14 to $584 {PhiDef($7, $e, $544)} . The SSA definition for ByrefExposed (#30) at start of BB07 is $253 {253} The SSA definition for GcHeap (#31) at start of BB07 is $16b {16b} ***** BB07, STMT00026(before) N003 ( 7, 5) [000127] -A------R--- * ASG int N002 ( 3, 2) [000126] D------N---- +--* LCL_VAR int V06 loc0 d:4 N001 ( 3, 2) [000125] ------------ \--* LCL_VAR int V07 loc1 u:14 (last use) N001 [000125] LCL_VAR V07 loc1 u:14 (last use) => $584 {PhiDef($7, $e, $544)} N002 [000126] LCL_VAR V06 loc0 d:4 => $584 {PhiDef($7, $e, $544)} N003 [000127] ASG => $584 {PhiDef($7, $e, $544)} ***** BB07, STMT00026(after) N003 ( 7, 5) [000127] -A------R--- * ASG int $584 N002 ( 3, 2) [000126] D------N---- +--* LCL_VAR int V06 loc0 d:4 $584 N001 ( 3, 2) [000125] ------------ \--* LCL_VAR int V07 loc1 u:14 (last use) $584 finish(BB07). Succ(BB08). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 6/3 to $585 {PhiDef($6, $3, $545)} . The SSA definition for ByrefExposed (#2) at start of BB08 is $240 {240} The SSA definition for GcHeap (#3) at start of BB08 is $141 {141} ***** BB08, STMT00027(before) N002 ( 4, 3) [000129] ------------ * RETURN int N001 ( 3, 2) [000128] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) N001 [000128] LCL_VAR V06 loc0 u:3 (last use) => $585 {PhiDef($6, $3, $545)} N002 [000129] RETURN => $214 {214} ***** BB08, STMT00027(after) N002 ( 4, 3) [000129] ------------ * RETURN int $214 N001 ( 3, 2) [000128] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) $585 finish(BB08). SSA PHI definition: set VN of local 7/11 to $586 {PhiDef($7, $b, $544)} . Building phi application: $5c = SSA# 44. Building phi application: $5d = SSA# 30. Building phi application: $36c = phi($5d, $5c). The SSA definition for ByrefExposed (#32) at start of BB09 is $36d {PhiMemoryDef($1d2, $36c)} Building phi application: $5e = SSA# 45. Building phi application: $5f = SSA# 31. Building phi application: $36e = phi($5f, $5e). The SSA definition for GcHeap (#33) at start of BB09 is $36f {PhiMemoryDef($1d2, $36e)} ***** BB09, STMT00013(before) N017 ( 59, 54) [000073] -ACXG---R--- * ASG struct (copy) N016 ( 3, 2) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 d:2 N015 ( 55, 51) [000070] --CXG------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA N009 ( 26, 26) [000360] -ACXG---R-L- this SETUP +--* ASG ref N008 ( 3, 2) [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 d:2 N007 ( 22, 23) [000066] --CXG------- | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current N004 ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref N005 ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N012 ( 3, 2) [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 u:2 (last use) N013 ( 3, 2) [000069] ------------ arg2 in rsi +--* LCL_VAR ref V01 arg1 u:1 N014 ( 3, 10) [000356] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N001 [000358] ARGPLACE => $48b {48b} N002 [000357] ARGPLACE => $18b {18b} N003 [000067] CNS_INT(h) 0xd1ffab1e class => $1d1 {Hnd const: 0x00000000D1FFAB1E} N004 [000068] IND => N005 [000064] LCL_VAR V08 loc2 ref V08._array (offs=0x00) -> V21 tmp10 int V08._index (offs=0x08) -> V22 tmp11 => $4c5 {ByrefExposedLoad($4b, $408, $36d)} N006 [000065] ADDR => $48c {48c} VN of ARGPLACE tree [000357] updated to $48c {48c} fgCurMemoryVN[GcHeap] assigned for CALL at [000066] to VN: $16d. N007 [000066] CALL r2r_ind => $16c {16c} N008 [000359] LCL_VAR V26 tmp15 d:2 => $16c {16c} N009 [000360] ASG => $16c {16c} N010 [000363] ARGPLACE => $18d {18d} N011 [000362] ARGPLACE => $16f {16f} N012 [000361] LCL_VAR V26 tmp15 u:2 (last use) => $16c {16c} N013 [000069] LCL_VAR V01 arg1 u:1 => $81 {InitVal($41)} N014 [000356] CNS_INT(h) 0xd1ffab1e ftn => $1d3 {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000363] updated to $16c {16c} VN of ARGPLACE tree [000362] updated to $1d3 {Hnd const: 0x00000000D1FFAB1E} fgCurMemoryVN[GcHeap] assigned for CALL at [000070] to VN: $170. N015 [000070] CALLV stub => $502 {502} Tree [000073] assigned VN to local var V13/2: new uniq $505 {505} N017 [000073] ASG => $VN.Void ***** BB09, STMT00013(after) N017 ( 59, 54) [000073] -ACXG---R--- * ASG struct (copy) $VN.Void N016 ( 3, 2) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 d:2 N015 ( 55, 51) [000070] --CXG------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 N009 ( 26, 26) [000360] -ACXG---R-L- this SETUP +--* ASG ref $16c N008 ( 3, 2) [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 d:2 $16c N007 ( 22, 23) [000066] --CXG------- | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c N004 ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref $48c N005 ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c5 N012 ( 3, 2) [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 u:2 (last use) $16c N013 ( 3, 2) [000069] ------------ arg2 in rsi +--* LCL_VAR ref V01 arg1 u:1 $81 N014 ( 3, 10) [000356] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 --------- ***** BB09, STMT00014(before) N003 ( 7, 7) [000078] -A------R--- * ASG ref N002 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V10 loc4 d:2 N001 ( 3, 4) [000076] ------------ \--* LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) VNApplySelectors: VNForHandle(Type) is $1d4, fieldType is ref VNForMapSelect($505, $1d4):ref returns $370 {$505[$1d4]} VNApplySelectors: VNForHandle(Type) is $1d4, fieldType is ref VNForMapSelect($505, $1d4):ref returns $370 {$505[$1d4]} N001 [000076] LCL_FLD V13 tmp2 u:2[+0] Fseq[Type] (last use) => $370 {$505[$1d4]} N002 [000077] LCL_VAR V10 loc4 d:2 => $370 {$505[$1d4]} N003 [000078] ASG => $370 {$505[$1d4]} ***** BB09, STMT00014(after) N003 ( 7, 7) [000078] -A------R--- * ASG ref $370 N002 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V10 loc4 d:2 $370 N001 ( 3, 4) [000076] ------------ \--* LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) $370 --------- ***** BB09, STMT00046(before) N008 ( 30, 26) [000228] --CXG------- * JTRUE void N007 ( 28, 24) [000249] J-CXG--N---- \--* NE int N005 ( 26, 22) [000247] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind N003 ( 3, 2) [000080] ------------ this in rdi | +--* LCL_VAR ref V10 loc4 u:2 N004 ( 3, 10) [000365] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N006 ( 1, 1) [000248] ------------ \--* CNS_INT int 4 N001 [000366] ARGPLACE => $172 {172} N002 [000367] ARGPLACE => $18e {18e} N003 [000080] LCL_VAR V10 loc4 u:2 => $370 {$505[$1d4]} N004 [000365] CNS_INT(h) 0xd1ffab1e ftn => $1c0 {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000367] updated to $370 {$505[$1d4]} fgCurMemoryVN[GcHeap] assigned for CALL at [000247] to VN: $173. N005 [000247] CALLV stub => $215 {215} N006 [000248] CNS_INT 4 => $44 {IntCns 4} N007 [000249] NE => $296 {NE($215, $44)} ***** BB09, STMT00046(after) N008 ( 30, 26) [000228] --CXG------- * JTRUE void N007 ( 28, 24) [000249] J-CXG--N---- \--* NE int $296 N005 ( 26, 22) [000247] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 N003 ( 3, 2) [000080] ------------ this in rdi | +--* LCL_VAR ref V10 loc4 u:2 $370 N004 ( 3, 10) [000365] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 N006 ( 1, 1) [000248] ------------ \--* CNS_INT int 4 $44 finish(BB09). Succ(BB10). Not yet completed. All preds complete, adding to allDone. Succ(BB14). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#34) at start of BB14 is $256 {256} The SSA definition for GcHeap (#35) at start of BB14 is $173 {173} ***** BB14, STMT00048(before) N010 ( 24, 17) [000234] -ACXG---R--- * ASG bool N009 ( 3, 2) [000233] D------N---- +--* LCL_VAR int V19 tmp8 d:2 N008 ( 20, 14) [000232] --CXG------- \--* CAST int <- bool <- int N007 ( 19, 12) [000230] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion N004 ( 1, 1) [000079] ------------ arg0 in rdi +--* LCL_VAR ref V03 arg3 u:1 N005 ( 3, 2) [000229] ------------ arg1 in rsi +--* LCL_VAR ref V10 loc4 u:2 N006 ( 1, 1) [000081] ------------ arg2 in rdx \--* LCL_VAR byref V05 arg5 u:1 N001 [000371] ARGPLACE => $174 {174} N002 [000372] ARGPLACE => $175 {175} N003 [000373] ARGPLACE => $48d {48d} N004 [000079] LCL_VAR V03 arg3 u:1 => $83 {InitVal($43)} N005 [000229] LCL_VAR V10 loc4 u:2 => $370 {$505[$1d4]} N006 [000081] LCL_VAR V05 arg5 u:1 => $c0 {InitVal($45)} VN of ARGPLACE tree [000371] updated to $83 {InitVal($43)} VN of ARGPLACE tree [000372] updated to $370 {$505[$1d4]} VN of ARGPLACE tree [000373] updated to $c0 {InitVal($45)} fgCurMemoryVN[GcHeap] assigned for CALL at [000230] to VN: $176. N007 [000230] CALL r2r_ind => $216 {216} VNForCastOper(bool) is $44 N008 [000232] CAST => $297 {Cast($216, $44)} N009 [000233] LCL_VAR V19 tmp8 d:2 => $297 {Cast($216, $44)} N010 [000234] ASG => $297 {Cast($216, $44)} ***** BB14, STMT00048(after) N010 ( 24, 17) [000234] -ACXG---R--- * ASG bool $297 N009 ( 3, 2) [000233] D------N---- +--* LCL_VAR int V19 tmp8 d:2 $297 N008 ( 20, 14) [000232] --CXG------- \--* CAST int <- bool <- int $297 N007 ( 19, 12) [000230] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 N004 ( 1, 1) [000079] ------------ arg0 in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 2) [000229] ------------ arg1 in rsi +--* LCL_VAR ref V10 loc4 u:2 $370 N006 ( 1, 1) [000081] ------------ arg2 in rdx \--* LCL_VAR byref V05 arg5 u:1 $c0 --------- ***** BB14, STMT00016(before) N004 ( 7, 6) [000087] ------------ * JTRUE void N003 ( 5, 4) [000086] J------N---- \--* EQ int N001 ( 3, 2) [000235] ------------ +--* LCL_VAR int V19 tmp8 u:2 (last use) N002 ( 1, 1) [000085] ------------ \--* CNS_INT int 0 N001 [000235] LCL_VAR V19 tmp8 u:2 (last use) => $297 {Cast($216, $44)} N002 [000085] CNS_INT 0 => $40 {IntCns 0} N003 [000086] EQ => $298 {EQ($297, $40)} ***** BB14, STMT00016(after) N004 ( 7, 6) [000087] ------------ * JTRUE void N003 ( 5, 4) [000086] J------N---- \--* EQ int $298 N001 ( 3, 2) [000235] ------------ +--* LCL_VAR int V19 tmp8 u:2 (last use) $297 N002 ( 1, 1) [000085] ------------ \--* CNS_INT int 0 $40 finish(BB14). Succ(BB15). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB19). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#34) at start of BB10 is $256 {256} The SSA definition for GcHeap (#35) at start of BB10 is $173 {173} ***** BB10, STMT00049(before) N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics N003 ( 3, 2) [000237] ------------ arg0 in rdi +--* LCL_VAR ref V10 loc4 u:2 N004 ( 1, 1) [000238] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 N001 [000368] ARGPLACE => $177 {177} N002 [000369] ARGPLACE => $48e {48e} N003 [000237] LCL_VAR V10 loc4 u:2 => $370 {$505[$1d4]} N004 [000238] LCL_VAR V05 arg5 u:1 => $c0 {InitVal($45)} VN of ARGPLACE tree [000368] updated to $370 {$505[$1d4]} VN of ARGPLACE tree [000369] updated to $c0 {InitVal($45)} fgCurMemoryVN[GcHeap] assigned for CALL at [000239] to VN: $178. N005 [000239] CALL r2r_ind => $VN.Void ***** BB10, STMT00049(after) N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void N003 ( 3, 2) [000237] ------------ arg0 in rdi +--* LCL_VAR ref V10 loc4 u:2 $370 N004 ( 1, 1) [000238] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 --------- ***** BB10, STMT00050(before) N003 ( 5, 4) [000242] -A------R--- * ASG bool N002 ( 3, 2) [000241] D------N---- +--* LCL_VAR int V19 tmp8 d:3 N001 ( 1, 1) [000240] ------------ \--* CNS_INT int 0 N001 [000240] CNS_INT 0 => $40 {IntCns 0} N002 [000241] LCL_VAR V19 tmp8 d:3 => $40 {IntCns 0} N003 [000242] ASG => $40 {IntCns 0} ***** BB10, STMT00050(after) N003 ( 5, 4) [000242] -A------R--- * ASG bool $40 N002 ( 3, 2) [000241] D------N---- +--* LCL_VAR int V19 tmp8 d:3 $40 N001 ( 1, 1) [000240] ------------ \--* CNS_INT int 0 $40 --------- ***** BB10, STMT00058(before) N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] J------N---- \--* NE int N001 ( 3, 2) [000422] ------------ +--* LCL_VAR int V19 tmp8 u:3 (last use) N002 ( 1, 1) [000423] ------------ \--* CNS_INT int 0 N001 [000422] LCL_VAR V19 tmp8 u:3 (last use) => $40 {IntCns 0} N002 [000423] CNS_INT 0 => $40 {IntCns 0} N003 [000421] NE => $40 {IntCns 0} ***** BB10, STMT00058(after) N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] J------N---- \--* NE int $40 N001 ( 3, 2) [000422] ------------ +--* LCL_VAR int V19 tmp8 u:3 (last use) $40 N002 ( 1, 1) [000423] ------------ \--* CNS_INT int 0 $40 finish(BB10). Succ(BB11). Not yet completed. All preds complete, adding to allDone. Succ(BB15). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#48) at start of BB11 is $258 {258} The SSA definition for GcHeap (#49) at start of BB11 is $178 {178} finish(BB11). Succ(BB19). Not yet completed. All preds complete, adding to allDone. Building phi application: $60 = SSA# 48. Building phi application: $61 = SSA# 46. Building phi application: $371 = phi($61, $60). The SSA definition for ByrefExposed (#36) at start of BB19 is $372 {PhiMemoryDef($1d5, $371)} Building phi application: $62 = SSA# 49. Building phi application: $63 = SSA# 47. Building phi application: $373 = phi($63, $62). The SSA definition for GcHeap (#37) at start of BB19 is $374 {PhiMemoryDef($1d5, $373)} ***** BB19, STMT00017(before) N004 ( 7, 6) [000091] ------------ * JTRUE void N003 ( 5, 4) [000090] J------N---- \--* EQ int N001 ( 3, 2) [000088] ------------ +--* LCL_VAR ref V04 arg4 u:1 N002 ( 1, 1) [000089] ------------ \--* CNS_INT ref null N001 [000088] LCL_VAR V04 arg4 u:1 => $84 {InitVal($44)} N002 [000089] CNS_INT null => $VN.Null N003 [000090] EQ => $284 {EQ($84, $0)} ***** BB19, STMT00017(after) N004 ( 7, 6) [000091] ------------ * JTRUE void N003 ( 5, 4) [000090] J------N---- \--* EQ int $284 N001 ( 3, 2) [000088] ------------ +--* LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000089] ------------ \--* CNS_INT ref null $VN.Null finish(BB19). Succ(BB20). Not yet completed. All preds complete, adding to allDone. Succ(BB21). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#36) at start of BB20 is $372 {PhiMemoryDef($1d5, $371)} The SSA definition for GcHeap (#37) at start of BB20 is $374 {PhiMemoryDef($1d5, $373)} ***** BB20, STMT00019(before) N005 ( 19, 10) [000101] -ACXG---R--- * ASG ref N004 ( 3, 2) [000100] D------N---- +--* LCL_VAR ref V14 tmp3 d:2 N003 ( 15, 7) [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 N002 ( 1, 1) [000098] ------------ arg0 in rdi \--* CNS_INT long 2 N001 [000374] ARGPLACE => $18f {18f} N002 [000098] CNS_INT 2 => $2c4 {LngCns: 2} VN of ARGPLACE tree [000374] updated to $2c4 {LngCns: 2} N003 [000099] CALL help r2r_ind => $376 {norm=$385 {JitReadyToRunNewArr($1c2, $2c4, $179)}, exc=$375 {NewArrOverflowExc($2c4)}} N004 [000100] LCL_VAR V14 tmp3 d:2 => $385 {JitReadyToRunNewArr($1c2, $2c4, $179)} N005 [000101] ASG => $376 {norm=$385 {JitReadyToRunNewArr($1c2, $2c4, $179)}, exc=$375 {NewArrOverflowExc($2c4)}} ***** BB20, STMT00019(after) N005 ( 19, 10) [000101] -ACXG---R--- * ASG ref $376 N004 ( 3, 2) [000100] D------N---- +--* LCL_VAR ref V14 tmp3 d:2 $385 N003 ( 15, 7) [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 N002 ( 1, 1) [000098] ------------ arg0 in rdi \--* CNS_INT long 2 $2c4 --------- ***** BB20, STMT00020(before) N011 ( 18, 19) [000107] -A-XG------- * ASG ref N009 ( 16, 17) [000384] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000378] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 N003 ( 5, 4) [000377] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000103] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 N008 ( 6, 5) [000106] a---G--N---- | \--* IND ref N007 ( 4, 3) [000383] -------N---- | \--* ADD byref N005 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 N006 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N010 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 N001 [000104] CNS_INT 0 => $40 {IntCns 0} N002 [000103] LCL_VAR V14 tmp3 u:2 => $385 {JitReadyToRunNewArr($1c2, $2c4, $179)} N003 [000377] ARR_LENGTH => $299 {norm=$3c1 {ARR_LENGTH($385)}, exc=$377 {NullPtrExc($385)}} N004 [000378] ARR_BOUNDS_CHECK_Rng => $37c {norm=$3 {3}, exc=$37b( {NullPtrExc($385)}, {IndexOutOfRangeExc($40, $3c1)})} N005 [000375] LCL_VAR V14 tmp3 u:2 => $385 {JitReadyToRunNewArr($1c2, $2c4, $179)} N006 [000382] CNS_INT 16 Fseq[#FirstElem] => $2c1 {LngCns: 16} N007 [000383] ADD => $409 {ADD($2c1, $385)} VNForHandle(arrElemType: ref) is $1c3 Relabeled IND_ARR_INDEX address node [000383] with l:$441: {PtrToArrElem($1c3, $385, $2c2, $0)} N009 [000384] COMMA => $37c {norm=$3 {3}, exc=$37b( {NullPtrExc($385)}, {IndexOutOfRangeExc($40, $3c1)})} N010 [000105] LCL_VAR V03 arg3 u:1 => $83 {InitVal($43)} Tree [000107] assigns to an array element: VNForMapSelect($374, $1c3):ref returns $37f {$374[$1c3]} VNForMapSelect($37f, $385):ref returns $640 {$37f[$385]} VNForMapSelect($640, $2c2):ref returns $641 {$640[$2c2]} VNForMapStore($640, $2c2, $83):ref returns $386 {$640[$2c2 := $83]} VNForMapStore($37f, $385, $386):ref returns $387 {$37f[$385 := $386]} hAtArrType $37f is MapSelect(curGcHeap($374), ref[]). hAtArrTypeAtArr $640 is MapSelect(hAtArrType($37f), arr=$385) hAtArrTypeAtArrAtInx $641 is MapSelect(hAtArrTypeAtArr($640), inx=$2c2):ref newValAtInd $83 is {InitVal($43)} newValAtArr $386 is {$640[$2c2 := $83]} newValAtArrType $387 is {$37f[$385 := $386]} VNForMapStore($374, $1c3, $387):ref returns $388 {$374[$1c3 := $387]} fgCurMemoryVN[GcHeap] assigned for ArrIndexAssign (case 1) at [000107] to VN: $388. N011 [000107] ASG => $VN.Void ***** BB20, STMT00020(after) N011 ( 18, 19) [000107] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000384] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000378] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 $40 N003 ( 5, 4) [000377] ---X-------- | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 $385 N008 ( 6, 5) [000106] a---G--N---- | \--* IND ref $83 N007 ( 4, 3) [000383] -------N---- | \--* ADD byref $441 N005 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N010 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 --------- ***** BB20, STMT00021(before) N011 ( 20, 20) [000112] -A-XG------- * ASG ref N009 ( 16, 17) [000394] ---XG--N---- +--* COMMA ref N004 ( 10, 12) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 N003 ( 5, 4) [000387] ---X-------- | | \--* ARR_LENGTH int N002 ( 3, 2) [000108] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 N008 ( 6, 5) [000111] a---G--N---- | \--* IND ref N007 ( 4, 3) [000393] -------N---- | \--* ADD byref N005 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 N006 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] N010 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) N001 [000109] CNS_INT 1 => $41 {IntCns 1} N002 [000108] LCL_VAR V14 tmp3 u:2 => $385 {JitReadyToRunNewArr($1c2, $2c4, $179)} N003 [000387] ARR_LENGTH => $299 {norm=$3c1 {ARR_LENGTH($385)}, exc=$377 {NullPtrExc($385)}} N004 [000388] ARR_BOUNDS_CHECK_Rng => $645 {norm=$3 {3}, exc=$644( {NullPtrExc($385)}, {IndexOutOfRangeExc($41, $3c1)})} N005 [000385] LCL_VAR V14 tmp3 u:2 => $385 {JitReadyToRunNewArr($1c2, $2c4, $179)} N006 [000392] CNS_INT 24 Fseq[#ConstantIndex, #FirstElem] => $2c5 {LngCns: 24} N007 [000393] ADD => $40a {ADD($2c5, $385)} VNForHandle(arrElemType: ref) is $1c3 Relabeled IND_ARR_INDEX address node [000393] with l:$442: {PtrToArrElem($1c3, $385, $2c0, $0)} N009 [000394] COMMA => $645 {norm=$3 {3}, exc=$644( {NullPtrExc($385)}, {IndexOutOfRangeExc($41, $3c1)})} N010 [000110] LCL_VAR V10 loc4 u:2 (last use) => $370 {$505[$1d4]} Tree [000112] assigns to an array element: AX1: select([$374]store($388, $1c3, $387), $1c3) ==> $387. VNForMapSelect($388, $1c3):ref returns $387 {$37f[$385 := $386]} AX1: select([$37f]store($387, $385, $386), $385) ==> $386. VNForMapSelect($387, $385):ref returns $386 {$640[$2c2 := $83]} AX2: $2c0 != $2c2 ==> select([$386]store($640, $2c2, $83), $2c0) ==> select($640, $2c0). VNForMapSelect($386, $2c0):ref returns $646 {$640[$2c0]} VNForMapStore($386, $2c0, $370):ref returns $389 {$386[$2c0 := $370]} VNForMapStore($387, $385, $389):ref returns $38a {$387[$385 := $389]} hAtArrType $387 is MapSelect(curGcHeap($388), ref[]). hAtArrTypeAtArr $386 is MapSelect(hAtArrType($387), arr=$385) hAtArrTypeAtArrAtInx $646 is MapSelect(hAtArrTypeAtArr($386), inx=$2c0):ref newValAtInd $370 is {$505[$1d4]} newValAtArr $389 is {$386[$2c0 := $370]} newValAtArrType $38a is {$387[$385 := $389]} VNForMapStore($388, $1c3, $38a):ref returns $38b {$388[$1c3 := $38a]} fgCurMemoryVN[GcHeap] assigned for ArrIndexAssign (case 1) at [000112] to VN: $38b. N011 [000112] ASG => $VN.Void ***** BB20, STMT00021(after) N011 ( 20, 20) [000112] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000394] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 $41 N003 ( 5, 4) [000387] ---X-------- | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000108] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 $385 N008 ( 6, 5) [000111] a---G--N---- | \--* IND ref $370 N007 ( 4, 3) [000393] -------N---- | \--* ADD byref $442 N005 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 N010 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) $370 --------- ***** BB20, STMT00052(before) N003 ( 18, 8) [000261] -AC-----R--- * ASG ref N002 ( 3, 2) [000260] D------N---- +--* LCL_VAR ref V20 tmp9 d:2 N001 ( 14, 5) [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW N001 [000259] CALL help r2r_ind => $647 {JitReadyToRunNew($1c4, $17b)} N002 [000260] LCL_VAR V20 tmp9 d:2 => $647 {JitReadyToRunNew($1c4, $17b)} N003 [000261] ASG => $647 {JitReadyToRunNew($1c4, $17b)} ***** BB20, STMT00052(after) N003 ( 18, 8) [000261] -AC-----R--- * ASG ref $647 N002 ( 3, 2) [000260] D------N---- +--* LCL_VAR ref V20 tmp9 d:2 $647 N001 ( 14, 5) [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 --------- ***** BB20, STMT00053(before) N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor N007 ( 21, 14) [000396] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 d:2 N005 ( 17, 11) [000255] --CXG------- | \--* IND ref N004 ( 15, 9) [000254] --CXG--N---- | \--* ADD byref N002 ( 14, 5) [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE N003 ( 1, 4) [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] N010 ( 3, 2) [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 u:2 N012 ( 3, 2) [000102] ------------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 u:2 (last use) N013 ( 1, 4) [000256] ------------ arg2 in rdx \--* CNS_INT int 0x7D2C N001 [000398] ARGPLACE => $17d {17d} N002 [000252] CALL help r2r_ind => $401 {norm=$c1 {ReadyToRunStaticBase($1c5)}, exc=$340 {HelperMultipleExc()}} N003 [000253] CNS_INT 0x418 Fseq[Instance] => $48 {IntCns 0x418} N004 [000254] ADD => $403 {norm=$402 {ADD($48, $c1)}, exc=$340 {HelperMultipleExc()}} VNApplySelectors: VNForHandle(Instance) is $1c6, fieldType is ref AX2: $1c6 != $1c3 ==> select([$38b]store($388, $1c3, $38a), $1c6) ==> select($388, $1c6). AX2: $1c6 != $1c3 ==> select([$388]store($374, $1c3, $387), $1c6) ==> select($374, $1c6). VNForMapSelect($38b, $1c6):ref returns $64a {$374[$1c6]} VNForMapSelect($64a, $c1):ref returns $64b {$64a[$c1]} N005 [000255] IND => N006 [000395] LCL_VAR V27 tmp16 d:2 => N007 [000396] ASG => N008 [000400] ARGPLACE => $219 {219} N009 [000399] ARGPLACE => $680 {680} N010 [000397] LCL_VAR V27 tmp16 u:2 (last use) => N011 [000262] LCL_VAR V20 tmp9 u:2 => $647 {JitReadyToRunNew($1c4, $17b)} N012 [000102] LCL_VAR V14 tmp3 u:2 (last use) => $385 {JitReadyToRunNewArr($1c2, $2c4, $179)} N013 [000256] CNS_INT 0x7D2C => $64 {IntCns 0x7D2C} VN of ARGPLACE tree [000400] updated to VN of ARGPLACE tree [000399] updated to $64 {IntCns 0x7D2C} fgCurMemoryVN[GcHeap] assigned for CALL at [000263] to VN: $681. N014 [000263] CALL r2r_ind => $VN.Void ***** BB20, STMT00053(after) N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N007 ( 21, 14) [000396] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 d:2 N005 ( 17, 11) [000255] --CXG------- | \--* IND ref N004 ( 15, 9) [000254] --CXG--N---- | \--* ADD byref $403 N002 ( 14, 5) [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] $48 N010 ( 3, 2) [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 u:2 $647 N012 ( 3, 2) [000102] ------------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 u:2 (last use) $385 N013 ( 1, 4) [000256] ------------ arg2 in rdx \--* CNS_INT int 0x7D2C $64 --------- ***** BB20, STMT00054(before) N003 ( 5, 4) [000269] IA------R--- * ASG struct (init) N002 ( 3, 2) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 d:2 N001 ( 1, 1) [000268] ------------ \--* CNS_INT int 0 N001 [000268] CNS_INT 0 => $40 {IntCns 0} N003 [000269] ASG V15/2 => $VN.ZeroMap N003 [000269] ASG => $VN.Void ***** BB20, STMT00054(after) N003 ( 5, 4) [000269] IA------R--- * ASG struct (init) $VN.Void N002 ( 3, 2) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 d:2 N001 ( 1, 1) [000268] ------------ \--* CNS_INT int 0 $40 --------- ***** BB20, STMT00055(before) N003 ( 5, 6) [000273] -A------R--- * ASG ref N002 ( 3, 4) [000272] U------N---- +--* LCL_FLD ref V15 tmp4 ud:2->3[+0] Fseq[TypeParameter] N001 ( 1, 1) [000096] ------------ \--* LCL_VAR ref V02 arg2 u:1 N001 [000096] LCL_VAR V02 arg2 u:1 => $82 {InitVal($42)} VNApplySelectors: VNForHandle(TypeParameter) is $1d6, fieldType is ref VNForMapSelect($1, $1d6):ref returns $VN.Null VNApplySelectors: VNForHandle(TypeParameter) is $1d6, fieldType is ref VNForMapSelect($1, $1d6):ref returns $VN.Null N002 [000272] LCL_FLD V15 tmp4 ud:2->3[+0] Fseq[TypeParameter] => $VN.Null VNApplySelectorsAssign: VNForHandle(TypeParameter) is $1d6, fieldType is ref VNForMapStore($1, $1d6, $82):ref returns $38c {$VN.ZeroMap[$1d6 := $82]} VNApplySelectorsAssign: VNForHandle(TypeParameter) is $1d6, fieldType is ref VNForMapStore($1, $1d6, $82):ref returns $38c {$VN.ZeroMap[$1d6 := $82]} N002 [000272] LCL_FLD V15 tmp4 ud:2->3[+0] Fseq[TypeParameter] => $38c {$VN.ZeroMap[$1d6 := $82]} N003 [000273] ASG => $82 {InitVal($42)} ***** BB20, STMT00055(after) N003 ( 5, 6) [000273] -A------R--- * ASG ref $82 N002 ( 3, 4) [000272] U------N---- +--* LCL_FLD ref V15 tmp4 ud:2->3[+0] Fseq[TypeParameter] $38c N001 ( 1, 1) [000096] ------------ \--* LCL_VAR ref V02 arg2 u:1 $82 --------- ***** BB20, STMT00056(before) N003 ( 7, 7) [000277] -A------R--- * ASG ref N002 ( 3, 4) [000276] U------N---- +--* LCL_FLD ref V15 tmp4 ud:3->4[+8] Fseq[DiagnosticInfo] N001 ( 3, 2) [000264] ------------ \--* LCL_VAR ref V20 tmp9 u:2 (last use) N001 [000264] LCL_VAR V20 tmp9 u:2 (last use) => $647 {JitReadyToRunNew($1c4, $17b)} VNApplySelectors: VNForHandle(DiagnosticInfo) is $1d7, fieldType is ref AX2: $1d7 != $1d6 ==> select([$38c]store($1, $1d6, $82), $1d7) ==> select($1, $1d7). VNForMapSelect($38c, $1d7):ref returns $VN.Null VNApplySelectors: VNForHandle(DiagnosticInfo) is $1d7, fieldType is ref AX2: $1d7 != $1d6 ==> select([$38c]store($1, $1d6, $82), $1d7) ==> select($1, $1d7). VNForMapSelect($38c, $1d7):ref returns $VN.Null N002 [000276] LCL_FLD V15 tmp4 ud:3->4[+8] Fseq[DiagnosticInfo] => $VN.Null VNApplySelectorsAssign: VNForHandle(DiagnosticInfo) is $1d7, fieldType is ref VNForMapStore($38c, $1d7, $647):ref returns $38d {$38c[$1d7 := $647]} VNApplySelectorsAssign: VNForHandle(DiagnosticInfo) is $1d7, fieldType is ref VNForMapStore($38c, $1d7, $647):ref returns $38d {$38c[$1d7 := $647]} N002 [000276] LCL_FLD V15 tmp4 ud:3->4[+8] Fseq[DiagnosticInfo] => $38d {$38c[$1d7 := $647]} N003 [000277] ASG => $647 {JitReadyToRunNew($1c4, $17b)} ***** BB20, STMT00056(after) N003 ( 7, 7) [000277] -A------R--- * ASG ref $647 N002 ( 3, 4) [000276] U------N---- +--* LCL_FLD ref V15 tmp4 ud:3->4[+8] Fseq[DiagnosticInfo] $38d N001 ( 3, 2) [000264] ------------ \--* LCL_VAR ref V20 tmp9 u:2 (last use) $647 --------- ***** BB20, STMT00025(before) N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000123] ------------ | \--* ADDR byref N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 N001 [000402] ARGPLACE => $682 {682} N002 [000403] ARGPLACE => $190 {190} N003 [000121] LCL_VAR V15 tmp4 u:4 (last use) => $38d {$38c[$1d7 := $647]} N004 [000123] ADDR => $40b {PtrToLoc($4b, $0)} N005 [000124] OBJ => $507 {507} N006 [000095] LCL_VAR V04 arg4 u:1 => $84 {InitVal($44)} N007 [000401] CNS_INT(h) 0xd1ffab1e ftn => $1c7 {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000403] updated to $84 {InitVal($44)} fgCurMemoryVN[GcHeap] assigned for CALL at [000122] to VN: $683. N008 [000122] CALLV stub => $VN.Void ***** BB20, STMT00025(after) N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct $507 N004 ( 3, 3) [000123] ------------ | \--* ADDR byref $40b N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 finish(BB20). Succ(BB21). Not yet completed. All preds complete, adding to allDone. Building phi application: $65 = SSA# 40. Building phi application: $66 = SSA# 36. Building phi application: $650 = phi($66, $65). The SSA definition for ByrefExposed (#38) at start of BB21 is $651 {PhiMemoryDef($1d8, $650)} Building phi application: $67 = SSA# 41. Building phi application: $68 = SSA# 37. Building phi application: $652 = phi($68, $67). The SSA definition for GcHeap (#39) at start of BB21 is $653 {PhiMemoryDef($1d8, $652)} ***** BB21, STMT00018(before) N003 ( 5, 4) [000094] -A------R--- * ASG int N002 ( 3, 2) [000093] D------N---- +--* LCL_VAR int V07 loc1 d:12 N001 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 N001 [000092] CNS_INT 0 => $40 {IntCns 0} N002 [000093] LCL_VAR V07 loc1 d:12 => $40 {IntCns 0} N003 [000094] ASG => $40 {IntCns 0} ***** BB21, STMT00018(after) N003 ( 5, 4) [000094] -A------R--- * ASG int $40 N002 ( 3, 2) [000093] D------N---- +--* LCL_VAR int V07 loc1 d:12 $40 N001 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 $40 finish(BB21). Succ(BB15). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 7/13 to $587 {PhiDef($7, $d, $546)} . Building phi application: $60 = SSA# 48. Building phi application: $61 = SSA# 46. Building phi application: $371 = phi($61, $60). Building phi application: $6a = SSA# 38. Building phi application: $654 = phi($6a, $371). The SSA definition for ByrefExposed (#42) at start of BB15 is $655 {PhiMemoryDef($1d9, $654)} Building phi application: $62 = SSA# 49. Building phi application: $63 = SSA# 47. Building phi application: $373 = phi($63, $62). Building phi application: $6b = SSA# 39. Building phi application: $656 = phi($6b, $373). The SSA definition for GcHeap (#43) at start of BB15 is $657 {PhiMemoryDef($1d9, $656)} ***** BB15, STMT00012(before) N011 ( 27, 29) [000063] --CXG------- * JTRUE void N010 ( 25, 27) [000062] J-CXG--N---- \--* NE int N008 ( 23, 25) [000060] --CXG------- +--* CAST int <- bool <- int N007 ( 22, 23) [000057] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext N004 ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref N005 ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 N009 ( 1, 1) [000061] ------------ \--* CNS_INT int 0 N001 [000406] ARGPLACE => $48f {48f} N002 [000405] ARGPLACE => $191 {191} N003 [000058] CNS_INT(h) 0xd1ffab1e class => $1d1 {Hnd const: 0x00000000D1FFAB1E} N004 [000059] IND => N005 [000055] LCL_VAR V08 loc2 ref V08._array (offs=0x00) -> V21 tmp10 int V08._index (offs=0x08) -> V22 tmp11 => $4c6 {ByrefExposedLoad($4b, $408, $655)} N006 [000056] ADDR => $490 {490} VN of ARGPLACE tree [000405] updated to $490 {490} fgCurMemoryVN[GcHeap] assigned for CALL at [000057] to VN: $684. N007 [000057] CALL r2r_ind => $21b {21b} VNForCastOper(bool) is $44 N008 [000060] CAST => $29a {Cast($21b, $44)} N009 [000061] CNS_INT 0 => $40 {IntCns 0} N010 [000062] NE => $29b {NE($29a, $40)} ***** BB15, STMT00012(after) N011 ( 27, 29) [000063] --CXG------- * JTRUE void N010 ( 25, 27) [000062] J-CXG--N---- \--* NE int $29b N008 ( 23, 25) [000060] --CXG------- +--* CAST int <- bool <- int $29a N007 ( 22, 23) [000057] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $21b N004 ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref $490 N005 ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c6 N009 ( 1, 1) [000061] ------------ \--* CNS_INT int 0 $40 finish(BB15). Succ(BB16). Not yet completed. All preds complete, adding to allDone. Succ(BB09). The SSA definition for ByrefExposed (#44) at start of BB16 is $25d {25d} The SSA definition for GcHeap (#45) at start of BB16 is $684 {684} finish(BB16). Succ(BB07). *************** Finishing PHASE Do value numbering *************** Starting PHASE Hoist loop code *************** Finishing PHASE Hoist loop code *************** Starting PHASE VN based copy prop *************** In optVnCopyProp() Copy Assertion for BB01 curSsaName stack: { } Copy Assertion for BB24 curSsaName stack: { 3-[000000]:V03 } Live vars: {} => {V06} Copy Assertion for BB08 curSsaName stack: { 3-[000000]:V03 } Live vars: {V06} => {} Copy Assertion for BB02 curSsaName stack: { 3-[000000]:V03 } Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V07} Copy Assertion for BB25 curSsaName stack: { 3-[000000]:V03 7-[000008]:V07 } Copy Assertion for BB27 curSsaName stack: { 3-[000000]:V03 4-[000166]:V04 7-[000008]:V07 } Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V07} Copy Assertion for BB26 curSsaName stack: { 3-[000000]:V03 4-[000166]:V04 7-[000008]:V07 } Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V16} Live vars: {V00 V01 V02 V03 V04 V05 V16} => {V00 V01 V02 V03 V04 V05 V16 V18} Live vars: {V00 V01 V02 V03 V04 V05 V16 V18} => {V00 V01 V02 V03 V04 V05 V16 V18 V24} Live vars: {V00 V01 V02 V03 V04 V05 V16 V18 V24} => {V00 V01 V02 V03 V04 V05 V16 V18} Live vars: {V00 V01 V02 V03 V04 V05 V16 V18} => {V00 V01 V02 V03 V04 V05 V18} Live vars: {V00 V01 V02 V03 V04 V05 V18} => {V00 V01 V02 V03 V04 V05} Copy Assertion for BB03 curSsaName stack: { 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 7-[000008]:V07 } Copy Assertion for BB22 curSsaName stack: { 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 7-[000445]:V07 } Copy Assertion for BB23 curSsaName stack: { 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 7-[000445]:V07 } Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V07} Copy Assertion for BB04 curSsaName stack: { 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 7-[000445]:V07 } Copy Assertion for BB17 curSsaName stack: { 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 7-[000442]:V07 } Copy Assertion for BB18 curSsaName stack: { 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 7-[000442]:V07 } Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V07} Copy Assertion for BB05 curSsaName stack: { 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 7-[000442]:V07 } Copy Assertion for BB12 curSsaName stack: { 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 7-[000439]:V07 } Live vars: {V00 V01 V02 V03 V04 V05 V07} => {V01 V02 V03 V04 V05 V07} Copy Assertion for BB28 curSsaName stack: { 0-[000130]:V00 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000439]:V07 } Live vars: {V01 V02 V03 V04 V05} => {V01 V02 V03 V04 V05 V07} Copy Assertion for BB13 curSsaName stack: { 0-[000130]:V00 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000439]:V07 } Copy Assertion for BB06 curSsaName stack: { 0-[000130]:V00 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000439]:V07 } Live vars: {V01 V02 V03 V04 V05 V07} => {V01 V02 V03 V04 V05 V07 V25} Live vars: {V01 V02 V03 V04 V05 V07 V25} => {V01 V02 V03 V04 V05 V07} Copy Assertion for BB09 curSsaName stack: { 0-[000130]:V00 25-[000342]:V25 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000436]:V07 } Live vars: {V01 V02 V03 V04 V05 V07} => {V01 V02 V03 V04 V05 V07 V26} Live vars: {V01 V02 V03 V04 V05 V07 V26} => {V01 V02 V03 V04 V05 V07} Live vars: {V01 V02 V03 V04 V05 V07} => {V01 V02 V03 V04 V05 V07 V13} Live vars: {V01 V02 V03 V04 V05 V07 V13} => {V01 V02 V03 V04 V05 V07} Live vars: {V01 V02 V03 V04 V05 V07} => {V01 V02 V03 V04 V05 V07 V10} Copy Assertion for BB19 curSsaName stack: { 0-[000130]:V00 1-[000069]:V01 25-[000342]:V25 2-[000174]:V02 26-[000359]:V26 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000433]:V07 10-[000077]:V10 13-[000071]:V13 } Copy Assertion for BB21 curSsaName stack: { 0-[000130]:V00 1-[000069]:V01 25-[000342]:V25 2-[000174]:V02 26-[000359]:V26 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000433]:V07 10-[000077]:V10 13-[000071]:V13 } Live vars: {V01 V02 V03 V04 V05} => {V01 V02 V03 V04 V05 V07} Copy Assertion for BB20 curSsaName stack: { 0-[000130]:V00 1-[000069]:V01 25-[000342]:V25 2-[000174]:V02 26-[000359]:V26 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000433]:V07 10-[000077]:V10 13-[000071]:V13 } Live vars: {V01 V02 V03 V04 V05 V10} => {V01 V02 V03 V04 V05 V10 V14} Live vars: {V01 V02 V03 V04 V05 V10 V14} => {V01 V02 V03 V04 V05 V14} Live vars: {V01 V02 V03 V04 V05 V14} => {V01 V02 V03 V04 V05 V14 V20} Live vars: {V01 V02 V03 V04 V05 V14 V20} => {V01 V02 V03 V04 V05 V14 V20 V27} Live vars: {V01 V02 V03 V04 V05 V14 V20 V27} => {V01 V02 V03 V04 V05 V14 V20} Live vars: {V01 V02 V03 V04 V05 V14 V20} => {V01 V02 V03 V04 V05 V20} Live vars: {V01 V02 V03 V04 V05 V20} => {V01 V02 V03 V04 V05 V15 V20} Live vars: {V01 V02 V03 V04 V05 V15 V20} => {V01 V02 V03 V04 V05 V15} Live vars: {V01 V02 V03 V04 V05 V15} => {V01 V02 V03 V04 V05} Copy Assertion for BB15 curSsaName stack: { 0-[000130]:V00 1-[000069]:V01 25-[000342]:V25 2-[000174]:V02 26-[000359]:V26 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000433]:V07 10-[000077]:V10 13-[000071]:V13 } Copy Assertion for BB16 curSsaName stack: { 0-[000130]:V00 1-[000069]:V01 25-[000342]:V25 2-[000174]:V02 26-[000359]:V26 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000427]:V07 10-[000077]:V10 13-[000071]:V13 } Copy Assertion for BB14 curSsaName stack: { 0-[000130]:V00 1-[000069]:V01 25-[000342]:V25 2-[000174]:V02 26-[000359]:V26 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000433]:V07 10-[000077]:V10 13-[000071]:V13 } Live vars: {V01 V02 V03 V04 V05 V07 V10} => {V01 V02 V03 V04 V05 V07 V10 V19} Live vars: {V01 V02 V03 V04 V05 V07 V10 V19} => {V01 V02 V03 V04 V05 V07 V10} Copy Assertion for BB10 curSsaName stack: { 0-[000130]:V00 1-[000069]:V01 25-[000342]:V25 2-[000174]:V02 26-[000359]:V26 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000433]:V07 10-[000077]:V10 13-[000071]:V13 } Live vars: {V01 V02 V03 V04 V05 V07 V10} => {V01 V02 V03 V04 V05 V07 V10 V19} Live vars: {V01 V02 V03 V04 V05 V07 V10 V19} => {V01 V02 V03 V04 V05 V07 V10} Copy Assertion for BB11 curSsaName stack: { 0-[000130]:V00 1-[000069]:V01 25-[000342]:V25 2-[000174]:V02 26-[000359]:V26 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000433]:V07 10-[000077]:V10 13-[000071]:V13 19-[000241]:V19 } Copy Assertion for BB07 curSsaName stack: { 0-[000130]:V00 1-[000069]:V01 25-[000342]:V25 2-[000174]:V02 3-[000000]:V03 4-[000166]:V04 5-[000134]:V05 7-[000436]:V07 } Live vars: {V07} => {} Live vars: {} => {V06} *************** Finishing PHASE VN based copy prop *************** Starting PHASE Optimize Valnum CSEs *************** In optOptimizeCSEs() Blocks/Trees at start of optOptimizeCSE phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB15 ( cond ) i gcsafe bwd BB11 [0034] 1 BB10 0.58 [???..???)-> BB19 (always) internal gcsafe BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 3 BB10,BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB11 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} ***** BB01 STMT00001 (IL ???... ???) N008 ( 28, 25) [000006] --CXG------- * JTRUE void N007 ( 26, 23) [000200] J-CXG--N---- \--* EQ int $280 N005 ( 24, 21) [000198] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 N003 ( 1, 1) [000000] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N004 ( 3, 10) [000279] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 N006 ( 1, 1) [000199] ------------ \--* CNS_INT int 4 $44 ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} ***** BB02 STMT00002 (IL 0x00F...0x010) N003 ( 5, 4) [000009] -A------R--- * ASG int $41 N002 ( 3, 2) [000008] D------N---- +--* LCL_VAR int V07 loc1 d:2 $41 N001 ( 1, 1) [000007] ------------ \--* CNS_INT int 1 $41 ***** BB02 STMT00004 (IL ???... ???) N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int $283 N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} ***** BB03 STMT00066 (IL ???... ???) N005 ( 0, 0) [000447] -A------R--- * ASG bool N004 ( 0, 0) [000445] D------N---- +--* LCL_VAR bool V07 loc1 d:4 N003 ( 0, 0) [000446] ------------ \--* PHI bool N001 ( 0, 0) [000450] ------------ pred BB27 +--* PHI_ARG bool V07 loc1 u:3 $40 N002 ( 0, 0) [000449] ------------ pred BB02 \--* PHI_ARG bool V07 loc1 u:2 $41 ***** BB03 STMT00005 (IL 0x040...0x046) N009 ( 29, 27) [000022] --CXG------- * JTRUE void N008 ( 27, 25) [000021] J-CXG--N---- \--* NE int $287 N006 ( 25, 23) [000019] --CXG------- +--* CAST int <- bool <- int $286 N005 ( 24, 21) [000018] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 N003 ( 1, 1) [000017] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000312] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca N007 ( 1, 1) [000020] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} ***** BB04 STMT00065 (IL ???... ???) N005 ( 0, 0) [000444] -A------R--- * ASG bool N004 ( 0, 0) [000442] D------N---- +--* LCL_VAR bool V07 loc1 d:6 N003 ( 0, 0) [000443] ------------ \--* PHI bool N001 ( 0, 0) [000452] ------------ pred BB23 +--* PHI_ARG bool V07 loc1 u:5 $40 N002 ( 0, 0) [000451] ------------ pred BB03 \--* PHI_ARG bool V07 loc1 u:4 $580 ***** BB04 STMT00006 (IL 0x055...0x05B) N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int $28b N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 $40 ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} ***** BB05 STMT00064 (IL ???... ???) N005 ( 0, 0) [000441] -A------R--- * ASG bool N004 ( 0, 0) [000439] D------N---- +--* LCL_VAR bool V07 loc1 d:8 N003 ( 0, 0) [000440] ------------ \--* PHI bool N001 ( 0, 0) [000454] ------------ pred BB18 +--* PHI_ARG bool V07 loc1 u:7 $40 N002 ( 0, 0) [000453] ------------ pred BB04 \--* PHI_ARG bool V07 loc1 u:6 $581 ***** BB05 STMT00007 (IL 0x06A...0x070) N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int $28f N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 $40 ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} ***** BB06 STMT00063 (IL ???... ???) N005 ( 0, 0) [000438] -A------R--- * ASG bool N004 ( 0, 0) [000436] D------N---- +--* LCL_VAR bool V07 loc1 d:10 N003 ( 0, 0) [000437] ------------ \--* PHI bool N001 ( 0, 0) [000456] ------------ pred BB28 +--* PHI_ARG bool V07 loc1 u:9 $40 N002 ( 0, 0) [000455] ------------ pred BB05 \--* PHI_ARG bool V07 loc1 u:8 $582 ***** BB06 STMT00009 (IL ???... ???) N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref $167 N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB06 STMT00010 (IL 0x08B...0x092) N009 ( 26, 26) [000050] -ACXG---R--- * ASG struct (copy) $VN.Void N008 ( 3, 2) [000048] D------N---- +--* LCL_VAR struct(AX) V12 tmp1 N007 ( 22, 23) [000045] --CXG------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 N004 ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long N003 ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class $1d0 N006 ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref $486 N005 ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 $4c2 ***** BB06 STMT00011 (IL ???... ???) N016 ( 18, 15) [000355] -A-XG------- * COMMA void N009 ( 10, 8) [000348] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref $487 N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref $487 N001 ( 3, 2) [000341] -------N---- | | \--* LCL_VAR struct(AX) V12 tmp1 $4c3 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 N015 ( 8, 7) [000354] -A-XG---R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] ---X-------- \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 ***** BB06 STMT00057 (IL 0x0E1... ???) N011 ( 27, 29) [000419] --CXG------- * JTRUE void N010 ( 25, 27) [000409] J-CXG--N---- \--* NE int $295 N008 ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int $294 N007 ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $212 N004 ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref $48a N005 ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c4 N009 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} ***** BB07 STMT00061 (IL ???... ???) N005 ( 0, 0) [000432] -A------R--- * ASG bool N004 ( 0, 0) [000430] D------N---- +--* LCL_VAR bool V07 loc1 d:14 N003 ( 0, 0) [000431] ------------ \--* PHI bool N001 ( 0, 0) [000461] ------------ pred BB16 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 $583 ***** BB07 STMT00026 (IL 0x0EA...0x0EB) N003 ( 7, 5) [000127] -A------R--- * ASG int $584 N002 ( 3, 2) [000126] D------N---- +--* LCL_VAR int V06 loc0 d:4 $584 N001 ( 3, 2) [000125] ------------ \--* LCL_VAR int V07 loc1 u:14 (last use) $584 ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} ***** BB08 STMT00059 (IL ???... ???) N005 ( 0, 0) [000426] -A------R--- * ASG bool N004 ( 0, 0) [000424] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000425] ------------ \--* PHI bool N001 ( 0, 0) [000463] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:4 $584 N002 ( 0, 0) [000448] ------------ pred BB24 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB08 STMT00027 (IL 0x0EC...0x0ED) N002 ( 4, 3) [000129] ------------ * RETURN int $214 N001 ( 3, 2) [000128] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) $585 ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} ***** BB09 STMT00062 (IL ???... ???) N005 ( 0, 0) [000435] -A------R--- * ASG bool N004 ( 0, 0) [000433] D------N---- +--* LCL_VAR bool V07 loc1 d:11 N003 ( 0, 0) [000434] ------------ \--* PHI bool N001 ( 0, 0) [000460] ------------ pred BB15 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 $583 ***** BB09 STMT00013 (IL 0x095...0x0A7) N017 ( 59, 54) [000073] -ACXG---R--- * ASG struct (copy) $VN.Void N016 ( 3, 2) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 d:2 N015 ( 55, 51) [000070] --CXG------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 N009 ( 26, 26) [000360] -ACXG---R-L- this SETUP +--* ASG ref $16c N008 ( 3, 2) [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 d:2 $16c N007 ( 22, 23) [000066] --CXG------- | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c N004 ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref $48c N005 ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c5 N012 ( 3, 2) [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 u:2 (last use) $16c N013 ( 3, 2) [000069] ------------ arg2 in rsi +--* LCL_VAR ref V01 arg1 u:1 $81 N014 ( 3, 10) [000356] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 ***** BB09 STMT00014 (IL ???... ???) N003 ( 7, 7) [000078] -A------R--- * ASG ref $370 N002 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V10 loc4 d:2 $370 N001 ( 3, 4) [000076] ------------ \--* LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) $370 ***** BB09 STMT00046 (IL 0x0A9... ???) N008 ( 30, 26) [000228] --CXG------- * JTRUE void N007 ( 28, 24) [000249] J-CXG--N---- \--* NE int $296 N005 ( 26, 22) [000247] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 N003 ( 3, 2) [000080] ------------ this in rdi | +--* LCL_VAR ref V10 loc4 u:2 $370 N004 ( 3, 10) [000365] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 N006 ( 1, 1) [000248] ------------ \--* CNS_INT int 4 $44 ------------ BB10 [0A9..0AA) -> BB15 (cond), preds={BB09} succs={BB11,BB15} ***** BB10 STMT00049 (IL 0x0A9... ???) N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void N003 ( 3, 2) [000237] ------------ arg0 in rdi +--* LCL_VAR ref V10 loc4 u:2 $370 N004 ( 1, 1) [000238] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB10 STMT00050 (IL 0x0A9... ???) N003 ( 5, 4) [000242] -A------R--- * ASG bool $40 N002 ( 3, 2) [000241] D------N---- +--* LCL_VAR int V19 tmp8 d:3 $40 N001 ( 1, 1) [000240] ------------ \--* CNS_INT int 0 $40 ***** BB10 STMT00058 (IL ???... ???) N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] J------N---- \--* NE int $40 N001 ( 3, 2) [000422] ------------ +--* LCL_VAR int V19 tmp8 u:3 (last use) $40 N002 ( 1, 1) [000423] ------------ \--* CNS_INT int 0 $40 ------------ BB11 [???..???) -> BB19 (always), preds={BB10} succs={BB19} ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} ***** BB12 STMT00028 (IL 0x072...0x07E) N015 ( 28, 23) [000139] --CXG------- * JTRUE void N014 ( 26, 21) [000138] J-CXG--N---- \--* EQ int $291 N012 ( 24, 19) [000136] --CXG------- +--* CAST int <- bool <- int $290 N011 ( 23, 17) [000135] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f N006 ( 3, 2) [000130] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 (last use) $80 N007 ( 1, 1) [000131] ------------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 u:1 $82 N008 ( 1, 1) [000132] ------------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 u:1 $83 N009 ( 3, 2) [000133] ------------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 u:1 $84 N010 ( 1, 1) [000134] ------------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 u:1 $c0 N013 ( 1, 1) [000137] ------------ \--* CNS_INT int 0 $40 ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} ***** BB14 STMT00048 (IL 0x0A9... ???) N010 ( 24, 17) [000234] -ACXG---R--- * ASG bool $297 N009 ( 3, 2) [000233] D------N---- +--* LCL_VAR int V19 tmp8 d:2 $297 N008 ( 20, 14) [000232] --CXG------- \--* CAST int <- bool <- int $297 N007 ( 19, 12) [000230] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 N004 ( 1, 1) [000079] ------------ arg0 in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 2) [000229] ------------ arg1 in rsi +--* LCL_VAR ref V10 loc4 u:2 $370 N006 ( 1, 1) [000081] ------------ arg2 in rdx \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB14 STMT00016 (IL ???... ???) N004 ( 7, 6) [000087] ------------ * JTRUE void N003 ( 5, 4) [000086] J------N---- \--* EQ int $298 N001 ( 3, 2) [000235] ------------ +--* LCL_VAR int V19 tmp8 u:2 (last use) $297 N002 ( 1, 1) [000085] ------------ \--* CNS_INT int 0 $40 ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB10,BB14,BB21} succs={BB16,BB09} ***** BB15 STMT00060 (IL ???... ???) N005 ( 0, 0) [000429] -A------R--- * ASG bool N004 ( 0, 0) [000427] D------N---- +--* LCL_VAR bool V07 loc1 d:13 N003 ( 0, 0) [000428] ------------ \--* PHI bool N001 ( 0, 0) [000462] ------------ pred BB14 +--* PHI_ARG bool V07 loc1 u:11 $586 N002 ( 0, 0) [000459] ------------ pred BB21 \--* PHI_ARG bool V07 loc1 u:12 $40 ***** BB15 STMT00012 (IL 0x0E1...0x0E8) N011 ( 27, 29) [000063] --CXG------- * JTRUE void N010 ( 25, 27) [000062] J-CXG--N---- \--* NE int $29b N008 ( 23, 25) [000060] --CXG------- +--* CAST int <- bool <- int $29a N007 ( 22, 23) [000057] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $21b N004 ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref $490 N005 ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c6 N009 ( 1, 1) [000061] ------------ \--* CNS_INT int 0 $40 ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} ***** BB17 STMT00031 (IL ???... ???) N011 ( 24, 18) [000151] --CXG------- * JTRUE void N010 ( 22, 16) [000150] J-CXG--N---- \--* NE int $28d N008 ( 20, 14) [000148] --CXG------- +--* CAST int <- bool <- int $28c N007 ( 19, 12) [000146] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c N004 ( 1, 1) [000143] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000144] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000145] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 $84 N009 ( 1, 1) [000149] ------------ \--* CNS_INT int 0 $40 ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} ***** BB18 STMT00032 (IL 0x068...0x069) N003 ( 5, 4) [000154] -A------R--- * ASG int $40 N002 ( 3, 2) [000153] D------N---- +--* LCL_VAR int V07 loc1 d:7 $40 N001 ( 1, 1) [000152] ------------ \--* CNS_INT int 0 $40 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB11} succs={BB20,BB21} ***** BB19 STMT00017 (IL 0x0B5...0x0B7) N004 ( 7, 6) [000091] ------------ * JTRUE void N003 ( 5, 4) [000090] J------N---- \--* EQ int $284 N001 ( 3, 2) [000088] ------------ +--* LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000089] ------------ \--* CNS_INT ref null $VN.Null ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} ***** BB20 STMT00019 (IL 0x0B9...0x0CA) N005 ( 19, 10) [000101] -ACXG---R--- * ASG ref $376 N004 ( 3, 2) [000100] D------N---- +--* LCL_VAR ref V14 tmp3 d:2 $385 N003 ( 15, 7) [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 N002 ( 1, 1) [000098] ------------ arg0 in rdi \--* CNS_INT long 2 $2c4 ***** BB20 STMT00020 (IL ???... ???) N011 ( 18, 19) [000107] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000384] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000378] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 $40 N003 ( 5, 4) [000377] ---X-------- | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 $385 N008 ( 6, 5) [000106] a---G--N---- | \--* IND ref $83 N007 ( 4, 3) [000383] -------N---- | \--* ADD byref $441 N005 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N010 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 ***** BB20 STMT00021 (IL ???...0x0CF) N011 ( 20, 20) [000112] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000394] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 $41 N003 ( 5, 4) [000387] ---X-------- | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000108] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 $385 N008 ( 6, 5) [000111] a---G--N---- | \--* IND ref $370 N007 ( 4, 3) [000393] -------N---- | \--* ADD byref $442 N005 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 N010 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) $370 ***** BB20 STMT00052 (IL ???... ???) N003 ( 18, 8) [000261] -AC-----R--- * ASG ref $647 N002 ( 3, 2) [000260] D------N---- +--* LCL_VAR ref V20 tmp9 d:2 $647 N001 ( 14, 5) [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 ***** BB20 STMT00053 (IL ???... ???) N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N007 ( 21, 14) [000396] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 d:2 N005 ( 17, 11) [000255] --CXG------- | \--* IND ref N004 ( 15, 9) [000254] --CXG--N---- | \--* ADD byref $403 N002 ( 14, 5) [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] $48 N010 ( 3, 2) [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 u:2 $647 N012 ( 3, 2) [000102] ------------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 u:2 (last use) $385 N013 ( 1, 4) [000256] ------------ arg2 in rdx \--* CNS_INT int 0x7D2C $64 ***** BB20 STMT00054 (IL ???... ???) N003 ( 5, 4) [000269] IA------R--- * ASG struct (init) $VN.Void N002 ( 3, 2) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 d:2 N001 ( 1, 1) [000268] ------------ \--* CNS_INT int 0 $40 ***** BB20 STMT00055 (IL ???... ???) N003 ( 5, 6) [000273] -A------R--- * ASG ref $82 N002 ( 3, 4) [000272] U------N---- +--* LCL_FLD ref V15 tmp4 ud:2->3[+0] Fseq[TypeParameter] $38c N001 ( 1, 1) [000096] ------------ \--* LCL_VAR ref V02 arg2 u:1 $82 ***** BB20 STMT00056 (IL ???... ???) N003 ( 7, 7) [000277] -A------R--- * ASG ref $647 N002 ( 3, 4) [000276] U------N---- +--* LCL_FLD ref V15 tmp4 ud:3->4[+8] Fseq[DiagnosticInfo] $38d N001 ( 3, 2) [000264] ------------ \--* LCL_VAR ref V20 tmp9 u:2 (last use) $647 ***** BB20 STMT00025 (IL 0x0DA... ???) N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct $507 N004 ( 3, 3) [000123] ------------ | \--* ADDR byref $40b N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} ***** BB21 STMT00018 (IL 0x0DF...0x0E0) N003 ( 5, 4) [000094] -A------R--- * ASG int $40 N002 ( 3, 2) [000093] D------N---- +--* LCL_VAR int V07 loc1 d:12 $40 N001 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 $40 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} ***** BB22 STMT00033 (IL 0x048...0x051) N011 ( 24, 18) [000162] --CXG------- * JTRUE void N010 ( 22, 16) [000161] J-CXG--N---- \--* NE int $289 N008 ( 20, 14) [000159] --CXG------- +--* CAST int <- bool <- int $288 N007 ( 19, 12) [000158] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 N004 ( 1, 1) [000155] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000156] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000157] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 $84 N009 ( 1, 1) [000160] ------------ \--* CNS_INT int 0 $40 ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} ***** BB23 STMT00034 (IL 0x053...0x054) N003 ( 5, 4) [000165] -A------R--- * ASG int $40 N002 ( 3, 2) [000164] D------N---- +--* LCL_VAR int V07 loc1 d:5 $40 N001 ( 1, 1) [000163] ------------ \--* CNS_INT int 0 $40 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} ***** BB24 STMT00042 (IL 0x008...0x009) N003 ( 5, 4) [000197] -A------R--- * ASG int $41 N002 ( 3, 2) [000196] D------N---- +--* LCL_VAR int V06 loc0 d:2 $41 N001 ( 1, 1) [000195] ------------ \--* CNS_INT int 1 $41 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} ***** BB25 STMT00035 (IL 0x019...0x01B) N004 ( 7, 6) [000169] ------------ * JTRUE void N003 ( 5, 4) [000168] J------N---- \--* EQ int $284 N001 ( 3, 2) [000166] ------------ +--* LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000167] ------------ \--* CNS_INT ref null $VN.Null ------------ BB26 [01D..03E), preds={BB25} succs={BB27} ***** BB26 STMT00037 (IL 0x01D...0x02E) N005 ( 19, 10) [000179] -ACXG---R--- * ASG ref $342 N004 ( 3, 2) [000178] D------N---- +--* LCL_VAR ref V16 tmp5 d:2 $380 N003 ( 15, 7) [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 N002 ( 1, 1) [000176] ------------ arg0 in rdi \--* CNS_INT long 1 $2c0 ***** BB26 STMT00038 (IL ???... ???) N011 ( 18, 19) [000185] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000298] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000292] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $348 N001 ( 1, 1) [000182] ------------ | | +--* CNS_INT int 0 $40 N003 ( 5, 4) [000291] ---X-------- | | \--* ARR_LENGTH int $285 N002 ( 3, 2) [000181] ------------ | | \--* LCL_VAR ref V16 tmp5 u:2 $380 N008 ( 6, 5) [000184] a---G--N---- | \--* IND ref $83 N007 ( 4, 3) [000297] -------N---- | \--* ADD byref $440 N005 ( 3, 2) [000289] ------------ | +--* LCL_VAR ref V16 tmp5 u:2 $380 N006 ( 1, 1) [000296] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N010 ( 1, 1) [000183] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 ***** BB26 STMT00043 (IL ???... ???) N003 ( 18, 8) [000216] -AC-----R--- * ASG ref $34c N002 ( 3, 2) [000215] D------N---- +--* LCL_VAR ref V18 tmp7 d:2 $34c N001 ( 14, 5) [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c ***** BB26 STMT00044 (IL ???... ???) N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N007 ( 21, 14) [000300] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 d:2 N005 ( 17, 11) [000210] --CXG------- | \--* IND ref N004 ( 15, 9) [000209] --CXG--N---- | \--* ADD byref $403 N002 ( 14, 5) [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] $48 N010 ( 3, 2) [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 u:2 $34c N012 ( 3, 2) [000180] ------------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 u:2 (last use) $380 N013 ( 1, 4) [000211] ------------ arg2 in rdx \--* CNS_INT int 0x7AA4 $49 ***** BB26 STMT00040 (IL ???... ???) N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void N004 ( 3, 3) [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 $481 N005 ( 1, 1) [000174] ------------ arg1 in rsi +--* LCL_VAR ref V02 arg2 u:1 $82 N006 ( 3, 2) [000219] ------------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 u:2 (last use) $34c ***** BB26 STMT00041 (IL 0x039... ???) N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 $4c0 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} ***** BB27 STMT00036 (IL 0x03E...0x03F) N003 ( 5, 4) [000172] -A------R--- * ASG int $40 N002 ( 3, 2) [000171] D------N---- +--* LCL_VAR int V07 loc1 d:3 $40 N001 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 $40 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} ***** BB28 STMT00029 (IL 0x080...0x081) N003 ( 5, 4) [000142] -A------R--- * ASG int $40 N002 ( 3, 2) [000141] D------N---- +--* LCL_VAR int V07 loc1 d:9 $40 N001 ( 1, 1) [000140] ------------ \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- *************** In optOptimizeValnumCSEs() CSE candidate #01, vn=$3c1 in BB20, [cost= 5, size= 4]: N003 ( 5, 4) CSE #01 (use)[000387] ---X-------- * ARR_LENGTH int $299 N002 ( 3, 2) [000108] ------------ \--* LCL_VAR ref V14 tmp3 u:2 $385 CSE candidate #02, vn=$c1 in BB26, [cost=14, size= 5]: N002 ( 14, 5) CSE #02 (use)[000207] H-CXG------- * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 Blocks that generate CSE def/uses BB20 cseGen = 0000000000000005 BB26 cseGen = 0000000000000004 Performing DataFlow for ValnumCSE's StartMerge BB01 :: cseOut = 000000000000001F EndMerge BB01 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB02 :: cseOut = 000000000000001F Merge BB02 and BB01 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB02 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB24 :: cseOut = 000000000000001F Merge BB24 and BB01 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB24 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB03 :: cseOut = 000000000000001F Merge BB03 and BB02 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB03 and BB27 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB03 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB25 :: cseOut = 000000000000001F Merge BB25 and BB02 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB25 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB08 :: cseOut = 000000000000001F Merge BB08 and BB24 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB08 and BB07 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB08 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB04 :: cseOut = 000000000000001F Merge BB04 and BB03 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB04 and BB22 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB04 and BB23 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB04 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB22 :: cseOut = 000000000000001F Merge BB22 and BB03 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB22 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB26 :: cseOut = 000000000000001F Merge BB26 and BB25 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB26 :: cseIn = 0000000000000000 :: cseGen = 0000000000000004 => cseOut = 0000000000000004 != preMerge = 000000000000001F, => true StartMerge BB27 :: cseOut = 000000000000001F Merge BB27 and BB25 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB27 and BB26 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB27 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB05 :: cseOut = 000000000000001F Merge BB05 and BB04 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB05 and BB17 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB05 and BB18 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB05 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB17 :: cseOut = 000000000000001F Merge BB17 and BB04 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB17 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB23 :: cseOut = 000000000000001F Merge BB23 and BB22 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB23 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB04 :: cseOut = 0000000000000000 Merge BB04 and BB03 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB04 and BB22 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB04 and BB23 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB04 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB27 :: cseOut = 0000000000000000 Merge BB27 and BB25 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB27 and BB26 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB27 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB03 :: cseOut = 0000000000000000 Merge BB03 and BB02 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB03 and BB27 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB03 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB06 :: cseOut = 000000000000001F Merge BB06 and BB05 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB06 and BB13 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB06 and BB28 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB06 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB12 :: cseOut = 000000000000001F Merge BB12 and BB05 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB12 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB18 :: cseOut = 000000000000001F Merge BB18 and BB17 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB18 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB05 :: cseOut = 0000000000000000 Merge BB05 and BB04 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB05 and BB17 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB05 and BB18 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB05 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB04 :: cseOut = 0000000000000000 Merge BB04 and BB03 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB04 and BB22 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB04 and BB23 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB04 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB07 :: cseOut = 000000000000001F Merge BB07 and BB06 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB07 and BB16 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB07 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB09 :: cseOut = 000000000000001F Merge BB09 and BB06 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB09 and BB15 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB09 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB13 :: cseOut = 000000000000001F Merge BB13 and BB12 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB13 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB28 :: cseOut = 000000000000001F Merge BB28 and BB12 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB28 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB05 :: cseOut = 0000000000000000 Merge BB05 and BB04 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB05 and BB17 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB05 and BB18 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB05 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB08 :: cseOut = 0000000000000000 Merge BB08 and BB24 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB08 and BB07 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB08 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB10 :: cseOut = 000000000000001F Merge BB10 and BB09 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB10 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB14 :: cseOut = 000000000000001F Merge BB14 and BB09 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB14 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB06 :: cseOut = 0000000000000000 Merge BB06 and BB05 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB06 and BB13 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB06 and BB28 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB06 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB06 :: cseOut = 0000000000000000 Merge BB06 and BB05 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB06 and BB13 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB06 and BB28 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB06 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB11 :: cseOut = 000000000000001F Merge BB11 and BB10 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB11 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB15 :: cseOut = 000000000000001F Merge BB15 and BB10 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB15 and BB14 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB15 and BB21 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB15 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB15 :: cseOut = 0000000000000000 Merge BB15 and BB10 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB15 and BB14 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB15 and BB21 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB15 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB19 :: cseOut = 000000000000001F Merge BB19 and BB14 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB19 and BB11 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB19 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB19 :: cseOut = 0000000000000000 Merge BB19 and BB14 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB19 and BB11 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB19 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB16 :: cseOut = 000000000000001F Merge BB16 and BB15 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB16 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB09 :: cseOut = 0000000000000000 Merge BB09 and BB06 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB09 and BB15 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB09 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB20 :: cseOut = 000000000000001F Merge BB20 and BB19 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB20 :: cseIn = 0000000000000000 :: cseGen = 0000000000000005 => cseOut = 0000000000000005 != preMerge = 000000000000001F, => true StartMerge BB21 :: cseOut = 000000000000001F Merge BB21 and BB19 :: cseIn = 000000000000001F :: cseOut = 000000000000001F => cseIn = 0000000000000000 Merge BB21 and BB20 :: cseIn = 0000000000000000 :: cseOut = 000000000000001F => cseIn = 0000000000000000 EndMerge BB21 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 000000000000001F, => true StartMerge BB07 :: cseOut = 0000000000000000 Merge BB07 and BB06 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB07 and BB16 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB07 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB21 :: cseOut = 0000000000000000 Merge BB21 and BB19 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB21 and BB20 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB21 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false StartMerge BB15 :: cseOut = 0000000000000000 Merge BB15 and BB10 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB15 and BB14 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 Merge BB15 and BB21 :: cseIn = 0000000000000000 :: cseOut = 0000000000000000 => cseIn = 0000000000000000 EndMerge BB15 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0000000000000000, => false After performing DataFlow for ValnumCSE's BB01 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB02 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB03 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB04 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB05 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB06 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB07 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB08 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB09 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB10 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB11 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB12 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB13 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB14 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB15 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB16 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB17 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB18 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB19 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB20 cseIn = 0000000000000000, cseGen = 0000000000000005, cseOut = 0000000000000005 BB21 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB22 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB23 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB24 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB25 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB26 cseIn = 0000000000000000, cseGen = 0000000000000004, cseOut = 0000000000000004 BB27 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB28 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 Labeling the CSEs with Use/Def information BB20 [000377] Def of CSE #01 [weight=0.02] BB20 [000387] Use of CSE #01 [weight=0.02] BB20 [000252] Def of CSE #02 [weight=0.02] BB26 [000207] Def of CSE #02 [weight=0 ] ************ Trees at start of optValnumCSE_Heuristic() ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} ***** BB01 STMT00001 (IL ???... ???) N008 ( 28, 25) [000006] --CXG------- * JTRUE void N007 ( 26, 23) [000200] J-CXG--N---- \--* EQ int $280 N005 ( 24, 21) [000198] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 N003 ( 1, 1) [000000] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N004 ( 3, 10) [000279] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 N006 ( 1, 1) [000199] ------------ \--* CNS_INT int 4 $44 ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} ***** BB02 STMT00002 (IL 0x00F...0x010) N003 ( 5, 4) [000009] -A------R--- * ASG int $41 N002 ( 3, 2) [000008] D------N---- +--* LCL_VAR int V07 loc1 d:2 $41 N001 ( 1, 1) [000007] ------------ \--* CNS_INT int 1 $41 ***** BB02 STMT00004 (IL ???... ???) N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int $283 N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} ***** BB03 STMT00066 (IL ???... ???) N005 ( 0, 0) [000447] -A------R--- * ASG bool N004 ( 0, 0) [000445] D------N---- +--* LCL_VAR bool V07 loc1 d:4 N003 ( 0, 0) [000446] ------------ \--* PHI bool N001 ( 0, 0) [000450] ------------ pred BB27 +--* PHI_ARG bool V07 loc1 u:3 $40 N002 ( 0, 0) [000449] ------------ pred BB02 \--* PHI_ARG bool V07 loc1 u:2 $41 ***** BB03 STMT00005 (IL 0x040...0x046) N009 ( 29, 27) [000022] --CXG------- * JTRUE void N008 ( 27, 25) [000021] J-CXG--N---- \--* NE int $287 N006 ( 25, 23) [000019] --CXG------- +--* CAST int <- bool <- int $286 N005 ( 24, 21) [000018] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 N003 ( 1, 1) [000017] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000312] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca N007 ( 1, 1) [000020] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} ***** BB04 STMT00065 (IL ???... ???) N005 ( 0, 0) [000444] -A------R--- * ASG bool N004 ( 0, 0) [000442] D------N---- +--* LCL_VAR bool V07 loc1 d:6 N003 ( 0, 0) [000443] ------------ \--* PHI bool N001 ( 0, 0) [000452] ------------ pred BB23 +--* PHI_ARG bool V07 loc1 u:5 $40 N002 ( 0, 0) [000451] ------------ pred BB03 \--* PHI_ARG bool V07 loc1 u:4 $580 ***** BB04 STMT00006 (IL 0x055...0x05B) N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int $28b N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 $40 ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} ***** BB05 STMT00064 (IL ???... ???) N005 ( 0, 0) [000441] -A------R--- * ASG bool N004 ( 0, 0) [000439] D------N---- +--* LCL_VAR bool V07 loc1 d:8 N003 ( 0, 0) [000440] ------------ \--* PHI bool N001 ( 0, 0) [000454] ------------ pred BB18 +--* PHI_ARG bool V07 loc1 u:7 $40 N002 ( 0, 0) [000453] ------------ pred BB04 \--* PHI_ARG bool V07 loc1 u:6 $581 ***** BB05 STMT00007 (IL 0x06A...0x070) N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int $28f N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 $40 ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} ***** BB06 STMT00063 (IL ???... ???) N005 ( 0, 0) [000438] -A------R--- * ASG bool N004 ( 0, 0) [000436] D------N---- +--* LCL_VAR bool V07 loc1 d:10 N003 ( 0, 0) [000437] ------------ \--* PHI bool N001 ( 0, 0) [000456] ------------ pred BB28 +--* PHI_ARG bool V07 loc1 u:9 $40 N002 ( 0, 0) [000455] ------------ pred BB05 \--* PHI_ARG bool V07 loc1 u:8 $582 ***** BB06 STMT00009 (IL ???... ???) N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref $167 N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB06 STMT00010 (IL 0x08B...0x092) N009 ( 26, 26) [000050] -ACXG---R--- * ASG struct (copy) $VN.Void N008 ( 3, 2) [000048] D------N---- +--* LCL_VAR struct(AX) V12 tmp1 N007 ( 22, 23) [000045] --CXG------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 N004 ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long N003 ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class $1d0 N006 ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref $486 N005 ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 $4c2 ***** BB06 STMT00011 (IL ???... ???) N016 ( 18, 15) [000355] -A-XG------- * COMMA void N009 ( 10, 8) [000348] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref $487 N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref $487 N001 ( 3, 2) [000341] -------N---- | | \--* LCL_VAR struct(AX) V12 tmp1 $4c3 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 N015 ( 8, 7) [000354] -A-XG---R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] ---X-------- \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 ***** BB06 STMT00057 (IL 0x0E1... ???) N011 ( 27, 29) [000419] --CXG------- * JTRUE void N010 ( 25, 27) [000409] J-CXG--N---- \--* NE int $295 N008 ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int $294 N007 ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $212 N004 ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref $48a N005 ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c4 N009 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} ***** BB07 STMT00061 (IL ???... ???) N005 ( 0, 0) [000432] -A------R--- * ASG bool N004 ( 0, 0) [000430] D------N---- +--* LCL_VAR bool V07 loc1 d:14 N003 ( 0, 0) [000431] ------------ \--* PHI bool N001 ( 0, 0) [000461] ------------ pred BB16 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 $583 ***** BB07 STMT00026 (IL 0x0EA...0x0EB) N003 ( 7, 5) [000127] -A------R--- * ASG int $584 N002 ( 3, 2) [000126] D------N---- +--* LCL_VAR int V06 loc0 d:4 $584 N001 ( 3, 2) [000125] ------------ \--* LCL_VAR int V07 loc1 u:14 (last use) $584 ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} ***** BB08 STMT00059 (IL ???... ???) N005 ( 0, 0) [000426] -A------R--- * ASG bool N004 ( 0, 0) [000424] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000425] ------------ \--* PHI bool N001 ( 0, 0) [000463] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:4 $584 N002 ( 0, 0) [000448] ------------ pred BB24 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB08 STMT00027 (IL 0x0EC...0x0ED) N002 ( 4, 3) [000129] ------------ * RETURN int $214 N001 ( 3, 2) [000128] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) $585 ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} ***** BB09 STMT00062 (IL ???... ???) N005 ( 0, 0) [000435] -A------R--- * ASG bool N004 ( 0, 0) [000433] D------N---- +--* LCL_VAR bool V07 loc1 d:11 N003 ( 0, 0) [000434] ------------ \--* PHI bool N001 ( 0, 0) [000460] ------------ pred BB15 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 $583 ***** BB09 STMT00013 (IL 0x095...0x0A7) N017 ( 59, 54) [000073] -ACXG---R--- * ASG struct (copy) $VN.Void N016 ( 3, 2) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 d:2 N015 ( 55, 51) [000070] --CXG------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 N009 ( 26, 26) [000360] -ACXG---R-L- this SETUP +--* ASG ref $16c N008 ( 3, 2) [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 d:2 $16c N007 ( 22, 23) [000066] --CXG------- | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c N004 ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref $48c N005 ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c5 N012 ( 3, 2) [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 u:2 (last use) $16c N013 ( 3, 2) [000069] ------------ arg2 in rsi +--* LCL_VAR ref V01 arg1 u:1 $81 N014 ( 3, 10) [000356] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 ***** BB09 STMT00014 (IL ???... ???) N003 ( 7, 7) [000078] -A------R--- * ASG ref $370 N002 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V10 loc4 d:2 $370 N001 ( 3, 4) [000076] ------------ \--* LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) $370 ***** BB09 STMT00046 (IL 0x0A9... ???) N008 ( 30, 26) [000228] --CXG------- * JTRUE void N007 ( 28, 24) [000249] J-CXG--N---- \--* NE int $296 N005 ( 26, 22) [000247] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 N003 ( 3, 2) [000080] ------------ this in rdi | +--* LCL_VAR ref V10 loc4 u:2 $370 N004 ( 3, 10) [000365] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 N006 ( 1, 1) [000248] ------------ \--* CNS_INT int 4 $44 ------------ BB10 [0A9..0AA) -> BB15 (cond), preds={BB09} succs={BB11,BB15} ***** BB10 STMT00049 (IL 0x0A9... ???) N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void N003 ( 3, 2) [000237] ------------ arg0 in rdi +--* LCL_VAR ref V10 loc4 u:2 $370 N004 ( 1, 1) [000238] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB10 STMT00050 (IL 0x0A9... ???) N003 ( 5, 4) [000242] -A------R--- * ASG bool $40 N002 ( 3, 2) [000241] D------N---- +--* LCL_VAR int V19 tmp8 d:3 $40 N001 ( 1, 1) [000240] ------------ \--* CNS_INT int 0 $40 ***** BB10 STMT00058 (IL ???... ???) N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] J------N---- \--* NE int $40 N001 ( 3, 2) [000422] ------------ +--* LCL_VAR int V19 tmp8 u:3 (last use) $40 N002 ( 1, 1) [000423] ------------ \--* CNS_INT int 0 $40 ------------ BB11 [???..???) -> BB19 (always), preds={BB10} succs={BB19} ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} ***** BB12 STMT00028 (IL 0x072...0x07E) N015 ( 28, 23) [000139] --CXG------- * JTRUE void N014 ( 26, 21) [000138] J-CXG--N---- \--* EQ int $291 N012 ( 24, 19) [000136] --CXG------- +--* CAST int <- bool <- int $290 N011 ( 23, 17) [000135] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f N006 ( 3, 2) [000130] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 (last use) $80 N007 ( 1, 1) [000131] ------------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 u:1 $82 N008 ( 1, 1) [000132] ------------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 u:1 $83 N009 ( 3, 2) [000133] ------------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 u:1 $84 N010 ( 1, 1) [000134] ------------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 u:1 $c0 N013 ( 1, 1) [000137] ------------ \--* CNS_INT int 0 $40 ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} ***** BB14 STMT00048 (IL 0x0A9... ???) N010 ( 24, 17) [000234] -ACXG---R--- * ASG bool $297 N009 ( 3, 2) [000233] D------N---- +--* LCL_VAR int V19 tmp8 d:2 $297 N008 ( 20, 14) [000232] --CXG------- \--* CAST int <- bool <- int $297 N007 ( 19, 12) [000230] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 N004 ( 1, 1) [000079] ------------ arg0 in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 2) [000229] ------------ arg1 in rsi +--* LCL_VAR ref V10 loc4 u:2 $370 N006 ( 1, 1) [000081] ------------ arg2 in rdx \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB14 STMT00016 (IL ???... ???) N004 ( 7, 6) [000087] ------------ * JTRUE void N003 ( 5, 4) [000086] J------N---- \--* EQ int $298 N001 ( 3, 2) [000235] ------------ +--* LCL_VAR int V19 tmp8 u:2 (last use) $297 N002 ( 1, 1) [000085] ------------ \--* CNS_INT int 0 $40 ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB10,BB14,BB21} succs={BB16,BB09} ***** BB15 STMT00060 (IL ???... ???) N005 ( 0, 0) [000429] -A------R--- * ASG bool N004 ( 0, 0) [000427] D------N---- +--* LCL_VAR bool V07 loc1 d:13 N003 ( 0, 0) [000428] ------------ \--* PHI bool N001 ( 0, 0) [000462] ------------ pred BB14 +--* PHI_ARG bool V07 loc1 u:11 $586 N002 ( 0, 0) [000459] ------------ pred BB21 \--* PHI_ARG bool V07 loc1 u:12 $40 ***** BB15 STMT00012 (IL 0x0E1...0x0E8) N011 ( 27, 29) [000063] --CXG------- * JTRUE void N010 ( 25, 27) [000062] J-CXG--N---- \--* NE int $29b N008 ( 23, 25) [000060] --CXG------- +--* CAST int <- bool <- int $29a N007 ( 22, 23) [000057] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $21b N004 ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref $490 N005 ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c6 N009 ( 1, 1) [000061] ------------ \--* CNS_INT int 0 $40 ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} ***** BB17 STMT00031 (IL ???... ???) N011 ( 24, 18) [000151] --CXG------- * JTRUE void N010 ( 22, 16) [000150] J-CXG--N---- \--* NE int $28d N008 ( 20, 14) [000148] --CXG------- +--* CAST int <- bool <- int $28c N007 ( 19, 12) [000146] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c N004 ( 1, 1) [000143] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000144] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000145] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 $84 N009 ( 1, 1) [000149] ------------ \--* CNS_INT int 0 $40 ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} ***** BB18 STMT00032 (IL 0x068...0x069) N003 ( 5, 4) [000154] -A------R--- * ASG int $40 N002 ( 3, 2) [000153] D------N---- +--* LCL_VAR int V07 loc1 d:7 $40 N001 ( 1, 1) [000152] ------------ \--* CNS_INT int 0 $40 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB11} succs={BB20,BB21} ***** BB19 STMT00017 (IL 0x0B5...0x0B7) N004 ( 7, 6) [000091] ------------ * JTRUE void N003 ( 5, 4) [000090] J------N---- \--* EQ int $284 N001 ( 3, 2) [000088] ------------ +--* LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000089] ------------ \--* CNS_INT ref null $VN.Null ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} ***** BB20 STMT00019 (IL 0x0B9...0x0CA) N005 ( 19, 10) [000101] -ACXG---R--- * ASG ref $376 N004 ( 3, 2) [000100] D------N---- +--* LCL_VAR ref V14 tmp3 d:2 $385 N003 ( 15, 7) [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 N002 ( 1, 1) [000098] ------------ arg0 in rdi \--* CNS_INT long 2 $2c4 ***** BB20 STMT00020 (IL ???... ???) N011 ( 18, 19) [000107] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000384] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000378] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 $40 N003 ( 5, 4) CSE #01 (def)[000377] ---X-------- | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 $385 N008 ( 6, 5) [000106] a---G--N---- | \--* IND ref $83 N007 ( 4, 3) [000383] -------N---- | \--* ADD byref $441 N005 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N010 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 ***** BB20 STMT00021 (IL ???...0x0CF) N011 ( 20, 20) [000112] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000394] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 $41 N003 ( 5, 4) CSE #01 (use)[000387] ---X-------- | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000108] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 $385 N008 ( 6, 5) [000111] a---G--N---- | \--* IND ref $370 N007 ( 4, 3) [000393] -------N---- | \--* ADD byref $442 N005 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 N010 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) $370 ***** BB20 STMT00052 (IL ???... ???) N003 ( 18, 8) [000261] -AC-----R--- * ASG ref $647 N002 ( 3, 2) [000260] D------N---- +--* LCL_VAR ref V20 tmp9 d:2 $647 N001 ( 14, 5) [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 ***** BB20 STMT00053 (IL ???... ???) N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N007 ( 21, 14) [000396] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 d:2 N005 ( 17, 11) [000255] --CXG------- | \--* IND ref N004 ( 15, 9) [000254] --CXG--N---- | \--* ADD byref $403 N002 ( 14, 5) CSE #02 (def)[000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] $48 N010 ( 3, 2) [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 u:2 $647 N012 ( 3, 2) [000102] ------------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 u:2 (last use) $385 N013 ( 1, 4) [000256] ------------ arg2 in rdx \--* CNS_INT int 0x7D2C $64 ***** BB20 STMT00054 (IL ???... ???) N003 ( 5, 4) [000269] IA------R--- * ASG struct (init) $VN.Void N002 ( 3, 2) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 d:2 N001 ( 1, 1) [000268] ------------ \--* CNS_INT int 0 $40 ***** BB20 STMT00055 (IL ???... ???) N003 ( 5, 6) [000273] -A------R--- * ASG ref $82 N002 ( 3, 4) [000272] U------N---- +--* LCL_FLD ref V15 tmp4 ud:2->3[+0] Fseq[TypeParameter] $38c N001 ( 1, 1) [000096] ------------ \--* LCL_VAR ref V02 arg2 u:1 $82 ***** BB20 STMT00056 (IL ???... ???) N003 ( 7, 7) [000277] -A------R--- * ASG ref $647 N002 ( 3, 4) [000276] U------N---- +--* LCL_FLD ref V15 tmp4 ud:3->4[+8] Fseq[DiagnosticInfo] $38d N001 ( 3, 2) [000264] ------------ \--* LCL_VAR ref V20 tmp9 u:2 (last use) $647 ***** BB20 STMT00025 (IL 0x0DA... ???) N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct $507 N004 ( 3, 3) [000123] ------------ | \--* ADDR byref $40b N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} ***** BB21 STMT00018 (IL 0x0DF...0x0E0) N003 ( 5, 4) [000094] -A------R--- * ASG int $40 N002 ( 3, 2) [000093] D------N---- +--* LCL_VAR int V07 loc1 d:12 $40 N001 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 $40 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} ***** BB22 STMT00033 (IL 0x048...0x051) N011 ( 24, 18) [000162] --CXG------- * JTRUE void N010 ( 22, 16) [000161] J-CXG--N---- \--* NE int $289 N008 ( 20, 14) [000159] --CXG------- +--* CAST int <- bool <- int $288 N007 ( 19, 12) [000158] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 N004 ( 1, 1) [000155] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000156] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000157] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 $84 N009 ( 1, 1) [000160] ------------ \--* CNS_INT int 0 $40 ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} ***** BB23 STMT00034 (IL 0x053...0x054) N003 ( 5, 4) [000165] -A------R--- * ASG int $40 N002 ( 3, 2) [000164] D------N---- +--* LCL_VAR int V07 loc1 d:5 $40 N001 ( 1, 1) [000163] ------------ \--* CNS_INT int 0 $40 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} ***** BB24 STMT00042 (IL 0x008...0x009) N003 ( 5, 4) [000197] -A------R--- * ASG int $41 N002 ( 3, 2) [000196] D------N---- +--* LCL_VAR int V06 loc0 d:2 $41 N001 ( 1, 1) [000195] ------------ \--* CNS_INT int 1 $41 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} ***** BB25 STMT00035 (IL 0x019...0x01B) N004 ( 7, 6) [000169] ------------ * JTRUE void N003 ( 5, 4) [000168] J------N---- \--* EQ int $284 N001 ( 3, 2) [000166] ------------ +--* LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000167] ------------ \--* CNS_INT ref null $VN.Null ------------ BB26 [01D..03E), preds={BB25} succs={BB27} ***** BB26 STMT00037 (IL 0x01D...0x02E) N005 ( 19, 10) [000179] -ACXG---R--- * ASG ref $342 N004 ( 3, 2) [000178] D------N---- +--* LCL_VAR ref V16 tmp5 d:2 $380 N003 ( 15, 7) [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 N002 ( 1, 1) [000176] ------------ arg0 in rdi \--* CNS_INT long 1 $2c0 ***** BB26 STMT00038 (IL ???... ???) N011 ( 18, 19) [000185] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000298] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000292] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $348 N001 ( 1, 1) [000182] ------------ | | +--* CNS_INT int 0 $40 N003 ( 5, 4) [000291] ---X-------- | | \--* ARR_LENGTH int $285 N002 ( 3, 2) [000181] ------------ | | \--* LCL_VAR ref V16 tmp5 u:2 $380 N008 ( 6, 5) [000184] a---G--N---- | \--* IND ref $83 N007 ( 4, 3) [000297] -------N---- | \--* ADD byref $440 N005 ( 3, 2) [000289] ------------ | +--* LCL_VAR ref V16 tmp5 u:2 $380 N006 ( 1, 1) [000296] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N010 ( 1, 1) [000183] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 ***** BB26 STMT00043 (IL ???... ???) N003 ( 18, 8) [000216] -AC-----R--- * ASG ref $34c N002 ( 3, 2) [000215] D------N---- +--* LCL_VAR ref V18 tmp7 d:2 $34c N001 ( 14, 5) [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c ***** BB26 STMT00044 (IL ???... ???) N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N007 ( 21, 14) [000300] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 d:2 N005 ( 17, 11) [000210] --CXG------- | \--* IND ref N004 ( 15, 9) [000209] --CXG--N---- | \--* ADD byref $403 N002 ( 14, 5) CSE #02 (def)[000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] $48 N010 ( 3, 2) [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 u:2 $34c N012 ( 3, 2) [000180] ------------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 u:2 (last use) $380 N013 ( 1, 4) [000211] ------------ arg2 in rdx \--* CNS_INT int 0x7AA4 $49 ***** BB26 STMT00040 (IL ???... ???) N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void N004 ( 3, 3) [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 $481 N005 ( 1, 1) [000174] ------------ arg1 in rsi +--* LCL_VAR ref V02 arg2 u:1 $82 N006 ( 3, 2) [000219] ------------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 u:2 (last use) $34c ***** BB26 STMT00041 (IL 0x039... ???) N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 $4c0 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} ***** BB27 STMT00036 (IL 0x03E...0x03F) N003 ( 5, 4) [000172] -A------R--- * ASG int $40 N002 ( 3, 2) [000171] D------N---- +--* LCL_VAR int V07 loc1 d:3 $40 N001 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 $40 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} ***** BB28 STMT00029 (IL 0x080...0x081) N003 ( 5, 4) [000142] -A------R--- * ASG int $40 N002 ( 3, 2) [000141] D------N---- +--* LCL_VAR int V07 loc1 d:9 $40 N001 ( 1, 1) [000140] ------------ \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- Aggressive CSE Promotion cutoff is 303 Moderate CSE Promotion cutoff is 100 enregCount is 18 Framesize estimate is 0x0088 We have a large frame Sorted CSE candidates: CSE #02, {$c1 , $4 } useCnt=0: [def= 2, use= 0, cost= 14 ] :: N002 ( 14, 5) CSE #02 (def)[000252] H-CXG------- * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 CSE #01, {$3c1, $377} useCnt=1: [def= 2, use= 2, cost= 5 ] :: N003 ( 5, 4) CSE #01 (def)[000377] ---X-------- * ARR_LENGTH int $299 Skipped CSE #02 because use count is 0 Considering CSE #01 {$3c1, $377} [def= 2, use= 2, cost= 5 ] CSE Expression : N003 ( 5, 4) CSE #01 (def)[000377] ---X-------- * ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ \--* LCL_VAR ref V14 tmp3 u:2 $385 Conservative CSE Promotion (CSE never live at call) (6 < 100) cseRefCnt=6, aggressiveRefCnt=303, moderateRefCnt=100 defCnt=2, useCnt=2, cost=5, size=4 def_cost=2, use_cost=2, extra_no_cost=4, extra_yes_cost=0 CSE cost savings check (14 >= 8) passes Promoting CSE: lvaGrabTemp returning 28 (V28 rat0) (a long lifetime temp) called for CSE - conservative. CSE #01 is single-def, so associated CSE temp V28 will be in SSA CSE #01 def at [000377] replaced in BB20 with def of V28 fgMorphTree (before 288): N011 ( 18, 19) [000107] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000384] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000378] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 $40 [000467] -A-X-------- | | \--* COMMA int $299 [000465] -A-X-------- | | +--* ASG int $VN.Void [000464] D------N---- | | | +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- | | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | | | \--* LCL_VAR ref V14 tmp3 u:2 $385 [000466] ------------ | | \--* LCL_VAR int V28 cse0 u:1 $299 N008 ( 6, 5) [000106] a---G--N---- | \--* IND ref $83 N007 ( 4, 3) [000383] -------N---- | \--* ADD byref $441 N005 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N010 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 fgMorphTree (before 289): N009 ( 16, 17) [000384] ---XG--N---- * COMMA ref $VN.Void N004 ( 10, 12) [000378] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ | +--* CNS_INT int 0 $40 [000467] -A-X-------- | \--* COMMA int $299 [000465] -A-X-------- | +--* ASG int $VN.Void [000464] D------N---- | | +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 $385 [000466] ------------ | \--* LCL_VAR int V28 cse0 u:1 $299 N008 ( 6, 5) [000106] a---G--N---- \--* IND ref $83 N007 ( 4, 3) [000383] -------N---- \--* ADD byref $441 N005 ( 3, 2) [000375] ------------ +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000382] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 fgMorphTree (before 290): N004 ( 10, 12) [000378] ---X-------- * ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ +--* CNS_INT int 0 $40 [000467] -A-X-------- \--* COMMA int $299 [000465] -A-X-------- +--* ASG int $VN.Void [000464] D------N---- | +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | \--* LCL_VAR ref V14 tmp3 u:2 $385 [000466] ------------ \--* LCL_VAR int V28 cse0 u:1 $299 fgMorphTree (before 291): N001 ( 1, 1) [000104] ------------ * CNS_INT int 0 $40 fgMorphTree (after 291): N001 ( 1, 1) [000104] ------------ * CNS_INT int 0 $40 fgMorphTree (before 292): [000467] -A-X-------- * COMMA int $299 [000465] -A-X-------- +--* ASG int $VN.Void [000464] D------N---- | +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | \--* LCL_VAR ref V14 tmp3 u:2 $385 [000466] ------------ \--* LCL_VAR int V28 cse0 u:1 $299 fgMorphTree (before 293): [000465] -A-X-------- * ASG int $VN.Void [000464] D------N---- +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ \--* LCL_VAR ref V14 tmp3 u:2 $385 fgMorphTree (before 294): [000464] D------N---- * LCL_VAR int V28 cse0 d:1 $299 fgMorphTree (after 294): [000464] D------N---- * LCL_VAR int V28 cse0 d:1 $299 fgMorphTree (before 295): N003 ( 5, 4) [000377] ---X-------- * ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ \--* LCL_VAR ref V14 tmp3 u:2 $385 fgMorphTree (before 296): N002 ( 3, 2) [000103] ------------ * LCL_VAR ref V14 tmp3 u:2 $385 fgMorphTree (after 296): N002 ( 3, 2) [000103] ------------ * LCL_VAR ref V14 tmp3 u:2 $385 fgMorphTree (after 295): N003 ( 5, 4) [000377] ---X-------- * ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ \--* LCL_VAR ref V14 tmp3 u:2 $385 fgMorphTree (after 293): [000465] -A-X-------- * ASG int $VN.Void [000464] D------N---- +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ \--* LCL_VAR ref V14 tmp3 u:2 $385 fgMorphTree (before 297): [000466] ------------ * LCL_VAR int V28 cse0 u:1 $299 fgMorphTree (after 297): [000466] ------------ * LCL_VAR int V28 cse0 u:1 $299 fgMorphTree (after 292): [000467] -A-X-------- * COMMA int $299 [000465] -A-X-------- +--* ASG int $VN.Void [000464] D------N---- | +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | \--* LCL_VAR ref V14 tmp3 u:2 $385 [000466] ------------ \--* LCL_VAR int V28 cse0 u:1 $299 fgMorphTree (after 290): N004 ( 10, 12) [000378] -A-X-------- * ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ +--* CNS_INT int 0 $40 [000467] -A-X-------- \--* COMMA int $299 [000465] -A-X-------- +--* ASG int $VN.Void [000464] D------N---- | +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | \--* LCL_VAR ref V14 tmp3 u:2 $385 [000466] ------------ \--* LCL_VAR int V28 cse0 u:1 $299 fgMorphTree (before 298): N008 ( 6, 5) [000106] a---G--N---- * IND ref $83 N007 ( 4, 3) [000383] -------N---- \--* ADD byref $441 N005 ( 3, 2) [000375] ------------ +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000382] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 fgMorphTree (before 299): N007 ( 4, 3) [000383] -------N---- * ADD byref $441 N005 ( 3, 2) [000375] ------------ +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000382] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 fgMorphTree (before 300): N005 ( 3, 2) [000375] ------------ * LCL_VAR ref V14 tmp3 u:2 $385 fgMorphTree (after 300): N005 ( 3, 2) [000375] ------------ * LCL_VAR ref V14 tmp3 u:2 $385 fgMorphTree (before 301): N006 ( 1, 1) [000382] ------------ * CNS_INT long 16 Fseq[#FirstElem] $2c1 fgMorphTree (after 301): N006 ( 1, 1) [000382] ------------ * CNS_INT long 16 Fseq[#FirstElem] $2c1 fgMorphTree (after 299): N007 ( 4, 3) [000383] -------N---- * ADD byref $441 N005 ( 3, 2) [000375] ------------ +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000382] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 fgMorphTree (after 298): N008 ( 6, 5) [000106] a---G--N---- * IND ref $83 N007 ( 4, 3) [000383] -------N---- \--* ADD byref $441 N005 ( 3, 2) [000375] ------------ +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000382] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 fgMorphTree (after 289): N009 ( 16, 17) [000384] -A-XG--N---- * COMMA ref $VN.Void N004 ( 10, 12) [000378] -A-X-------- +--* ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ | +--* CNS_INT int 0 $40 [000467] -A-X-------- | \--* COMMA int $299 [000465] -A-X-------- | +--* ASG int $VN.Void [000464] D------N---- | | +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | | \--* LCL_VAR ref V14 tmp3 u:2 $385 [000466] ------------ | \--* LCL_VAR int V28 cse0 u:1 $299 N008 ( 6, 5) [000106] a---G--N---- \--* IND ref $83 N007 ( 4, 3) [000383] -------N---- \--* ADD byref $441 N005 ( 3, 2) [000375] ------------ +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000382] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 fgMorphTree (before 302): N010 ( 1, 1) [000105] ------------ * LCL_VAR ref V03 arg3 u:1 $83 fgMorphTree (after 302): N010 ( 1, 1) [000105] ------------ * LCL_VAR ref V03 arg3 u:1 $83 fgMorphTree (after 288): N011 ( 18, 19) [000107] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000384] -A-XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000378] -A-X-------- | +--* ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 $40 [000467] -A-X-------- | | \--* COMMA int $299 [000465] -A-X-------- | | +--* ASG int $VN.Void [000464] D------N---- | | | +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- | | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | | | \--* LCL_VAR ref V14 tmp3 u:2 $385 [000466] ------------ | | \--* LCL_VAR int V28 cse0 u:1 $299 N008 ( 6, 5) [000106] a---G--N---- | \--* IND ref $83 N007 ( 4, 3) [000383] -------N---- | \--* ADD byref $441 N005 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N010 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 optValnumCSE morphed tree: N015 ( 25, 24) [000107] -A-XG------- * ASG ref $VN.Void N013 ( 23, 22) [000384] -A-XG--N---- +--* COMMA ref $VN.Void N008 ( 17, 17) [000378] -A-X-------- | +--* ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 $40 N007 ( 12, 9) [000467] -A-X-------- | | \--* COMMA int $299 N005 ( 9, 7) [000465] -A-X----R--- | | +--* ASG int $VN.Void N004 ( 3, 2) [000464] D------N---- | | | +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- | | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | | | \--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 3, 2) [000466] ------------ | | \--* LCL_VAR int V28 cse0 u:1 $299 N012 ( 6, 5) [000106] a---G--N---- | \--* IND ref $83 N011 ( 4, 3) [000383] -------N---- | \--* ADD byref $441 N009 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N010 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N014 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 Working on the replacement of the CSE #01 use at [000387] in BB20 fgMorphTree (before 303): N011 ( 20, 20) [000112] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000394] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 $41 [000468] ------------ | | \--* LCL_VAR int V28 cse0 u:1 $3c1 N008 ( 6, 5) [000111] a---G--N---- | \--* IND ref $370 N007 ( 4, 3) [000393] -------N---- | \--* ADD byref $442 N005 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 N010 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) $370 fgMorphTree (before 304): N009 ( 16, 17) [000394] ---XG--N---- * COMMA ref $VN.Void N004 ( 10, 12) [000388] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ | +--* CNS_INT int 1 $41 [000468] ------------ | \--* LCL_VAR int V28 cse0 u:1 $3c1 N008 ( 6, 5) [000111] a---G--N---- \--* IND ref $370 N007 ( 4, 3) [000393] -------N---- \--* ADD byref $442 N005 ( 3, 2) [000385] ------------ +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000392] ------------ \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 fgMorphTree (before 305): N004 ( 10, 12) [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ +--* CNS_INT int 1 $41 [000468] ------------ \--* LCL_VAR int V28 cse0 u:1 $3c1 fgMorphTree (before 306): N001 ( 1, 1) [000109] ------------ * CNS_INT int 1 $41 fgMorphTree (after 306): N001 ( 1, 1) [000109] ------------ * CNS_INT int 1 $41 fgMorphTree (before 307): [000468] ------------ * LCL_VAR int V28 cse0 u:1 $3c1 fgMorphTree (after 307): [000468] ------------ * LCL_VAR int V28 cse0 u:1 $3c1 fgMorphTree (after 305): N004 ( 10, 12) [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ +--* CNS_INT int 1 $41 [000468] ------------ \--* LCL_VAR int V28 cse0 u:1 $3c1 fgMorphTree (before 308): N008 ( 6, 5) [000111] a---G--N---- * IND ref $370 N007 ( 4, 3) [000393] -------N---- \--* ADD byref $442 N005 ( 3, 2) [000385] ------------ +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000392] ------------ \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 fgMorphTree (before 309): N007 ( 4, 3) [000393] -------N---- * ADD byref $442 N005 ( 3, 2) [000385] ------------ +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000392] ------------ \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 fgMorphTree (before 310): N005 ( 3, 2) [000385] ------------ * LCL_VAR ref V14 tmp3 u:2 $385 fgMorphTree (after 310): N005 ( 3, 2) [000385] ------------ * LCL_VAR ref V14 tmp3 u:2 $385 fgMorphTree (before 311): N006 ( 1, 1) [000392] ------------ * CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 fgMorphTree (after 311): N006 ( 1, 1) [000392] ------------ * CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 fgMorphTree (after 309): N007 ( 4, 3) [000393] -------N---- * ADD byref $442 N005 ( 3, 2) [000385] ------------ +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000392] ------------ \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 fgMorphTree (after 308): N008 ( 6, 5) [000111] a---G--N---- * IND ref $370 N007 ( 4, 3) [000393] -------N---- \--* ADD byref $442 N005 ( 3, 2) [000385] ------------ +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000392] ------------ \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 fgMorphTree (after 304): N009 ( 16, 17) [000394] ---XG--N---- * COMMA ref $VN.Void N004 ( 10, 12) [000388] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ | +--* CNS_INT int 1 $41 [000468] ------------ | \--* LCL_VAR int V28 cse0 u:1 $3c1 N008 ( 6, 5) [000111] a---G--N---- \--* IND ref $370 N007 ( 4, 3) [000393] -------N---- \--* ADD byref $442 N005 ( 3, 2) [000385] ------------ +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000392] ------------ \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 fgMorphTree (before 312): N010 ( 3, 2) [000110] ------------ * LCL_VAR ref V10 loc4 u:2 (last use) $370 fgMorphTree (after 312): N010 ( 3, 2) [000110] ------------ * LCL_VAR ref V10 loc4 u:2 (last use) $370 fgMorphTree (after 303): N011 ( 20, 20) [000112] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000394] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 $41 [000468] ------------ | | \--* LCL_VAR int V28 cse0 u:1 $3c1 N008 ( 6, 5) [000111] a---G--N---- | \--* IND ref $370 N007 ( 4, 3) [000393] -------N---- | \--* ADD byref $442 N005 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 N010 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) $370 optValnumCSE morphed tree: N010 ( 18, 18) [000112] -A-XG------- * ASG ref $VN.Void N008 ( 14, 15) [000394] ---XG--N---- +--* COMMA ref $VN.Void N003 ( 8, 10) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 $41 N002 ( 3, 2) [000468] ------------ | | \--* LCL_VAR int V28 cse0 u:1 $3c1 N007 ( 6, 5) [000111] a---G--N---- | \--* IND ref $370 N006 ( 4, 3) [000393] -------N---- | \--* ADD byref $442 N004 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N005 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 N009 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) $370 *************** Finishing PHASE Optimize Valnum CSEs *************** Starting PHASE Assertion prop *************** In optAssertionPropMain() Blocks/Trees at start of phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB15 ( cond ) i gcsafe bwd BB11 [0034] 1 BB10 0.58 [???..???)-> BB19 (always) internal gcsafe BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 3 BB10,BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB11 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} ***** BB01 STMT00001 (IL ???... ???) N008 ( 28, 25) [000006] --CXG------- * JTRUE void N007 ( 26, 23) [000200] J-CXG--N---- \--* EQ int $280 N005 ( 24, 21) [000198] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 N003 ( 1, 1) [000000] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N004 ( 3, 10) [000279] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 N006 ( 1, 1) [000199] ------------ \--* CNS_INT int 4 $44 ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} ***** BB02 STMT00002 (IL 0x00F...0x010) N003 ( 5, 4) [000009] -A------R--- * ASG int $41 N002 ( 3, 2) [000008] D------N---- +--* LCL_VAR int V07 loc1 d:2 $41 N001 ( 1, 1) [000007] ------------ \--* CNS_INT int 1 $41 ***** BB02 STMT00004 (IL ???... ???) N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int $283 N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} ***** BB03 STMT00066 (IL ???... ???) N005 ( 0, 0) [000447] -A------R--- * ASG bool N004 ( 0, 0) [000445] D------N---- +--* LCL_VAR bool V07 loc1 d:4 N003 ( 0, 0) [000446] ------------ \--* PHI bool N001 ( 0, 0) [000450] ------------ pred BB27 +--* PHI_ARG bool V07 loc1 u:3 $40 N002 ( 0, 0) [000449] ------------ pred BB02 \--* PHI_ARG bool V07 loc1 u:2 $41 ***** BB03 STMT00005 (IL 0x040...0x046) N009 ( 29, 27) [000022] --CXG------- * JTRUE void N008 ( 27, 25) [000021] J-CXG--N---- \--* NE int $287 N006 ( 25, 23) [000019] --CXG------- +--* CAST int <- bool <- int $286 N005 ( 24, 21) [000018] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 N003 ( 1, 1) [000017] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000312] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca N007 ( 1, 1) [000020] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} ***** BB04 STMT00065 (IL ???... ???) N005 ( 0, 0) [000444] -A------R--- * ASG bool N004 ( 0, 0) [000442] D------N---- +--* LCL_VAR bool V07 loc1 d:6 N003 ( 0, 0) [000443] ------------ \--* PHI bool N001 ( 0, 0) [000452] ------------ pred BB23 +--* PHI_ARG bool V07 loc1 u:5 $40 N002 ( 0, 0) [000451] ------------ pred BB03 \--* PHI_ARG bool V07 loc1 u:4 $580 ***** BB04 STMT00006 (IL 0x055...0x05B) N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int $28b N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 $40 ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} ***** BB05 STMT00064 (IL ???... ???) N005 ( 0, 0) [000441] -A------R--- * ASG bool N004 ( 0, 0) [000439] D------N---- +--* LCL_VAR bool V07 loc1 d:8 N003 ( 0, 0) [000440] ------------ \--* PHI bool N001 ( 0, 0) [000454] ------------ pred BB18 +--* PHI_ARG bool V07 loc1 u:7 $40 N002 ( 0, 0) [000453] ------------ pred BB04 \--* PHI_ARG bool V07 loc1 u:6 $581 ***** BB05 STMT00007 (IL 0x06A...0x070) N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int $28f N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 $40 ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} ***** BB06 STMT00063 (IL ???... ???) N005 ( 0, 0) [000438] -A------R--- * ASG bool N004 ( 0, 0) [000436] D------N---- +--* LCL_VAR bool V07 loc1 d:10 N003 ( 0, 0) [000437] ------------ \--* PHI bool N001 ( 0, 0) [000456] ------------ pred BB28 +--* PHI_ARG bool V07 loc1 u:9 $40 N002 ( 0, 0) [000455] ------------ pred BB05 \--* PHI_ARG bool V07 loc1 u:8 $582 ***** BB06 STMT00009 (IL ???... ???) N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref $167 N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB06 STMT00010 (IL 0x08B...0x092) N009 ( 26, 26) [000050] -ACXG---R--- * ASG struct (copy) $VN.Void N008 ( 3, 2) [000048] D------N---- +--* LCL_VAR struct(AX) V12 tmp1 N007 ( 22, 23) [000045] --CXG------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 N004 ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long N003 ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class $1d0 N006 ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref $486 N005 ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 $4c2 ***** BB06 STMT00011 (IL ???... ???) N016 ( 18, 15) [000355] -A-XG------- * COMMA void N009 ( 10, 8) [000348] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref $487 N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref $487 N001 ( 3, 2) [000341] -------N---- | | \--* LCL_VAR struct(AX) V12 tmp1 $4c3 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 N015 ( 8, 7) [000354] -A-XG---R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] ---X-------- \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 ***** BB06 STMT00057 (IL 0x0E1... ???) N011 ( 27, 29) [000419] --CXG------- * JTRUE void N010 ( 25, 27) [000409] J-CXG--N---- \--* NE int $295 N008 ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int $294 N007 ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $212 N004 ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref $48a N005 ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c4 N009 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} ***** BB07 STMT00061 (IL ???... ???) N005 ( 0, 0) [000432] -A------R--- * ASG bool N004 ( 0, 0) [000430] D------N---- +--* LCL_VAR bool V07 loc1 d:14 N003 ( 0, 0) [000431] ------------ \--* PHI bool N001 ( 0, 0) [000461] ------------ pred BB16 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 $583 ***** BB07 STMT00026 (IL 0x0EA...0x0EB) N003 ( 7, 5) [000127] -A------R--- * ASG int $584 N002 ( 3, 2) [000126] D------N---- +--* LCL_VAR int V06 loc0 d:4 $584 N001 ( 3, 2) [000125] ------------ \--* LCL_VAR int V07 loc1 u:14 (last use) $584 ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} ***** BB08 STMT00059 (IL ???... ???) N005 ( 0, 0) [000426] -A------R--- * ASG bool N004 ( 0, 0) [000424] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000425] ------------ \--* PHI bool N001 ( 0, 0) [000463] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:4 $584 N002 ( 0, 0) [000448] ------------ pred BB24 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB08 STMT00027 (IL 0x0EC...0x0ED) N002 ( 4, 3) [000129] ------------ * RETURN int $214 N001 ( 3, 2) [000128] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) $585 ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} ***** BB09 STMT00062 (IL ???... ???) N005 ( 0, 0) [000435] -A------R--- * ASG bool N004 ( 0, 0) [000433] D------N---- +--* LCL_VAR bool V07 loc1 d:11 N003 ( 0, 0) [000434] ------------ \--* PHI bool N001 ( 0, 0) [000460] ------------ pred BB15 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 $583 ***** BB09 STMT00013 (IL 0x095...0x0A7) N017 ( 59, 54) [000073] -ACXG---R--- * ASG struct (copy) $VN.Void N016 ( 3, 2) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 d:2 N015 ( 55, 51) [000070] --CXG------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 N009 ( 26, 26) [000360] -ACXG---R-L- this SETUP +--* ASG ref $16c N008 ( 3, 2) [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 d:2 $16c N007 ( 22, 23) [000066] --CXG------- | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c N004 ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref $48c N005 ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c5 N012 ( 3, 2) [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 u:2 (last use) $16c N013 ( 3, 2) [000069] ------------ arg2 in rsi +--* LCL_VAR ref V01 arg1 u:1 $81 N014 ( 3, 10) [000356] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 ***** BB09 STMT00014 (IL ???... ???) N003 ( 7, 7) [000078] -A------R--- * ASG ref $370 N002 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V10 loc4 d:2 $370 N001 ( 3, 4) [000076] ------------ \--* LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) $370 ***** BB09 STMT00046 (IL 0x0A9... ???) N008 ( 30, 26) [000228] --CXG------- * JTRUE void N007 ( 28, 24) [000249] J-CXG--N---- \--* NE int $296 N005 ( 26, 22) [000247] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 N003 ( 3, 2) [000080] ------------ this in rdi | +--* LCL_VAR ref V10 loc4 u:2 $370 N004 ( 3, 10) [000365] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 N006 ( 1, 1) [000248] ------------ \--* CNS_INT int 4 $44 ------------ BB10 [0A9..0AA) -> BB15 (cond), preds={BB09} succs={BB11,BB15} ***** BB10 STMT00049 (IL 0x0A9... ???) N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void N003 ( 3, 2) [000237] ------------ arg0 in rdi +--* LCL_VAR ref V10 loc4 u:2 $370 N004 ( 1, 1) [000238] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB10 STMT00050 (IL 0x0A9... ???) N003 ( 5, 4) [000242] -A------R--- * ASG bool $40 N002 ( 3, 2) [000241] D------N---- +--* LCL_VAR int V19 tmp8 d:3 $40 N001 ( 1, 1) [000240] ------------ \--* CNS_INT int 0 $40 ***** BB10 STMT00058 (IL ???... ???) N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] J------N---- \--* NE int $40 N001 ( 3, 2) [000422] ------------ +--* LCL_VAR int V19 tmp8 u:3 (last use) $40 N002 ( 1, 1) [000423] ------------ \--* CNS_INT int 0 $40 ------------ BB11 [???..???) -> BB19 (always), preds={BB10} succs={BB19} ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} ***** BB12 STMT00028 (IL 0x072...0x07E) N015 ( 28, 23) [000139] --CXG------- * JTRUE void N014 ( 26, 21) [000138] J-CXG--N---- \--* EQ int $291 N012 ( 24, 19) [000136] --CXG------- +--* CAST int <- bool <- int $290 N011 ( 23, 17) [000135] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f N006 ( 3, 2) [000130] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 (last use) $80 N007 ( 1, 1) [000131] ------------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 u:1 $82 N008 ( 1, 1) [000132] ------------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 u:1 $83 N009 ( 3, 2) [000133] ------------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 u:1 $84 N010 ( 1, 1) [000134] ------------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 u:1 $c0 N013 ( 1, 1) [000137] ------------ \--* CNS_INT int 0 $40 ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} ***** BB14 STMT00048 (IL 0x0A9... ???) N010 ( 24, 17) [000234] -ACXG---R--- * ASG bool $297 N009 ( 3, 2) [000233] D------N---- +--* LCL_VAR int V19 tmp8 d:2 $297 N008 ( 20, 14) [000232] --CXG------- \--* CAST int <- bool <- int $297 N007 ( 19, 12) [000230] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 N004 ( 1, 1) [000079] ------------ arg0 in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 2) [000229] ------------ arg1 in rsi +--* LCL_VAR ref V10 loc4 u:2 $370 N006 ( 1, 1) [000081] ------------ arg2 in rdx \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB14 STMT00016 (IL ???... ???) N004 ( 7, 6) [000087] ------------ * JTRUE void N003 ( 5, 4) [000086] J------N---- \--* EQ int $298 N001 ( 3, 2) [000235] ------------ +--* LCL_VAR int V19 tmp8 u:2 (last use) $297 N002 ( 1, 1) [000085] ------------ \--* CNS_INT int 0 $40 ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB10,BB14,BB21} succs={BB16,BB09} ***** BB15 STMT00060 (IL ???... ???) N005 ( 0, 0) [000429] -A------R--- * ASG bool N004 ( 0, 0) [000427] D------N---- +--* LCL_VAR bool V07 loc1 d:13 N003 ( 0, 0) [000428] ------------ \--* PHI bool N001 ( 0, 0) [000462] ------------ pred BB14 +--* PHI_ARG bool V07 loc1 u:11 $586 N002 ( 0, 0) [000459] ------------ pred BB21 \--* PHI_ARG bool V07 loc1 u:12 $40 ***** BB15 STMT00012 (IL 0x0E1...0x0E8) N011 ( 27, 29) [000063] --CXG------- * JTRUE void N010 ( 25, 27) [000062] J-CXG--N---- \--* NE int $29b N008 ( 23, 25) [000060] --CXG------- +--* CAST int <- bool <- int $29a N007 ( 22, 23) [000057] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $21b N004 ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref $490 N005 ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c6 N009 ( 1, 1) [000061] ------------ \--* CNS_INT int 0 $40 ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} ***** BB17 STMT00031 (IL ???... ???) N011 ( 24, 18) [000151] --CXG------- * JTRUE void N010 ( 22, 16) [000150] J-CXG--N---- \--* NE int $28d N008 ( 20, 14) [000148] --CXG------- +--* CAST int <- bool <- int $28c N007 ( 19, 12) [000146] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c N004 ( 1, 1) [000143] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000144] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000145] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 $84 N009 ( 1, 1) [000149] ------------ \--* CNS_INT int 0 $40 ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} ***** BB18 STMT00032 (IL 0x068...0x069) N003 ( 5, 4) [000154] -A------R--- * ASG int $40 N002 ( 3, 2) [000153] D------N---- +--* LCL_VAR int V07 loc1 d:7 $40 N001 ( 1, 1) [000152] ------------ \--* CNS_INT int 0 $40 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB11} succs={BB20,BB21} ***** BB19 STMT00017 (IL 0x0B5...0x0B7) N004 ( 7, 6) [000091] ------------ * JTRUE void N003 ( 5, 4) [000090] J------N---- \--* EQ int $284 N001 ( 3, 2) [000088] ------------ +--* LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000089] ------------ \--* CNS_INT ref null $VN.Null ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} ***** BB20 STMT00019 (IL 0x0B9...0x0CA) N005 ( 19, 10) [000101] -ACXG---R--- * ASG ref $376 N004 ( 3, 2) [000100] D------N---- +--* LCL_VAR ref V14 tmp3 d:2 $385 N003 ( 15, 7) [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 N002 ( 1, 1) [000098] ------------ arg0 in rdi \--* CNS_INT long 2 $2c4 ***** BB20 STMT00020 (IL ???... ???) N015 ( 25, 24) [000107] -A-XG------- * ASG ref $VN.Void N013 ( 23, 22) [000384] -A-XG--N---- +--* COMMA ref $VN.Void N008 ( 17, 17) [000378] -A-X-------- | +--* ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 $40 N007 ( 12, 9) [000467] -A-X-------- | | \--* COMMA int $299 N005 ( 9, 7) [000465] -A-X----R--- | | +--* ASG int $VN.Void N004 ( 3, 2) [000464] D------N---- | | | +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- | | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | | | \--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 3, 2) [000466] ------------ | | \--* LCL_VAR int V28 cse0 u:1 $299 N012 ( 6, 5) [000106] a---G--N---- | \--* IND ref $83 N011 ( 4, 3) [000383] -------N---- | \--* ADD byref $441 N009 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N010 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N014 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 ***** BB20 STMT00021 (IL ???...0x0CF) N010 ( 18, 18) [000112] -A-XG------- * ASG ref $VN.Void N008 ( 14, 15) [000394] ---XG--N---- +--* COMMA ref $VN.Void N003 ( 8, 10) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 $41 N002 ( 3, 2) [000468] ------------ | | \--* LCL_VAR int V28 cse0 u:1 $3c1 N007 ( 6, 5) [000111] a---G--N---- | \--* IND ref $370 N006 ( 4, 3) [000393] -------N---- | \--* ADD byref $442 N004 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N005 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 N009 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) $370 ***** BB20 STMT00052 (IL ???... ???) N003 ( 18, 8) [000261] -AC-----R--- * ASG ref $647 N002 ( 3, 2) [000260] D------N---- +--* LCL_VAR ref V20 tmp9 d:2 $647 N001 ( 14, 5) [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 ***** BB20 STMT00053 (IL ???... ???) N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N007 ( 21, 14) [000396] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 d:2 N005 ( 17, 11) [000255] --CXG------- | \--* IND ref N004 ( 15, 9) [000254] --CXG--N---- | \--* ADD byref $403 N002 ( 14, 5) [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] $48 N010 ( 3, 2) [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 u:2 $647 N012 ( 3, 2) [000102] ------------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 u:2 (last use) $385 N013 ( 1, 4) [000256] ------------ arg2 in rdx \--* CNS_INT int 0x7D2C $64 ***** BB20 STMT00054 (IL ???... ???) N003 ( 5, 4) [000269] IA------R--- * ASG struct (init) $VN.Void N002 ( 3, 2) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 d:2 N001 ( 1, 1) [000268] ------------ \--* CNS_INT int 0 $40 ***** BB20 STMT00055 (IL ???... ???) N003 ( 5, 6) [000273] -A------R--- * ASG ref $82 N002 ( 3, 4) [000272] U------N---- +--* LCL_FLD ref V15 tmp4 ud:2->3[+0] Fseq[TypeParameter] $38c N001 ( 1, 1) [000096] ------------ \--* LCL_VAR ref V02 arg2 u:1 $82 ***** BB20 STMT00056 (IL ???... ???) N003 ( 7, 7) [000277] -A------R--- * ASG ref $647 N002 ( 3, 4) [000276] U------N---- +--* LCL_FLD ref V15 tmp4 ud:3->4[+8] Fseq[DiagnosticInfo] $38d N001 ( 3, 2) [000264] ------------ \--* LCL_VAR ref V20 tmp9 u:2 (last use) $647 ***** BB20 STMT00025 (IL 0x0DA... ???) N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct $507 N004 ( 3, 3) [000123] ------------ | \--* ADDR byref $40b N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} ***** BB21 STMT00018 (IL 0x0DF...0x0E0) N003 ( 5, 4) [000094] -A------R--- * ASG int $40 N002 ( 3, 2) [000093] D------N---- +--* LCL_VAR int V07 loc1 d:12 $40 N001 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 $40 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} ***** BB22 STMT00033 (IL 0x048...0x051) N011 ( 24, 18) [000162] --CXG------- * JTRUE void N010 ( 22, 16) [000161] J-CXG--N---- \--* NE int $289 N008 ( 20, 14) [000159] --CXG------- +--* CAST int <- bool <- int $288 N007 ( 19, 12) [000158] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 N004 ( 1, 1) [000155] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000156] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000157] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 $84 N009 ( 1, 1) [000160] ------------ \--* CNS_INT int 0 $40 ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} ***** BB23 STMT00034 (IL 0x053...0x054) N003 ( 5, 4) [000165] -A------R--- * ASG int $40 N002 ( 3, 2) [000164] D------N---- +--* LCL_VAR int V07 loc1 d:5 $40 N001 ( 1, 1) [000163] ------------ \--* CNS_INT int 0 $40 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} ***** BB24 STMT00042 (IL 0x008...0x009) N003 ( 5, 4) [000197] -A------R--- * ASG int $41 N002 ( 3, 2) [000196] D------N---- +--* LCL_VAR int V06 loc0 d:2 $41 N001 ( 1, 1) [000195] ------------ \--* CNS_INT int 1 $41 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} ***** BB25 STMT00035 (IL 0x019...0x01B) N004 ( 7, 6) [000169] ------------ * JTRUE void N003 ( 5, 4) [000168] J------N---- \--* EQ int $284 N001 ( 3, 2) [000166] ------------ +--* LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000167] ------------ \--* CNS_INT ref null $VN.Null ------------ BB26 [01D..03E), preds={BB25} succs={BB27} ***** BB26 STMT00037 (IL 0x01D...0x02E) N005 ( 19, 10) [000179] -ACXG---R--- * ASG ref $342 N004 ( 3, 2) [000178] D------N---- +--* LCL_VAR ref V16 tmp5 d:2 $380 N003 ( 15, 7) [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 N002 ( 1, 1) [000176] ------------ arg0 in rdi \--* CNS_INT long 1 $2c0 ***** BB26 STMT00038 (IL ???... ???) N011 ( 18, 19) [000185] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000298] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000292] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $348 N001 ( 1, 1) [000182] ------------ | | +--* CNS_INT int 0 $40 N003 ( 5, 4) [000291] ---X-------- | | \--* ARR_LENGTH int $285 N002 ( 3, 2) [000181] ------------ | | \--* LCL_VAR ref V16 tmp5 u:2 $380 N008 ( 6, 5) [000184] a---G--N---- | \--* IND ref $83 N007 ( 4, 3) [000297] -------N---- | \--* ADD byref $440 N005 ( 3, 2) [000289] ------------ | +--* LCL_VAR ref V16 tmp5 u:2 $380 N006 ( 1, 1) [000296] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N010 ( 1, 1) [000183] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 ***** BB26 STMT00043 (IL ???... ???) N003 ( 18, 8) [000216] -AC-----R--- * ASG ref $34c N002 ( 3, 2) [000215] D------N---- +--* LCL_VAR ref V18 tmp7 d:2 $34c N001 ( 14, 5) [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c ***** BB26 STMT00044 (IL ???... ???) N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N007 ( 21, 14) [000300] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 d:2 N005 ( 17, 11) [000210] --CXG------- | \--* IND ref N004 ( 15, 9) [000209] --CXG--N---- | \--* ADD byref $403 N002 ( 14, 5) [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] $48 N010 ( 3, 2) [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 u:2 $34c N012 ( 3, 2) [000180] ------------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 u:2 (last use) $380 N013 ( 1, 4) [000211] ------------ arg2 in rdx \--* CNS_INT int 0x7AA4 $49 ***** BB26 STMT00040 (IL ???... ???) N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void N004 ( 3, 3) [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 $481 N005 ( 1, 1) [000174] ------------ arg1 in rsi +--* LCL_VAR ref V02 arg2 u:1 $82 N006 ( 3, 2) [000219] ------------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 u:2 (last use) $34c ***** BB26 STMT00041 (IL 0x039... ???) N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 $4c0 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} ***** BB27 STMT00036 (IL 0x03E...0x03F) N003 ( 5, 4) [000172] -A------R--- * ASG int $40 N002 ( 3, 2) [000171] D------N---- +--* LCL_VAR int V07 loc1 d:3 $40 N001 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 $40 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} ***** BB28 STMT00029 (IL 0x080...0x081) N003 ( 5, 4) [000142] -A------R--- * ASG int $40 N002 ( 3, 2) [000141] D------N---- +--* LCL_VAR int V07 loc1 d:9 $40 N001 ( 1, 1) [000140] ------------ \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- GenTreeNode creates assertion: N005 ( 24, 21) [000198] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 In BB01 New Global Constant Assertion: (131, 0) ($83,$0) V03.01 != null index=#01, mask=0000000000000001 GenTreeNode creates assertion: N005 ( 24, 21) [000018] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 In BB03 New Global Constant Assertion: (130, 0) ($82,$0) V02.01 != null index=#02, mask=0000000000000002 GenTreeNode creates assertion: N006 ( 3, 2) [000346] ---X-------- * IND ref In BB06 New Global Constant Assertion: (1159, 0) ($487,$0) Value_Number {487} is not 0 index=#03, mask=0000000000000004 GenTreeNode creates assertion: N015 ( 55, 51) [000070] --CXG------- * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 In BB09 New Global Constant Assertion: (364, 0) ($16c,$0) V26.02 != null index=#04, mask=0000000000000008 GenTreeNode creates assertion: N005 ( 26, 22) [000247] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 In BB09 New Global Constant Assertion: (880, 0) ($370,$0) V10.02 != null index=#05, mask=0000000000000010 After constant propagation on [000420]: STMT00058 (IL ???... ???) N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] J------N---- \--* NE int $40 [000469] ------------ +--* CNS_INT int 0 $40 [000470] ------------ \--* CNS_INT int 0 $40 fgMorphTree (before 313): N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] J------N---- \--* NE int $40 [000469] ------------ +--* CNS_INT int 0 $40 [000470] ------------ \--* CNS_INT int 0 $40 fgMorphTree (before 314): N003 ( 5, 4) [000421] J------N---- * NE int $40 [000469] ------------ +--* CNS_INT int 0 $40 [000470] ------------ \--* CNS_INT int 0 $40 fgMorphTree (before 315): [000469] ------------ * CNS_INT int 0 $40 fgMorphTree (after 315): [000469] ------------ * CNS_INT int 0 $40 fgMorphTree (before 316): [000470] ------------ * CNS_INT int 0 $40 fgMorphTree (after 316): [000470] ------------ * CNS_INT int 0 $40 Folding operator with constant nodes into a constant: N003 ( 5, 4) [000421] J------N---- * NE int $40 [000469] ------------ +--* CNS_INT int 0 $40 [000470] ------------ \--* CNS_INT int 0 $40 Bashed to int constant: N003 ( 5, 4) [000421] ------------ * CNS_INT int 0 $40 fgMorphTree (after 314): N003 ( 5, 4) [000421] ------------ * CNS_INT int 0 $40 fgMorphTree (after 313): N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] ------------ \--* CNS_INT int 0 $40 Removing statement STMT00058 (IL ???... ???) N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] ------------ \--* CNS_INT int 0 $40 in BB10 as useless: Conditional folded at BB10 BB10 becomes a BBJ_NONE optVNAssertionPropCurStmt removed tree: N004 ( 7, 6) [000420] ------------ * JTRUE void N003 ( 5, 4) [000421] ------------ \--* CNS_INT int 0 $40 GenTreeNode creates assertion: N004 ( 7, 6) [000087] ------------ * JTRUE void In BB14 New Global Constant Assertion: (663, 64) ($297,$40) V19.02 == 0 index=#06, mask=0000000000000020 GenTreeNode creates assertion: N004 ( 7, 6) [000087] ------------ * JTRUE void In BB14 New Global Constant Assertion: (663, 64) ($297,$40) V19.02 != 0 index=#07, mask=0000000000000040 GenTreeNode creates assertion: N004 ( 7, 6) [000091] ------------ * JTRUE void In BB19 New Global Constant Assertion: (132, 0) ($84,$0) V04.01 == null index=#08, mask=0000000000000080 GenTreeNode creates assertion: N004 ( 7, 6) [000091] ------------ * JTRUE void In BB19 New Global Constant Assertion: (132, 0) ($84,$0) V04.01 != null index=#09, mask=0000000000000100 GenTreeNode creates assertion: N003 ( 5, 4) [000377] ---X-------- * ARR_LENGTH int $299 In BB20 New Global Constant Assertion: (901, 0) ($385,$0) V14.02 != null index=#10, mask=0000000000000200 GenTreeNode creates assertion: N008 ( 17, 17) [000378] -A-X-------- * ARR_BOUNDS_CHECK_Rng void $37c In BB20 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {IntCns 0};len: {ARR_LENGTH($385)}] in range index=#11, mask=0000000000000400 GenTreeNode creates assertion: N003 ( 8, 10) [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void $645 In BB20 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {IntCns 1};len: {ARR_LENGTH($385)}] in range index=#12, mask=0000000000000800 GenTreeNode creates assertion: N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void In BB20 New Global Constant Assertion: (132, 0) ($84,$0) V04.01 != null index=#13, mask=0000000000001000 GenTreeNode creates assertion: N003 ( 5, 4) [000291] ---X-------- * ARR_LENGTH int $285 In BB26 New Global Constant Assertion: (896, 0) ($380,$0) V16.02 != null index=#14, mask=0000000000002000 GenTreeNode creates assertion: N004 ( 10, 12) [000292] ---X-------- * ARR_BOUNDS_CHECK_Rng void $348 In BB26 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {IntCns 0};len: {ARR_LENGTH($380)}] in range index=#15, mask=0000000000004000 BB01 valueGen = 0000000000000001 => BB24 valueGen = 0000000000000001, BB02 valueGen = 0000000000000001 => BB25 valueGen = 0000000000000001, BB03 valueGen = 0000000000000002 => BB22 valueGen = 0000000000000002, BB04 valueGen = 0000000000000002 => BB17 valueGen = 0000000000000002, BB05 valueGen = 0000000000000002 => BB12 valueGen = 0000000000000002, BB06 valueGen = 0000000000000006 => BB09 valueGen = 0000000000000006, BB07 valueGen = 0000000000000000 BB08 valueGen = 0000000000000000 BB09 valueGen = 0000000000000018 => BB14 valueGen = 0000000000000018, BB10 valueGen = 0000000000000000 BB11 valueGen = 0000000000000000 BB12 valueGen = 0000000000000000 => BB28 valueGen = 0000000000000000, BB13 valueGen = 0000000000000000 BB14 valueGen = 0000000000000040 => BB19 valueGen = 0000000000000020, BB15 valueGen = 0000000000000000 => BB09 valueGen = 0000000000000000, BB16 valueGen = 0000000000000000 BB17 valueGen = 0000000000000000 => BB05 valueGen = 0000000000000000, BB18 valueGen = 0000000000000000 BB19 valueGen = 0000000000000100 => BB21 valueGen = 0000000000000080, BB20 valueGen = 0000000000001E00 BB21 valueGen = 0000000000000000 BB22 valueGen = 0000000000000000 => BB04 valueGen = 0000000000000000, BB23 valueGen = 0000000000000000 BB24 valueGen = 0000000000000000 BB25 valueGen = 0000000000000100 => BB27 valueGen = 0000000000000080, BB26 valueGen = 0000000000007000 BB27 valueGen = 0000000000000000 BB28 valueGen = 0000000000000000 AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000 AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000 AssertionPropCallback::Changed : BB01 before out -> 0000000000007FFF; after out -> 0000000000000001; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000001; AssertionPropCallback::StartMerge: BB02 in -> 0000000000007FFF AssertionPropCallback::Merge : BB02 in -> 0000000000007FFF, predBlock BB01 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB02 in -> 0000000000000001 AssertionPropCallback::Changed : BB02 before out -> 0000000000007FFF; after out -> 0000000000000001; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000001; AssertionPropCallback::StartMerge: BB24 in -> 0000000000007FFF AssertionPropCallback::Merge : BB24 in -> 0000000000007FFF, predBlock BB01 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB24 in -> 0000000000000001 AssertionPropCallback::Changed : BB24 before out -> 0000000000007FFF; after out -> 0000000000000001; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000001; AssertionPropCallback::StartMerge: BB03 in -> 0000000000007FFF AssertionPropCallback::Merge : BB03 in -> 0000000000007FFF, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::Merge : BB03 in -> 0000000000000001, predBlock BB27 out -> 0000000000007FFF AssertionPropCallback::EndMerge : BB03 in -> 0000000000000001 AssertionPropCallback::Changed : BB03 before out -> 0000000000007FFF; after out -> 0000000000000003; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB25 in -> 0000000000007FFF AssertionPropCallback::Merge : BB25 in -> 0000000000007FFF, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB25 in -> 0000000000000001 AssertionPropCallback::Changed : BB25 before out -> 0000000000007FFF; after out -> 0000000000000101; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000081; AssertionPropCallback::StartMerge: BB08 in -> 0000000000007FFF AssertionPropCallback::Merge : BB08 in -> 0000000000007FFF, predBlock BB24 out -> 0000000000000001 AssertionPropCallback::Merge : BB08 in -> 0000000000000001, predBlock BB07 out -> 0000000000007FFF AssertionPropCallback::EndMerge : BB08 in -> 0000000000000001 AssertionPropCallback::Changed : BB08 before out -> 0000000000007FFF; after out -> 0000000000000001; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000001; AssertionPropCallback::StartMerge: BB04 in -> 0000000000007FFF AssertionPropCallback::Merge : BB04 in -> 0000000000007FFF, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB04 in -> 0000000000000003, predBlock BB22 out -> 0000000000007FFF AssertionPropCallback::Merge : BB04 in -> 0000000000000003, predBlock BB23 out -> 0000000000007FFF AssertionPropCallback::EndMerge : BB04 in -> 0000000000000003 AssertionPropCallback::Changed : BB04 before out -> 0000000000007FFF; after out -> 0000000000000003; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB22 in -> 0000000000007FFF AssertionPropCallback::Merge : BB22 in -> 0000000000007FFF, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB22 in -> 0000000000000003 AssertionPropCallback::Changed : BB22 before out -> 0000000000007FFF; after out -> 0000000000000003; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB26 in -> 0000000000007FFF AssertionPropCallback::Merge : BB26 in -> 0000000000007FFF, predBlock BB25 out -> 0000000000000101 AssertionPropCallback::EndMerge : BB26 in -> 0000000000000101 AssertionPropCallback::Changed : BB26 before out -> 0000000000007FFF; after out -> 0000000000007101; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000101; AssertionPropCallback::StartMerge: BB27 in -> 0000000000007FFF AssertionPropCallback::Merge : BB27 in -> 0000000000007FFF, predBlock BB25 out -> 0000000000000101 AssertionPropCallback::Merge : BB27 in -> 0000000000000081, predBlock BB26 out -> 0000000000007101 AssertionPropCallback::EndMerge : BB27 in -> 0000000000000001 AssertionPropCallback::Changed : BB27 before out -> 0000000000007FFF; after out -> 0000000000000001; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000001; AssertionPropCallback::StartMerge: BB05 in -> 0000000000007FFF AssertionPropCallback::Merge : BB05 in -> 0000000000007FFF, predBlock BB04 out -> 0000000000000003 AssertionPropCallback::Merge : BB05 in -> 0000000000000003, predBlock BB17 out -> 0000000000007FFF AssertionPropCallback::Merge : BB05 in -> 0000000000000003, predBlock BB18 out -> 0000000000007FFF AssertionPropCallback::EndMerge : BB05 in -> 0000000000000003 AssertionPropCallback::Changed : BB05 before out -> 0000000000007FFF; after out -> 0000000000000003; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB17 in -> 0000000000007FFF AssertionPropCallback::Merge : BB17 in -> 0000000000007FFF, predBlock BB04 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB17 in -> 0000000000000003 AssertionPropCallback::Changed : BB17 before out -> 0000000000007FFF; after out -> 0000000000000003; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB23 in -> 0000000000007FFF AssertionPropCallback::Merge : BB23 in -> 0000000000007FFF, predBlock BB22 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB23 in -> 0000000000000003 AssertionPropCallback::Changed : BB23 before out -> 0000000000007FFF; after out -> 0000000000000003; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB04 in -> 0000000000000003 AssertionPropCallback::Merge : BB04 in -> 0000000000000003, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB04 in -> 0000000000000003, predBlock BB22 out -> 0000000000000003 AssertionPropCallback::Merge : BB04 in -> 0000000000000003, predBlock BB23 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB04 in -> 0000000000000003 AssertionPropCallback::Unchanged : BB04 out -> 0000000000000003; jumpDest out -> 0000000000000003 AssertionPropCallback::StartMerge: BB27 in -> 0000000000000001 AssertionPropCallback::Merge : BB27 in -> 0000000000000001, predBlock BB25 out -> 0000000000000101 AssertionPropCallback::Merge : BB27 in -> 0000000000000001, predBlock BB26 out -> 0000000000007101 AssertionPropCallback::EndMerge : BB27 in -> 0000000000000001 AssertionPropCallback::Unchanged : BB27 out -> 0000000000000001; jumpDest out -> 0000000000000001 AssertionPropCallback::StartMerge: BB03 in -> 0000000000000001 AssertionPropCallback::Merge : BB03 in -> 0000000000000001, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::Merge : BB03 in -> 0000000000000001, predBlock BB27 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB03 in -> 0000000000000001 AssertionPropCallback::Unchanged : BB03 out -> 0000000000000003; jumpDest out -> 0000000000000003 AssertionPropCallback::StartMerge: BB06 in -> 0000000000007FFF AssertionPropCallback::Merge : BB06 in -> 0000000000007FFF, predBlock BB05 out -> 0000000000000003 AssertionPropCallback::Merge : BB06 in -> 0000000000000003, predBlock BB13 out -> 0000000000007FFF AssertionPropCallback::Merge : BB06 in -> 0000000000000003, predBlock BB28 out -> 0000000000007FFF AssertionPropCallback::EndMerge : BB06 in -> 0000000000000003 AssertionPropCallback::Changed : BB06 before out -> 0000000000007FFF; after out -> 0000000000000007; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000007; AssertionPropCallback::StartMerge: BB12 in -> 0000000000007FFF AssertionPropCallback::Merge : BB12 in -> 0000000000007FFF, predBlock BB05 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB12 in -> 0000000000000003 AssertionPropCallback::Changed : BB12 before out -> 0000000000007FFF; after out -> 0000000000000003; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB18 in -> 0000000000007FFF AssertionPropCallback::Merge : BB18 in -> 0000000000007FFF, predBlock BB17 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB18 in -> 0000000000000003 AssertionPropCallback::Changed : BB18 before out -> 0000000000007FFF; after out -> 0000000000000003; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB05 in -> 0000000000000003 AssertionPropCallback::Merge : BB05 in -> 0000000000000003, predBlock BB04 out -> 0000000000000003 AssertionPropCallback::Merge : BB05 in -> 0000000000000003, predBlock BB17 out -> 0000000000000003 AssertionPropCallback::Merge : BB05 in -> 0000000000000003, predBlock BB18 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB05 in -> 0000000000000003 AssertionPropCallback::Unchanged : BB05 out -> 0000000000000003; jumpDest out -> 0000000000000003 AssertionPropCallback::StartMerge: BB04 in -> 0000000000000003 AssertionPropCallback::Merge : BB04 in -> 0000000000000003, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB04 in -> 0000000000000003, predBlock BB22 out -> 0000000000000003 AssertionPropCallback::Merge : BB04 in -> 0000000000000003, predBlock BB23 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB04 in -> 0000000000000003 AssertionPropCallback::Unchanged : BB04 out -> 0000000000000003; jumpDest out -> 0000000000000003 AssertionPropCallback::StartMerge: BB07 in -> 0000000000007FFF AssertionPropCallback::Merge : BB07 in -> 0000000000007FFF, predBlock BB06 out -> 0000000000000007 AssertionPropCallback::Merge : BB07 in -> 0000000000000007, predBlock BB16 out -> 0000000000007FFF AssertionPropCallback::EndMerge : BB07 in -> 0000000000000007 AssertionPropCallback::Changed : BB07 before out -> 0000000000007FFF; after out -> 0000000000000007; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000007; AssertionPropCallback::StartMerge: BB09 in -> 0000000000007FFF AssertionPropCallback::Merge : BB09 in -> 0000000000007FFF, predBlock BB06 out -> 0000000000000007 AssertionPropCallback::Merge : BB09 in -> 0000000000000007, predBlock BB15 out -> 0000000000007FFF AssertionPropCallback::EndMerge : BB09 in -> 0000000000000007 AssertionPropCallback::Changed : BB09 before out -> 0000000000007FFF; after out -> 000000000000001F; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 000000000000001F; AssertionPropCallback::StartMerge: BB13 in -> 0000000000007FFF AssertionPropCallback::Merge : BB13 in -> 0000000000007FFF, predBlock BB12 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB13 in -> 0000000000000003 AssertionPropCallback::Changed : BB13 before out -> 0000000000007FFF; after out -> 0000000000000003; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB28 in -> 0000000000007FFF AssertionPropCallback::Merge : BB28 in -> 0000000000007FFF, predBlock BB12 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB28 in -> 0000000000000003 AssertionPropCallback::Changed : BB28 before out -> 0000000000007FFF; after out -> 0000000000000003; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB05 in -> 0000000000000003 AssertionPropCallback::Merge : BB05 in -> 0000000000000003, predBlock BB04 out -> 0000000000000003 AssertionPropCallback::Merge : BB05 in -> 0000000000000003, predBlock BB17 out -> 0000000000000003 AssertionPropCallback::Merge : BB05 in -> 0000000000000003, predBlock BB18 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB05 in -> 0000000000000003 AssertionPropCallback::Unchanged : BB05 out -> 0000000000000003; jumpDest out -> 0000000000000003 AssertionPropCallback::StartMerge: BB08 in -> 0000000000000001 AssertionPropCallback::Merge : BB08 in -> 0000000000000001, predBlock BB24 out -> 0000000000000001 AssertionPropCallback::Merge : BB08 in -> 0000000000000001, predBlock BB07 out -> 0000000000000007 AssertionPropCallback::EndMerge : BB08 in -> 0000000000000001 AssertionPropCallback::Unchanged : BB08 out -> 0000000000000001; jumpDest out -> 0000000000000001 AssertionPropCallback::StartMerge: BB10 in -> 0000000000007FFF AssertionPropCallback::Merge : BB10 in -> 0000000000007FFF, predBlock BB09 out -> 000000000000001F AssertionPropCallback::EndMerge : BB10 in -> 000000000000001F AssertionPropCallback::Changed : BB10 before out -> 0000000000007FFF; after out -> 000000000000001F; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 000000000000001F; AssertionPropCallback::StartMerge: BB14 in -> 0000000000007FFF AssertionPropCallback::Merge : BB14 in -> 0000000000007FFF, predBlock BB09 out -> 000000000000001F AssertionPropCallback::EndMerge : BB14 in -> 000000000000001F AssertionPropCallback::Changed : BB14 before out -> 0000000000007FFF; after out -> 000000000000005F; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 000000000000003F; AssertionPropCallback::StartMerge: BB06 in -> 0000000000000003 AssertionPropCallback::Merge : BB06 in -> 0000000000000003, predBlock BB05 out -> 0000000000000003 AssertionPropCallback::Merge : BB06 in -> 0000000000000003, predBlock BB13 out -> 0000000000000003 AssertionPropCallback::Merge : BB06 in -> 0000000000000003, predBlock BB28 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB06 in -> 0000000000000003 AssertionPropCallback::Unchanged : BB06 out -> 0000000000000007; jumpDest out -> 0000000000000007 AssertionPropCallback::StartMerge: BB06 in -> 0000000000000003 AssertionPropCallback::Merge : BB06 in -> 0000000000000003, predBlock BB05 out -> 0000000000000003 AssertionPropCallback::Merge : BB06 in -> 0000000000000003, predBlock BB13 out -> 0000000000000003 AssertionPropCallback::Merge : BB06 in -> 0000000000000003, predBlock BB28 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB06 in -> 0000000000000003 AssertionPropCallback::Unchanged : BB06 out -> 0000000000000007; jumpDest out -> 0000000000000007 AssertionPropCallback::StartMerge: BB11 in -> 0000000000007FFF AssertionPropCallback::Merge : BB11 in -> 0000000000007FFF, predBlock BB10 out -> 000000000000001F AssertionPropCallback::EndMerge : BB11 in -> 000000000000001F AssertionPropCallback::Changed : BB11 before out -> 0000000000007FFF; after out -> 000000000000001F; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 000000000000001F; AssertionPropCallback::StartMerge: BB15 in -> 0000000000007FFF AssertionPropCallback::Merge : BB15 in -> 0000000000007FFF, predBlock BB14 out -> 000000000000005F AssertionPropCallback::Merge : BB15 in -> 000000000000005F, predBlock BB21 out -> 0000000000007FFF AssertionPropCallback::EndMerge : BB15 in -> 000000000000005F AssertionPropCallback::Changed : BB15 before out -> 0000000000007FFF; after out -> 000000000000005F; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 000000000000005F; AssertionPropCallback::StartMerge: BB19 in -> 0000000000007FFF AssertionPropCallback::Merge : BB19 in -> 0000000000007FFF, predBlock BB14 out -> 000000000000005F AssertionPropCallback::Merge : BB19 in -> 000000000000003F, predBlock BB11 out -> 000000000000001F AssertionPropCallback::EndMerge : BB19 in -> 000000000000001F AssertionPropCallback::Changed : BB19 before out -> 0000000000007FFF; after out -> 000000000000011F; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 000000000000009F; AssertionPropCallback::StartMerge: BB19 in -> 000000000000001F AssertionPropCallback::Merge : BB19 in -> 000000000000001F, predBlock BB14 out -> 000000000000005F AssertionPropCallback::Merge : BB19 in -> 000000000000001F, predBlock BB11 out -> 000000000000001F AssertionPropCallback::EndMerge : BB19 in -> 000000000000001F AssertionPropCallback::Unchanged : BB19 out -> 000000000000011F; jumpDest out -> 000000000000009F AssertionPropCallback::StartMerge: BB16 in -> 0000000000007FFF AssertionPropCallback::Merge : BB16 in -> 0000000000007FFF, predBlock BB15 out -> 000000000000005F AssertionPropCallback::EndMerge : BB16 in -> 000000000000005F AssertionPropCallback::Changed : BB16 before out -> 0000000000007FFF; after out -> 000000000000005F; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 000000000000005F; AssertionPropCallback::StartMerge: BB09 in -> 0000000000000007 AssertionPropCallback::Merge : BB09 in -> 0000000000000007, predBlock BB06 out -> 0000000000000007 AssertionPropCallback::Merge : BB09 in -> 0000000000000007, predBlock BB15 out -> 000000000000005F AssertionPropCallback::EndMerge : BB09 in -> 0000000000000007 AssertionPropCallback::Unchanged : BB09 out -> 000000000000001F; jumpDest out -> 000000000000001F AssertionPropCallback::StartMerge: BB20 in -> 0000000000007FFF AssertionPropCallback::Merge : BB20 in -> 0000000000007FFF, predBlock BB19 out -> 000000000000011F AssertionPropCallback::EndMerge : BB20 in -> 000000000000011F AssertionPropCallback::Changed : BB20 before out -> 0000000000007FFF; after out -> 0000000000001F1F; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 000000000000011F; AssertionPropCallback::StartMerge: BB21 in -> 0000000000007FFF AssertionPropCallback::Merge : BB21 in -> 0000000000007FFF, predBlock BB19 out -> 000000000000011F AssertionPropCallback::Merge : BB21 in -> 000000000000009F, predBlock BB20 out -> 0000000000001F1F AssertionPropCallback::EndMerge : BB21 in -> 000000000000001F AssertionPropCallback::Changed : BB21 before out -> 0000000000007FFF; after out -> 000000000000001F; jumpDest before out -> 0000000000007FFF; jumpDest after out -> 000000000000001F; AssertionPropCallback::StartMerge: BB07 in -> 0000000000000007 AssertionPropCallback::Merge : BB07 in -> 0000000000000007, predBlock BB06 out -> 0000000000000007 AssertionPropCallback::Merge : BB07 in -> 0000000000000007, predBlock BB16 out -> 000000000000005F AssertionPropCallback::EndMerge : BB07 in -> 0000000000000007 AssertionPropCallback::Unchanged : BB07 out -> 0000000000000007; jumpDest out -> 0000000000000007 AssertionPropCallback::StartMerge: BB21 in -> 000000000000001F AssertionPropCallback::Merge : BB21 in -> 000000000000001F, predBlock BB19 out -> 000000000000011F AssertionPropCallback::Merge : BB21 in -> 000000000000001F, predBlock BB20 out -> 0000000000001F1F AssertionPropCallback::EndMerge : BB21 in -> 000000000000001F AssertionPropCallback::Unchanged : BB21 out -> 000000000000001F; jumpDest out -> 000000000000001F AssertionPropCallback::StartMerge: BB15 in -> 000000000000005F AssertionPropCallback::Merge : BB15 in -> 000000000000005F, predBlock BB14 out -> 000000000000005F AssertionPropCallback::Merge : BB15 in -> 000000000000005F, predBlock BB21 out -> 000000000000001F AssertionPropCallback::EndMerge : BB15 in -> 000000000000001F AssertionPropCallback::Changed : BB15 before out -> 000000000000005F; after out -> 000000000000001F; jumpDest before out -> 000000000000005F; jumpDest after out -> 000000000000001F; AssertionPropCallback::StartMerge: BB16 in -> 000000000000005F AssertionPropCallback::Merge : BB16 in -> 000000000000005F, predBlock BB15 out -> 000000000000001F AssertionPropCallback::EndMerge : BB16 in -> 000000000000001F AssertionPropCallback::Changed : BB16 before out -> 000000000000005F; after out -> 000000000000001F; jumpDest before out -> 000000000000005F; jumpDest after out -> 000000000000001F; AssertionPropCallback::StartMerge: BB09 in -> 0000000000000007 AssertionPropCallback::Merge : BB09 in -> 0000000000000007, predBlock BB06 out -> 0000000000000007 AssertionPropCallback::Merge : BB09 in -> 0000000000000007, predBlock BB15 out -> 000000000000001F AssertionPropCallback::EndMerge : BB09 in -> 0000000000000007 AssertionPropCallback::Unchanged : BB09 out -> 000000000000001F; jumpDest out -> 000000000000001F AssertionPropCallback::StartMerge: BB07 in -> 0000000000000007 AssertionPropCallback::Merge : BB07 in -> 0000000000000007, predBlock BB06 out -> 0000000000000007 AssertionPropCallback::Merge : BB07 in -> 0000000000000007, predBlock BB16 out -> 000000000000001F AssertionPropCallback::EndMerge : BB07 in -> 0000000000000007 AssertionPropCallback::Unchanged : BB07 out -> 0000000000000007; jumpDest out -> 0000000000000007 BB01 valueIn = 0000000000000000 valueOut = 0000000000000001 => BB24 valueOut= 0000000000000001 BB02 valueIn = 0000000000000001 valueOut = 0000000000000001 => BB25 valueOut= 0000000000000001 BB03 valueIn = 0000000000000001 valueOut = 0000000000000003 => BB22 valueOut= 0000000000000003 BB04 valueIn = 0000000000000003 valueOut = 0000000000000003 => BB17 valueOut= 0000000000000003 BB05 valueIn = 0000000000000003 valueOut = 0000000000000003 => BB12 valueOut= 0000000000000003 BB06 valueIn = 0000000000000003 valueOut = 0000000000000007 => BB09 valueOut= 0000000000000007 BB07 valueIn = 0000000000000007 valueOut = 0000000000000007 BB08 valueIn = 0000000000000001 valueOut = 0000000000000001 BB09 valueIn = 0000000000000007 valueOut = 000000000000001F => BB14 valueOut= 000000000000001F BB10 valueIn = 000000000000001F valueOut = 000000000000001F BB11 valueIn = 000000000000001F valueOut = 000000000000001F BB12 valueIn = 0000000000000003 valueOut = 0000000000000003 => BB28 valueOut= 0000000000000003 BB13 valueIn = 0000000000000003 valueOut = 0000000000000003 BB14 valueIn = 000000000000001F valueOut = 000000000000005F => BB19 valueOut= 000000000000003F BB15 valueIn = 000000000000001F valueOut = 000000000000001F => BB09 valueOut= 000000000000001F BB16 valueIn = 000000000000001F valueOut = 000000000000001F BB17 valueIn = 0000000000000003 valueOut = 0000000000000003 => BB05 valueOut= 0000000000000003 BB18 valueIn = 0000000000000003 valueOut = 0000000000000003 BB19 valueIn = 000000000000001F valueOut = 000000000000011F => BB21 valueOut= 000000000000009F BB20 valueIn = 000000000000011F valueOut = 0000000000001F1F BB21 valueIn = 000000000000001F valueOut = 000000000000001F BB22 valueIn = 0000000000000003 valueOut = 0000000000000003 => BB04 valueOut= 0000000000000003 BB23 valueIn = 0000000000000003 valueOut = 0000000000000003 BB24 valueIn = 0000000000000001 valueOut = 0000000000000001 BB25 valueIn = 0000000000000001 valueOut = 0000000000000101 => BB27 valueOut= 0000000000000081 BB26 valueIn = 0000000000000101 valueOut = 0000000000007101 BB27 valueIn = 0000000000000001 valueOut = 0000000000000001 BB28 valueIn = 0000000000000003 valueOut = 0000000000000003 Propagating 0000000000000000 assertions for BB01, stmt STMT00001, tree [000280], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00001, tree [000281], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00001, tree [000000], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00001, tree [000279], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00001, tree [000198], tree -> 1 Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000199], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000200], tree -> 0 Propagating 0000000000000001 assertions for BB01, stmt STMT00001, tree [000006], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00002, tree [000007], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00002, tree [000008], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00002, tree [000009], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000287], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000285], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000286], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000010], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000284], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000202], tree -> 1 Non-null prop for index #01 in BB02: N006 ( 24, 21) [000202] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000203], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000204], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000205], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000014], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000015], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt STMT00004, tree [000016], tree -> 0 Re-morphing this stmt: STMT00004 (IL ???... ???) N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int $283 N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 fgMorphTree (before 317): N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int $283 N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 fgMorphTree (before 318): N011 ( 42, 33) [000015] J-CXG--N---- * NE int $283 N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 fgMorphTree (before 319): N009 ( 40, 31) [000205] --CXG------- * CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 fgMorphTree (before 320): N008 ( 39, 29) [000204] --CXG------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 ReMorphing args for 204.CALL: fgMorphTree (before 321): N007 ( 25, 23) [000203] --CXG------- * CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 fgMorphTree (before 322): N006 ( 24, 21) [000202] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 ReMorphing args for 202.CALL: fgMorphTree (before 323): N004 ( 1, 1) [000010] ------------ * LCL_VAR ref V03 arg3 u:1 $83 fgMorphTree (after 323): N004 ( 1, 1) [000010] ------------ * LCL_VAR ref V03 arg3 u:1 $83 fgMorphTree (before 324): N005 ( 3, 10) [000284] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 fgMorphTree (after 324): N005 ( 3, 10) [000284] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 fgMorphTree (before 325): N002 ( 0, 0) [000285] ----------L- * ARGPLACE ref $142 fgMorphTree (after 325): N002 ( 0, 0) [000285] ----------L- * ARGPLACE ref $142 fgMorphTree (before 326): N003 ( 0, 0) [000286] ----------L- * ARGPLACE long $83 fgMorphTree (after 326): N003 ( 0, 0) [000286] ----------L- * ARGPLACE long $83 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 202.CALL after fgMorphArgs: fgArgTabEntry[arg 0 10.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 284.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 322): N006 ( 24, 21) [000202] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 fgMorphTree (after 321): N007 ( 25, 23) [000203] --CXG------- * CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --CXG------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 fgMorphTree (before 327): N001 ( 0, 0) [000287] ----------L- * ARGPLACE int $281 fgMorphTree (after 327): N001 ( 0, 0) [000287] ----------L- * ARGPLACE int $281 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 204.CALL after fgMorphArgs: fgArgTabEntry[arg 0 203.CAST int, 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree (after 320): N008 ( 39, 29) [000204] --CXG------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --CXG------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 fgMorphTree (after 319): N009 ( 40, 31) [000205] --CXG------- * CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --CXG------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 fgMorphTree (before 328): N010 ( 1, 1) [000014] ------------ * CNS_INT int 0 $40 fgMorphTree (after 328): N010 ( 1, 1) [000014] ------------ * CNS_INT int 0 $40 fgMorphTree (after 318): N011 ( 42, 33) [000015] J-CXG--N---- * NE int $283 N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 fgMorphTree (after 317): N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int $283 N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 optAssertionPropMain morphed tree: N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int $283 N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 Propagating 0000000000000001 assertions for BB03, stmt STMT00005, tree [000313], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt STMT00005, tree [000314], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt STMT00005, tree [000017], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt STMT00005, tree [000312], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt STMT00005, tree [000018], tree -> 2 Propagating 0000000000000003 assertions for BB03, stmt STMT00005, tree [000019], tree -> 0 Propagating 0000000000000003 assertions for BB03, stmt STMT00005, tree [000020], tree -> 0 Propagating 0000000000000003 assertions for BB03, stmt STMT00005, tree [000021], tree -> 0 Propagating 0000000000000003 assertions for BB03, stmt STMT00005, tree [000022], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt STMT00006, tree [000320], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt STMT00006, tree [000321], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt STMT00006, tree [000023], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt STMT00006, tree [000319], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt STMT00006, tree [000024], tree -> 2 Non-null prop for index #02 in BB04: N005 ( 24, 21) [000024] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b Propagating 0000000000000003 assertions for BB04, stmt STMT00006, tree [000025], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt STMT00006, tree [000026], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt STMT00006, tree [000027], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt STMT00006, tree [000028], tree -> 0 Re-morphing this stmt: STMT00006 (IL 0x055...0x05B) N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int $28b N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 $40 fgMorphTree (before 329): N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int $28b N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 $40 fgMorphTree (before 330): N008 ( 27, 25) [000027] J-CXG--N---- * NE int $28b N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 $40 fgMorphTree (before 331): N006 ( 25, 23) [000025] --CXG------- * CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc fgMorphTree (before 332): N005 ( 24, 21) [000024] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc ReMorphing args for 24.CALL: fgMorphTree (before 333): N003 ( 1, 1) [000023] ------------ * LCL_VAR ref V02 arg2 u:1 $82 fgMorphTree (after 333): N003 ( 1, 1) [000023] ------------ * LCL_VAR ref V02 arg2 u:1 $82 fgMorphTree (before 334): N004 ( 3, 10) [000319] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc fgMorphTree (after 334): N004 ( 3, 10) [000319] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc fgMorphTree (before 335): N001 ( 0, 0) [000320] ----------L- * ARGPLACE ref $159 fgMorphTree (after 335): N001 ( 0, 0) [000320] ----------L- * ARGPLACE ref $159 fgMorphTree (before 336): N002 ( 0, 0) [000321] ----------L- * ARGPLACE long $82 fgMorphTree (after 336): N002 ( 0, 0) [000321] ----------L- * ARGPLACE long $82 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 24.CALL after fgMorphArgs: fgArgTabEntry[arg 0 23.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 319.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 332): N005 ( 24, 21) [000024] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc fgMorphTree (after 331): N006 ( 25, 23) [000025] --CXG------- * CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --CXG------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc fgMorphTree (before 337): N007 ( 1, 1) [000026] ------------ * CNS_INT int 0 $40 fgMorphTree (after 337): N007 ( 1, 1) [000026] ------------ * CNS_INT int 0 $40 fgMorphTree (after 330): N008 ( 27, 25) [000027] J-CXG--N---- * NE int $28b N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 $40 fgMorphTree (after 329): N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int $28b N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 $40 optAssertionPropMain morphed tree: N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int $28b N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 $40 Propagating 0000000000000003 assertions for BB05, stmt STMT00007, tree [000327], tree -> 0 Propagating 0000000000000003 assertions for BB05, stmt STMT00007, tree [000328], tree -> 0 Propagating 0000000000000003 assertions for BB05, stmt STMT00007, tree [000029], tree -> 0 Propagating 0000000000000003 assertions for BB05, stmt STMT00007, tree [000326], tree -> 0 Propagating 0000000000000003 assertions for BB05, stmt STMT00007, tree [000030], tree -> 2 Non-null prop for index #02 in BB05: N005 ( 24, 21) [000030] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e Propagating 0000000000000003 assertions for BB05, stmt STMT00007, tree [000031], tree -> 0 Propagating 0000000000000003 assertions for BB05, stmt STMT00007, tree [000032], tree -> 0 Propagating 0000000000000003 assertions for BB05, stmt STMT00007, tree [000033], tree -> 0 Propagating 0000000000000003 assertions for BB05, stmt STMT00007, tree [000034], tree -> 0 Re-morphing this stmt: STMT00007 (IL 0x06A...0x070) N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int $28f N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 $40 fgMorphTree (before 338): N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int $28f N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 $40 fgMorphTree (before 339): N008 ( 27, 25) [000033] J-CXG--N---- * NE int $28f N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --C-G------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 $40 fgMorphTree (before 340): N006 ( 25, 23) [000031] --CXG------- * CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --C-G------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce fgMorphTree (before 341): N005 ( 24, 21) [000030] --C-G------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce ReMorphing args for 30.CALL: fgMorphTree (before 342): N003 ( 1, 1) [000029] ------------ * LCL_VAR ref V02 arg2 u:1 $82 fgMorphTree (after 342): N003 ( 1, 1) [000029] ------------ * LCL_VAR ref V02 arg2 u:1 $82 fgMorphTree (before 343): N004 ( 3, 10) [000326] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce fgMorphTree (after 343): N004 ( 3, 10) [000326] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce fgMorphTree (before 344): N001 ( 0, 0) [000327] ----------L- * ARGPLACE ref $15f fgMorphTree (after 344): N001 ( 0, 0) [000327] ----------L- * ARGPLACE ref $15f fgMorphTree (before 345): N002 ( 0, 0) [000328] ----------L- * ARGPLACE long $82 fgMorphTree (after 345): N002 ( 0, 0) [000328] ----------L- * ARGPLACE long $82 argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 30.CALL after fgMorphArgs: fgArgTabEntry[arg 0 29.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 326.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 341): N005 ( 24, 21) [000030] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce fgMorphTree (after 340): N006 ( 25, 23) [000031] --CXG------- * CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --CXG------- \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce fgMorphTree (before 346): N007 ( 1, 1) [000032] ------------ * CNS_INT int 0 $40 fgMorphTree (after 346): N007 ( 1, 1) [000032] ------------ * CNS_INT int 0 $40 fgMorphTree (after 339): N008 ( 27, 25) [000033] J-CXG--N---- * NE int $28f N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 $40 fgMorphTree (after 338): N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int $28f N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 $40 optAssertionPropMain morphed tree: N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int $28f N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 $40 Propagating 0000000000000003 assertions for BB06, stmt STMT00009, tree [000335], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00009, tree [000336], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00009, tree [000035], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00009, tree [000036], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00009, tree [000037], tree -> 2 Non-null prop for index #02 in BB06: N005 ( 16, 10) [000037] --CXG------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 Propagating 0000000000000003 assertions for BB06, stmt STMT00009, tree [000039], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00009, tree [000042], tree -> 0 Re-morphing this stmt: STMT00009 (IL ???... ???) N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref $167 N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --C-G------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 fgMorphTree (before 347): N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref $167 N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --C-G------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 fgMorphTree (before 348): N006 ( 3, 2) [000039] D---G--N---- * LCL_VAR ref (AX) V23 tmp12 fgMorphTree (after 348): N006 ( 3, 2) [000039] D---G--N---- * LCL_VAR ref (AX) V23 tmp12 fgMorphTree (before 349): N005 ( 16, 10) [000037] --C-G------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 ReMorphing args for 37.CALL: fgMorphTree (before 350): N003 ( 1, 1) [000035] ------------ * LCL_VAR ref V02 arg2 u:1 $82 fgMorphTree (after 350): N003 ( 1, 1) [000035] ------------ * LCL_VAR ref V02 arg2 u:1 $82 fgMorphTree (before 351): N004 ( 1, 1) [000036] ------------ * LCL_VAR byref V05 arg5 u:1 $c0 fgMorphTree (after 351): N004 ( 1, 1) [000036] ------------ * LCL_VAR byref V05 arg5 u:1 $c0 fgMorphTree (before 352): N001 ( 0, 0) [000335] ----------L- * ARGPLACE ref $166 fgMorphTree (after 352): N001 ( 0, 0) [000335] ----------L- * ARGPLACE ref $166 fgMorphTree (before 353): N002 ( 0, 0) [000336] ----------L- * ARGPLACE byref $82 fgMorphTree (after 353): N002 ( 0, 0) [000336] ----------L- * ARGPLACE byref $82 argSlots=2, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 37.CALL after fgMorphArgs: fgArgTabEntry[arg 0 35.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 36.LCL_VAR byref, 1 reg: rsi, align=1, lateArgInx=1, processed] fgMorphTree (after 349): N005 ( 16, 10) [000037] --CXG------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 fgMorphTree (after 347): N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref $167 N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 optAssertionPropMain morphed tree: N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref $167 N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 Propagating 0000000000000003 assertions for BB06, stmt STMT00010, tree [000338], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00010, tree [000337], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00010, tree [000046], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00010, tree [000047], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00010, tree [000043], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00010, tree [000044], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00010, tree [000045], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00010, tree [000048], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00010, tree [000050], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00011, tree [000341], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00011, tree [000340], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00011, tree [000342], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00011, tree [000343], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00011, tree [000345], tree -> 0 Propagating 0000000000000003 assertions for BB06, stmt STMT00011, tree [000346], tree -> 3 Propagating 0000000000000007 assertions for BB06, stmt STMT00011, tree [000344], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00011, tree [000347], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00011, tree [000348], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00011, tree [000350], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00011, tree [000351], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00011, tree [000352], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00011, tree [000353], tree -> 3 Non-null prop for index #03 in BB06: N013 ( 4, 4) [000353] ---X-------- * IND int Propagating 0000000000000007 assertions for BB06, stmt STMT00011, tree [000349], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00011, tree [000354], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00011, tree [000355], tree -> 0 Re-morphing this stmt: STMT00011 (IL ???... ???) N016 ( 18, 15) [000355] -A-XG------- * COMMA void N009 ( 10, 8) [000348] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref $487 N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref $487 N001 ( 3, 2) [000341] -------N---- | | \--* LCL_VAR struct(AX) V12 tmp1 $4c3 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 N015 ( 8, 7) [000354] -A-XG---R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] n----O------ \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 fgMorphTree (before 354): N016 ( 18, 15) [000355] -A-XG------- * COMMA void N009 ( 10, 8) [000348] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref $487 N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref $487 N001 ( 3, 2) [000341] -------N---- | | \--* LCL_VAR struct(AX) V12 tmp1 $4c3 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 N015 ( 8, 7) [000354] -A-XG---R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] n----O------ \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 fgMorphTree (before 355): N009 ( 10, 8) [000348] -A-XG------- * COMMA void N004 ( 3, 3) [000343] -A------R--- +--* ASG byref $487 N003 ( 1, 1) [000342] D------N---- | +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ | \--* ADDR byref $487 N001 ( 3, 2) [000341] -------N---- | \--* LCL_VAR struct(AX) V12 tmp1 $4c3 N008 ( 7, 5) [000347] -A-XG---R--- \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- \--* IND ref N005 ( 1, 1) [000345] ------------ \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 fgMorphTree (before 356): N004 ( 3, 3) [000343] -A------R--- * ASG byref $487 N003 ( 1, 1) [000342] D------N---- +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ \--* ADDR byref $487 N001 ( 3, 2) [000341] -------N---- \--* LCL_VAR struct(AX) V12 tmp1 $4c3 fgMorphTree (before 357): N003 ( 1, 1) [000342] D------N---- * LCL_VAR byref V25 tmp14 d:2 $487 fgMorphTree (after 357): N003 ( 1, 1) [000342] D------N---- * LCL_VAR byref V25 tmp14 d:2 $487 fgMorphTree (before 358): N002 ( 3, 3) [000340] ------------ * ADDR byref $487 N001 ( 3, 2) [000341] -------N---- \--* LCL_VAR struct(AX) V12 tmp1 $4c3 fgMorphTree (before 359): N001 ( 3, 2) [000341] -------N---- * LCL_VAR struct(AX) V12 tmp1 $4c3 fgMorphTree (after 359): N001 ( 3, 2) [000341] ----G--N---- * LCL_VAR struct(AX) V12 tmp1 $4c3 fgMorphTree (after 358): N002 ( 3, 3) [000340] ------------ * ADDR byref $487 N001 ( 3, 2) [000341] ----G--N---- \--* LCL_VAR struct(AX) V12 tmp1 $4c3 fgMorphTree (after 356): N004 ( 3, 3) [000343] -A------R--- * ASG byref $487 N003 ( 1, 1) [000342] D------N---- +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ \--* ADDR byref $487 N001 ( 3, 2) [000341] ----G--N---- \--* LCL_VAR struct(AX) V12 tmp1 $4c3 fgMorphTree (before 360): N008 ( 7, 5) [000347] -A-XG---R--- * ASG ref N007 ( 3, 2) [000344] D---G--N---- +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- \--* IND ref N005 ( 1, 1) [000345] ------------ \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 fgMorphTree (before 361): N007 ( 3, 2) [000344] D---G--N---- * LCL_VAR ref (AX) V21 tmp10 fgMorphTree (after 361): N007 ( 3, 2) [000344] D---G--N---- * LCL_VAR ref (AX) V21 tmp10 fgMorphTree (before 362): N006 ( 3, 2) [000346] ---X-------- * IND ref N005 ( 1, 1) [000345] ------------ \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 fgMorphTree (before 363): N005 ( 1, 1) [000345] ------------ * LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 fgMorphTree (after 363): N005 ( 1, 1) [000345] ------------ * LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 fgMorphTree (after 362): N006 ( 3, 2) [000346] ---X-------- * IND ref N005 ( 1, 1) [000345] ------------ \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 fgMorphTree (after 360): N008 ( 7, 5) [000347] -A-XG---R--- * ASG ref N007 ( 3, 2) [000344] D---G--N---- +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- \--* IND ref N005 ( 1, 1) [000345] ------------ \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 fgMorphTree (after 355): N009 ( 10, 8) [000348] -A-XG------- * COMMA void N004 ( 3, 3) [000343] -A------R--- +--* ASG byref $487 N003 ( 1, 1) [000342] D------N---- | +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ | \--* ADDR byref $487 N001 ( 3, 2) [000341] ----G--N---- | \--* LCL_VAR struct(AX) V12 tmp1 $4c3 N008 ( 7, 5) [000347] -A-XG---R--- \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- \--* IND ref N005 ( 1, 1) [000345] ------------ \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 fgMorphTree (before 364): N015 ( 8, 7) [000354] -A-XG---R--- * ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] n----O------ \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 fgMorphTree (before 365): N014 ( 3, 2) [000349] D---G--N---- * LCL_VAR int (AX) V22 tmp11 fgMorphTree (after 365): N014 ( 3, 2) [000349] D---G--N---- * LCL_VAR int (AX) V22 tmp11 fgMorphTree (before 366): N013 ( 4, 4) [000353] n----O------ * IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 fgMorphTree (before 367): N012 ( 2, 2) [000352] -------N---- * ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 fgMorphTree (before 368): N010 ( 1, 1) [000350] ------------ * LCL_VAR byref V25 tmp14 u:2 (last use) $487 fgMorphTree (after 368): N010 ( 1, 1) [000350] ------------ * LCL_VAR byref V25 tmp14 u:2 (last use) $487 fgMorphTree (before 369): N011 ( 1, 1) [000351] ------------ * CNS_INT long 8 Fseq[_index] $2c3 fgMorphTree (after 369): N011 ( 1, 1) [000351] ------------ * CNS_INT long 8 Fseq[_index] $2c3 fgMorphTree (after 367): N012 ( 2, 2) [000352] -------N---- * ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 fgMorphTree (after 366): N013 ( 4, 4) [000353] n----O------ * IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 fgMorphTree (after 364): N015 ( 8, 7) [000354] -A--GO--R--- * ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] n----O------ \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 fgMorphTree (after 354): N016 ( 18, 15) [000355] -A-XGO------ * COMMA void [000471] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref $487 N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref $487 N001 ( 3, 2) [000341] ----G--N---- | | \--* LCL_VAR struct(AX) V12 tmp1 $4c3 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 N015 ( 8, 7) [000354] -A--GO--R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] n----O------ \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 optAssertionPropMain morphed tree: N016 ( 18, 15) [000355] -A-XGO------ * COMMA void N009 ( 10, 8) [000471] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref $487 N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref $487 N001 ( 3, 2) [000341] ----G--N---- | | \--* LCL_VAR struct(AX) V12 tmp1 $4c3 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 N015 ( 8, 7) [000354] -A--GO--R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] n----O------ \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 Propagating 0000000000000007 assertions for BB06, stmt STMT00057, tree [000412], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00057, tree [000413], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00057, tree [000415], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00057, tree [000414], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00057, tree [000417], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00057, tree [000416], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00057, tree [000411], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00057, tree [000410], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00057, tree [000418], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00057, tree [000409], tree -> 0 Propagating 0000000000000007 assertions for BB06, stmt STMT00057, tree [000419], tree -> 0 Propagating 0000000000000007 assertions for BB07, stmt STMT00026, tree [000125], tree -> 0 Propagating 0000000000000007 assertions for BB07, stmt STMT00026, tree [000126], tree -> 0 Propagating 0000000000000007 assertions for BB07, stmt STMT00026, tree [000127], tree -> 0 Propagating 0000000000000001 assertions for BB08, stmt STMT00027, tree [000128], tree -> 0 Propagating 0000000000000001 assertions for BB08, stmt STMT00027, tree [000129], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000358], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000357], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000067], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000068], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000064], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000065], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000066], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000359], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000360], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000363], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000362], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000361], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000069], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000356], tree -> 0 Propagating 0000000000000007 assertions for BB09, stmt STMT00013, tree [000070], tree -> 4 Propagating 000000000000000F assertions for BB09, stmt STMT00013, tree [000071], tree -> 0 Propagating 000000000000000F assertions for BB09, stmt STMT00013, tree [000073], tree -> 0 Propagating 000000000000000F assertions for BB09, stmt STMT00014, tree [000076], tree -> 0 Propagating 000000000000000F assertions for BB09, stmt STMT00014, tree [000077], tree -> 0 Propagating 000000000000000F assertions for BB09, stmt STMT00014, tree [000078], tree -> 0 Propagating 000000000000000F assertions for BB09, stmt STMT00046, tree [000366], tree -> 0 Propagating 000000000000000F assertions for BB09, stmt STMT00046, tree [000367], tree -> 0 Propagating 000000000000000F assertions for BB09, stmt STMT00046, tree [000080], tree -> 0 Propagating 000000000000000F assertions for BB09, stmt STMT00046, tree [000365], tree -> 0 Propagating 000000000000000F assertions for BB09, stmt STMT00046, tree [000247], tree -> 5 Propagating 000000000000001F assertions for BB09, stmt STMT00046, tree [000248], tree -> 0 Propagating 000000000000001F assertions for BB09, stmt STMT00046, tree [000249], tree -> 0 Propagating 000000000000001F assertions for BB09, stmt STMT00046, tree [000228], tree -> 0 Propagating 000000000000001F assertions for BB10, stmt STMT00049, tree [000368], tree -> 0 Propagating 000000000000001F assertions for BB10, stmt STMT00049, tree [000369], tree -> 0 Propagating 000000000000001F assertions for BB10, stmt STMT00049, tree [000237], tree -> 0 Propagating 000000000000001F assertions for BB10, stmt STMT00049, tree [000238], tree -> 0 Propagating 000000000000001F assertions for BB10, stmt STMT00049, tree [000239], tree -> 0 Propagating 000000000000001F assertions for BB10, stmt STMT00050, tree [000240], tree -> 0 Propagating 000000000000001F assertions for BB10, stmt STMT00050, tree [000241], tree -> 0 Propagating 000000000000001F assertions for BB10, stmt STMT00050, tree [000242], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000329], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000330], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000331], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000332], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000333], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000130], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000131], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000132], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000133], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000134], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000135], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000136], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000137], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000138], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt STMT00028, tree [000139], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00048, tree [000371], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00048, tree [000372], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00048, tree [000373], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00048, tree [000079], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00048, tree [000229], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00048, tree [000081], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00048, tree [000230], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00048, tree [000232], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00048, tree [000233], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00048, tree [000234], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00016, tree [000235], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00016, tree [000085], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00016, tree [000086], tree -> 0 Propagating 000000000000001F assertions for BB14, stmt STMT00016, tree [000087], tree -> 6 Propagating 000000000000001F assertions for BB15, stmt STMT00012, tree [000406], tree -> 0 Propagating 000000000000001F assertions for BB15, stmt STMT00012, tree [000405], tree -> 0 Propagating 000000000000001F assertions for BB15, stmt STMT00012, tree [000058], tree -> 0 Propagating 000000000000001F assertions for BB15, stmt STMT00012, tree [000059], tree -> 0 Propagating 000000000000001F assertions for BB15, stmt STMT00012, tree [000055], tree -> 0 Propagating 000000000000001F assertions for BB15, stmt STMT00012, tree [000056], tree -> 0 Propagating 000000000000001F assertions for BB15, stmt STMT00012, tree [000057], tree -> 0 Propagating 000000000000001F assertions for BB15, stmt STMT00012, tree [000060], tree -> 0 Propagating 000000000000001F assertions for BB15, stmt STMT00012, tree [000061], tree -> 0 Propagating 000000000000001F assertions for BB15, stmt STMT00012, tree [000062], tree -> 0 Propagating 000000000000001F assertions for BB15, stmt STMT00012, tree [000063], tree -> 0 Propagating 0000000000000003 assertions for BB17, stmt STMT00031, tree [000322], tree -> 0 Propagating 0000000000000003 assertions for BB17, stmt STMT00031, tree [000323], tree -> 0 Propagating 0000000000000003 assertions for BB17, stmt STMT00031, tree [000324], tree -> 0 Propagating 0000000000000003 assertions for BB17, stmt STMT00031, tree [000143], tree -> 0 Propagating 0000000000000003 assertions for BB17, stmt STMT00031, tree [000144], tree -> 0 Propagating 0000000000000003 assertions for BB17, stmt STMT00031, tree [000145], tree -> 0 Propagating 0000000000000003 assertions for BB17, stmt STMT00031, tree [000146], tree -> 0 Propagating 0000000000000003 assertions for BB17, stmt STMT00031, tree [000148], tree -> 0 Propagating 0000000000000003 assertions for BB17, stmt STMT00031, tree [000149], tree -> 0 Propagating 0000000000000003 assertions for BB17, stmt STMT00031, tree [000150], tree -> 0 Propagating 0000000000000003 assertions for BB17, stmt STMT00031, tree [000151], tree -> 0 Propagating 0000000000000003 assertions for BB18, stmt STMT00032, tree [000152], tree -> 0 Propagating 0000000000000003 assertions for BB18, stmt STMT00032, tree [000153], tree -> 0 Propagating 0000000000000003 assertions for BB18, stmt STMT00032, tree [000154], tree -> 0 Propagating 000000000000001F assertions for BB19, stmt STMT00017, tree [000088], tree -> 0 Propagating 000000000000001F assertions for BB19, stmt STMT00017, tree [000089], tree -> 0 Propagating 000000000000001F assertions for BB19, stmt STMT00017, tree [000090], tree -> 0 Propagating 000000000000001F assertions for BB19, stmt STMT00017, tree [000091], tree -> 8 Propagating 000000000000011F assertions for BB20, stmt STMT00019, tree [000374], tree -> 0 Propagating 000000000000011F assertions for BB20, stmt STMT00019, tree [000098], tree -> 0 Propagating 000000000000011F assertions for BB20, stmt STMT00019, tree [000099], tree -> 0 Propagating 000000000000011F assertions for BB20, stmt STMT00019, tree [000100], tree -> 0 Propagating 000000000000011F assertions for BB20, stmt STMT00019, tree [000101], tree -> 0 Propagating 000000000000011F assertions for BB20, stmt STMT00020, tree [000104], tree -> 0 Propagating 000000000000011F assertions for BB20, stmt STMT00020, tree [000103], tree -> 0 Propagating 000000000000011F assertions for BB20, stmt STMT00020, tree [000377], tree -> 10 Propagating 000000000000031F assertions for BB20, stmt STMT00020, tree [000464], tree -> 0 Propagating 000000000000031F assertions for BB20, stmt STMT00020, tree [000465], tree -> 0 Propagating 000000000000031F assertions for BB20, stmt STMT00020, tree [000466], tree -> 0 Propagating 000000000000031F assertions for BB20, stmt STMT00020, tree [000467], tree -> 0 Propagating 000000000000031F assertions for BB20, stmt STMT00020, tree [000378], tree -> 11 Propagating 000000000000071F assertions for BB20, stmt STMT00020, tree [000375], tree -> 0 Propagating 000000000000071F assertions for BB20, stmt STMT00020, tree [000382], tree -> 0 Propagating 000000000000071F assertions for BB20, stmt STMT00020, tree [000383], tree -> 0 Propagating 000000000000071F assertions for BB20, stmt STMT00020, tree [000106], tree -> 10 Propagating 000000000000071F assertions for BB20, stmt STMT00020, tree [000384], tree -> 0 Propagating 000000000000071F assertions for BB20, stmt STMT00020, tree [000105], tree -> 0 Propagating 000000000000071F assertions for BB20, stmt STMT00020, tree [000107], tree -> 0 Propagating 000000000000071F assertions for BB20, stmt STMT00021, tree [000109], tree -> 0 Propagating 000000000000071F assertions for BB20, stmt STMT00021, tree [000468], tree -> 0 Propagating 000000000000071F assertions for BB20, stmt STMT00021, tree [000388], tree -> 12 Propagating 0000000000000F1F assertions for BB20, stmt STMT00021, tree [000385], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00021, tree [000392], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00021, tree [000393], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00021, tree [000111], tree -> 10 Propagating 0000000000000F1F assertions for BB20, stmt STMT00021, tree [000394], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00021, tree [000110], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00021, tree [000112], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00052, tree [000259], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00052, tree [000260], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00052, tree [000261], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000398], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000252], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000253], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000254], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000255], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000395], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000396], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000400], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000399], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000397], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000262], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000102], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000256], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00053, tree [000263], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00054, tree [000268], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00054, tree [000267], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00054, tree [000269], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00055, tree [000096], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00055, tree [000272], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00055, tree [000273], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00056, tree [000264], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00056, tree [000276], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00056, tree [000277], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00025, tree [000402], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00025, tree [000403], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00025, tree [000121], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00025, tree [000123], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00025, tree [000124], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00025, tree [000095], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00025, tree [000401], tree -> 0 Propagating 0000000000000F1F assertions for BB20, stmt STMT00025, tree [000122], tree -> 13 Non-null prop for index #09 in BB20: N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void Re-morphing this stmt: STMT00025 (IL 0x0DA... ???) N008 ( 38, 29) [000122] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct $507 N004 ( 3, 3) [000123] ------------ | \--* ADDR byref $40b N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 fgMorphTree (before 370): N008 ( 38, 29) [000122] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct $507 N004 ( 3, 3) [000123] ------------ | \--* ADDR byref $40b N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 ReMorphing args for 122.CALL: fgMorphTree (before 371): N006 ( 3, 2) [000095] ------------ * LCL_VAR ref V04 arg4 u:1 $84 fgMorphTree (after 371): N006 ( 3, 2) [000095] ------------ * LCL_VAR ref V04 arg4 u:1 $84 fgMorphTree (before 372): N007 ( 3, 10) [000401] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 fgMorphTree (after 372): N007 ( 3, 10) [000401] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 fgMorphTree (before 373): N001 ( 0, 0) [000402] ----------L- * ARGPLACE ref $682 fgMorphTree (after 373): N001 ( 0, 0) [000402] ----------L- * ARGPLACE ref $682 fgMorphTree (before 374): N002 ( 0, 0) [000403] ----------L- * ARGPLACE long $84 fgMorphTree (after 374): N002 ( 0, 0) [000403] ----------L- * ARGPLACE long $84 fgMorphTree (before 375): N005 ( 9, 7) [000124] n----------- * OBJ struct $507 N004 ( 3, 3) [000123] ------------ \--* ADDR byref $40b N003 ( 3, 2) [000121] -------N---- \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d fgMorphTree (before 376): N004 ( 3, 3) [000123] ------------ * ADDR byref $40b N003 ( 3, 2) [000121] -------N---- \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d fgMorphTree (before 377): N003 ( 3, 2) [000121] -------N---- * LCL_VAR struct V15 tmp4 u:4 (last use) $38d fgMorphTree (after 377): N003 ( 3, 2) [000121] -------N---- * LCL_VAR struct V15 tmp4 u:4 (last use) $38d fgMorphTree (after 376): N004 ( 3, 3) [000123] ------------ * ADDR byref $40b N003 ( 3, 2) [000121] -------N---- \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d fgMorphTree (after 375): N005 ( 9, 7) [000124] n----------- * OBJ struct $507 N004 ( 3, 3) [000123] ------------ \--* ADDR byref $40b N003 ( 3, 2) [000121] -------N---- \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d argSlots=6, preallocatedArgCount=5, nextSlotNum=5, outgoingArgSpaceSize=40 Local V15 should not be enregistered because: it is a struct arg ArgTable for 122.CALL after fgMorphArgs: fgArgTabEntry[arg 2 124.OBJ struct, numSlots=5, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 0 95.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 401.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 370): N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct $507 N004 ( 3, 3) [000123] ------------ | \--* ADDR byref $40b N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 optAssertionPropMain morphed tree: N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct $507 N004 ( 3, 3) [000123] ------------ | \--* ADDR byref $40b N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 Propagating 000000000000001F assertions for BB21, stmt STMT00018, tree [000092], tree -> 0 Propagating 000000000000001F assertions for BB21, stmt STMT00018, tree [000093], tree -> 0 Propagating 000000000000001F assertions for BB21, stmt STMT00018, tree [000094], tree -> 0 Propagating 0000000000000003 assertions for BB22, stmt STMT00033, tree [000315], tree -> 0 Propagating 0000000000000003 assertions for BB22, stmt STMT00033, tree [000316], tree -> 0 Propagating 0000000000000003 assertions for BB22, stmt STMT00033, tree [000317], tree -> 0 Propagating 0000000000000003 assertions for BB22, stmt STMT00033, tree [000155], tree -> 0 Propagating 0000000000000003 assertions for BB22, stmt STMT00033, tree [000156], tree -> 0 Propagating 0000000000000003 assertions for BB22, stmt STMT00033, tree [000157], tree -> 0 Propagating 0000000000000003 assertions for BB22, stmt STMT00033, tree [000158], tree -> 0 Propagating 0000000000000003 assertions for BB22, stmt STMT00033, tree [000159], tree -> 0 Propagating 0000000000000003 assertions for BB22, stmt STMT00033, tree [000160], tree -> 0 Propagating 0000000000000003 assertions for BB22, stmt STMT00033, tree [000161], tree -> 0 Propagating 0000000000000003 assertions for BB22, stmt STMT00033, tree [000162], tree -> 0 Propagating 0000000000000003 assertions for BB23, stmt STMT00034, tree [000163], tree -> 0 Propagating 0000000000000003 assertions for BB23, stmt STMT00034, tree [000164], tree -> 0 Propagating 0000000000000003 assertions for BB23, stmt STMT00034, tree [000165], tree -> 0 Propagating 0000000000000001 assertions for BB24, stmt STMT00042, tree [000195], tree -> 0 Propagating 0000000000000001 assertions for BB24, stmt STMT00042, tree [000196], tree -> 0 Propagating 0000000000000001 assertions for BB24, stmt STMT00042, tree [000197], tree -> 0 Propagating 0000000000000001 assertions for BB25, stmt STMT00035, tree [000166], tree -> 0 Propagating 0000000000000001 assertions for BB25, stmt STMT00035, tree [000167], tree -> 0 Propagating 0000000000000001 assertions for BB25, stmt STMT00035, tree [000168], tree -> 0 Propagating 0000000000000001 assertions for BB25, stmt STMT00035, tree [000169], tree -> 8 Propagating 0000000000000101 assertions for BB26, stmt STMT00037, tree [000288], tree -> 0 Propagating 0000000000000101 assertions for BB26, stmt STMT00037, tree [000176], tree -> 0 Propagating 0000000000000101 assertions for BB26, stmt STMT00037, tree [000177], tree -> 0 Propagating 0000000000000101 assertions for BB26, stmt STMT00037, tree [000178], tree -> 0 Propagating 0000000000000101 assertions for BB26, stmt STMT00037, tree [000179], tree -> 0 Propagating 0000000000000101 assertions for BB26, stmt STMT00038, tree [000182], tree -> 0 Propagating 0000000000000101 assertions for BB26, stmt STMT00038, tree [000181], tree -> 0 Propagating 0000000000000101 assertions for BB26, stmt STMT00038, tree [000291], tree -> 14 Propagating 0000000000002101 assertions for BB26, stmt STMT00038, tree [000292], tree -> 15 Propagating 0000000000006101 assertions for BB26, stmt STMT00038, tree [000289], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00038, tree [000296], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00038, tree [000297], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00038, tree [000184], tree -> 14 Propagating 0000000000006101 assertions for BB26, stmt STMT00038, tree [000298], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00038, tree [000183], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00038, tree [000185], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00043, tree [000214], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00043, tree [000215], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00043, tree [000216], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000302], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000207], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000208], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000209], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000210], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000299], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000300], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000304], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000303], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000301], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000217], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000180], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000211], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00044, tree [000218], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00040, tree [000305], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00040, tree [000306], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00040, tree [000307], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00040, tree [000189], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00040, tree [000174], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00040, tree [000219], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00040, tree [000190], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00041, tree [000309], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00041, tree [000310], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00041, tree [000191], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00041, tree [000193], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00041, tree [000194], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00041, tree [000173], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00041, tree [000308], tree -> 0 Propagating 0000000000006101 assertions for BB26, stmt STMT00041, tree [000192], tree -> 13 Non-null prop for index #09 in BB26: N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void Re-morphing this stmt: STMT00041 (IL 0x039... ???) N008 ( 38, 29) [000192] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 $4c0 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 fgMorphTree (before 378): N008 ( 38, 29) [000192] --C-G------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 $4c0 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 ReMorphing args for 192.CALL: fgMorphTree (before 379): N006 ( 3, 2) [000173] ------------ * LCL_VAR ref V04 arg4 u:1 $84 fgMorphTree (after 379): N006 ( 3, 2) [000173] ------------ * LCL_VAR ref V04 arg4 u:1 $84 fgMorphTree (before 380): N007 ( 3, 10) [000308] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 fgMorphTree (after 380): N007 ( 3, 10) [000308] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 fgMorphTree (before 381): N001 ( 0, 0) [000309] ----------L- * ARGPLACE ref $151 fgMorphTree (after 381): N001 ( 0, 0) [000309] ----------L- * ARGPLACE ref $151 fgMorphTree (before 382): N002 ( 0, 0) [000310] ----------L- * ARGPLACE long $84 fgMorphTree (after 382): N002 ( 0, 0) [000310] ----------L- * ARGPLACE long $84 fgMorphTree (before 383): N005 ( 9, 7) [000194] n---G------- * OBJ struct N004 ( 3, 3) [000193] ------------ \--* ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- \--* LCL_VAR struct(AX) V17 tmp6 $4c0 fgMorphTree (before 384): N004 ( 3, 3) [000193] ------------ * ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- \--* LCL_VAR struct(AX) V17 tmp6 $4c0 fgMorphTree (before 385): N003 ( 3, 2) [000191] ----G--N---- * LCL_VAR struct(AX) V17 tmp6 $4c0 fgMorphTree (after 385): N003 ( 3, 2) [000191] ----G--N---- * LCL_VAR struct(AX) V17 tmp6 $4c0 fgMorphTree (after 384): N004 ( 3, 3) [000193] ------------ * ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- \--* LCL_VAR struct(AX) V17 tmp6 $4c0 fgMorphTree (after 383): N005 ( 9, 7) [000194] n---G------- * OBJ struct N004 ( 3, 3) [000193] ------------ \--* ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- \--* LCL_VAR struct(AX) V17 tmp6 $4c0 argSlots=6, preallocatedArgCount=5, nextSlotNum=5, outgoingArgSpaceSize=40 Local V17 should not be enregistered because: it is a struct arg ArgTable for 192.CALL after fgMorphArgs: fgArgTabEntry[arg 2 194.OBJ struct, numSlots=5, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 0 173.LCL_VAR ref, 1 reg: rdi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 308.CNS_INT long, 1 reg: r11, align=1, lateArgInx=1, processed, isNonStandard] fgMorphTree (after 378): N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 $4c0 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 optAssertionPropMain morphed tree: N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 $4c0 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 Propagating 0000000000000001 assertions for BB27, stmt STMT00036, tree [000170], tree -> 0 Propagating 0000000000000001 assertions for BB27, stmt STMT00036, tree [000171], tree -> 0 Propagating 0000000000000001 assertions for BB27, stmt STMT00036, tree [000172], tree -> 0 Propagating 0000000000000003 assertions for BB28, stmt STMT00029, tree [000140], tree -> 0 Propagating 0000000000000003 assertions for BB28, stmt STMT00029, tree [000141], tree -> 0 Propagating 0000000000000003 assertions for BB28, stmt STMT00029, tree [000142], tree -> 0 *************** In fgDebugCheckBBlist *************** Finishing PHASE Assertion prop *************** Starting PHASE Optimize index checks *************** In OptimizeRangeChecks() Blocks/trees before phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.58 [0A9..0AA) i gcsafe bwd BB11 [0034] 1 BB10 0.58 [???..???)-> BB19 (always) internal gcsafe BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB11 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} ***** BB01 STMT00001 (IL ???... ???) N008 ( 28, 25) [000006] --CXG------- * JTRUE void N007 ( 26, 23) [000200] J-CXG--N---- \--* EQ int $280 N005 ( 24, 21) [000198] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 N003 ( 1, 1) [000000] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N004 ( 3, 10) [000279] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 N006 ( 1, 1) [000199] ------------ \--* CNS_INT int 4 $44 ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} ***** BB02 STMT00002 (IL 0x00F...0x010) N003 ( 5, 4) [000009] -A------R--- * ASG int $41 N002 ( 3, 2) [000008] D------N---- +--* LCL_VAR int V07 loc1 d:2 $41 N001 ( 1, 1) [000007] ------------ \--* CNS_INT int 1 $41 ***** BB02 STMT00004 (IL ???... ???) N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int $283 N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} ***** BB03 STMT00066 (IL ???... ???) N005 ( 0, 0) [000447] -A------R--- * ASG bool N004 ( 0, 0) [000445] D------N---- +--* LCL_VAR bool V07 loc1 d:4 N003 ( 0, 0) [000446] ------------ \--* PHI bool N001 ( 0, 0) [000450] ------------ pred BB27 +--* PHI_ARG bool V07 loc1 u:3 $40 N002 ( 0, 0) [000449] ------------ pred BB02 \--* PHI_ARG bool V07 loc1 u:2 $41 ***** BB03 STMT00005 (IL 0x040...0x046) N009 ( 29, 27) [000022] --CXG------- * JTRUE void N008 ( 27, 25) [000021] J-CXG--N---- \--* NE int $287 N006 ( 25, 23) [000019] --CXG------- +--* CAST int <- bool <- int $286 N005 ( 24, 21) [000018] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 N003 ( 1, 1) [000017] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000312] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca N007 ( 1, 1) [000020] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} ***** BB04 STMT00065 (IL ???... ???) N005 ( 0, 0) [000444] -A------R--- * ASG bool N004 ( 0, 0) [000442] D------N---- +--* LCL_VAR bool V07 loc1 d:6 N003 ( 0, 0) [000443] ------------ \--* PHI bool N001 ( 0, 0) [000452] ------------ pred BB23 +--* PHI_ARG bool V07 loc1 u:5 $40 N002 ( 0, 0) [000451] ------------ pred BB03 \--* PHI_ARG bool V07 loc1 u:4 $580 ***** BB04 STMT00006 (IL 0x055...0x05B) N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int $28b N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 $40 ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} ***** BB05 STMT00064 (IL ???... ???) N005 ( 0, 0) [000441] -A------R--- * ASG bool N004 ( 0, 0) [000439] D------N---- +--* LCL_VAR bool V07 loc1 d:8 N003 ( 0, 0) [000440] ------------ \--* PHI bool N001 ( 0, 0) [000454] ------------ pred BB18 +--* PHI_ARG bool V07 loc1 u:7 $40 N002 ( 0, 0) [000453] ------------ pred BB04 \--* PHI_ARG bool V07 loc1 u:6 $581 ***** BB05 STMT00007 (IL 0x06A...0x070) N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int $28f N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 $40 ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} ***** BB06 STMT00063 (IL ???... ???) N005 ( 0, 0) [000438] -A------R--- * ASG bool N004 ( 0, 0) [000436] D------N---- +--* LCL_VAR bool V07 loc1 d:10 N003 ( 0, 0) [000437] ------------ \--* PHI bool N001 ( 0, 0) [000456] ------------ pred BB28 +--* PHI_ARG bool V07 loc1 u:9 $40 N002 ( 0, 0) [000455] ------------ pred BB05 \--* PHI_ARG bool V07 loc1 u:8 $582 ***** BB06 STMT00009 (IL ???... ???) N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref $167 N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB06 STMT00010 (IL 0x08B...0x092) N009 ( 26, 26) [000050] -ACXG---R--- * ASG struct (copy) $VN.Void N008 ( 3, 2) [000048] D------N---- +--* LCL_VAR struct(AX) V12 tmp1 N007 ( 22, 23) [000045] --CXG------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 N004 ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long N003 ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class $1d0 N006 ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref $486 N005 ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 $4c2 ***** BB06 STMT00011 (IL ???... ???) N016 ( 18, 15) [000355] -A-XGO------ * COMMA void N009 ( 10, 8) [000471] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref $487 N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref $487 N001 ( 3, 2) [000341] ----G--N---- | | \--* LCL_VAR struct(AX) V12 tmp1 $4c3 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 N015 ( 8, 7) [000354] -A--GO--R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] n----O------ \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 ***** BB06 STMT00057 (IL 0x0E1... ???) N011 ( 27, 29) [000419] --CXG------- * JTRUE void N010 ( 25, 27) [000409] J-CXG--N---- \--* NE int $295 N008 ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int $294 N007 ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $212 N004 ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref $48a N005 ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c4 N009 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} ***** BB07 STMT00061 (IL ???... ???) N005 ( 0, 0) [000432] -A------R--- * ASG bool N004 ( 0, 0) [000430] D------N---- +--* LCL_VAR bool V07 loc1 d:14 N003 ( 0, 0) [000431] ------------ \--* PHI bool N001 ( 0, 0) [000461] ------------ pred BB16 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 $583 ***** BB07 STMT00026 (IL 0x0EA...0x0EB) N003 ( 7, 5) [000127] -A------R--- * ASG int $584 N002 ( 3, 2) [000126] D------N---- +--* LCL_VAR int V06 loc0 d:4 $584 N001 ( 3, 2) [000125] ------------ \--* LCL_VAR int V07 loc1 u:14 (last use) $584 ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} ***** BB08 STMT00059 (IL ???... ???) N005 ( 0, 0) [000426] -A------R--- * ASG bool N004 ( 0, 0) [000424] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000425] ------------ \--* PHI bool N001 ( 0, 0) [000463] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:4 $584 N002 ( 0, 0) [000448] ------------ pred BB24 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB08 STMT00027 (IL 0x0EC...0x0ED) N002 ( 4, 3) [000129] ------------ * RETURN int $214 N001 ( 3, 2) [000128] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) $585 ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} ***** BB09 STMT00062 (IL ???... ???) N005 ( 0, 0) [000435] -A------R--- * ASG bool N004 ( 0, 0) [000433] D------N---- +--* LCL_VAR bool V07 loc1 d:11 N003 ( 0, 0) [000434] ------------ \--* PHI bool N001 ( 0, 0) [000460] ------------ pred BB15 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 $583 ***** BB09 STMT00013 (IL 0x095...0x0A7) N017 ( 59, 54) [000073] -ACXG---R--- * ASG struct (copy) $VN.Void N016 ( 3, 2) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 d:2 N015 ( 55, 51) [000070] --CXG------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 N009 ( 26, 26) [000360] -ACXG---R-L- this SETUP +--* ASG ref $16c N008 ( 3, 2) [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 d:2 $16c N007 ( 22, 23) [000066] --CXG------- | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c N004 ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref $48c N005 ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c5 N012 ( 3, 2) [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 u:2 (last use) $16c N013 ( 3, 2) [000069] ------------ arg2 in rsi +--* LCL_VAR ref V01 arg1 u:1 $81 N014 ( 3, 10) [000356] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 ***** BB09 STMT00014 (IL ???... ???) N003 ( 7, 7) [000078] -A------R--- * ASG ref $370 N002 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V10 loc4 d:2 $370 N001 ( 3, 4) [000076] ------------ \--* LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) $370 ***** BB09 STMT00046 (IL 0x0A9... ???) N008 ( 30, 26) [000228] --CXG------- * JTRUE void N007 ( 28, 24) [000249] J-CXG--N---- \--* NE int $296 N005 ( 26, 22) [000247] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 N003 ( 3, 2) [000080] ------------ this in rdi | +--* LCL_VAR ref V10 loc4 u:2 $370 N004 ( 3, 10) [000365] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 N006 ( 1, 1) [000248] ------------ \--* CNS_INT int 4 $44 ------------ BB10 [0A9..0AA), preds={BB09} succs={BB11} ***** BB10 STMT00049 (IL 0x0A9... ???) N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void N003 ( 3, 2) [000237] ------------ arg0 in rdi +--* LCL_VAR ref V10 loc4 u:2 $370 N004 ( 1, 1) [000238] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB10 STMT00050 (IL 0x0A9... ???) N003 ( 5, 4) [000242] -A------R--- * ASG bool $40 N002 ( 3, 2) [000241] D------N---- +--* LCL_VAR int V19 tmp8 d:3 $40 N001 ( 1, 1) [000240] ------------ \--* CNS_INT int 0 $40 ------------ BB11 [???..???) -> BB19 (always), preds={BB10} succs={BB19} ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} ***** BB12 STMT00028 (IL 0x072...0x07E) N015 ( 28, 23) [000139] --CXG------- * JTRUE void N014 ( 26, 21) [000138] J-CXG--N---- \--* EQ int $291 N012 ( 24, 19) [000136] --CXG------- +--* CAST int <- bool <- int $290 N011 ( 23, 17) [000135] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f N006 ( 3, 2) [000130] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 (last use) $80 N007 ( 1, 1) [000131] ------------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 u:1 $82 N008 ( 1, 1) [000132] ------------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 u:1 $83 N009 ( 3, 2) [000133] ------------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 u:1 $84 N010 ( 1, 1) [000134] ------------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 u:1 $c0 N013 ( 1, 1) [000137] ------------ \--* CNS_INT int 0 $40 ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} ***** BB14 STMT00048 (IL 0x0A9... ???) N010 ( 24, 17) [000234] -ACXG---R--- * ASG bool $297 N009 ( 3, 2) [000233] D------N---- +--* LCL_VAR int V19 tmp8 d:2 $297 N008 ( 20, 14) [000232] --CXG------- \--* CAST int <- bool <- int $297 N007 ( 19, 12) [000230] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 N004 ( 1, 1) [000079] ------------ arg0 in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 2) [000229] ------------ arg1 in rsi +--* LCL_VAR ref V10 loc4 u:2 $370 N006 ( 1, 1) [000081] ------------ arg2 in rdx \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB14 STMT00016 (IL ???... ???) N004 ( 7, 6) [000087] ------------ * JTRUE void N003 ( 5, 4) [000086] J------N---- \--* EQ int $298 N001 ( 3, 2) [000235] ------------ +--* LCL_VAR int V19 tmp8 u:2 (last use) $297 N002 ( 1, 1) [000085] ------------ \--* CNS_INT int 0 $40 ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB14,BB21} succs={BB16,BB09} ***** BB15 STMT00060 (IL ???... ???) N005 ( 0, 0) [000429] -A------R--- * ASG bool N004 ( 0, 0) [000427] D------N---- +--* LCL_VAR bool V07 loc1 d:13 N003 ( 0, 0) [000428] ------------ \--* PHI bool N001 ( 0, 0) [000462] ------------ pred BB14 +--* PHI_ARG bool V07 loc1 u:11 $586 N002 ( 0, 0) [000459] ------------ pred BB21 \--* PHI_ARG bool V07 loc1 u:12 $40 ***** BB15 STMT00012 (IL 0x0E1...0x0E8) N011 ( 27, 29) [000063] --CXG------- * JTRUE void N010 ( 25, 27) [000062] J-CXG--N---- \--* NE int $29b N008 ( 23, 25) [000060] --CXG------- +--* CAST int <- bool <- int $29a N007 ( 22, 23) [000057] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $21b N004 ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref $490 N005 ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c6 N009 ( 1, 1) [000061] ------------ \--* CNS_INT int 0 $40 ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} ***** BB17 STMT00031 (IL ???... ???) N011 ( 24, 18) [000151] --CXG------- * JTRUE void N010 ( 22, 16) [000150] J-CXG--N---- \--* NE int $28d N008 ( 20, 14) [000148] --CXG------- +--* CAST int <- bool <- int $28c N007 ( 19, 12) [000146] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c N004 ( 1, 1) [000143] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000144] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000145] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 $84 N009 ( 1, 1) [000149] ------------ \--* CNS_INT int 0 $40 ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} ***** BB18 STMT00032 (IL 0x068...0x069) N003 ( 5, 4) [000154] -A------R--- * ASG int $40 N002 ( 3, 2) [000153] D------N---- +--* LCL_VAR int V07 loc1 d:7 $40 N001 ( 1, 1) [000152] ------------ \--* CNS_INT int 0 $40 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB11} succs={BB20,BB21} ***** BB19 STMT00017 (IL 0x0B5...0x0B7) N004 ( 7, 6) [000091] ------------ * JTRUE void N003 ( 5, 4) [000090] J------N---- \--* EQ int $284 N001 ( 3, 2) [000088] ------------ +--* LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000089] ------------ \--* CNS_INT ref null $VN.Null ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} ***** BB20 STMT00019 (IL 0x0B9...0x0CA) N005 ( 19, 10) [000101] -ACXG---R--- * ASG ref $376 N004 ( 3, 2) [000100] D------N---- +--* LCL_VAR ref V14 tmp3 d:2 $385 N003 ( 15, 7) [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 N002 ( 1, 1) [000098] ------------ arg0 in rdi \--* CNS_INT long 2 $2c4 ***** BB20 STMT00020 (IL ???... ???) N015 ( 25, 24) [000107] -A-XG------- * ASG ref $VN.Void N013 ( 23, 22) [000384] -A-XG--N---- +--* COMMA ref $VN.Void N008 ( 17, 17) [000378] -A-X-------- | +--* ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 $40 N007 ( 12, 9) [000467] -A-X-------- | | \--* COMMA int $299 N005 ( 9, 7) [000465] -A-X----R--- | | +--* ASG int $VN.Void N004 ( 3, 2) [000464] D------N---- | | | +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- | | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | | | \--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 3, 2) [000466] ------------ | | \--* LCL_VAR int V28 cse0 u:1 $299 N012 ( 6, 5) [000106] a---G--N---- | \--* IND ref $83 N011 ( 4, 3) [000383] -------N---- | \--* ADD byref $441 N009 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N010 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N014 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 ***** BB20 STMT00021 (IL ???...0x0CF) N010 ( 18, 18) [000112] -A-XG------- * ASG ref $VN.Void N008 ( 14, 15) [000394] ---XG--N---- +--* COMMA ref $VN.Void N003 ( 8, 10) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 $41 N002 ( 3, 2) [000468] ------------ | | \--* LCL_VAR int V28 cse0 u:1 $3c1 N007 ( 6, 5) [000111] a---G--N---- | \--* IND ref $370 N006 ( 4, 3) [000393] -------N---- | \--* ADD byref $442 N004 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N005 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 N009 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) $370 ***** BB20 STMT00052 (IL ???... ???) N003 ( 18, 8) [000261] -AC-----R--- * ASG ref $647 N002 ( 3, 2) [000260] D------N---- +--* LCL_VAR ref V20 tmp9 d:2 $647 N001 ( 14, 5) [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 ***** BB20 STMT00053 (IL ???... ???) N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N007 ( 21, 14) [000396] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 d:2 N005 ( 17, 11) [000255] --CXG------- | \--* IND ref N004 ( 15, 9) [000254] --CXG--N---- | \--* ADD byref $403 N002 ( 14, 5) [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] $48 N010 ( 3, 2) [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 u:2 $647 N012 ( 3, 2) [000102] ------------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 u:2 (last use) $385 N013 ( 1, 4) [000256] ------------ arg2 in rdx \--* CNS_INT int 0x7D2C $64 ***** BB20 STMT00054 (IL ???... ???) N003 ( 5, 4) [000269] IA------R--- * ASG struct (init) $VN.Void N002 ( 3, 2) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 d:2 N001 ( 1, 1) [000268] ------------ \--* CNS_INT int 0 $40 ***** BB20 STMT00055 (IL ???... ???) N003 ( 5, 6) [000273] -A------R--- * ASG ref $82 N002 ( 3, 4) [000272] U------N---- +--* LCL_FLD ref V15 tmp4 ud:2->3[+0] Fseq[TypeParameter] $38c N001 ( 1, 1) [000096] ------------ \--* LCL_VAR ref V02 arg2 u:1 $82 ***** BB20 STMT00056 (IL ???... ???) N003 ( 7, 7) [000277] -A------R--- * ASG ref $647 N002 ( 3, 4) [000276] U------N---- +--* LCL_FLD ref V15 tmp4 ud:3->4[+8] Fseq[DiagnosticInfo] $38d N001 ( 3, 2) [000264] ------------ \--* LCL_VAR ref V20 tmp9 u:2 (last use) $647 ***** BB20 STMT00025 (IL 0x0DA... ???) N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct $507 N004 ( 3, 3) [000123] ------------ | \--* ADDR byref $40b N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} ***** BB21 STMT00018 (IL 0x0DF...0x0E0) N003 ( 5, 4) [000094] -A------R--- * ASG int $40 N002 ( 3, 2) [000093] D------N---- +--* LCL_VAR int V07 loc1 d:12 $40 N001 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 $40 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} ***** BB22 STMT00033 (IL 0x048...0x051) N011 ( 24, 18) [000162] --CXG------- * JTRUE void N010 ( 22, 16) [000161] J-CXG--N---- \--* NE int $289 N008 ( 20, 14) [000159] --CXG------- +--* CAST int <- bool <- int $288 N007 ( 19, 12) [000158] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 N004 ( 1, 1) [000155] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000156] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000157] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 $84 N009 ( 1, 1) [000160] ------------ \--* CNS_INT int 0 $40 ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} ***** BB23 STMT00034 (IL 0x053...0x054) N003 ( 5, 4) [000165] -A------R--- * ASG int $40 N002 ( 3, 2) [000164] D------N---- +--* LCL_VAR int V07 loc1 d:5 $40 N001 ( 1, 1) [000163] ------------ \--* CNS_INT int 0 $40 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} ***** BB24 STMT00042 (IL 0x008...0x009) N003 ( 5, 4) [000197] -A------R--- * ASG int $41 N002 ( 3, 2) [000196] D------N---- +--* LCL_VAR int V06 loc0 d:2 $41 N001 ( 1, 1) [000195] ------------ \--* CNS_INT int 1 $41 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} ***** BB25 STMT00035 (IL 0x019...0x01B) N004 ( 7, 6) [000169] ------------ * JTRUE void N003 ( 5, 4) [000168] J------N---- \--* EQ int $284 N001 ( 3, 2) [000166] ------------ +--* LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000167] ------------ \--* CNS_INT ref null $VN.Null ------------ BB26 [01D..03E), preds={BB25} succs={BB27} ***** BB26 STMT00037 (IL 0x01D...0x02E) N005 ( 19, 10) [000179] -ACXG---R--- * ASG ref $342 N004 ( 3, 2) [000178] D------N---- +--* LCL_VAR ref V16 tmp5 d:2 $380 N003 ( 15, 7) [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 N002 ( 1, 1) [000176] ------------ arg0 in rdi \--* CNS_INT long 1 $2c0 ***** BB26 STMT00038 (IL ???... ???) N011 ( 18, 19) [000185] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000298] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000292] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $348 N001 ( 1, 1) [000182] ------------ | | +--* CNS_INT int 0 $40 N003 ( 5, 4) [000291] ---X-------- | | \--* ARR_LENGTH int $285 N002 ( 3, 2) [000181] ------------ | | \--* LCL_VAR ref V16 tmp5 u:2 $380 N008 ( 6, 5) [000184] a---G--N---- | \--* IND ref $83 N007 ( 4, 3) [000297] -------N---- | \--* ADD byref $440 N005 ( 3, 2) [000289] ------------ | +--* LCL_VAR ref V16 tmp5 u:2 $380 N006 ( 1, 1) [000296] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N010 ( 1, 1) [000183] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 ***** BB26 STMT00043 (IL ???... ???) N003 ( 18, 8) [000216] -AC-----R--- * ASG ref $34c N002 ( 3, 2) [000215] D------N---- +--* LCL_VAR ref V18 tmp7 d:2 $34c N001 ( 14, 5) [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c ***** BB26 STMT00044 (IL ???... ???) N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N007 ( 21, 14) [000300] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 d:2 N005 ( 17, 11) [000210] --CXG------- | \--* IND ref N004 ( 15, 9) [000209] --CXG--N---- | \--* ADD byref $403 N002 ( 14, 5) [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] $48 N010 ( 3, 2) [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 u:2 $34c N012 ( 3, 2) [000180] ------------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 u:2 (last use) $380 N013 ( 1, 4) [000211] ------------ arg2 in rdx \--* CNS_INT int 0x7AA4 $49 ***** BB26 STMT00040 (IL ???... ???) N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void N004 ( 3, 3) [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 $481 N005 ( 1, 1) [000174] ------------ arg1 in rsi +--* LCL_VAR ref V02 arg2 u:1 $82 N006 ( 3, 2) [000219] ------------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 u:2 (last use) $34c ***** BB26 STMT00041 (IL 0x039... ???) N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 $4c0 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} ***** BB27 STMT00036 (IL 0x03E...0x03F) N003 ( 5, 4) [000172] -A------R--- * ASG int $40 N002 ( 3, 2) [000171] D------N---- +--* LCL_VAR int V07 loc1 d:3 $40 N001 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 $40 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} ***** BB28 STMT00029 (IL 0x080...0x081) N003 ( 5, 4) [000142] -A------R--- * ASG int $40 N002 ( 3, 2) [000141] D------N---- +--* LCL_VAR int V07 loc1 d:9 $40 N001 ( 1, 1) [000140] ------------ \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- ArrSize for lengthVN:3C1 = 0 [RangeCheck::GetRange] BB20N001 ( 1, 1) [000104] ------------ * CNS_INT int 0 $40 { Computed Range [000104] => <0, 0> } Does overflow [000104]? [000104] does not overflow Range value <0, 0> [RangeCheck::Widen] BB20, [000104] <0, 0> BetweenBounds <0, [000467]> $3c1 upper bound is: {ARR_LENGTH($385)} Array size is: 0 ArrSize for lengthVN:3C1 = 0 [RangeCheck::GetRange] BB20N001 ( 1, 1) [000109] ------------ * CNS_INT int 1 $41 { Computed Range [000109] => <1, 1> } Does overflow [000109]? [000109] does not overflow Range value <1, 1> [RangeCheck::Widen] BB20, [000109] <1, 1> BetweenBounds <0, [000468]> $3c1 upper bound is: {ARR_LENGTH($385)} Array size is: 0 ArrSize for lengthVN:3C0 = 0 [RangeCheck::GetRange] BB26N001 ( 1, 1) [000182] ------------ * CNS_INT int 0 $40 { Computed Range [000182] => <0, 0> } Does overflow [000182]? [000182] does not overflow Range value <0, 0> [RangeCheck::Widen] BB26, [000182] <0, 0> BetweenBounds <0, [000291]> $3c0 upper bound is: {ARR_LENGTH($380)} Array size is: 0 *************** Finishing PHASE Optimize index checks *************** Starting PHASE Update flow graph opt pass *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.58 [0A9..0AA) i gcsafe bwd BB11 [0034] 1 BB10 0.58 [???..???)-> BB19 (always) internal gcsafe BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB11 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB10 and BB11: *************** In fgDebugCheckBBlist After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB19 (always) i gcsafe bwd BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB10 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Update flow graph opt pass *************** Starting PHASE Compute edge weights (2, false) fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights *************** Finishing PHASE Compute edge weights (2, false) *************** Starting PHASE Determine first cold block *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block Trees before Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB19 (always) i gcsafe bwd BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC BB19 [0017] 2 BB14,BB10 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} ***** BB01 STMT00001 (IL ???... ???) N008 ( 28, 25) [000006] --CXG------- * JTRUE void N007 ( 26, 23) [000200] J-CXG--N---- \--* EQ int $280 N005 ( 24, 21) [000198] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 N003 ( 1, 1) [000000] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N004 ( 3, 10) [000279] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 N006 ( 1, 1) [000199] ------------ \--* CNS_INT int 4 $44 ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} ***** BB02 STMT00002 (IL 0x00F...0x010) N003 ( 5, 4) [000009] -A------R--- * ASG int $41 N002 ( 3, 2) [000008] D------N---- +--* LCL_VAR int V07 loc1 d:2 $41 N001 ( 1, 1) [000007] ------------ \--* CNS_INT int 1 $41 ***** BB02 STMT00004 (IL ???... ???) N012 ( 44, 35) [000016] --CXG------- * JTRUE void N011 ( 42, 33) [000015] J-CXG--N---- \--* NE int $283 N009 ( 40, 31) [000205] --CXG------- +--* CAST int <- bool <- int $282 N008 ( 39, 29) [000204] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N007 ( 25, 23) [000203] --CXG------- arg0 in rdi | \--* CAST int <- byte <- int $281 N006 ( 24, 21) [000202] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 N004 ( 1, 1) [000010] ------------ this in rdi | +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 N010 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} ***** BB03 STMT00066 (IL ???... ???) N005 ( 0, 0) [000447] -A------R--- * ASG bool N004 ( 0, 0) [000445] D------N---- +--* LCL_VAR bool V07 loc1 d:4 N003 ( 0, 0) [000446] ------------ \--* PHI bool N001 ( 0, 0) [000450] ------------ pred BB27 +--* PHI_ARG bool V07 loc1 u:3 $40 N002 ( 0, 0) [000449] ------------ pred BB02 \--* PHI_ARG bool V07 loc1 u:2 $41 ***** BB03 STMT00005 (IL 0x040...0x046) N009 ( 29, 27) [000022] --CXG------- * JTRUE void N008 ( 27, 25) [000021] J-CXG--N---- \--* NE int $287 N006 ( 25, 23) [000019] --CXG------- +--* CAST int <- bool <- int $286 N005 ( 24, 21) [000018] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 N003 ( 1, 1) [000017] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000312] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca N007 ( 1, 1) [000020] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} ***** BB04 STMT00065 (IL ???... ???) N005 ( 0, 0) [000444] -A------R--- * ASG bool N004 ( 0, 0) [000442] D------N---- +--* LCL_VAR bool V07 loc1 d:6 N003 ( 0, 0) [000443] ------------ \--* PHI bool N001 ( 0, 0) [000452] ------------ pred BB23 +--* PHI_ARG bool V07 loc1 u:5 $40 N002 ( 0, 0) [000451] ------------ pred BB03 \--* PHI_ARG bool V07 loc1 u:4 $580 ***** BB04 STMT00006 (IL 0x055...0x05B) N009 ( 29, 27) [000028] --CXG------- * JTRUE void N008 ( 27, 25) [000027] J-CXG--N---- \--* NE int $28b N006 ( 25, 23) [000025] --CXG------- +--* CAST int <- bool <- int $28a N005 ( 24, 21) [000024] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N003 ( 1, 1) [000023] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc N007 ( 1, 1) [000026] ------------ \--* CNS_INT int 0 $40 ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} ***** BB05 STMT00064 (IL ???... ???) N005 ( 0, 0) [000441] -A------R--- * ASG bool N004 ( 0, 0) [000439] D------N---- +--* LCL_VAR bool V07 loc1 d:8 N003 ( 0, 0) [000440] ------------ \--* PHI bool N001 ( 0, 0) [000454] ------------ pred BB18 +--* PHI_ARG bool V07 loc1 u:7 $40 N002 ( 0, 0) [000453] ------------ pred BB04 \--* PHI_ARG bool V07 loc1 u:6 $581 ***** BB05 STMT00007 (IL 0x06A...0x070) N009 ( 29, 27) [000034] --CXG------- * JTRUE void N008 ( 27, 25) [000033] J-CXG--N---- \--* NE int $28f N006 ( 25, 23) [000031] --CXG------- +--* CAST int <- bool <- int $28e N005 ( 24, 21) [000030] --CXG------- | \--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N003 ( 1, 1) [000029] ------------ this in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce N007 ( 1, 1) [000032] ------------ \--* CNS_INT int 0 $40 ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} ***** BB06 STMT00063 (IL ???... ???) N005 ( 0, 0) [000438] -A------R--- * ASG bool N004 ( 0, 0) [000436] D------N---- +--* LCL_VAR bool V07 loc1 d:10 N003 ( 0, 0) [000437] ------------ \--* PHI bool N001 ( 0, 0) [000456] ------------ pred BB28 +--* PHI_ARG bool V07 loc1 u:9 $40 N002 ( 0, 0) [000455] ------------ pred BB05 \--* PHI_ARG bool V07 loc1 u:8 $582 ***** BB06 STMT00009 (IL ???... ???) N007 ( 20, 13) [000042] -ACXG---R--- * ASG ref $167 N006 ( 3, 2) [000039] D---G--N---- +--* LCL_VAR ref (AX) V23 tmp12 N005 ( 16, 10) [000037] --CXG------- \--* CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 N003 ( 1, 1) [000035] ------------ this in rdi +--* LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB06 STMT00010 (IL 0x08B...0x092) N009 ( 26, 26) [000050] -ACXG---R--- * ASG struct (copy) $VN.Void N008 ( 3, 2) [000048] D------N---- +--* LCL_VAR struct(AX) V12 tmp1 N007 ( 22, 23) [000045] --CXG------- \--* CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 N004 ( 5, 12) [000047] n----------- arg1 in rsi +--* IND long N003 ( 3, 10) [000046] ------------ | \--* CNS_INT(h) long 0xd1ffab1e class $1d0 N006 ( 3, 3) [000044] ------------ this in rdi \--* ADDR byref $486 N005 ( 3, 2) [000043] ----G--N---- \--* LCL_VAR struct(AX)(P) V09 loc3 \--* ref V09.array (offs=0x00) -> V23 tmp12 $4c2 ***** BB06 STMT00011 (IL ???... ???) N016 ( 18, 15) [000355] -A-XGO------ * COMMA void N009 ( 10, 8) [000471] -A-XG------- +--* COMMA void N004 ( 3, 3) [000343] -A------R--- | +--* ASG byref $487 N003 ( 1, 1) [000342] D------N---- | | +--* LCL_VAR byref V25 tmp14 d:2 $487 N002 ( 3, 3) [000340] ------------ | | \--* ADDR byref $487 N001 ( 3, 2) [000341] ----G--N---- | | \--* LCL_VAR struct(AX) V12 tmp1 $4c3 N008 ( 7, 5) [000347] -A-XG---R--- | \--* ASG ref N007 ( 3, 2) [000344] D---G--N---- | +--* LCL_VAR ref (AX) V21 tmp10 N006 ( 3, 2) [000346] ---X-------- | \--* IND ref N005 ( 1, 1) [000345] ------------ | \--* LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 N015 ( 8, 7) [000354] -A--GO--R--- \--* ASG int N014 ( 3, 2) [000349] D---G--N---- +--* LCL_VAR int (AX) V22 tmp11 N013 ( 4, 4) [000353] n----O------ \--* IND int N012 ( 2, 2) [000352] -------N---- \--* ADD byref $407 N010 ( 1, 1) [000350] ------------ +--* LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ \--* CNS_INT long 8 Fseq[_index] $2c3 ***** BB06 STMT00057 (IL 0x0E1... ???) N011 ( 27, 29) [000419] --CXG------- * JTRUE void N010 ( 25, 27) [000409] J-CXG--N---- \--* NE int $295 N008 ( 23, 25) [000410] --CXG------- +--* CAST int <- bool <- int $294 N007 ( 22, 23) [000411] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $212 N004 ( 5, 12) [000414] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000415] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000416] ----G------- this in rdi | \--* ADDR byref $48a N005 ( 3, 2) [000417] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c4 N009 ( 1, 1) [000418] ------------ \--* CNS_INT int 0 $40 ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} ***** BB07 STMT00061 (IL ???... ???) N005 ( 0, 0) [000432] -A------R--- * ASG bool N004 ( 0, 0) [000430] D------N---- +--* LCL_VAR bool V07 loc1 d:14 N003 ( 0, 0) [000431] ------------ \--* PHI bool N001 ( 0, 0) [000461] ------------ pred BB16 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 $583 ***** BB07 STMT00026 (IL 0x0EA...0x0EB) N003 ( 7, 5) [000127] -A------R--- * ASG int $584 N002 ( 3, 2) [000126] D------N---- +--* LCL_VAR int V06 loc0 d:4 $584 N001 ( 3, 2) [000125] ------------ \--* LCL_VAR int V07 loc1 u:14 (last use) $584 ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} ***** BB08 STMT00059 (IL ???... ???) N005 ( 0, 0) [000426] -A------R--- * ASG bool N004 ( 0, 0) [000424] D------N---- +--* LCL_VAR bool V06 loc0 d:3 N003 ( 0, 0) [000425] ------------ \--* PHI bool N001 ( 0, 0) [000463] ------------ pred BB07 +--* PHI_ARG bool V06 loc0 u:4 $584 N002 ( 0, 0) [000448] ------------ pred BB24 \--* PHI_ARG bool V06 loc0 u:2 $41 ***** BB08 STMT00027 (IL 0x0EC...0x0ED) N002 ( 4, 3) [000129] ------------ * RETURN int $214 N001 ( 3, 2) [000128] ------------ \--* LCL_VAR int V06 loc0 u:3 (last use) $585 ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} ***** BB09 STMT00062 (IL ???... ???) N005 ( 0, 0) [000435] -A------R--- * ASG bool N004 ( 0, 0) [000433] D------N---- +--* LCL_VAR bool V07 loc1 d:11 N003 ( 0, 0) [000434] ------------ \--* PHI bool N001 ( 0, 0) [000460] ------------ pred BB15 +--* PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ pred BB06 \--* PHI_ARG bool V07 loc1 u:10 $583 ***** BB09 STMT00013 (IL 0x095...0x0A7) N017 ( 59, 54) [000073] -ACXG---R--- * ASG struct (copy) $VN.Void N016 ( 3, 2) [000071] D------N---- +--* LCL_VAR struct V13 tmp2 d:2 N015 ( 55, 51) [000070] --CXG------- \--* CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 N009 ( 26, 26) [000360] -ACXG---R-L- this SETUP +--* ASG ref $16c N008 ( 3, 2) [000359] D------N---- | +--* LCL_VAR ref V26 tmp15 d:2 $16c N007 ( 22, 23) [000066] --CXG------- | \--* CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c N004 ( 5, 12) [000068] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000067] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000065] ------------ this in rdi | \--* ADDR byref $48c N005 ( 3, 2) [000064] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c5 N012 ( 3, 2) [000361] ------------ this in rdi +--* LCL_VAR ref V26 tmp15 u:2 (last use) $16c N013 ( 3, 2) [000069] ------------ arg2 in rsi +--* LCL_VAR ref V01 arg1 u:1 $81 N014 ( 3, 10) [000356] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 ***** BB09 STMT00014 (IL ???... ???) N003 ( 7, 7) [000078] -A------R--- * ASG ref $370 N002 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V10 loc4 d:2 $370 N001 ( 3, 4) [000076] ------------ \--* LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) $370 ***** BB09 STMT00046 (IL 0x0A9... ???) N008 ( 30, 26) [000228] --CXG------- * JTRUE void N007 ( 28, 24) [000249] J-CXG--N---- \--* NE int $296 N005 ( 26, 22) [000247] --CXG------- +--* CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 N003 ( 3, 2) [000080] ------------ this in rdi | +--* LCL_VAR ref V10 loc4 u:2 $370 N004 ( 3, 10) [000365] ------------ arg1 in r11 | \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 N006 ( 1, 1) [000248] ------------ \--* CNS_INT int 4 $44 ------------ BB10 [0A9..0AA) -> BB19 (always), preds={BB09} succs={BB19} ***** BB10 STMT00049 (IL 0x0A9... ???) N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void N003 ( 3, 2) [000237] ------------ arg0 in rdi +--* LCL_VAR ref V10 loc4 u:2 $370 N004 ( 1, 1) [000238] ------------ arg1 in rsi \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB10 STMT00050 (IL 0x0A9... ???) N003 ( 5, 4) [000242] -A------R--- * ASG bool $40 N002 ( 3, 2) [000241] D------N---- +--* LCL_VAR int V19 tmp8 d:3 $40 N001 ( 1, 1) [000240] ------------ \--* CNS_INT int 0 $40 ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} ***** BB12 STMT00028 (IL 0x072...0x07E) N015 ( 28, 23) [000139] --CXG------- * JTRUE void N014 ( 26, 21) [000138] J-CXG--N---- \--* EQ int $291 N012 ( 24, 19) [000136] --CXG------- +--* CAST int <- bool <- int $290 N011 ( 23, 17) [000135] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f N006 ( 3, 2) [000130] ------------ arg0 in rdi | +--* LCL_VAR ref V00 arg0 u:1 (last use) $80 N007 ( 1, 1) [000131] ------------ arg1 in rsi | +--* LCL_VAR ref V02 arg2 u:1 $82 N008 ( 1, 1) [000132] ------------ arg2 in rdx | +--* LCL_VAR ref V03 arg3 u:1 $83 N009 ( 3, 2) [000133] ------------ arg3 in rcx | +--* LCL_VAR ref V04 arg4 u:1 $84 N010 ( 1, 1) [000134] ------------ arg4 in r8 | \--* LCL_VAR byref V05 arg5 u:1 $c0 N013 ( 1, 1) [000137] ------------ \--* CNS_INT int 0 $40 ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} ***** BB14 STMT00048 (IL 0x0A9... ???) N010 ( 24, 17) [000234] -ACXG---R--- * ASG bool $297 N009 ( 3, 2) [000233] D------N---- +--* LCL_VAR int V19 tmp8 d:2 $297 N008 ( 20, 14) [000232] --CXG------- \--* CAST int <- bool <- int $297 N007 ( 19, 12) [000230] --CXG------- \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 N004 ( 1, 1) [000079] ------------ arg0 in rdi +--* LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 2) [000229] ------------ arg1 in rsi +--* LCL_VAR ref V10 loc4 u:2 $370 N006 ( 1, 1) [000081] ------------ arg2 in rdx \--* LCL_VAR byref V05 arg5 u:1 $c0 ***** BB14 STMT00016 (IL ???... ???) N004 ( 7, 6) [000087] ------------ * JTRUE void N003 ( 5, 4) [000086] J------N---- \--* EQ int $298 N001 ( 3, 2) [000235] ------------ +--* LCL_VAR int V19 tmp8 u:2 (last use) $297 N002 ( 1, 1) [000085] ------------ \--* CNS_INT int 0 $40 ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB14,BB21} succs={BB16,BB09} ***** BB15 STMT00060 (IL ???... ???) N005 ( 0, 0) [000429] -A------R--- * ASG bool N004 ( 0, 0) [000427] D------N---- +--* LCL_VAR bool V07 loc1 d:13 N003 ( 0, 0) [000428] ------------ \--* PHI bool N001 ( 0, 0) [000462] ------------ pred BB14 +--* PHI_ARG bool V07 loc1 u:11 $586 N002 ( 0, 0) [000459] ------------ pred BB21 \--* PHI_ARG bool V07 loc1 u:12 $40 ***** BB15 STMT00012 (IL 0x0E1...0x0E8) N011 ( 27, 29) [000063] --CXG------- * JTRUE void N010 ( 25, 27) [000062] J-CXG--N---- \--* NE int $29b N008 ( 23, 25) [000060] --CXG------- +--* CAST int <- bool <- int $29a N007 ( 22, 23) [000057] --CXG------- | \--* CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $21b N004 ( 5, 12) [000059] n----------- arg1 in rsi | +--* IND long N003 ( 3, 10) [000058] ------------ | | \--* CNS_INT(h) long 0xd1ffab1e class $1d1 N006 ( 3, 3) [000056] ------------ this in rdi | \--* ADDR byref $490 N005 ( 3, 2) [000055] ----G--N---- | \--* LCL_VAR struct(AX)(P) V08 loc2 | \--* ref V08._array (offs=0x00) -> V21 tmp10 | \--* int V08._index (offs=0x08) -> V22 tmp11 $4c6 N009 ( 1, 1) [000061] ------------ \--* CNS_INT int 0 $40 ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} ***** BB17 STMT00031 (IL ???... ???) N011 ( 24, 18) [000151] --CXG------- * JTRUE void N010 ( 22, 16) [000150] J-CXG--N---- \--* NE int $28d N008 ( 20, 14) [000148] --CXG------- +--* CAST int <- bool <- int $28c N007 ( 19, 12) [000146] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c N004 ( 1, 1) [000143] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000144] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000145] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 $84 N009 ( 1, 1) [000149] ------------ \--* CNS_INT int 0 $40 ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} ***** BB18 STMT00032 (IL 0x068...0x069) N003 ( 5, 4) [000154] -A------R--- * ASG int $40 N002 ( 3, 2) [000153] D------N---- +--* LCL_VAR int V07 loc1 d:7 $40 N001 ( 1, 1) [000152] ------------ \--* CNS_INT int 0 $40 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB10} succs={BB20,BB21} ***** BB19 STMT00017 (IL 0x0B5...0x0B7) N004 ( 7, 6) [000091] ------------ * JTRUE void N003 ( 5, 4) [000090] J------N---- \--* EQ int $284 N001 ( 3, 2) [000088] ------------ +--* LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000089] ------------ \--* CNS_INT ref null $VN.Null ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} ***** BB20 STMT00019 (IL 0x0B9...0x0CA) N005 ( 19, 10) [000101] -ACXG---R--- * ASG ref $376 N004 ( 3, 2) [000100] D------N---- +--* LCL_VAR ref V14 tmp3 d:2 $385 N003 ( 15, 7) [000099] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 N002 ( 1, 1) [000098] ------------ arg0 in rdi \--* CNS_INT long 2 $2c4 ***** BB20 STMT00020 (IL ???... ???) N015 ( 25, 24) [000107] -A-XG------- * ASG ref $VN.Void N013 ( 23, 22) [000384] -A-XG--N---- +--* COMMA ref $VN.Void N008 ( 17, 17) [000378] -A-X-------- | +--* ARR_BOUNDS_CHECK_Rng void $37c N001 ( 1, 1) [000104] ------------ | | +--* CNS_INT int 0 $40 N007 ( 12, 9) [000467] -A-X-------- | | \--* COMMA int $299 N005 ( 9, 7) [000465] -A-X----R--- | | +--* ASG int $VN.Void N004 ( 3, 2) [000464] D------N---- | | | +--* LCL_VAR int V28 cse0 d:1 $299 N003 ( 5, 4) [000377] ---X-------- | | | \--* ARR_LENGTH int $299 N002 ( 3, 2) [000103] ------------ | | | \--* LCL_VAR ref V14 tmp3 u:2 $385 N006 ( 3, 2) [000466] ------------ | | \--* LCL_VAR int V28 cse0 u:1 $299 N012 ( 6, 5) [000106] a---G--N---- | \--* IND ref $83 N011 ( 4, 3) [000383] -------N---- | \--* ADD byref $441 N009 ( 3, 2) [000375] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N010 ( 1, 1) [000382] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N014 ( 1, 1) [000105] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 ***** BB20 STMT00021 (IL ???...0x0CF) N010 ( 18, 18) [000112] -A-XG------- * ASG ref $VN.Void N008 ( 14, 15) [000394] ---XG--N---- +--* COMMA ref $VN.Void N003 ( 8, 10) [000388] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $645 N001 ( 1, 1) [000109] ------------ | | +--* CNS_INT int 1 $41 N002 ( 3, 2) [000468] ------------ | | \--* LCL_VAR int V28 cse0 u:1 $3c1 N007 ( 6, 5) [000111] a---G--N---- | \--* IND ref $370 N006 ( 4, 3) [000393] -------N---- | \--* ADD byref $442 N004 ( 3, 2) [000385] ------------ | +--* LCL_VAR ref V14 tmp3 u:2 $385 N005 ( 1, 1) [000392] ------------ | \--* CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 N009 ( 3, 2) [000110] ------------ \--* LCL_VAR ref V10 loc4 u:2 (last use) $370 ***** BB20 STMT00052 (IL ???... ???) N003 ( 18, 8) [000261] -AC-----R--- * ASG ref $647 N002 ( 3, 2) [000260] D------N---- +--* LCL_VAR ref V20 tmp9 d:2 $647 N001 ( 14, 5) [000259] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 ***** BB20 STMT00053 (IL ???... ???) N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N007 ( 21, 14) [000396] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000395] D------N---- | +--* LCL_VAR ref V27 tmp16 d:2 N005 ( 17, 11) [000255] --CXG------- | \--* IND ref N004 ( 15, 9) [000254] --CXG--N---- | \--* ADD byref $403 N002 ( 14, 5) [000252] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000253] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] $48 N010 ( 3, 2) [000397] ------------ arg1 in rsi +--* LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ this in rdi +--* LCL_VAR ref V20 tmp9 u:2 $647 N012 ( 3, 2) [000102] ------------ arg3 in rcx +--* LCL_VAR ref V14 tmp3 u:2 (last use) $385 N013 ( 1, 4) [000256] ------------ arg2 in rdx \--* CNS_INT int 0x7D2C $64 ***** BB20 STMT00054 (IL ???... ???) N003 ( 5, 4) [000269] IA------R--- * ASG struct (init) $VN.Void N002 ( 3, 2) [000267] D------N---- +--* LCL_VAR struct V15 tmp4 d:2 N001 ( 1, 1) [000268] ------------ \--* CNS_INT int 0 $40 ***** BB20 STMT00055 (IL ???... ???) N003 ( 5, 6) [000273] -A------R--- * ASG ref $82 N002 ( 3, 4) [000272] U------N---- +--* LCL_FLD ref V15 tmp4 ud:2->3[+0] Fseq[TypeParameter] $38c N001 ( 1, 1) [000096] ------------ \--* LCL_VAR ref V02 arg2 u:1 $82 ***** BB20 STMT00056 (IL ???... ???) N003 ( 7, 7) [000277] -A------R--- * ASG ref $647 N002 ( 3, 4) [000276] U------N---- +--* LCL_FLD ref V15 tmp4 ud:3->4[+8] Fseq[DiagnosticInfo] $38d N001 ( 3, 2) [000264] ------------ \--* LCL_VAR ref V20 tmp9 u:2 (last use) $647 ***** BB20 STMT00025 (IL 0x0DA... ???) N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000124] n----------- arg2 out+00 +--* OBJ struct $507 N004 ( 3, 3) [000123] ------------ | \--* ADDR byref $40b N003 ( 3, 2) [000121] -------N---- | \--* LCL_VAR struct V15 tmp4 u:4 (last use) $38d N006 ( 3, 2) [000095] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} ***** BB21 STMT00018 (IL 0x0DF...0x0E0) N003 ( 5, 4) [000094] -A------R--- * ASG int $40 N002 ( 3, 2) [000093] D------N---- +--* LCL_VAR int V07 loc1 d:12 $40 N001 ( 1, 1) [000092] ------------ \--* CNS_INT int 0 $40 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} ***** BB22 STMT00033 (IL 0x048...0x051) N011 ( 24, 18) [000162] --CXG------- * JTRUE void N010 ( 22, 16) [000161] J-CXG--N---- \--* NE int $289 N008 ( 20, 14) [000159] --CXG------- +--* CAST int <- bool <- int $288 N007 ( 19, 12) [000158] --CXG------- | \--* CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 N004 ( 1, 1) [000155] ------------ arg0 in rdi | +--* LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000156] ------------ arg1 in rsi | +--* LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000157] ------------ arg2 in rdx | \--* LCL_VAR ref V04 arg4 u:1 $84 N009 ( 1, 1) [000160] ------------ \--* CNS_INT int 0 $40 ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} ***** BB23 STMT00034 (IL 0x053...0x054) N003 ( 5, 4) [000165] -A------R--- * ASG int $40 N002 ( 3, 2) [000164] D------N---- +--* LCL_VAR int V07 loc1 d:5 $40 N001 ( 1, 1) [000163] ------------ \--* CNS_INT int 0 $40 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} ***** BB24 STMT00042 (IL 0x008...0x009) N003 ( 5, 4) [000197] -A------R--- * ASG int $41 N002 ( 3, 2) [000196] D------N---- +--* LCL_VAR int V06 loc0 d:2 $41 N001 ( 1, 1) [000195] ------------ \--* CNS_INT int 1 $41 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} ***** BB25 STMT00035 (IL 0x019...0x01B) N004 ( 7, 6) [000169] ------------ * JTRUE void N003 ( 5, 4) [000168] J------N---- \--* EQ int $284 N001 ( 3, 2) [000166] ------------ +--* LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000167] ------------ \--* CNS_INT ref null $VN.Null ------------ BB26 [01D..03E), preds={BB25} succs={BB27} ***** BB26 STMT00037 (IL 0x01D...0x02E) N005 ( 19, 10) [000179] -ACXG---R--- * ASG ref $342 N004 ( 3, 2) [000178] D------N---- +--* LCL_VAR ref V16 tmp5 d:2 $380 N003 ( 15, 7) [000177] --CXG------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 N002 ( 1, 1) [000176] ------------ arg0 in rdi \--* CNS_INT long 1 $2c0 ***** BB26 STMT00038 (IL ???... ???) N011 ( 18, 19) [000185] -A-XG------- * ASG ref $VN.Void N009 ( 16, 17) [000298] ---XG--N---- +--* COMMA ref $VN.Void N004 ( 10, 12) [000292] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void $348 N001 ( 1, 1) [000182] ------------ | | +--* CNS_INT int 0 $40 N003 ( 5, 4) [000291] ---X-------- | | \--* ARR_LENGTH int $285 N002 ( 3, 2) [000181] ------------ | | \--* LCL_VAR ref V16 tmp5 u:2 $380 N008 ( 6, 5) [000184] a---G--N---- | \--* IND ref $83 N007 ( 4, 3) [000297] -------N---- | \--* ADD byref $440 N005 ( 3, 2) [000289] ------------ | +--* LCL_VAR ref V16 tmp5 u:2 $380 N006 ( 1, 1) [000296] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $2c1 N010 ( 1, 1) [000183] ------------ \--* LCL_VAR ref V03 arg3 u:1 $83 ***** BB26 STMT00043 (IL ???... ???) N003 ( 18, 8) [000216] -AC-----R--- * ASG ref $34c N002 ( 3, 2) [000215] D------N---- +--* LCL_VAR ref V18 tmp7 d:2 $34c N001 ( 14, 5) [000214] --C--------- \--* CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c ***** BB26 STMT00044 (IL ???... ???) N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N007 ( 21, 14) [000300] -ACXG---R-L- arg1 SETUP +--* ASG ref N006 ( 3, 2) [000299] D------N---- | +--* LCL_VAR ref V24 tmp13 d:2 N005 ( 17, 11) [000210] --CXG------- | \--* IND ref N004 ( 15, 9) [000209] --CXG--N---- | \--* ADD byref $403 N002 ( 14, 5) [000207] H-CXG------- | +--* CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000208] ------------ | \--* CNS_INT int 0x418 Fseq[Instance] $48 N010 ( 3, 2) [000301] ------------ arg1 in rsi +--* LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ this in rdi +--* LCL_VAR ref V18 tmp7 u:2 $34c N012 ( 3, 2) [000180] ------------ arg3 in rcx +--* LCL_VAR ref V16 tmp5 u:2 (last use) $380 N013 ( 1, 4) [000211] ------------ arg2 in rdx \--* CNS_INT int 0x7AA4 $49 ***** BB26 STMT00040 (IL ???... ???) N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void N004 ( 3, 3) [000189] ------------ this in rdi +--* LCL_VAR_ADDR byref V17 tmp6 $481 N005 ( 1, 1) [000174] ------------ arg1 in rsi +--* LCL_VAR ref V02 arg2 u:1 $82 N006 ( 3, 2) [000219] ------------ arg2 in rdx \--* LCL_VAR ref V18 tmp7 u:2 (last use) $34c ***** BB26 STMT00041 (IL 0x039... ???) N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void N005 ( 9, 7) [000194] n---G------- arg2 out+00 +--* OBJ struct N004 ( 3, 3) [000193] ------------ | \--* ADDR byref $482 N003 ( 3, 2) [000191] ----G--N---- | \--* LCL_VAR struct(AX) V17 tmp6 $4c0 N006 ( 3, 2) [000173] ------------ this in rdi +--* LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ arg1 in r11 \--* CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} ***** BB27 STMT00036 (IL 0x03E...0x03F) N003 ( 5, 4) [000172] -A------R--- * ASG int $40 N002 ( 3, 2) [000171] D------N---- +--* LCL_VAR int V07 loc1 d:3 $40 N001 ( 1, 1) [000170] ------------ \--* CNS_INT int 0 $40 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} ***** BB28 STMT00029 (IL 0x080...0x081) N003 ( 5, 4) [000142] -A------R--- * ASG int $40 N002 ( 3, 2) [000141] D------N---- +--* LCL_VAR int V07 loc1 d:9 $40 N001 ( 1, 1) [000140] ------------ \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Rationalize IR rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000009] DA---------- * STORE_LCL_VAR int V07 loc1 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000447] DA---------- * STORE_LCL_VAR bool V07 loc1 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000444] DA---------- * STORE_LCL_VAR bool V07 loc1 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000441] DA---------- * STORE_LCL_VAR bool V07 loc1 d:8 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000438] DA---------- * STORE_LCL_VAR bool V07 loc1 d:10 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 20, 13) [000042] DACXG------- * STORE_LCL_VAR ref (AX) V23 tmp12 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N005 ( 3, 2) [000043] -------N---- t43 = LCL_VAR_ADDR byref V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 26, 26) [000050] DACXG------- * STORE_LCL_VAR struct(AX) V12 tmp1 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000341] -------N---- t341 = LCL_VAR_ADDR byref V12 tmp1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000343] DA---------- * STORE_LCL_VAR byref V25 tmp14 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 7, 5) [000347] DA-XG------- * STORE_LCL_VAR ref (AX) V21 tmp10 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N015 ( 8, 7) [000354] DA--GO------ * STORE_LCL_VAR int (AX) V22 tmp11 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N005 ( 3, 2) [000417] ----G--N---- t417 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000432] DA---------- * STORE_LCL_VAR bool V07 loc1 d:14 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000127] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000426] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000435] DA---------- * STORE_LCL_VAR bool V07 loc1 d:11 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N005 ( 3, 2) [000064] -------N---- t64 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 26, 26) [000360] DACXG-----L- * STORE_LCL_VAR ref V26 tmp15 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N017 ( 59, 54) [000073] DACXG------- * STORE_LCL_VAR struct V13 tmp2 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 7) [000078] DA---------- * STORE_LCL_VAR ref V10 loc4 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000242] DA---------- * STORE_LCL_VAR int V19 tmp8 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 24, 17) [000234] DACXG------- * STORE_LCL_VAR int V19 tmp8 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000429] DA---------- * STORE_LCL_VAR bool V07 loc1 d:13 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N005 ( 3, 2) [000055] -------N---- t55 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000154] DA---------- * STORE_LCL_VAR int V07 loc1 d:7 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 19, 10) [000101] DACXG------- * STORE_LCL_VAR ref V14 tmp3 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 9, 7) [000465] DA-X-------- * STORE_LCL_VAR int V28 cse0 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 18, 8) [000261] DAC--------- * STORE_LCL_VAR ref V20 tmp9 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 21, 14) [000396] DACXG-----L- * STORE_LCL_VAR ref V27 tmp16 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000269] DA---------- * STORE_LCL_VAR struct V15 tmp4 d:2 rewriting asg(LCL_FLD, X) to STORE_LCL_FLD(X) N003 ( 5, 6) [000273] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:2->0[+0] Fseq[TypeParameter] rewriting asg(LCL_FLD, X) to STORE_LCL_FLD(X) N003 ( 7, 7) [000277] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:3->0[+8] Fseq[DiagnosticInfo] Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N003 ( 3, 2) [000121] -------N---- t121 = LCL_VAR_ADDR byref V15 tmp4 u:4 (last use) rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000094] DA---------- * STORE_LCL_VAR int V07 loc1 d:12 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000165] DA---------- * STORE_LCL_VAR int V07 loc1 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000197] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 19, 10) [000179] DACXG------- * STORE_LCL_VAR ref V16 tmp5 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 18, 8) [000216] DAC--------- * STORE_LCL_VAR ref V18 tmp7 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 21, 14) [000300] DACXG-----L- * STORE_LCL_VAR ref V24 tmp13 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N003 ( 3, 2) [000191] -------N---- t191 = LCL_VAR_ADDR byref V17 tmp6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000172] DA---------- * STORE_LCL_VAR int V07 loc1 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000142] DA---------- * STORE_LCL_VAR int V07 loc1 d:9 *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC LIR BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC LIR BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC LIR BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC LIR BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC LIR BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC LIR BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC LIR BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC LIR BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC LIR BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB19 (always) i gcsafe bwd LIR BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC LIR BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC LIR BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC LIR BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC LIR BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe LIR BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC LIR BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC LIR BB19 [0017] 2 BB14,BB10 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC LIR BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC LIR BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC LIR BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC LIR BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC LIR BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC LIR BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC LIR BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC LIR BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC LIR BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} N003 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V03 arg3 u:1 $83 N004 ( 3, 10) [000279] ------------ t279 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t0 ref this in rdi +--* t279 long arg1 in r11 N005 ( 24, 21) [000198] --CXG------- t198 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 N006 ( 1, 1) [000199] ------------ t199 = CNS_INT int 4 $44 /--* t198 int +--* t199 int N007 ( 26, 23) [000200] J--XG--N---- t200 = * EQ int $280 /--* t200 int N008 ( 28, 25) [000006] ---XG------- * JTRUE void ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} [000472] ------------ IL_OFFSET void IL offset: 0xf N001 ( 1, 1) [000007] ------------ t7 = CNS_INT int 1 $41 /--* t7 int N003 ( 5, 4) [000009] DA---------- * STORE_LCL_VAR int V07 loc1 d:2 N004 ( 1, 1) [000010] ------------ t10 = LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ t284 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 /--* t10 ref this in rdi +--* t284 long arg1 in r11 N006 ( 24, 21) [000202] --CXG------- t202 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 /--* t202 int N007 ( 25, 23) [000203] ---XG------- t203 = * CAST int <- byte <- int $281 /--* t203 int arg0 in rdi N008 ( 39, 29) [000204] --CXG------- t204 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 /--* t204 int N009 ( 40, 31) [000205] ---XG------- t205 = * CAST int <- bool <- int $282 N010 ( 1, 1) [000014] ------------ t14 = CNS_INT int 0 $40 /--* t205 int +--* t14 int N011 ( 42, 33) [000015] J--XG--N---- t15 = * NE int $283 /--* t15 int N012 ( 44, 35) [000016] ---XG------- * JTRUE void ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} N001 ( 0, 0) [000450] ------------ t450 = PHI_ARG bool V07 loc1 u:3 $40 N002 ( 0, 0) [000449] ------------ t449 = PHI_ARG bool V07 loc1 u:2 $41 /--* t450 bool +--* t449 bool N003 ( 0, 0) [000446] ------------ t446 = * PHI bool /--* t446 bool N005 ( 0, 0) [000447] DA---------- * STORE_LCL_VAR bool V07 loc1 d:4 [000473] ------------ IL_OFFSET void IL offset: 0x40 N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000312] ------------ t312 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca /--* t17 ref this in rdi +--* t312 long arg1 in r11 N005 ( 24, 21) [000018] --CXG------- t18 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 /--* t18 int N006 ( 25, 23) [000019] ---XG------- t19 = * CAST int <- bool <- int $286 N007 ( 1, 1) [000020] ------------ t20 = CNS_INT int 0 $40 /--* t19 int +--* t20 int N008 ( 27, 25) [000021] J--XG--N---- t21 = * NE int $287 /--* t21 int N009 ( 29, 27) [000022] ---XG------- * JTRUE void ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} N001 ( 0, 0) [000452] ------------ t452 = PHI_ARG bool V07 loc1 u:5 $40 N002 ( 0, 0) [000451] ------------ t451 = PHI_ARG bool V07 loc1 u:4 $580 /--* t452 bool +--* t451 bool N003 ( 0, 0) [000443] ------------ t443 = * PHI bool /--* t443 bool N005 ( 0, 0) [000444] DA---------- * STORE_LCL_VAR bool V07 loc1 d:6 [000474] ------------ IL_OFFSET void IL offset: 0x55 N003 ( 1, 1) [000023] ------------ t23 = LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ t319 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc /--* t23 ref this in rdi +--* t319 long arg1 in r11 N005 ( 24, 21) [000024] --CXG------- t24 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b /--* t24 int N006 ( 25, 23) [000025] ---XG------- t25 = * CAST int <- bool <- int $28a N007 ( 1, 1) [000026] ------------ t26 = CNS_INT int 0 $40 /--* t25 int +--* t26 int N008 ( 27, 25) [000027] J--XG--N---- t27 = * NE int $28b /--* t27 int N009 ( 29, 27) [000028] ---XG------- * JTRUE void ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} N001 ( 0, 0) [000454] ------------ t454 = PHI_ARG bool V07 loc1 u:7 $40 N002 ( 0, 0) [000453] ------------ t453 = PHI_ARG bool V07 loc1 u:6 $581 /--* t454 bool +--* t453 bool N003 ( 0, 0) [000440] ------------ t440 = * PHI bool /--* t440 bool N005 ( 0, 0) [000441] DA---------- * STORE_LCL_VAR bool V07 loc1 d:8 [000475] ------------ IL_OFFSET void IL offset: 0x6a N003 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ t326 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce /--* t29 ref this in rdi +--* t326 long arg1 in r11 N005 ( 24, 21) [000030] --CXG------- t30 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e /--* t30 int N006 ( 25, 23) [000031] ---XG------- t31 = * CAST int <- bool <- int $28e N007 ( 1, 1) [000032] ------------ t32 = CNS_INT int 0 $40 /--* t31 int +--* t32 int N008 ( 27, 25) [000033] J--XG--N---- t33 = * NE int $28f /--* t33 int N009 ( 29, 27) [000034] ---XG------- * JTRUE void ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} N001 ( 0, 0) [000456] ------------ t456 = PHI_ARG bool V07 loc1 u:9 $40 N002 ( 0, 0) [000455] ------------ t455 = PHI_ARG bool V07 loc1 u:8 $582 /--* t456 bool +--* t455 bool N003 ( 0, 0) [000437] ------------ t437 = * PHI bool /--* t437 bool N005 ( 0, 0) [000438] DA---------- * STORE_LCL_VAR bool V07 loc1 d:10 N003 ( 1, 1) [000035] ------------ t35 = LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ t36 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t35 ref this in rdi +--* t36 byref arg1 in rsi N005 ( 16, 10) [000037] --CXG------- t37 = * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 /--* t37 ref N007 ( 20, 13) [000042] DA-XG------- * STORE_LCL_VAR ref (AX) V23 tmp12 [000476] ------------ IL_OFFSET void IL offset: 0x8b N003 ( 3, 10) [000046] ------------ t46 = CNS_INT(h) long 0xd1ffab1e class $1d0 /--* t46 long N004 ( 5, 12) [000047] n----------- t47 = * IND long N005 ( 3, 2) [000043] -------N---- t43 = LCL_VAR_ADDR byref V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 /--* t47 long arg1 in rsi +--* t43 byref this in rdi N007 ( 22, 23) [000045] --CXG------- t45 = * CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 /--* t45 struct N009 ( 26, 26) [000050] DA-XG------- * STORE_LCL_VAR struct(AX) V12 tmp1 N001 ( 3, 2) [000341] -------N---- t341 = LCL_VAR_ADDR byref V12 tmp1 /--* t341 byref N004 ( 3, 3) [000343] DA---------- * STORE_LCL_VAR byref V25 tmp14 d:2 N005 ( 1, 1) [000345] ------------ t345 = LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 /--* t345 byref N006 ( 3, 2) [000346] ---X-------- t346 = * IND ref /--* t346 ref N008 ( 7, 5) [000347] DA-XG------- * STORE_LCL_VAR ref (AX) V21 tmp10 N010 ( 1, 1) [000350] ------------ t350 = LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ t351 = CNS_INT long 8 Fseq[_index] $2c3 /--* t350 byref +--* t351 long N012 ( 2, 2) [000352] -------N---- t352 = * ADD byref $407 /--* t352 byref N013 ( 4, 4) [000353] n----O------ t353 = * IND int /--* t353 int N015 ( 8, 7) [000354] DA--GO------ * STORE_LCL_VAR int (AX) V22 tmp11 [000477] ------------ IL_OFFSET void IL offset: 0xe1 N003 ( 3, 10) [000415] ------------ t415 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t415 long N004 ( 5, 12) [000414] n----------- t414 = * IND long N005 ( 3, 2) [000417] ----G--N---- t417 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t414 long arg1 in rsi +--* t417 byref this in rdi N007 ( 22, 23) [000411] --CXG------- t411 = * CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $212 /--* t411 int N008 ( 23, 25) [000410] ---XG------- t410 = * CAST int <- bool <- int $294 N009 ( 1, 1) [000418] ------------ t418 = CNS_INT int 0 $40 /--* t410 int +--* t418 int N010 ( 25, 27) [000409] J--XG--N---- t409 = * NE int $295 /--* t409 int N011 ( 27, 29) [000419] ---XG------- * JTRUE void ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} N001 ( 0, 0) [000461] ------------ t461 = PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ t457 = PHI_ARG bool V07 loc1 u:10 $583 /--* t461 bool +--* t457 bool N003 ( 0, 0) [000431] ------------ t431 = * PHI bool /--* t431 bool N005 ( 0, 0) [000432] DA---------- * STORE_LCL_VAR bool V07 loc1 d:14 [000478] ------------ IL_OFFSET void IL offset: 0xea N001 ( 3, 2) [000125] ------------ t125 = LCL_VAR int V07 loc1 u:14 (last use) $584 /--* t125 int N003 ( 7, 5) [000127] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} N001 ( 0, 0) [000463] ------------ t463 = PHI_ARG bool V06 loc0 u:4 $584 N002 ( 0, 0) [000448] ------------ t448 = PHI_ARG bool V06 loc0 u:2 $41 /--* t463 bool +--* t448 bool N003 ( 0, 0) [000425] ------------ t425 = * PHI bool /--* t425 bool N005 ( 0, 0) [000426] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 [000479] ------------ IL_OFFSET void IL offset: 0xec N001 ( 3, 2) [000128] ------------ t128 = LCL_VAR int V06 loc0 u:3 (last use) $585 /--* t128 int N002 ( 4, 3) [000129] ------------ * RETURN int $214 ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} N001 ( 0, 0) [000460] ------------ t460 = PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ t458 = PHI_ARG bool V07 loc1 u:10 $583 /--* t460 bool +--* t458 bool N003 ( 0, 0) [000434] ------------ t434 = * PHI bool /--* t434 bool N005 ( 0, 0) [000435] DA---------- * STORE_LCL_VAR bool V07 loc1 d:11 [000480] ------------ IL_OFFSET void IL offset: 0x95 N003 ( 3, 10) [000067] ------------ t67 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t67 long N004 ( 5, 12) [000068] n----------- t68 = * IND long N005 ( 3, 2) [000064] -------N---- t64 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t68 long arg1 in rsi +--* t64 byref this in rdi N007 ( 22, 23) [000066] --CXG------- t66 = * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c /--* t66 ref N009 ( 26, 26) [000360] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp15 d:2 N012 ( 3, 2) [000361] ------------ t361 = LCL_VAR ref V26 tmp15 u:2 (last use) $16c N013 ( 3, 2) [000069] ------------ t69 = LCL_VAR ref V01 arg1 u:1 $81 N014 ( 3, 10) [000356] ------------ t356 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 /--* t361 ref this in rdi +--* t69 ref arg2 in rsi +--* t356 long arg1 in r11 N015 ( 55, 51) [000070] --CXG------- t70 = * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 /--* t70 struct N017 ( 59, 54) [000073] DA-XG------- * STORE_LCL_VAR struct V13 tmp2 d:2 N001 ( 3, 4) [000076] ------------ t76 = LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) $370 /--* t76 ref N003 ( 7, 7) [000078] DA---------- * STORE_LCL_VAR ref V10 loc4 d:2 [000481] ------------ IL_OFFSET void IL offset: 0xa9 N003 ( 3, 2) [000080] ------------ t80 = LCL_VAR ref V10 loc4 u:2 $370 N004 ( 3, 10) [000365] ------------ t365 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t80 ref this in rdi +--* t365 long arg1 in r11 N005 ( 26, 22) [000247] --CXG------- t247 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 N006 ( 1, 1) [000248] ------------ t248 = CNS_INT int 4 $44 /--* t247 int +--* t248 int N007 ( 28, 24) [000249] J--XG--N---- t249 = * NE int $296 /--* t249 int N008 ( 30, 26) [000228] ---XG------- * JTRUE void ------------ BB10 [0A9..0AA) -> BB19 (always), preds={BB09} succs={BB19} [000482] ------------ IL_OFFSET void IL offset: 0xa9 N003 ( 3, 2) [000237] ------------ t237 = LCL_VAR ref V10 loc4 u:2 $370 N004 ( 1, 1) [000238] ------------ t238 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t237 ref arg0 in rdi +--* t238 byref arg1 in rsi N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void [000483] ------------ IL_OFFSET void IL offset: 0xa9 N001 ( 1, 1) [000240] ------------ t240 = CNS_INT int 0 $40 /--* t240 int N003 ( 5, 4) [000242] DA---------- * STORE_LCL_VAR int V19 tmp8 d:3 ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} [000484] ------------ IL_OFFSET void IL offset: 0x72 N006 ( 3, 2) [000130] ------------ t130 = LCL_VAR ref V00 arg0 u:1 (last use) $80 N007 ( 1, 1) [000131] ------------ t131 = LCL_VAR ref V02 arg2 u:1 $82 N008 ( 1, 1) [000132] ------------ t132 = LCL_VAR ref V03 arg3 u:1 $83 N009 ( 3, 2) [000133] ------------ t133 = LCL_VAR ref V04 arg4 u:1 $84 N010 ( 1, 1) [000134] ------------ t134 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t130 ref arg0 in rdi +--* t131 ref arg1 in rsi +--* t132 ref arg2 in rdx +--* t133 ref arg3 in rcx +--* t134 byref arg4 in r8 N011 ( 23, 17) [000135] --CXG------- t135 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f /--* t135 int N012 ( 24, 19) [000136] ---XG------- t136 = * CAST int <- bool <- int $290 N013 ( 1, 1) [000137] ------------ t137 = CNS_INT int 0 $40 /--* t136 int +--* t137 int N014 ( 26, 21) [000138] J--XG--N---- t138 = * EQ int $291 /--* t138 int N015 ( 28, 23) [000139] ---XG------- * JTRUE void ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} [000485] ------------ IL_OFFSET void IL offset: 0xa9 N004 ( 1, 1) [000079] ------------ t79 = LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 2) [000229] ------------ t229 = LCL_VAR ref V10 loc4 u:2 $370 N006 ( 1, 1) [000081] ------------ t81 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t79 ref arg0 in rdi +--* t229 ref arg1 in rsi +--* t81 byref arg2 in rdx N007 ( 19, 12) [000230] --CXG------- t230 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 /--* t230 int N008 ( 20, 14) [000232] ---XG------- t232 = * CAST int <- bool <- int $297 /--* t232 int N010 ( 24, 17) [000234] DA-XG------- * STORE_LCL_VAR int V19 tmp8 d:2 N001 ( 3, 2) [000235] ------------ t235 = LCL_VAR int V19 tmp8 u:2 (last use) $297 N002 ( 1, 1) [000085] ------------ t85 = CNS_INT int 0 $40 /--* t235 int +--* t85 int N003 ( 5, 4) [000086] J------N---- t86 = * EQ int $298 /--* t86 int N004 ( 7, 6) [000087] ------------ * JTRUE void ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB14,BB21} succs={BB16,BB09} N001 ( 0, 0) [000462] ------------ t462 = PHI_ARG bool V07 loc1 u:11 $586 N002 ( 0, 0) [000459] ------------ t459 = PHI_ARG bool V07 loc1 u:12 $40 /--* t462 bool +--* t459 bool N003 ( 0, 0) [000428] ------------ t428 = * PHI bool /--* t428 bool N005 ( 0, 0) [000429] DA---------- * STORE_LCL_VAR bool V07 loc1 d:13 [000486] ------------ IL_OFFSET void IL offset: 0xe1 N003 ( 3, 10) [000058] ------------ t58 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t58 long N004 ( 5, 12) [000059] n----------- t59 = * IND long N005 ( 3, 2) [000055] -------N---- t55 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t59 long arg1 in rsi +--* t55 byref this in rdi N007 ( 22, 23) [000057] --CXG------- t57 = * CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $21b /--* t57 int N008 ( 23, 25) [000060] ---XG------- t60 = * CAST int <- bool <- int $29a N009 ( 1, 1) [000061] ------------ t61 = CNS_INT int 0 $40 /--* t60 int +--* t61 int N010 ( 25, 27) [000062] J--XG--N---- t62 = * NE int $29b /--* t62 int N011 ( 27, 29) [000063] ---XG------- * JTRUE void ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} N004 ( 1, 1) [000143] ------------ t143 = LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000144] ------------ t144 = LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000145] ------------ t145 = LCL_VAR ref V04 arg4 u:1 $84 /--* t143 ref arg0 in rdi +--* t144 ref arg1 in rsi +--* t145 ref arg2 in rdx N007 ( 19, 12) [000146] --CXG------- t146 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c /--* t146 int N008 ( 20, 14) [000148] ---XG------- t148 = * CAST int <- bool <- int $28c N009 ( 1, 1) [000149] ------------ t149 = CNS_INT int 0 $40 /--* t148 int +--* t149 int N010 ( 22, 16) [000150] J--XG--N---- t150 = * NE int $28d /--* t150 int N011 ( 24, 18) [000151] ---XG------- * JTRUE void ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} [000487] ------------ IL_OFFSET void IL offset: 0x68 N001 ( 1, 1) [000152] ------------ t152 = CNS_INT int 0 $40 /--* t152 int N003 ( 5, 4) [000154] DA---------- * STORE_LCL_VAR int V07 loc1 d:7 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB10} succs={BB20,BB21} [000488] ------------ IL_OFFSET void IL offset: 0xb5 N001 ( 3, 2) [000088] ------------ t88 = LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000089] ------------ t89 = CNS_INT ref null $VN.Null /--* t88 ref +--* t89 ref N003 ( 5, 4) [000090] J------N---- t90 = * EQ int $284 /--* t90 int N004 ( 7, 6) [000091] ------------ * JTRUE void ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} [000489] ------------ IL_OFFSET void IL offset: 0xb9 N002 ( 1, 1) [000098] ------------ t98 = CNS_INT long 2 $2c4 /--* t98 long arg0 in rdi N003 ( 15, 7) [000099] --CXG------- t99 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 /--* t99 ref N005 ( 19, 10) [000101] DA-XG------- * STORE_LCL_VAR ref V14 tmp3 d:2 N001 ( 1, 1) [000104] ------------ t104 = CNS_INT int 0 $40 N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V14 tmp3 u:2 $385 /--* t103 ref N003 ( 5, 4) [000377] ---X-------- t377 = * ARR_LENGTH int $299 /--* t377 int N005 ( 9, 7) [000465] DA-X-------- * STORE_LCL_VAR int V28 cse0 d:1 N006 ( 3, 2) [000466] ------------ t466 = LCL_VAR int V28 cse0 u:1 $299 /--* t104 int +--* t466 int N008 ( 17, 17) [000378] ---X-------- * ARR_BOUNDS_CHECK_Rng void $37c N009 ( 3, 2) [000375] ------------ t375 = LCL_VAR ref V14 tmp3 u:2 $385 N010 ( 1, 1) [000382] ------------ t382 = CNS_INT long 16 Fseq[#FirstElem] $2c1 /--* t375 ref +--* t382 long N011 ( 4, 3) [000383] -------N---- t383 = * ADD byref $441 N014 ( 1, 1) [000105] ------------ t105 = LCL_VAR ref V03 arg3 u:1 $83 /--* t383 byref +--* t105 ref [000490] -A-XG------- * STOREIND ref N001 ( 1, 1) [000109] ------------ t109 = CNS_INT int 1 $41 N002 ( 3, 2) [000468] ------------ t468 = LCL_VAR int V28 cse0 u:1 $3c1 /--* t109 int +--* t468 int N003 ( 8, 10) [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void $645 N004 ( 3, 2) [000385] ------------ t385 = LCL_VAR ref V14 tmp3 u:2 $385 N005 ( 1, 1) [000392] ------------ t392 = CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 /--* t385 ref +--* t392 long N006 ( 4, 3) [000393] -------N---- t393 = * ADD byref $442 N009 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V10 loc4 u:2 (last use) $370 /--* t393 byref +--* t110 ref [000491] -A-XG------- * STOREIND ref N001 ( 14, 5) [000259] --C--------- t259 = CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 /--* t259 ref N003 ( 18, 8) [000261] DA---------- * STORE_LCL_VAR ref V20 tmp9 d:2 N002 ( 14, 5) [000252] H-CXG------- t252 = CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000253] ------------ t253 = CNS_INT int 0x418 Fseq[Instance] $48 /--* t252 byref +--* t253 int N004 ( 15, 9) [000254] ---XG--N---- t254 = * ADD byref $403 /--* t254 byref N005 ( 17, 11) [000255] ---XG------- t255 = * IND ref /--* t255 ref N007 ( 21, 14) [000396] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp16 d:2 N010 ( 3, 2) [000397] ------------ t397 = LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ t262 = LCL_VAR ref V20 tmp9 u:2 $647 N012 ( 3, 2) [000102] ------------ t102 = LCL_VAR ref V14 tmp3 u:2 (last use) $385 N013 ( 1, 4) [000256] ------------ t256 = CNS_INT int 0x7D2C $64 /--* t397 ref arg1 in rsi +--* t262 ref this in rdi +--* t102 ref arg3 in rcx +--* t256 int arg2 in rdx N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N001 ( 1, 1) [000268] ------------ t268 = CNS_INT int 0 $40 /--* t268 int N003 ( 5, 4) [000269] DA---------- * STORE_LCL_VAR struct V15 tmp4 d:2 N001 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V02 arg2 u:1 $82 /--* t96 ref N003 ( 5, 6) [000273] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:2->0[+0] Fseq[TypeParameter] N001 ( 3, 2) [000264] ------------ t264 = LCL_VAR ref V20 tmp9 u:2 (last use) $647 /--* t264 ref N003 ( 7, 7) [000277] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:3->0[+8] Fseq[DiagnosticInfo] [000492] ------------ IL_OFFSET void IL offset: 0xda N003 ( 3, 2) [000121] -------N---- t121 = LCL_VAR_ADDR byref V15 tmp4 u:4 (last use) /--* t121 byref N005 ( 9, 7) [000124] n----------- t124 = * OBJ struct $507 N006 ( 3, 2) [000095] ------------ t95 = LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ t401 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t124 struct arg2 out+00 +--* t95 ref this in rdi +--* t401 long arg1 in r11 N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} [000493] ------------ IL_OFFSET void IL offset: 0xdf N001 ( 1, 1) [000092] ------------ t92 = CNS_INT int 0 $40 /--* t92 int N003 ( 5, 4) [000094] DA---------- * STORE_LCL_VAR int V07 loc1 d:12 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} [000494] ------------ IL_OFFSET void IL offset: 0x48 N004 ( 1, 1) [000155] ------------ t155 = LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000156] ------------ t156 = LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000157] ------------ t157 = LCL_VAR ref V04 arg4 u:1 $84 /--* t155 ref arg0 in rdi +--* t156 ref arg1 in rsi +--* t157 ref arg2 in rdx N007 ( 19, 12) [000158] --CXG------- t158 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 /--* t158 int N008 ( 20, 14) [000159] ---XG------- t159 = * CAST int <- bool <- int $288 N009 ( 1, 1) [000160] ------------ t160 = CNS_INT int 0 $40 /--* t159 int +--* t160 int N010 ( 22, 16) [000161] J--XG--N---- t161 = * NE int $289 /--* t161 int N011 ( 24, 18) [000162] ---XG------- * JTRUE void ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} [000495] ------------ IL_OFFSET void IL offset: 0x53 N001 ( 1, 1) [000163] ------------ t163 = CNS_INT int 0 $40 /--* t163 int N003 ( 5, 4) [000165] DA---------- * STORE_LCL_VAR int V07 loc1 d:5 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} [000496] ------------ IL_OFFSET void IL offset: 0x8 N001 ( 1, 1) [000195] ------------ t195 = CNS_INT int 1 $41 /--* t195 int N003 ( 5, 4) [000197] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} [000497] ------------ IL_OFFSET void IL offset: 0x19 N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000167] ------------ t167 = CNS_INT ref null $VN.Null /--* t166 ref +--* t167 ref N003 ( 5, 4) [000168] J------N---- t168 = * EQ int $284 /--* t168 int N004 ( 7, 6) [000169] ------------ * JTRUE void ------------ BB26 [01D..03E), preds={BB25} succs={BB27} [000498] ------------ IL_OFFSET void IL offset: 0x1d N002 ( 1, 1) [000176] ------------ t176 = CNS_INT long 1 $2c0 /--* t176 long arg0 in rdi N003 ( 15, 7) [000177] --CXG------- t177 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 /--* t177 ref N005 ( 19, 10) [000179] DA-XG------- * STORE_LCL_VAR ref V16 tmp5 d:2 N001 ( 1, 1) [000182] ------------ t182 = CNS_INT int 0 $40 N002 ( 3, 2) [000181] ------------ t181 = LCL_VAR ref V16 tmp5 u:2 $380 /--* t181 ref N003 ( 5, 4) [000291] ---X-------- t291 = * ARR_LENGTH int $285 /--* t182 int +--* t291 int N004 ( 10, 12) [000292] ---X-------- * ARR_BOUNDS_CHECK_Rng void $348 N005 ( 3, 2) [000289] ------------ t289 = LCL_VAR ref V16 tmp5 u:2 $380 N006 ( 1, 1) [000296] ------------ t296 = CNS_INT long 16 Fseq[#FirstElem] $2c1 /--* t289 ref +--* t296 long N007 ( 4, 3) [000297] -------N---- t297 = * ADD byref $440 N010 ( 1, 1) [000183] ------------ t183 = LCL_VAR ref V03 arg3 u:1 $83 /--* t297 byref +--* t183 ref [000499] -A-XG------- * STOREIND ref N001 ( 14, 5) [000214] --C--------- t214 = CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c /--* t214 ref N003 ( 18, 8) [000216] DA---------- * STORE_LCL_VAR ref V18 tmp7 d:2 N002 ( 14, 5) [000207] H-CXG------- t207 = CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000208] ------------ t208 = CNS_INT int 0x418 Fseq[Instance] $48 /--* t207 byref +--* t208 int N004 ( 15, 9) [000209] ---XG--N---- t209 = * ADD byref $403 /--* t209 byref N005 ( 17, 11) [000210] ---XG------- t210 = * IND ref /--* t210 ref N007 ( 21, 14) [000300] DA-XG-----L- * STORE_LCL_VAR ref V24 tmp13 d:2 N010 ( 3, 2) [000301] ------------ t301 = LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ t217 = LCL_VAR ref V18 tmp7 u:2 $34c N012 ( 3, 2) [000180] ------------ t180 = LCL_VAR ref V16 tmp5 u:2 (last use) $380 N013 ( 1, 4) [000211] ------------ t211 = CNS_INT int 0x7AA4 $49 /--* t301 ref arg1 in rsi +--* t217 ref this in rdi +--* t180 ref arg3 in rcx +--* t211 int arg2 in rdx N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N004 ( 3, 3) [000189] ------------ t189 = LCL_VAR_ADDR byref V17 tmp6 $481 N005 ( 1, 1) [000174] ------------ t174 = LCL_VAR ref V02 arg2 u:1 $82 N006 ( 3, 2) [000219] ------------ t219 = LCL_VAR ref V18 tmp7 u:2 (last use) $34c /--* t189 byref this in rdi +--* t174 ref arg1 in rsi +--* t219 ref arg2 in rdx N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void [000500] ------------ IL_OFFSET void IL offset: 0x39 N003 ( 3, 2) [000191] -------N---- t191 = LCL_VAR_ADDR byref V17 tmp6 /--* t191 byref N005 ( 9, 7) [000194] n---G------- t194 = * OBJ struct N006 ( 3, 2) [000173] ------------ t173 = LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ t308 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t194 struct arg2 out+00 +--* t173 ref this in rdi +--* t308 long arg1 in r11 N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} [000501] ------------ IL_OFFSET void IL offset: 0x3e N001 ( 1, 1) [000170] ------------ t170 = CNS_INT int 0 $40 /--* t170 int N003 ( 5, 4) [000172] DA---------- * STORE_LCL_VAR int V07 loc1 d:3 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} [000502] ------------ IL_OFFSET void IL offset: 0x80 N001 ( 1, 1) [000140] ------------ t140 = CNS_INT int 0 $40 /--* t140 int N003 ( 5, 4) [000142] DA---------- * STORE_LCL_VAR int V07 loc1 d:9 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Do 'simple' lowering outgoingArgSpaceSize 0 sufficient for call [000198], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000202], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000204], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000018], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000024], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000030], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000037], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000045], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000411], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000066], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000070], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000247], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000239], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000135], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000230], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000057], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000146], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000099], which needs 0 *** Computing fgRngChkTarget for block BB20 fgNewBBinRegion(jumpKind=3, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=true, insertAtEnd=true): inserting after BB28 New Basic Block BB29 [0038] created. fgAddCodeRef - Add BB in non-EH region for RNGCHK_FAIL, new block BB29 [0038] Initializing arg info for 505.CALL: ArgTable for 505.CALL after fgInitArgInfo: Morphing args for 505.CALL: argSlots=0, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 505.CALL after fgMorphArgs: *** Computing fgRngChkTarget for block BB20 outgoingArgSpaceSize 0 sufficient for call [000259], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000252], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000263], which needs 0 Bumping outgoingArgSpaceSize to 40 for call [000122] outgoingArgSpaceSize 40 sufficient for call [000158], which needs 0 outgoingArgSpaceSize 40 sufficient for call [000177], which needs 0 *** Computing fgRngChkTarget for block BB26 outgoingArgSpaceSize 40 sufficient for call [000214], which needs 0 outgoingArgSpaceSize 40 sufficient for call [000207], which needs 0 outgoingArgSpaceSize 40 sufficient for call [000218], which needs 0 outgoingArgSpaceSize 40 sufficient for call [000190], which needs 0 outgoingArgSpaceSize 40 sufficient for call [000192], which needs 40 outgoingArgSpaceSize 40 sufficient for call [000505], which needs 0 After fgSimpleLowering() added some RngChk throw blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC LIR BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC LIR BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC LIR BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC LIR BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC LIR BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC LIR BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC LIR BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC LIR BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC LIR BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB19 (always) i gcsafe bwd LIR BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC LIR BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC LIR BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC LIR BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC LIR BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe LIR BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC LIR BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC LIR BB19 [0017] 2 BB14,BB10 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC LIR BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC LIR BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC LIR BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC LIR BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC LIR BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC LIR BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC LIR BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC LIR BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC LIR BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC LIR BB29 [0038] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Do 'simple' lowering *************** In fgDebugCheckBBlist Trees before Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC LIR BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC LIR BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC LIR BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC LIR BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC LIR BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC LIR BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC LIR BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC LIR BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC LIR BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB19 (always) i gcsafe bwd LIR BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC LIR BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC LIR BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC LIR BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC LIR BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe LIR BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC LIR BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC LIR BB19 [0017] 2 BB14,BB10 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC LIR BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC LIR BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC LIR BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC LIR BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC LIR BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC LIR BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC LIR BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC LIR BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC LIR BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC LIR BB29 [0038] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} N003 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V03 arg3 u:1 $83 N004 ( 3, 10) [000279] ------------ t279 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t0 ref this in rdi +--* t279 long arg1 in r11 N005 ( 24, 21) [000198] --CXG------- t198 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 N006 ( 1, 1) [000199] ------------ t199 = CNS_INT int 4 $44 /--* t198 int +--* t199 int N007 ( 26, 23) [000200] J--XG--N---- t200 = * EQ int $280 /--* t200 int N008 ( 28, 25) [000006] ---XG------- * JTRUE void ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} [000472] ------------ IL_OFFSET void IL offset: 0xf N001 ( 1, 1) [000007] ------------ t7 = CNS_INT int 1 $41 /--* t7 int N003 ( 5, 4) [000009] DA---------- * STORE_LCL_VAR int V07 loc1 d:2 N004 ( 1, 1) [000010] ------------ t10 = LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ t284 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 /--* t10 ref this in rdi +--* t284 long arg1 in r11 N006 ( 24, 21) [000202] --CXG------- t202 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 /--* t202 int N007 ( 25, 23) [000203] ---XG------- t203 = * CAST int <- byte <- int $281 /--* t203 int arg0 in rdi N008 ( 39, 29) [000204] --CXG------- t204 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 /--* t204 int N009 ( 40, 31) [000205] ---XG------- t205 = * CAST int <- bool <- int $282 N010 ( 1, 1) [000014] ------------ t14 = CNS_INT int 0 $40 /--* t205 int +--* t14 int N011 ( 42, 33) [000015] J--XG--N---- t15 = * NE int $283 /--* t15 int N012 ( 44, 35) [000016] ---XG------- * JTRUE void ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} N001 ( 0, 0) [000450] ------------ t450 = PHI_ARG bool V07 loc1 u:3 $40 N002 ( 0, 0) [000449] ------------ t449 = PHI_ARG bool V07 loc1 u:2 $41 /--* t450 bool +--* t449 bool N003 ( 0, 0) [000446] ------------ t446 = * PHI bool /--* t446 bool N005 ( 0, 0) [000447] DA---------- * STORE_LCL_VAR bool V07 loc1 d:4 [000473] ------------ IL_OFFSET void IL offset: 0x40 N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000312] ------------ t312 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca /--* t17 ref this in rdi +--* t312 long arg1 in r11 N005 ( 24, 21) [000018] --CXG------- t18 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 /--* t18 int N006 ( 25, 23) [000019] ---XG------- t19 = * CAST int <- bool <- int $286 N007 ( 1, 1) [000020] ------------ t20 = CNS_INT int 0 $40 /--* t19 int +--* t20 int N008 ( 27, 25) [000021] J--XG--N---- t21 = * NE int $287 /--* t21 int N009 ( 29, 27) [000022] ---XG------- * JTRUE void ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} N001 ( 0, 0) [000452] ------------ t452 = PHI_ARG bool V07 loc1 u:5 $40 N002 ( 0, 0) [000451] ------------ t451 = PHI_ARG bool V07 loc1 u:4 $580 /--* t452 bool +--* t451 bool N003 ( 0, 0) [000443] ------------ t443 = * PHI bool /--* t443 bool N005 ( 0, 0) [000444] DA---------- * STORE_LCL_VAR bool V07 loc1 d:6 [000474] ------------ IL_OFFSET void IL offset: 0x55 N003 ( 1, 1) [000023] ------------ t23 = LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ t319 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc /--* t23 ref this in rdi +--* t319 long arg1 in r11 N005 ( 24, 21) [000024] --CXG------- t24 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b /--* t24 int N006 ( 25, 23) [000025] ---XG------- t25 = * CAST int <- bool <- int $28a N007 ( 1, 1) [000026] ------------ t26 = CNS_INT int 0 $40 /--* t25 int +--* t26 int N008 ( 27, 25) [000027] J--XG--N---- t27 = * NE int $28b /--* t27 int N009 ( 29, 27) [000028] ---XG------- * JTRUE void ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} N001 ( 0, 0) [000454] ------------ t454 = PHI_ARG bool V07 loc1 u:7 $40 N002 ( 0, 0) [000453] ------------ t453 = PHI_ARG bool V07 loc1 u:6 $581 /--* t454 bool +--* t453 bool N003 ( 0, 0) [000440] ------------ t440 = * PHI bool /--* t440 bool N005 ( 0, 0) [000441] DA---------- * STORE_LCL_VAR bool V07 loc1 d:8 [000475] ------------ IL_OFFSET void IL offset: 0x6a N003 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ t326 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce /--* t29 ref this in rdi +--* t326 long arg1 in r11 N005 ( 24, 21) [000030] --CXG------- t30 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e /--* t30 int N006 ( 25, 23) [000031] ---XG------- t31 = * CAST int <- bool <- int $28e N007 ( 1, 1) [000032] ------------ t32 = CNS_INT int 0 $40 /--* t31 int +--* t32 int N008 ( 27, 25) [000033] J--XG--N---- t33 = * NE int $28f /--* t33 int N009 ( 29, 27) [000034] ---XG------- * JTRUE void ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} N001 ( 0, 0) [000456] ------------ t456 = PHI_ARG bool V07 loc1 u:9 $40 N002 ( 0, 0) [000455] ------------ t455 = PHI_ARG bool V07 loc1 u:8 $582 /--* t456 bool +--* t455 bool N003 ( 0, 0) [000437] ------------ t437 = * PHI bool /--* t437 bool N005 ( 0, 0) [000438] DA---------- * STORE_LCL_VAR bool V07 loc1 d:10 N003 ( 1, 1) [000035] ------------ t35 = LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ t36 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t35 ref this in rdi +--* t36 byref arg1 in rsi N005 ( 16, 10) [000037] --CXG------- t37 = * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 /--* t37 ref N007 ( 20, 13) [000042] DA-XG------- * STORE_LCL_VAR ref (AX) V23 tmp12 [000476] ------------ IL_OFFSET void IL offset: 0x8b N003 ( 3, 10) [000046] ------------ t46 = CNS_INT(h) long 0xd1ffab1e class $1d0 /--* t46 long N004 ( 5, 12) [000047] n----------- t47 = * IND long N005 ( 3, 2) [000043] -------N---- t43 = LCL_VAR_ADDR byref V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 /--* t47 long arg1 in rsi +--* t43 byref this in rdi N007 ( 22, 23) [000045] --CXG------- t45 = * CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 /--* t45 struct N009 ( 26, 26) [000050] DA-XG------- * STORE_LCL_VAR struct(AX) V12 tmp1 N001 ( 3, 2) [000341] -------N---- t341 = LCL_VAR_ADDR byref V12 tmp1 /--* t341 byref N004 ( 3, 3) [000343] DA---------- * STORE_LCL_VAR byref V25 tmp14 d:2 N005 ( 1, 1) [000345] ------------ t345 = LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 /--* t345 byref N006 ( 3, 2) [000346] ---X-------- t346 = * IND ref /--* t346 ref N008 ( 7, 5) [000347] DA-XG------- * STORE_LCL_VAR ref (AX) V21 tmp10 N010 ( 1, 1) [000350] ------------ t350 = LCL_VAR byref V25 tmp14 u:2 (last use) $487 N011 ( 1, 1) [000351] ------------ t351 = CNS_INT long 8 Fseq[_index] $2c3 /--* t350 byref +--* t351 long N012 ( 2, 2) [000352] -------N---- t352 = * ADD byref $407 /--* t352 byref N013 ( 4, 4) [000353] n----O------ t353 = * IND int /--* t353 int N015 ( 8, 7) [000354] DA--GO------ * STORE_LCL_VAR int (AX) V22 tmp11 [000477] ------------ IL_OFFSET void IL offset: 0xe1 N003 ( 3, 10) [000415] ------------ t415 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t415 long N004 ( 5, 12) [000414] n----------- t414 = * IND long N005 ( 3, 2) [000417] ----G--N---- t417 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t414 long arg1 in rsi +--* t417 byref this in rdi N007 ( 22, 23) [000411] --CXG------- t411 = * CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $212 /--* t411 int N008 ( 23, 25) [000410] ---XG------- t410 = * CAST int <- bool <- int $294 N009 ( 1, 1) [000418] ------------ t418 = CNS_INT int 0 $40 /--* t410 int +--* t418 int N010 ( 25, 27) [000409] J--XG--N---- t409 = * NE int $295 /--* t409 int N011 ( 27, 29) [000419] ---XG------- * JTRUE void ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} N001 ( 0, 0) [000461] ------------ t461 = PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ t457 = PHI_ARG bool V07 loc1 u:10 $583 /--* t461 bool +--* t457 bool N003 ( 0, 0) [000431] ------------ t431 = * PHI bool /--* t431 bool N005 ( 0, 0) [000432] DA---------- * STORE_LCL_VAR bool V07 loc1 d:14 [000478] ------------ IL_OFFSET void IL offset: 0xea N001 ( 3, 2) [000125] ------------ t125 = LCL_VAR int V07 loc1 u:14 (last use) $584 /--* t125 int N003 ( 7, 5) [000127] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} N001 ( 0, 0) [000463] ------------ t463 = PHI_ARG bool V06 loc0 u:4 $584 N002 ( 0, 0) [000448] ------------ t448 = PHI_ARG bool V06 loc0 u:2 $41 /--* t463 bool +--* t448 bool N003 ( 0, 0) [000425] ------------ t425 = * PHI bool /--* t425 bool N005 ( 0, 0) [000426] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 [000479] ------------ IL_OFFSET void IL offset: 0xec N001 ( 3, 2) [000128] ------------ t128 = LCL_VAR int V06 loc0 u:3 (last use) $585 /--* t128 int N002 ( 4, 3) [000129] ------------ * RETURN int $214 ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} N001 ( 0, 0) [000460] ------------ t460 = PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ t458 = PHI_ARG bool V07 loc1 u:10 $583 /--* t460 bool +--* t458 bool N003 ( 0, 0) [000434] ------------ t434 = * PHI bool /--* t434 bool N005 ( 0, 0) [000435] DA---------- * STORE_LCL_VAR bool V07 loc1 d:11 [000480] ------------ IL_OFFSET void IL offset: 0x95 N003 ( 3, 10) [000067] ------------ t67 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t67 long N004 ( 5, 12) [000068] n----------- t68 = * IND long N005 ( 3, 2) [000064] -------N---- t64 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t68 long arg1 in rsi +--* t64 byref this in rdi N007 ( 22, 23) [000066] --CXG------- t66 = * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c /--* t66 ref N009 ( 26, 26) [000360] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp15 d:2 N012 ( 3, 2) [000361] ------------ t361 = LCL_VAR ref V26 tmp15 u:2 (last use) $16c N013 ( 3, 2) [000069] ------------ t69 = LCL_VAR ref V01 arg1 u:1 $81 N014 ( 3, 10) [000356] ------------ t356 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 /--* t361 ref this in rdi +--* t69 ref arg2 in rsi +--* t356 long arg1 in r11 N015 ( 55, 51) [000070] --CXG------- t70 = * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 /--* t70 struct N017 ( 59, 54) [000073] DA-XG------- * STORE_LCL_VAR struct V13 tmp2 d:2 N001 ( 3, 4) [000076] ------------ t76 = LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) $370 /--* t76 ref N003 ( 7, 7) [000078] DA---------- * STORE_LCL_VAR ref V10 loc4 d:2 [000481] ------------ IL_OFFSET void IL offset: 0xa9 N003 ( 3, 2) [000080] ------------ t80 = LCL_VAR ref V10 loc4 u:2 $370 N004 ( 3, 10) [000365] ------------ t365 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t80 ref this in rdi +--* t365 long arg1 in r11 N005 ( 26, 22) [000247] --CXG------- t247 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 N006 ( 1, 1) [000248] ------------ t248 = CNS_INT int 4 $44 /--* t247 int +--* t248 int N007 ( 28, 24) [000249] J--XG--N---- t249 = * NE int $296 /--* t249 int N008 ( 30, 26) [000228] ---XG------- * JTRUE void ------------ BB10 [0A9..0AA) -> BB19 (always), preds={BB09} succs={BB19} [000482] ------------ IL_OFFSET void IL offset: 0xa9 N003 ( 3, 2) [000237] ------------ t237 = LCL_VAR ref V10 loc4 u:2 $370 N004 ( 1, 1) [000238] ------------ t238 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t237 ref arg0 in rdi +--* t238 byref arg1 in rsi N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void [000483] ------------ IL_OFFSET void IL offset: 0xa9 N001 ( 1, 1) [000240] ------------ t240 = CNS_INT int 0 $40 /--* t240 int N003 ( 5, 4) [000242] DA---------- * STORE_LCL_VAR int V19 tmp8 d:3 ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} [000484] ------------ IL_OFFSET void IL offset: 0x72 N006 ( 3, 2) [000130] ------------ t130 = LCL_VAR ref V00 arg0 u:1 (last use) $80 N007 ( 1, 1) [000131] ------------ t131 = LCL_VAR ref V02 arg2 u:1 $82 N008 ( 1, 1) [000132] ------------ t132 = LCL_VAR ref V03 arg3 u:1 $83 N009 ( 3, 2) [000133] ------------ t133 = LCL_VAR ref V04 arg4 u:1 $84 N010 ( 1, 1) [000134] ------------ t134 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t130 ref arg0 in rdi +--* t131 ref arg1 in rsi +--* t132 ref arg2 in rdx +--* t133 ref arg3 in rcx +--* t134 byref arg4 in r8 N011 ( 23, 17) [000135] --CXG------- t135 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f /--* t135 int N012 ( 24, 19) [000136] ---XG------- t136 = * CAST int <- bool <- int $290 N013 ( 1, 1) [000137] ------------ t137 = CNS_INT int 0 $40 /--* t136 int +--* t137 int N014 ( 26, 21) [000138] J--XG--N---- t138 = * EQ int $291 /--* t138 int N015 ( 28, 23) [000139] ---XG------- * JTRUE void ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} [000485] ------------ IL_OFFSET void IL offset: 0xa9 N004 ( 1, 1) [000079] ------------ t79 = LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 2) [000229] ------------ t229 = LCL_VAR ref V10 loc4 u:2 $370 N006 ( 1, 1) [000081] ------------ t81 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t79 ref arg0 in rdi +--* t229 ref arg1 in rsi +--* t81 byref arg2 in rdx N007 ( 19, 12) [000230] --CXG------- t230 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 /--* t230 int N008 ( 20, 14) [000232] ---XG------- t232 = * CAST int <- bool <- int $297 /--* t232 int N010 ( 24, 17) [000234] DA-XG------- * STORE_LCL_VAR int V19 tmp8 d:2 N001 ( 3, 2) [000235] ------------ t235 = LCL_VAR int V19 tmp8 u:2 (last use) $297 N002 ( 1, 1) [000085] ------------ t85 = CNS_INT int 0 $40 /--* t235 int +--* t85 int N003 ( 5, 4) [000086] J------N---- t86 = * EQ int $298 /--* t86 int N004 ( 7, 6) [000087] ------------ * JTRUE void ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB14,BB21} succs={BB16,BB09} N001 ( 0, 0) [000462] ------------ t462 = PHI_ARG bool V07 loc1 u:11 $586 N002 ( 0, 0) [000459] ------------ t459 = PHI_ARG bool V07 loc1 u:12 $40 /--* t462 bool +--* t459 bool N003 ( 0, 0) [000428] ------------ t428 = * PHI bool /--* t428 bool N005 ( 0, 0) [000429] DA---------- * STORE_LCL_VAR bool V07 loc1 d:13 [000486] ------------ IL_OFFSET void IL offset: 0xe1 N003 ( 3, 10) [000058] ------------ t58 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t58 long N004 ( 5, 12) [000059] n----------- t59 = * IND long N005 ( 3, 2) [000055] -------N---- t55 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t59 long arg1 in rsi +--* t55 byref this in rdi N007 ( 22, 23) [000057] --CXG------- t57 = * CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $21b /--* t57 int N008 ( 23, 25) [000060] ---XG------- t60 = * CAST int <- bool <- int $29a N009 ( 1, 1) [000061] ------------ t61 = CNS_INT int 0 $40 /--* t60 int +--* t61 int N010 ( 25, 27) [000062] J--XG--N---- t62 = * NE int $29b /--* t62 int N011 ( 27, 29) [000063] ---XG------- * JTRUE void ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} N004 ( 1, 1) [000143] ------------ t143 = LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000144] ------------ t144 = LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000145] ------------ t145 = LCL_VAR ref V04 arg4 u:1 $84 /--* t143 ref arg0 in rdi +--* t144 ref arg1 in rsi +--* t145 ref arg2 in rdx N007 ( 19, 12) [000146] --CXG------- t146 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c /--* t146 int N008 ( 20, 14) [000148] ---XG------- t148 = * CAST int <- bool <- int $28c N009 ( 1, 1) [000149] ------------ t149 = CNS_INT int 0 $40 /--* t148 int +--* t149 int N010 ( 22, 16) [000150] J--XG--N---- t150 = * NE int $28d /--* t150 int N011 ( 24, 18) [000151] ---XG------- * JTRUE void ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} [000487] ------------ IL_OFFSET void IL offset: 0x68 N001 ( 1, 1) [000152] ------------ t152 = CNS_INT int 0 $40 /--* t152 int N003 ( 5, 4) [000154] DA---------- * STORE_LCL_VAR int V07 loc1 d:7 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB10} succs={BB20,BB21} [000488] ------------ IL_OFFSET void IL offset: 0xb5 N001 ( 3, 2) [000088] ------------ t88 = LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000089] ------------ t89 = CNS_INT ref null $VN.Null /--* t88 ref +--* t89 ref N003 ( 5, 4) [000090] J------N---- t90 = * EQ int $284 /--* t90 int N004 ( 7, 6) [000091] ------------ * JTRUE void ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} [000489] ------------ IL_OFFSET void IL offset: 0xb9 N002 ( 1, 1) [000098] ------------ t98 = CNS_INT long 2 $2c4 /--* t98 long arg0 in rdi N003 ( 15, 7) [000099] --CXG------- t99 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 /--* t99 ref N005 ( 19, 10) [000101] DA-XG------- * STORE_LCL_VAR ref V14 tmp3 d:2 N001 ( 1, 1) [000104] ------------ t104 = CNS_INT int 0 $40 N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V14 tmp3 u:2 $385 [000503] ------------ t503 = CNS_INT long 8 /--* t103 ref +--* t503 long [000504] ------------ t504 = * ADD ref /--* t504 ref N003 ( 5, 4) [000377] ---X-------- t377 = * IND int $299 /--* t377 int N005 ( 9, 7) [000465] DA-X-------- * STORE_LCL_VAR int V28 cse0 d:1 N006 ( 3, 2) [000466] ------------ t466 = LCL_VAR int V28 cse0 u:1 $299 /--* t104 int +--* t466 int N008 ( 17, 17) [000378] ---X-------- * ARR_BOUNDS_CHECK_Rng void $37c N009 ( 3, 2) [000375] ------------ t375 = LCL_VAR ref V14 tmp3 u:2 $385 N010 ( 1, 1) [000382] ------------ t382 = CNS_INT long 16 Fseq[#FirstElem] $2c1 /--* t375 ref +--* t382 long N011 ( 4, 3) [000383] -------N---- t383 = * ADD byref $441 N014 ( 1, 1) [000105] ------------ t105 = LCL_VAR ref V03 arg3 u:1 $83 /--* t383 byref +--* t105 ref [000490] -A-XG------- * STOREIND ref N001 ( 1, 1) [000109] ------------ t109 = CNS_INT int 1 $41 N002 ( 3, 2) [000468] ------------ t468 = LCL_VAR int V28 cse0 u:1 $3c1 /--* t109 int +--* t468 int N003 ( 8, 10) [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void $645 N004 ( 3, 2) [000385] ------------ t385 = LCL_VAR ref V14 tmp3 u:2 $385 N005 ( 1, 1) [000392] ------------ t392 = CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 /--* t385 ref +--* t392 long N006 ( 4, 3) [000393] -------N---- t393 = * ADD byref $442 N009 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V10 loc4 u:2 (last use) $370 /--* t393 byref +--* t110 ref [000491] -A-XG------- * STOREIND ref N001 ( 14, 5) [000259] --C--------- t259 = CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 /--* t259 ref N003 ( 18, 8) [000261] DA---------- * STORE_LCL_VAR ref V20 tmp9 d:2 N002 ( 14, 5) [000252] H-CXG------- t252 = CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000253] ------------ t253 = CNS_INT int 0x418 Fseq[Instance] $48 /--* t252 byref +--* t253 int N004 ( 15, 9) [000254] ---XG--N---- t254 = * ADD byref $403 /--* t254 byref N005 ( 17, 11) [000255] ---XG------- t255 = * IND ref /--* t255 ref N007 ( 21, 14) [000396] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp16 d:2 N010 ( 3, 2) [000397] ------------ t397 = LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ t262 = LCL_VAR ref V20 tmp9 u:2 $647 N012 ( 3, 2) [000102] ------------ t102 = LCL_VAR ref V14 tmp3 u:2 (last use) $385 N013 ( 1, 4) [000256] ------------ t256 = CNS_INT int 0x7D2C $64 /--* t397 ref arg1 in rsi +--* t262 ref this in rdi +--* t102 ref arg3 in rcx +--* t256 int arg2 in rdx N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N001 ( 1, 1) [000268] ------------ t268 = CNS_INT int 0 $40 /--* t268 int N003 ( 5, 4) [000269] DA---------- * STORE_LCL_VAR struct V15 tmp4 d:2 N001 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V02 arg2 u:1 $82 /--* t96 ref N003 ( 5, 6) [000273] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:2->0[+0] Fseq[TypeParameter] N001 ( 3, 2) [000264] ------------ t264 = LCL_VAR ref V20 tmp9 u:2 (last use) $647 /--* t264 ref N003 ( 7, 7) [000277] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:3->0[+8] Fseq[DiagnosticInfo] [000492] ------------ IL_OFFSET void IL offset: 0xda N003 ( 3, 2) [000121] -------N---- t121 = LCL_VAR_ADDR byref V15 tmp4 u:4 (last use) /--* t121 byref N005 ( 9, 7) [000124] n----------- t124 = * OBJ struct $507 N006 ( 3, 2) [000095] ------------ t95 = LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ t401 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t124 struct arg2 out+00 +--* t95 ref this in rdi +--* t401 long arg1 in r11 N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} [000493] ------------ IL_OFFSET void IL offset: 0xdf N001 ( 1, 1) [000092] ------------ t92 = CNS_INT int 0 $40 /--* t92 int N003 ( 5, 4) [000094] DA---------- * STORE_LCL_VAR int V07 loc1 d:12 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} [000494] ------------ IL_OFFSET void IL offset: 0x48 N004 ( 1, 1) [000155] ------------ t155 = LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000156] ------------ t156 = LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000157] ------------ t157 = LCL_VAR ref V04 arg4 u:1 $84 /--* t155 ref arg0 in rdi +--* t156 ref arg1 in rsi +--* t157 ref arg2 in rdx N007 ( 19, 12) [000158] --CXG------- t158 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 /--* t158 int N008 ( 20, 14) [000159] ---XG------- t159 = * CAST int <- bool <- int $288 N009 ( 1, 1) [000160] ------------ t160 = CNS_INT int 0 $40 /--* t159 int +--* t160 int N010 ( 22, 16) [000161] J--XG--N---- t161 = * NE int $289 /--* t161 int N011 ( 24, 18) [000162] ---XG------- * JTRUE void ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} [000495] ------------ IL_OFFSET void IL offset: 0x53 N001 ( 1, 1) [000163] ------------ t163 = CNS_INT int 0 $40 /--* t163 int N003 ( 5, 4) [000165] DA---------- * STORE_LCL_VAR int V07 loc1 d:5 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} [000496] ------------ IL_OFFSET void IL offset: 0x8 N001 ( 1, 1) [000195] ------------ t195 = CNS_INT int 1 $41 /--* t195 int N003 ( 5, 4) [000197] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} [000497] ------------ IL_OFFSET void IL offset: 0x19 N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000167] ------------ t167 = CNS_INT ref null $VN.Null /--* t166 ref +--* t167 ref N003 ( 5, 4) [000168] J------N---- t168 = * EQ int $284 /--* t168 int N004 ( 7, 6) [000169] ------------ * JTRUE void ------------ BB26 [01D..03E), preds={BB25} succs={BB27} [000498] ------------ IL_OFFSET void IL offset: 0x1d N002 ( 1, 1) [000176] ------------ t176 = CNS_INT long 1 $2c0 /--* t176 long arg0 in rdi N003 ( 15, 7) [000177] --CXG------- t177 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 /--* t177 ref N005 ( 19, 10) [000179] DA-XG------- * STORE_LCL_VAR ref V16 tmp5 d:2 N001 ( 1, 1) [000182] ------------ t182 = CNS_INT int 0 $40 N002 ( 3, 2) [000181] ------------ t181 = LCL_VAR ref V16 tmp5 u:2 $380 [000506] ------------ t506 = CNS_INT long 8 /--* t181 ref +--* t506 long [000507] ------------ t507 = * ADD ref /--* t507 ref N003 ( 5, 4) [000291] ---X-------- t291 = * IND int $285 /--* t182 int +--* t291 int N004 ( 10, 12) [000292] ---X-------- * ARR_BOUNDS_CHECK_Rng void $348 N005 ( 3, 2) [000289] ------------ t289 = LCL_VAR ref V16 tmp5 u:2 $380 N006 ( 1, 1) [000296] ------------ t296 = CNS_INT long 16 Fseq[#FirstElem] $2c1 /--* t289 ref +--* t296 long N007 ( 4, 3) [000297] -------N---- t297 = * ADD byref $440 N010 ( 1, 1) [000183] ------------ t183 = LCL_VAR ref V03 arg3 u:1 $83 /--* t297 byref +--* t183 ref [000499] -A-XG------- * STOREIND ref N001 ( 14, 5) [000214] --C--------- t214 = CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c /--* t214 ref N003 ( 18, 8) [000216] DA---------- * STORE_LCL_VAR ref V18 tmp7 d:2 N002 ( 14, 5) [000207] H-CXG------- t207 = CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 N003 ( 1, 4) [000208] ------------ t208 = CNS_INT int 0x418 Fseq[Instance] $48 /--* t207 byref +--* t208 int N004 ( 15, 9) [000209] ---XG--N---- t209 = * ADD byref $403 /--* t209 byref N005 ( 17, 11) [000210] ---XG------- t210 = * IND ref /--* t210 ref N007 ( 21, 14) [000300] DA-XG-----L- * STORE_LCL_VAR ref V24 tmp13 d:2 N010 ( 3, 2) [000301] ------------ t301 = LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ t217 = LCL_VAR ref V18 tmp7 u:2 $34c N012 ( 3, 2) [000180] ------------ t180 = LCL_VAR ref V16 tmp5 u:2 (last use) $380 N013 ( 1, 4) [000211] ------------ t211 = CNS_INT int 0x7AA4 $49 /--* t301 ref arg1 in rsi +--* t217 ref this in rdi +--* t180 ref arg3 in rcx +--* t211 int arg2 in rdx N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N004 ( 3, 3) [000189] ------------ t189 = LCL_VAR_ADDR byref V17 tmp6 $481 N005 ( 1, 1) [000174] ------------ t174 = LCL_VAR ref V02 arg2 u:1 $82 N006 ( 3, 2) [000219] ------------ t219 = LCL_VAR ref V18 tmp7 u:2 (last use) $34c /--* t189 byref this in rdi +--* t174 ref arg1 in rsi +--* t219 ref arg2 in rdx N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void [000500] ------------ IL_OFFSET void IL offset: 0x39 N003 ( 3, 2) [000191] -------N---- t191 = LCL_VAR_ADDR byref V17 tmp6 /--* t191 byref N005 ( 9, 7) [000194] n---G------- t194 = * OBJ struct N006 ( 3, 2) [000173] ------------ t173 = LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ t308 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t194 struct arg2 out+00 +--* t173 ref this in rdi +--* t308 long arg1 in r11 N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} [000501] ------------ IL_OFFSET void IL offset: 0x3e N001 ( 1, 1) [000170] ------------ t170 = CNS_INT int 0 $40 /--* t170 int N003 ( 5, 4) [000172] DA---------- * STORE_LCL_VAR int V07 loc1 d:3 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} [000502] ------------ IL_OFFSET void IL offset: 0x80 N001 ( 1, 1) [000140] ------------ t140 = CNS_INT int 0 $40 /--* t140 int N003 ( 5, 4) [000142] DA---------- * STORE_LCL_VAR int V07 loc1 d:9 ------------ BB29 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [000505] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Lowering nodeinfo lowering call (before): N003 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V03 arg3 u:1 $83 N004 ( 3, 10) [000279] ------------ t279 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t0 ref this in rdi +--* t279 long arg1 in r11 N005 ( 24, 21) [000198] --CXG------- t198 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 objp: ====== lowering arg : N001 ( 0, 0) [000280] ----------L- * ARGPLACE ref $140 args: ====== lowering arg : N002 ( 0, 0) [000281] ----------L- * ARGPLACE long $83 late: ====== lowering arg : N003 ( 1, 1) [000000] ------------ * LCL_VAR ref V03 arg3 u:1 $83 new node is : [000508] ------------ * PUTARG_REG ref REG rdi lowering arg : N004 ( 3, 10) [000279] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 new node is : [000509] ------------ * PUTARG_REG long REG r11 results of lowering call: N001 ( 3, 10) [000510] ------------ t510 = CNS_INT(h) long 0xd1ffab1e ftn /--* t510 long N002 ( 5, 12) [000511] ------------ t511 = * IND long lowering call (after): N003 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V03 arg3 u:1 $83 /--* t0 ref [000508] ------------ t508 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000279] ------------ t279 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t279 long [000509] ------------ t509 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000510] ------------ t510 = CNS_INT(h) long 0xd1ffab1e ftn /--* t510 long N002 ( 5, 12) [000511] -c---------- t511 = * IND long REG NA /--* t508 ref this in rdi +--* t509 long arg1 in r11 +--* t511 long control expr N005 ( 24, 21) [000198] --CXG------- t198 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 lowering call (before): N004 ( 1, 1) [000010] ------------ t10 = LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 10) [000284] ------------ t284 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 /--* t10 ref this in rdi +--* t284 long arg1 in r11 N006 ( 24, 21) [000202] --CXG------- t202 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 objp: ====== lowering arg : N002 ( 0, 0) [000285] ----------L- * ARGPLACE ref $142 args: ====== lowering arg : N003 ( 0, 0) [000286] ----------L- * ARGPLACE long $83 late: ====== lowering arg : N004 ( 1, 1) [000010] ------------ * LCL_VAR ref V03 arg3 u:1 $83 new node is : [000512] ------------ * PUTARG_REG ref REG rdi lowering arg : N005 ( 3, 10) [000284] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 new node is : [000513] ------------ * PUTARG_REG long REG r11 results of lowering call: N001 ( 3, 10) [000514] ------------ t514 = CNS_INT(h) long 0xd1ffab1e ftn /--* t514 long N002 ( 5, 12) [000515] ------------ t515 = * IND long lowering call (after): N004 ( 1, 1) [000010] ------------ t10 = LCL_VAR ref V03 arg3 u:1 $83 /--* t10 ref [000512] ------------ t512 = * PUTARG_REG ref REG rdi N005 ( 3, 10) [000284] ------------ t284 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 /--* t284 long [000513] ------------ t513 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000514] ------------ t514 = CNS_INT(h) long 0xd1ffab1e ftn /--* t514 long N002 ( 5, 12) [000515] -c---------- t515 = * IND long REG NA /--* t512 ref this in rdi +--* t513 long arg1 in r11 +--* t515 long control expr N006 ( 24, 21) [000202] --CXG------- t202 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 lowering call (before): N004 ( 1, 1) [000010] ------------ t10 = LCL_VAR ref V03 arg3 u:1 $83 /--* t10 ref [000512] ------------ t512 = * PUTARG_REG ref REG rdi N005 ( 3, 10) [000284] ------------ t284 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 /--* t284 long [000513] ------------ t513 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000514] ------------ t514 = CNS_INT(h) long 0xd1ffab1e ftn /--* t514 long N002 ( 5, 12) [000515] -c---------- t515 = * IND long REG NA /--* t512 ref this in rdi +--* t513 long arg1 in r11 +--* t515 long control expr N006 ( 24, 21) [000202] --CXG------- t202 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 /--* t202 int N007 ( 25, 23) [000203] ---XG------- t203 = * CAST int <- byte <- int $281 /--* t203 int arg0 in rdi N008 ( 39, 29) [000204] --CXG------- t204 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000287] ----------L- * ARGPLACE int $281 late: ====== lowering arg : N007 ( 25, 23) [000203] ---XG------- * CAST int <- byte <- int $281 new node is : [000516] ---XG------- * PUTARG_REG int REG rdi results of lowering call: N001 ( 3, 10) [000517] ------------ t517 = CNS_INT(h) long 0xd1ffab1e ftn /--* t517 long N002 ( 5, 12) [000518] ------------ t518 = * IND long lowering call (after): N004 ( 1, 1) [000010] ------------ t10 = LCL_VAR ref V03 arg3 u:1 $83 /--* t10 ref [000512] ------------ t512 = * PUTARG_REG ref REG rdi N005 ( 3, 10) [000284] ------------ t284 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 /--* t284 long [000513] ------------ t513 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000514] ------------ t514 = CNS_INT(h) long 0xd1ffab1e ftn /--* t514 long N002 ( 5, 12) [000515] -c---------- t515 = * IND long REG NA /--* t512 ref this in rdi +--* t513 long arg1 in r11 +--* t515 long control expr N006 ( 24, 21) [000202] --CXG------- t202 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 /--* t202 int N007 ( 25, 23) [000203] ---XG------- t203 = * CAST int <- byte <- int $281 /--* t203 int [000516] ---XG------- t516 = * PUTARG_REG int REG rdi N001 ( 3, 10) [000517] ------------ t517 = CNS_INT(h) long 0xd1ffab1e ftn /--* t517 long N002 ( 5, 12) [000518] -c---------- t518 = * IND long REG NA /--* t516 int arg0 in rdi +--* t518 long control expr N008 ( 39, 29) [000204] --CXG------- t204 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 lowering call (before): N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000312] ------------ t312 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca /--* t17 ref this in rdi +--* t312 long arg1 in r11 N005 ( 24, 21) [000018] --CXG------- t18 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 objp: ====== lowering arg : N001 ( 0, 0) [000313] ----------L- * ARGPLACE ref $153 args: ====== lowering arg : N002 ( 0, 0) [000314] ----------L- * ARGPLACE long $82 late: ====== lowering arg : N003 ( 1, 1) [000017] ------------ * LCL_VAR ref V02 arg2 u:1 $82 new node is : [000519] ------------ * PUTARG_REG ref REG rdi lowering arg : N004 ( 3, 10) [000312] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca new node is : [000520] ------------ * PUTARG_REG long REG r11 results of lowering call: N001 ( 3, 10) [000521] ------------ t521 = CNS_INT(h) long 0xd1ffab1e ftn /--* t521 long N002 ( 5, 12) [000522] ------------ t522 = * IND long lowering call (after): N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR ref V02 arg2 u:1 $82 /--* t17 ref [000519] ------------ t519 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000312] ------------ t312 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca /--* t312 long [000520] ------------ t520 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000521] ------------ t521 = CNS_INT(h) long 0xd1ffab1e ftn /--* t521 long N002 ( 5, 12) [000522] -c---------- t522 = * IND long REG NA /--* t519 ref this in rdi +--* t520 long arg1 in r11 +--* t522 long control expr N005 ( 24, 21) [000018] --CXG------- t18 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 lowering call (before): N003 ( 1, 1) [000023] ------------ t23 = LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000319] ------------ t319 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc /--* t23 ref this in rdi +--* t319 long arg1 in r11 N005 ( 24, 21) [000024] --CXG------- t24 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b objp: ====== lowering arg : N001 ( 0, 0) [000320] ----------L- * ARGPLACE ref $159 args: ====== lowering arg : N002 ( 0, 0) [000321] ----------L- * ARGPLACE long $82 late: ====== lowering arg : N003 ( 1, 1) [000023] ------------ * LCL_VAR ref V02 arg2 u:1 $82 new node is : [000523] ------------ * PUTARG_REG ref REG rdi lowering arg : N004 ( 3, 10) [000319] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc new node is : [000524] ------------ * PUTARG_REG long REG r11 results of lowering call: N001 ( 3, 10) [000525] ------------ t525 = CNS_INT(h) long 0xd1ffab1e ftn /--* t525 long N002 ( 5, 12) [000526] ------------ t526 = * IND long lowering call (after): N003 ( 1, 1) [000023] ------------ t23 = LCL_VAR ref V02 arg2 u:1 $82 /--* t23 ref [000523] ------------ t523 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000319] ------------ t319 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc /--* t319 long [000524] ------------ t524 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000525] ------------ t525 = CNS_INT(h) long 0xd1ffab1e ftn /--* t525 long N002 ( 5, 12) [000526] -c---------- t526 = * IND long REG NA /--* t523 ref this in rdi +--* t524 long arg1 in r11 +--* t526 long control expr N005 ( 24, 21) [000024] --CXG------- t24 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b lowering call (before): N003 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V02 arg2 u:1 $82 N004 ( 3, 10) [000326] ------------ t326 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce /--* t29 ref this in rdi +--* t326 long arg1 in r11 N005 ( 24, 21) [000030] --CXG------- t30 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e objp: ====== lowering arg : N001 ( 0, 0) [000327] ----------L- * ARGPLACE ref $15f args: ====== lowering arg : N002 ( 0, 0) [000328] ----------L- * ARGPLACE long $82 late: ====== lowering arg : N003 ( 1, 1) [000029] ------------ * LCL_VAR ref V02 arg2 u:1 $82 new node is : [000527] ------------ * PUTARG_REG ref REG rdi lowering arg : N004 ( 3, 10) [000326] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce new node is : [000528] ------------ * PUTARG_REG long REG r11 results of lowering call: N001 ( 3, 10) [000529] ------------ t529 = CNS_INT(h) long 0xd1ffab1e ftn /--* t529 long N002 ( 5, 12) [000530] ------------ t530 = * IND long lowering call (after): N003 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V02 arg2 u:1 $82 /--* t29 ref [000527] ------------ t527 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000326] ------------ t326 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce /--* t326 long [000528] ------------ t528 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000529] ------------ t529 = CNS_INT(h) long 0xd1ffab1e ftn /--* t529 long N002 ( 5, 12) [000530] -c---------- t530 = * IND long REG NA /--* t527 ref this in rdi +--* t528 long arg1 in r11 +--* t530 long control expr N005 ( 24, 21) [000030] --CXG------- t30 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e lowering call (before): N003 ( 1, 1) [000035] ------------ t35 = LCL_VAR ref V02 arg2 u:1 $82 N004 ( 1, 1) [000036] ------------ t36 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t35 ref this in rdi +--* t36 byref arg1 in rsi N005 ( 16, 10) [000037] --CXG------- t37 = * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 objp: ====== lowering arg : N001 ( 0, 0) [000335] ----------L- * ARGPLACE ref $166 args: ====== lowering arg : N002 ( 0, 0) [000336] ----------L- * ARGPLACE byref $82 late: ====== lowering arg : N003 ( 1, 1) [000035] ------------ * LCL_VAR ref V02 arg2 u:1 $82 new node is : [000531] ------------ * PUTARG_REG ref REG rdi lowering arg : N004 ( 1, 1) [000036] ------------ * LCL_VAR byref V05 arg5 u:1 $c0 new node is : [000532] ------------ * PUTARG_REG byref REG rsi results of lowering call: N001 ( 3, 10) [000533] ------------ t533 = CNS_INT(h) long 0xd1ffab1e ftn /--* t533 long N002 ( 5, 12) [000534] ------------ t534 = * IND long lowering call (after): N003 ( 1, 1) [000035] ------------ t35 = LCL_VAR ref V02 arg2 u:1 $82 /--* t35 ref [000531] ------------ t531 = * PUTARG_REG ref REG rdi N004 ( 1, 1) [000036] ------------ t36 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t36 byref [000532] ------------ t532 = * PUTARG_REG byref REG rsi N001 ( 3, 10) [000533] ------------ t533 = CNS_INT(h) long 0xd1ffab1e ftn /--* t533 long N002 ( 5, 12) [000534] -c---------- t534 = * IND long REG NA /--* t531 ref this in rdi +--* t532 byref arg1 in rsi +--* t534 long control expr N005 ( 16, 10) [000037] --CXG------- t37 = * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 lowering call (before): N003 ( 3, 10) [000046] ------------ t46 = CNS_INT(h) long 0xd1ffab1e class $1d0 /--* t46 long N004 ( 5, 12) [000047] n----------- t47 = * IND long N005 ( 3, 2) [000043] -------N---- t43 = LCL_VAR_ADDR byref V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 /--* t47 long arg1 in rsi +--* t43 byref this in rdi N007 ( 22, 23) [000045] --CXG------- t45 = * CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 objp: ====== lowering arg : N001 ( 0, 0) [000338] ----------L- * ARGPLACE byref $485 args: ====== lowering arg : N002 ( 0, 0) [000337] ----------L- * ARGPLACE long $486 late: ====== lowering arg : N004 ( 5, 12) [000047] n----------- * IND long new node is : [000535] ------------ * PUTARG_REG long REG rsi lowering arg : N005 ( 3, 2) [000043] -------N---- * LCL_VAR_ADDR byref V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 new node is : [000536] ------------ * PUTARG_REG byref REG rdi results of lowering call: N001 ( 3, 10) [000537] ------------ t537 = CNS_INT(h) long 0xd1ffab1e ftn /--* t537 long N002 ( 5, 12) [000538] ------------ t538 = * IND long lowering call (after): N003 ( 3, 10) [000046] ------------ t46 = CNS_INT(h) long 0xd1ffab1e class $1d0 /--* t46 long N004 ( 5, 12) [000047] n----------- t47 = * IND long /--* t47 long [000535] ------------ t535 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000043] -------N---- t43 = LCL_VAR_ADDR byref V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 /--* t43 byref [000536] ------------ t536 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000537] ------------ t537 = CNS_INT(h) long 0xd1ffab1e ftn /--* t537 long N002 ( 5, 12) [000538] -c---------- t538 = * IND long REG NA /--* t535 long arg1 in rsi +--* t536 byref this in rdi +--* t538 long control expr N007 ( 22, 23) [000045] --CXG------- t45 = * CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 Addressing mode: Base N010 ( 1, 1) [000350] ------------ * LCL_VAR byref V25 tmp14 u:2 (last use) $487 + 8 Removing unused node: N011 ( 1, 1) [000351] -c---------- * CNS_INT long 8 Fseq[_index] $2c3 New addressing mode node: N012 ( 2, 2) [000352] ------------ * LEA(b+8) byref lowering call (before): N003 ( 3, 10) [000415] ------------ t415 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t415 long N004 ( 5, 12) [000414] n----------- t414 = * IND long N005 ( 3, 2) [000417] ----G--N---- t417 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t414 long arg1 in rsi +--* t417 byref this in rdi N007 ( 22, 23) [000411] --CXG------- t411 = * CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $212 objp: ====== lowering arg : N001 ( 0, 0) [000412] ----------L- * ARGPLACE byref $489 args: ====== lowering arg : N002 ( 0, 0) [000413] ----------L- * ARGPLACE long $48a late: ====== lowering arg : N004 ( 5, 12) [000414] n----------- * IND long new node is : [000539] ------------ * PUTARG_REG long REG rsi lowering arg : N005 ( 3, 2) [000417] ----G--N---- * LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 new node is : [000540] ----G------- * PUTARG_REG byref REG rdi results of lowering call: N001 ( 3, 10) [000541] ------------ t541 = CNS_INT(h) long 0xd1ffab1e ftn /--* t541 long N002 ( 5, 12) [000542] ------------ t542 = * IND long lowering call (after): N003 ( 3, 10) [000415] ------------ t415 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t415 long N004 ( 5, 12) [000414] n----------- t414 = * IND long /--* t414 long [000539] ------------ t539 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000417] ----G--N---- t417 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t417 byref [000540] ----G------- t540 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000541] ------------ t541 = CNS_INT(h) long 0xd1ffab1e ftn /--* t541 long N002 ( 5, 12) [000542] -c---------- t542 = * IND long REG NA /--* t539 long arg1 in rsi +--* t540 byref this in rdi +--* t542 long control expr N007 ( 22, 23) [000411] --CXG------- t411 = * CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $212 lowering GT_RETURN N002 ( 4, 3) [000129] ------------ * RETURN int $214 ============lowering call (before): N003 ( 3, 10) [000067] ------------ t67 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t67 long N004 ( 5, 12) [000068] n----------- t68 = * IND long N005 ( 3, 2) [000064] -------N---- t64 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t68 long arg1 in rsi +--* t64 byref this in rdi N007 ( 22, 23) [000066] --CXG------- t66 = * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c objp: ====== lowering arg : N001 ( 0, 0) [000358] ----------L- * ARGPLACE byref $48b args: ====== lowering arg : N002 ( 0, 0) [000357] ----------L- * ARGPLACE long $48c late: ====== lowering arg : N004 ( 5, 12) [000068] n----------- * IND long new node is : [000543] ------------ * PUTARG_REG long REG rsi lowering arg : N005 ( 3, 2) [000064] -------N---- * LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 new node is : [000544] ------------ * PUTARG_REG byref REG rdi results of lowering call: N001 ( 3, 10) [000545] ------------ t545 = CNS_INT(h) long 0xd1ffab1e ftn /--* t545 long N002 ( 5, 12) [000546] ------------ t546 = * IND long lowering call (after): N003 ( 3, 10) [000067] ------------ t67 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t67 long N004 ( 5, 12) [000068] n----------- t68 = * IND long /--* t68 long [000543] ------------ t543 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000064] -------N---- t64 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t64 byref [000544] ------------ t544 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000545] ------------ t545 = CNS_INT(h) long 0xd1ffab1e ftn /--* t545 long N002 ( 5, 12) [000546] -c---------- t546 = * IND long REG NA /--* t543 long arg1 in rsi +--* t544 byref this in rdi +--* t546 long control expr N007 ( 22, 23) [000066] --CXG------- t66 = * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c lowering call (before): N003 ( 3, 10) [000067] ------------ t67 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t67 long N004 ( 5, 12) [000068] n----------- t68 = * IND long /--* t68 long [000543] ------------ t543 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000064] -------N---- t64 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t64 byref [000544] ------------ t544 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000545] ------------ t545 = CNS_INT(h) long 0xd1ffab1e ftn /--* t545 long N002 ( 5, 12) [000546] -c---------- t546 = * IND long REG NA /--* t543 long arg1 in rsi +--* t544 byref this in rdi +--* t546 long control expr N007 ( 22, 23) [000066] --CXG------- t66 = * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c /--* t66 ref N009 ( 26, 26) [000360] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp15 d:2 N012 ( 3, 2) [000361] ------------ t361 = LCL_VAR ref V26 tmp15 u:2 (last use) $16c N013 ( 3, 2) [000069] ------------ t69 = LCL_VAR ref V01 arg1 u:1 $81 N014 ( 3, 10) [000356] ------------ t356 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 /--* t361 ref this in rdi +--* t69 ref arg2 in rsi +--* t356 long arg1 in r11 N015 ( 55, 51) [000070] --CXG------- t70 = * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 objp: ====== lowering arg : N009 ( 26, 26) [000360] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp15 d:2 args: ====== lowering arg : N010 ( 0, 0) [000363] ----------L- * ARGPLACE long $16c lowering arg : N011 ( 0, 0) [000362] ----------L- * ARGPLACE ref $1d3 late: ====== lowering arg : N012 ( 3, 2) [000361] ------------ * LCL_VAR ref V26 tmp15 u:2 (last use) $16c new node is : [000547] ------------ * PUTARG_REG ref REG rdi lowering arg : N013 ( 3, 2) [000069] ------------ * LCL_VAR ref V01 arg1 u:1 $81 new node is : [000548] ------------ * PUTARG_REG ref REG rsi lowering arg : N014 ( 3, 10) [000356] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 new node is : [000549] ------------ * PUTARG_REG long REG r11 results of lowering call: N001 ( 3, 10) [000550] ------------ t550 = CNS_INT(h) long 0xd1ffab1e ftn /--* t550 long N002 ( 5, 12) [000551] ------------ t551 = * IND long lowering call (after): N003 ( 3, 10) [000067] ------------ t67 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t67 long N004 ( 5, 12) [000068] n----------- t68 = * IND long /--* t68 long [000543] ------------ t543 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000064] -------N---- t64 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t64 byref [000544] ------------ t544 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000545] ------------ t545 = CNS_INT(h) long 0xd1ffab1e ftn /--* t545 long N002 ( 5, 12) [000546] -c---------- t546 = * IND long REG NA /--* t543 long arg1 in rsi +--* t544 byref this in rdi +--* t546 long control expr N007 ( 22, 23) [000066] --CXG------- t66 = * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c /--* t66 ref N009 ( 26, 26) [000360] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp15 d:2 N012 ( 3, 2) [000361] ------------ t361 = LCL_VAR ref V26 tmp15 u:2 (last use) $16c /--* t361 ref [000547] ------------ t547 = * PUTARG_REG ref REG rdi N013 ( 3, 2) [000069] ------------ t69 = LCL_VAR ref V01 arg1 u:1 $81 /--* t69 ref [000548] ------------ t548 = * PUTARG_REG ref REG rsi N014 ( 3, 10) [000356] ------------ t356 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 /--* t356 long [000549] ------------ t549 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000550] ------------ t550 = CNS_INT(h) long 0xd1ffab1e ftn /--* t550 long N002 ( 5, 12) [000551] -c---------- t551 = * IND long REG NA /--* t547 ref this in rdi +--* t548 ref arg2 in rsi +--* t549 long arg1 in r11 +--* t551 long control expr N015 ( 55, 51) [000070] --CXG------- t70 = * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 lowering call (before): N003 ( 3, 2) [000080] ------------ t80 = LCL_VAR ref V10 loc4 u:2 $370 N004 ( 3, 10) [000365] ------------ t365 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t80 ref this in rdi +--* t365 long arg1 in r11 N005 ( 26, 22) [000247] --CXG------- t247 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 objp: ====== lowering arg : N001 ( 0, 0) [000366] ----------L- * ARGPLACE ref $172 args: ====== lowering arg : N002 ( 0, 0) [000367] ----------L- * ARGPLACE long $370 late: ====== lowering arg : N003 ( 3, 2) [000080] ------------ * LCL_VAR ref V10 loc4 u:2 $370 new node is : [000552] ------------ * PUTARG_REG ref REG rdi lowering arg : N004 ( 3, 10) [000365] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 new node is : [000553] ------------ * PUTARG_REG long REG r11 results of lowering call: N001 ( 3, 10) [000554] ------------ t554 = CNS_INT(h) long 0xd1ffab1e ftn /--* t554 long N002 ( 5, 12) [000555] ------------ t555 = * IND long lowering call (after): N003 ( 3, 2) [000080] ------------ t80 = LCL_VAR ref V10 loc4 u:2 $370 /--* t80 ref [000552] ------------ t552 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000365] ------------ t365 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t365 long [000553] ------------ t553 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000554] ------------ t554 = CNS_INT(h) long 0xd1ffab1e ftn /--* t554 long N002 ( 5, 12) [000555] -c---------- t555 = * IND long REG NA /--* t552 ref this in rdi +--* t553 long arg1 in r11 +--* t555 long control expr N005 ( 26, 22) [000247] --CXG------- t247 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 lowering call (before): N003 ( 3, 2) [000237] ------------ t237 = LCL_VAR ref V10 loc4 u:2 $370 N004 ( 1, 1) [000238] ------------ t238 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t237 ref arg0 in rdi +--* t238 byref arg1 in rsi N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000368] ----------L- * ARGPLACE ref $370 lowering arg : N002 ( 0, 0) [000369] ----------L- * ARGPLACE byref $c0 late: ====== lowering arg : N003 ( 3, 2) [000237] ------------ * LCL_VAR ref V10 loc4 u:2 $370 new node is : [000556] ------------ * PUTARG_REG ref REG rdi lowering arg : N004 ( 1, 1) [000238] ------------ * LCL_VAR byref V05 arg5 u:1 $c0 new node is : [000557] ------------ * PUTARG_REG byref REG rsi results of lowering call: N001 ( 3, 10) [000558] ------------ t558 = CNS_INT(h) long 0xd1ffab1e ftn /--* t558 long N002 ( 5, 12) [000559] ------------ t559 = * IND long lowering call (after): N003 ( 3, 2) [000237] ------------ t237 = LCL_VAR ref V10 loc4 u:2 $370 /--* t237 ref [000556] ------------ t556 = * PUTARG_REG ref REG rdi N004 ( 1, 1) [000238] ------------ t238 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t238 byref [000557] ------------ t557 = * PUTARG_REG byref REG rsi N001 ( 3, 10) [000558] ------------ t558 = CNS_INT(h) long 0xd1ffab1e ftn /--* t558 long N002 ( 5, 12) [000559] -c---------- t559 = * IND long REG NA /--* t556 ref arg0 in rdi +--* t557 byref arg1 in rsi +--* t559 long control expr N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void lowering call (before): N006 ( 3, 2) [000130] ------------ t130 = LCL_VAR ref V00 arg0 u:1 (last use) $80 N007 ( 1, 1) [000131] ------------ t131 = LCL_VAR ref V02 arg2 u:1 $82 N008 ( 1, 1) [000132] ------------ t132 = LCL_VAR ref V03 arg3 u:1 $83 N009 ( 3, 2) [000133] ------------ t133 = LCL_VAR ref V04 arg4 u:1 $84 N010 ( 1, 1) [000134] ------------ t134 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t130 ref arg0 in rdi +--* t131 ref arg1 in rsi +--* t132 ref arg2 in rdx +--* t133 ref arg3 in rcx +--* t134 byref arg4 in r8 N011 ( 23, 17) [000135] --CXG------- t135 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000329] ----------L- * ARGPLACE ref $80 lowering arg : N002 ( 0, 0) [000330] ----------L- * ARGPLACE ref $82 lowering arg : N003 ( 0, 0) [000331] ----------L- * ARGPLACE ref $83 lowering arg : N004 ( 0, 0) [000332] ----------L- * ARGPLACE ref $84 lowering arg : N005 ( 0, 0) [000333] ----------L- * ARGPLACE byref $c0 late: ====== lowering arg : N006 ( 3, 2) [000130] ------------ * LCL_VAR ref V00 arg0 u:1 (last use) $80 new node is : [000560] ------------ * PUTARG_REG ref REG rdi lowering arg : N007 ( 1, 1) [000131] ------------ * LCL_VAR ref V02 arg2 u:1 $82 new node is : [000561] ------------ * PUTARG_REG ref REG rsi lowering arg : N008 ( 1, 1) [000132] ------------ * LCL_VAR ref V03 arg3 u:1 $83 new node is : [000562] ------------ * PUTARG_REG ref REG rdx lowering arg : N009 ( 3, 2) [000133] ------------ * LCL_VAR ref V04 arg4 u:1 $84 new node is : [000563] ------------ * PUTARG_REG ref REG rcx lowering arg : N010 ( 1, 1) [000134] ------------ * LCL_VAR byref V05 arg5 u:1 $c0 new node is : [000564] ------------ * PUTARG_REG byref REG r8 results of lowering call: N001 ( 3, 10) [000565] ------------ t565 = CNS_INT(h) long 0xd1ffab1e ftn /--* t565 long N002 ( 5, 12) [000566] ------------ t566 = * IND long lowering call (after): N006 ( 3, 2) [000130] ------------ t130 = LCL_VAR ref V00 arg0 u:1 (last use) $80 /--* t130 ref [000560] ------------ t560 = * PUTARG_REG ref REG rdi N007 ( 1, 1) [000131] ------------ t131 = LCL_VAR ref V02 arg2 u:1 $82 /--* t131 ref [000561] ------------ t561 = * PUTARG_REG ref REG rsi N008 ( 1, 1) [000132] ------------ t132 = LCL_VAR ref V03 arg3 u:1 $83 /--* t132 ref [000562] ------------ t562 = * PUTARG_REG ref REG rdx N009 ( 3, 2) [000133] ------------ t133 = LCL_VAR ref V04 arg4 u:1 $84 /--* t133 ref [000563] ------------ t563 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000134] ------------ t134 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t134 byref [000564] ------------ t564 = * PUTARG_REG byref REG r8 N001 ( 3, 10) [000565] ------------ t565 = CNS_INT(h) long 0xd1ffab1e ftn /--* t565 long N002 ( 5, 12) [000566] -c---------- t566 = * IND long REG NA /--* t560 ref arg0 in rdi +--* t561 ref arg1 in rsi +--* t562 ref arg2 in rdx +--* t563 ref arg3 in rcx +--* t564 byref arg4 in r8 +--* t566 long control expr N011 ( 23, 17) [000135] --CXG------- t135 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f lowering call (before): N004 ( 1, 1) [000079] ------------ t79 = LCL_VAR ref V03 arg3 u:1 $83 N005 ( 3, 2) [000229] ------------ t229 = LCL_VAR ref V10 loc4 u:2 $370 N006 ( 1, 1) [000081] ------------ t81 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t79 ref arg0 in rdi +--* t229 ref arg1 in rsi +--* t81 byref arg2 in rdx N007 ( 19, 12) [000230] --CXG------- t230 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000371] ----------L- * ARGPLACE ref $83 lowering arg : N002 ( 0, 0) [000372] ----------L- * ARGPLACE ref $370 lowering arg : N003 ( 0, 0) [000373] ----------L- * ARGPLACE byref $c0 late: ====== lowering arg : N004 ( 1, 1) [000079] ------------ * LCL_VAR ref V03 arg3 u:1 $83 new node is : [000567] ------------ * PUTARG_REG ref REG rdi lowering arg : N005 ( 3, 2) [000229] ------------ * LCL_VAR ref V10 loc4 u:2 $370 new node is : [000568] ------------ * PUTARG_REG ref REG rsi lowering arg : N006 ( 1, 1) [000081] ------------ * LCL_VAR byref V05 arg5 u:1 $c0 new node is : [000569] ------------ * PUTARG_REG byref REG rdx results of lowering call: N001 ( 3, 10) [000570] ------------ t570 = CNS_INT(h) long 0xd1ffab1e ftn /--* t570 long N002 ( 5, 12) [000571] ------------ t571 = * IND long lowering call (after): N004 ( 1, 1) [000079] ------------ t79 = LCL_VAR ref V03 arg3 u:1 $83 /--* t79 ref [000567] ------------ t567 = * PUTARG_REG ref REG rdi N005 ( 3, 2) [000229] ------------ t229 = LCL_VAR ref V10 loc4 u:2 $370 /--* t229 ref [000568] ------------ t568 = * PUTARG_REG ref REG rsi N006 ( 1, 1) [000081] ------------ t81 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t81 byref [000569] ------------ t569 = * PUTARG_REG byref REG rdx N001 ( 3, 10) [000570] ------------ t570 = CNS_INT(h) long 0xd1ffab1e ftn /--* t570 long N002 ( 5, 12) [000571] -c---------- t571 = * IND long REG NA /--* t567 ref arg0 in rdi +--* t568 ref arg1 in rsi +--* t569 byref arg2 in rdx +--* t571 long control expr N007 ( 19, 12) [000230] --CXG------- t230 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 lowering call (before): N003 ( 3, 10) [000058] ------------ t58 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t58 long N004 ( 5, 12) [000059] n----------- t59 = * IND long N005 ( 3, 2) [000055] -------N---- t55 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t59 long arg1 in rsi +--* t55 byref this in rdi N007 ( 22, 23) [000057] --CXG------- t57 = * CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $21b objp: ====== lowering arg : N001 ( 0, 0) [000406] ----------L- * ARGPLACE byref $48f args: ====== lowering arg : N002 ( 0, 0) [000405] ----------L- * ARGPLACE long $490 late: ====== lowering arg : N004 ( 5, 12) [000059] n----------- * IND long new node is : [000572] ------------ * PUTARG_REG long REG rsi lowering arg : N005 ( 3, 2) [000055] -------N---- * LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 new node is : [000573] ------------ * PUTARG_REG byref REG rdi results of lowering call: N001 ( 3, 10) [000574] ------------ t574 = CNS_INT(h) long 0xd1ffab1e ftn /--* t574 long N002 ( 5, 12) [000575] ------------ t575 = * IND long lowering call (after): N003 ( 3, 10) [000058] ------------ t58 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t58 long N004 ( 5, 12) [000059] n----------- t59 = * IND long /--* t59 long [000572] ------------ t572 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000055] -------N---- t55 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t55 byref [000573] ------------ t573 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000574] ------------ t574 = CNS_INT(h) long 0xd1ffab1e ftn /--* t574 long N002 ( 5, 12) [000575] -c---------- t575 = * IND long REG NA /--* t572 long arg1 in rsi +--* t573 byref this in rdi +--* t575 long control expr N007 ( 22, 23) [000057] --CXG------- t57 = * CALL r2r_ind int Enumerator[__Canon][System.__Canon].MoveNext $21b lowering call (before): N004 ( 1, 1) [000143] ------------ t143 = LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000144] ------------ t144 = LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000145] ------------ t145 = LCL_VAR ref V04 arg4 u:1 $84 /--* t143 ref arg0 in rdi +--* t144 ref arg1 in rsi +--* t145 ref arg2 in rdx N007 ( 19, 12) [000146] --CXG------- t146 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000322] ----------L- * ARGPLACE ref $82 lowering arg : N002 ( 0, 0) [000323] ----------L- * ARGPLACE ref $83 lowering arg : N003 ( 0, 0) [000324] ----------L- * ARGPLACE ref $84 late: ====== lowering arg : N004 ( 1, 1) [000143] ------------ * LCL_VAR ref V02 arg2 u:1 $82 new node is : [000576] ------------ * PUTARG_REG ref REG rdi lowering arg : N005 ( 1, 1) [000144] ------------ * LCL_VAR ref V03 arg3 u:1 $83 new node is : [000577] ------------ * PUTARG_REG ref REG rsi lowering arg : N006 ( 3, 2) [000145] ------------ * LCL_VAR ref V04 arg4 u:1 $84 new node is : [000578] ------------ * PUTARG_REG ref REG rdx results of lowering call: N001 ( 3, 10) [000579] ------------ t579 = CNS_INT(h) long 0xd1ffab1e ftn /--* t579 long N002 ( 5, 12) [000580] ------------ t580 = * IND long lowering call (after): N004 ( 1, 1) [000143] ------------ t143 = LCL_VAR ref V02 arg2 u:1 $82 /--* t143 ref [000576] ------------ t576 = * PUTARG_REG ref REG rdi N005 ( 1, 1) [000144] ------------ t144 = LCL_VAR ref V03 arg3 u:1 $83 /--* t144 ref [000577] ------------ t577 = * PUTARG_REG ref REG rsi N006 ( 3, 2) [000145] ------------ t145 = LCL_VAR ref V04 arg4 u:1 $84 /--* t145 ref [000578] ------------ t578 = * PUTARG_REG ref REG rdx N001 ( 3, 10) [000579] ------------ t579 = CNS_INT(h) long 0xd1ffab1e ftn /--* t579 long N002 ( 5, 12) [000580] -c---------- t580 = * IND long REG NA /--* t576 ref arg0 in rdi +--* t577 ref arg1 in rsi +--* t578 ref arg2 in rdx +--* t580 long control expr N007 ( 19, 12) [000146] --CXG------- t146 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c lowering call (before): N002 ( 1, 1) [000098] ------------ t98 = CNS_INT long 2 $2c4 /--* t98 long arg0 in rdi N003 ( 15, 7) [000099] --CXG------- t99 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000374] ----------L- * ARGPLACE long $2c4 late: ====== lowering arg : N002 ( 1, 1) [000098] ------------ * CNS_INT long 2 $2c4 new node is : [000581] ------------ * PUTARG_REG long REG rdi results of lowering call: N001 ( 3, 10) [000582] ------------ t582 = CNS_INT(h) long 0xd1ffab1e ftn /--* t582 long N002 ( 5, 12) [000583] ------------ t583 = * IND long lowering call (after): N002 ( 1, 1) [000098] ------------ t98 = CNS_INT long 2 $2c4 /--* t98 long [000581] ------------ t581 = * PUTARG_REG long REG rdi N001 ( 3, 10) [000582] ------------ t582 = CNS_INT(h) long 0xd1ffab1e ftn /--* t582 long N002 ( 5, 12) [000583] -c---------- t583 = * IND long REG NA /--* t581 long arg0 in rdi +--* t583 long control expr N003 ( 15, 7) [000099] --CXG------- t99 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 Addressing mode: Base N002 ( 3, 2) [000103] ------------ * LCL_VAR ref V14 tmp3 u:2 $385 + 8 Removing unused node: [000503] -c---------- * CNS_INT long 8 New addressing mode node: [000504] ------------ * LEA(b+8) ref Addressing mode: Base N009 ( 3, 2) [000375] ------------ * LCL_VAR ref V14 tmp3 u:2 $385 + 16 Removing unused node: N010 ( 1, 1) [000382] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $2c1 New addressing mode node: N011 ( 4, 3) [000383] ------------ * LEA(b+16) byref Addressing mode: Base N004 ( 3, 2) [000385] ------------ * LCL_VAR ref V14 tmp3 u:2 $385 + 24 Removing unused node: N005 ( 1, 1) [000392] -c---------- * CNS_INT long 24 Fseq[#ConstantIndex, #FirstElem] $2c5 New addressing mode node: N006 ( 4, 3) [000393] ------------ * LEA(b+24) byref lowering call (before): N001 ( 14, 5) [000259] --C--------- t259 = CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 objp: ====== args: ====== late: ====== results of lowering call: N001 ( 3, 10) [000584] ------------ t584 = CNS_INT(h) long 0xd1ffab1e ftn /--* t584 long N002 ( 5, 12) [000585] ------------ t585 = * IND long lowering call (after): N001 ( 3, 10) [000584] ------------ t584 = CNS_INT(h) long 0xd1ffab1e ftn /--* t584 long N002 ( 5, 12) [000585] -c---------- t585 = * IND long REG NA /--* t585 long control expr N001 ( 14, 5) [000259] --C--------- t259 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 lowering call (before): N002 ( 14, 5) [000252] H-CXG------- t252 = CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 objp: ====== args: ====== late: ====== results of lowering call: N001 ( 3, 10) [000586] ------------ t586 = CNS_INT(h) long 0xd1ffab1e ftn /--* t586 long N002 ( 5, 12) [000587] ------------ t587 = * IND long lowering call (after): N001 ( 3, 10) [000586] ------------ t586 = CNS_INT(h) long 0xd1ffab1e ftn /--* t586 long N002 ( 5, 12) [000587] -c---------- t587 = * IND long REG NA /--* t587 long control expr N002 ( 14, 5) [000252] H-CXG------- t252 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 Addressing mode: Base N002 ( 14, 5) [000252] H-CXG------- * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 + 1048 Removing unused node: N003 ( 1, 4) [000253] -c---------- * CNS_INT int 0x418 Fseq[Instance] $48 New addressing mode node: N004 ( 15, 9) [000254] ------------ * LEA(b+1048) byref lowering call (before): N001 ( 3, 10) [000586] ------------ t586 = CNS_INT(h) long 0xd1ffab1e ftn /--* t586 long N002 ( 5, 12) [000587] -c---------- t587 = * IND long REG NA /--* t587 long control expr N002 ( 14, 5) [000252] H-CXG------- t252 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 /--* t252 byref N004 ( 15, 9) [000254] -c---------- t254 = * LEA(b+1048) byref /--* t254 byref N005 ( 17, 11) [000255] ---XG------- t255 = * IND ref /--* t255 ref N007 ( 21, 14) [000396] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp16 d:2 N010 ( 3, 2) [000397] ------------ t397 = LCL_VAR ref V27 tmp16 u:2 (last use) N011 ( 3, 2) [000262] ------------ t262 = LCL_VAR ref V20 tmp9 u:2 $647 N012 ( 3, 2) [000102] ------------ t102 = LCL_VAR ref V14 tmp3 u:2 (last use) $385 N013 ( 1, 4) [000256] ------------ t256 = CNS_INT int 0x7D2C $64 /--* t397 ref arg1 in rsi +--* t262 ref this in rdi +--* t102 ref arg3 in rcx +--* t256 int arg2 in rdx N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void objp: ====== lowering arg : N001 ( 0, 0) [000398] ----------L- * ARGPLACE ref $17d args: ====== lowering arg : N007 ( 21, 14) [000396] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp16 d:2 lowering arg : N008 ( 0, 0) [000400] ----------L- * ARGPLACE int lowering arg : N009 ( 0, 0) [000399] ----------L- * ARGPLACE ref $64 late: ====== lowering arg : N010 ( 3, 2) [000397] ------------ * LCL_VAR ref V27 tmp16 u:2 (last use) new node is : [000588] ------------ * PUTARG_REG ref REG rsi lowering arg : N011 ( 3, 2) [000262] ------------ * LCL_VAR ref V20 tmp9 u:2 $647 new node is : [000589] ------------ * PUTARG_REG ref REG rdi lowering arg : N012 ( 3, 2) [000102] ------------ * LCL_VAR ref V14 tmp3 u:2 (last use) $385 new node is : [000590] ------------ * PUTARG_REG ref REG rcx lowering arg : N013 ( 1, 4) [000256] ------------ * CNS_INT int 0x7D2C $64 new node is : [000591] ------------ * PUTARG_REG int REG rdx results of lowering call: N001 ( 3, 10) [000592] ------------ t592 = CNS_INT(h) long 0xd1ffab1e ftn /--* t592 long N002 ( 5, 12) [000593] ------------ t593 = * IND long lowering call (after): N001 ( 3, 10) [000586] ------------ t586 = CNS_INT(h) long 0xd1ffab1e ftn /--* t586 long N002 ( 5, 12) [000587] -c---------- t587 = * IND long REG NA /--* t587 long control expr N002 ( 14, 5) [000252] H-CXG------- t252 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 /--* t252 byref N004 ( 15, 9) [000254] -c---------- t254 = * LEA(b+1048) byref /--* t254 byref N005 ( 17, 11) [000255] ---XG------- t255 = * IND ref /--* t255 ref N007 ( 21, 14) [000396] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp16 d:2 N010 ( 3, 2) [000397] ------------ t397 = LCL_VAR ref V27 tmp16 u:2 (last use) /--* t397 ref [000588] ------------ t588 = * PUTARG_REG ref REG rsi N011 ( 3, 2) [000262] ------------ t262 = LCL_VAR ref V20 tmp9 u:2 $647 /--* t262 ref [000589] ------------ t589 = * PUTARG_REG ref REG rdi N012 ( 3, 2) [000102] ------------ t102 = LCL_VAR ref V14 tmp3 u:2 (last use) $385 /--* t102 ref [000590] ------------ t590 = * PUTARG_REG ref REG rcx N013 ( 1, 4) [000256] ------------ t256 = CNS_INT int 0x7D2C $64 /--* t256 int [000591] ------------ t591 = * PUTARG_REG int REG rdx N001 ( 3, 10) [000592] ------------ t592 = CNS_INT(h) long 0xd1ffab1e ftn /--* t592 long N002 ( 5, 12) [000593] -c---------- t593 = * IND long REG NA /--* t588 ref arg1 in rsi +--* t589 ref this in rdi +--* t590 ref arg3 in rcx +--* t591 int arg2 in rdx +--* t593 long control expr N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void lowering call (before): N003 ( 3, 2) [000121] -c-----N---- t121 = LCL_VAR_ADDR byref V15 tmp4 u:4 (last use) /--* t121 byref N005 ( 9, 7) [000124] n----------- t124 = * OBJ struct $507 N006 ( 3, 2) [000095] ------------ t95 = LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000401] ------------ t401 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t124 struct arg2 out+00 +--* t95 ref this in rdi +--* t401 long arg1 in r11 N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void objp: ====== lowering arg : N001 ( 0, 0) [000402] ----------L- * ARGPLACE ref $682 args: ====== lowering arg : N002 ( 0, 0) [000403] ----------L- * ARGPLACE long $84 lowering arg : N005 ( 9, 7) [000124] n----------- * OBJ struct $507 new node is : [000595] ------------ * PUTARG_STK [+0x00] void (5 slots) late: ====== lowering arg : N006 ( 3, 2) [000095] ------------ * LCL_VAR ref V04 arg4 u:1 $84 new node is : [000596] ------------ * PUTARG_REG ref REG rdi lowering arg : N007 ( 3, 10) [000401] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 new node is : [000597] ------------ * PUTARG_REG long REG r11 results of lowering call: N001 ( 3, 10) [000598] ------------ t598 = CNS_INT(h) long 0xd1ffab1e ftn /--* t598 long N002 ( 5, 12) [000599] ------------ t599 = * IND long lowering call (after): N003 ( 3, 2) [000121] -c-----N---- t121 = LCL_VAR_ADDR byref V15 tmp4 u:4 (last use) /--* t121 byref N005 ( 9, 7) [000124] nc---------- t124 = * OBJ struct $507 /--* t124 struct [000595] ------------ * PUTARG_STK [+0x00] void (5 slots) (RepInstr) N006 ( 3, 2) [000095] ------------ t95 = LCL_VAR ref V04 arg4 u:1 $84 /--* t95 ref [000596] ------------ t596 = * PUTARG_REG ref REG rdi N007 ( 3, 10) [000401] ------------ t401 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t401 long [000597] ------------ t597 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000598] ------------ t598 = CNS_INT(h) long 0xd1ffab1e ftn /--* t598 long N002 ( 5, 12) [000599] -c---------- t599 = * IND long REG NA /--* t596 ref this in rdi +--* t597 long arg1 in r11 +--* t599 long control expr N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void lowering call (before): N004 ( 1, 1) [000155] ------------ t155 = LCL_VAR ref V02 arg2 u:1 $82 N005 ( 1, 1) [000156] ------------ t156 = LCL_VAR ref V03 arg3 u:1 $83 N006 ( 3, 2) [000157] ------------ t157 = LCL_VAR ref V04 arg4 u:1 $84 /--* t155 ref arg0 in rdi +--* t156 ref arg1 in rsi +--* t157 ref arg2 in rdx N007 ( 19, 12) [000158] --CXG------- t158 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000315] ----------L- * ARGPLACE ref $82 lowering arg : N002 ( 0, 0) [000316] ----------L- * ARGPLACE ref $83 lowering arg : N003 ( 0, 0) [000317] ----------L- * ARGPLACE ref $84 late: ====== lowering arg : N004 ( 1, 1) [000155] ------------ * LCL_VAR ref V02 arg2 u:1 $82 new node is : [000600] ------------ * PUTARG_REG ref REG rdi lowering arg : N005 ( 1, 1) [000156] ------------ * LCL_VAR ref V03 arg3 u:1 $83 new node is : [000601] ------------ * PUTARG_REG ref REG rsi lowering arg : N006 ( 3, 2) [000157] ------------ * LCL_VAR ref V04 arg4 u:1 $84 new node is : [000602] ------------ * PUTARG_REG ref REG rdx results of lowering call: N001 ( 3, 10) [000603] ------------ t603 = CNS_INT(h) long 0xd1ffab1e ftn /--* t603 long N002 ( 5, 12) [000604] ------------ t604 = * IND long lowering call (after): N004 ( 1, 1) [000155] ------------ t155 = LCL_VAR ref V02 arg2 u:1 $82 /--* t155 ref [000600] ------------ t600 = * PUTARG_REG ref REG rdi N005 ( 1, 1) [000156] ------------ t156 = LCL_VAR ref V03 arg3 u:1 $83 /--* t156 ref [000601] ------------ t601 = * PUTARG_REG ref REG rsi N006 ( 3, 2) [000157] ------------ t157 = LCL_VAR ref V04 arg4 u:1 $84 /--* t157 ref [000602] ------------ t602 = * PUTARG_REG ref REG rdx N001 ( 3, 10) [000603] ------------ t603 = CNS_INT(h) long 0xd1ffab1e ftn /--* t603 long N002 ( 5, 12) [000604] -c---------- t604 = * IND long REG NA /--* t600 ref arg0 in rdi +--* t601 ref arg1 in rsi +--* t602 ref arg2 in rdx +--* t604 long control expr N007 ( 19, 12) [000158] --CXG------- t158 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 lowering call (before): N002 ( 1, 1) [000176] ------------ t176 = CNS_INT long 1 $2c0 /--* t176 long arg0 in rdi N003 ( 15, 7) [000177] --CXG------- t177 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000288] ----------L- * ARGPLACE long $2c0 late: ====== lowering arg : N002 ( 1, 1) [000176] ------------ * CNS_INT long 1 $2c0 new node is : [000605] ------------ * PUTARG_REG long REG rdi results of lowering call: N001 ( 3, 10) [000606] ------------ t606 = CNS_INT(h) long 0xd1ffab1e ftn /--* t606 long N002 ( 5, 12) [000607] ------------ t607 = * IND long lowering call (after): N002 ( 1, 1) [000176] ------------ t176 = CNS_INT long 1 $2c0 /--* t176 long [000605] ------------ t605 = * PUTARG_REG long REG rdi N001 ( 3, 10) [000606] ------------ t606 = CNS_INT(h) long 0xd1ffab1e ftn /--* t606 long N002 ( 5, 12) [000607] -c---------- t607 = * IND long REG NA /--* t605 long arg0 in rdi +--* t607 long control expr N003 ( 15, 7) [000177] --CXG------- t177 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 Addressing mode: Base N002 ( 3, 2) [000181] ------------ * LCL_VAR ref V16 tmp5 u:2 $380 + 8 Removing unused node: [000506] -c---------- * CNS_INT long 8 New addressing mode node: [000507] ------------ * LEA(b+8) ref Addressing mode: Base N005 ( 3, 2) [000289] ------------ * LCL_VAR ref V16 tmp5 u:2 $380 + 16 Removing unused node: N006 ( 1, 1) [000296] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $2c1 New addressing mode node: N007 ( 4, 3) [000297] ------------ * LEA(b+16) byref lowering call (before): N001 ( 14, 5) [000214] --C--------- t214 = CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c objp: ====== args: ====== late: ====== results of lowering call: N001 ( 3, 10) [000608] ------------ t608 = CNS_INT(h) long 0xd1ffab1e ftn /--* t608 long N002 ( 5, 12) [000609] ------------ t609 = * IND long lowering call (after): N001 ( 3, 10) [000608] ------------ t608 = CNS_INT(h) long 0xd1ffab1e ftn /--* t608 long N002 ( 5, 12) [000609] -c---------- t609 = * IND long REG NA /--* t609 long control expr N001 ( 14, 5) [000214] --C--------- t214 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c lowering call (before): N002 ( 14, 5) [000207] H-CXG------- t207 = CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 objp: ====== args: ====== late: ====== results of lowering call: N001 ( 3, 10) [000610] ------------ t610 = CNS_INT(h) long 0xd1ffab1e ftn /--* t610 long N002 ( 5, 12) [000611] ------------ t611 = * IND long lowering call (after): N001 ( 3, 10) [000610] ------------ t610 = CNS_INT(h) long 0xd1ffab1e ftn /--* t610 long N002 ( 5, 12) [000611] -c---------- t611 = * IND long REG NA /--* t611 long control expr N002 ( 14, 5) [000207] H-CXG------- t207 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 Addressing mode: Base N002 ( 14, 5) [000207] H-CXG------- * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 + 1048 Removing unused node: N003 ( 1, 4) [000208] -c---------- * CNS_INT int 0x418 Fseq[Instance] $48 New addressing mode node: N004 ( 15, 9) [000209] ------------ * LEA(b+1048) byref lowering call (before): N001 ( 3, 10) [000610] ------------ t610 = CNS_INT(h) long 0xd1ffab1e ftn /--* t610 long N002 ( 5, 12) [000611] -c---------- t611 = * IND long REG NA /--* t611 long control expr N002 ( 14, 5) [000207] H-CXG------- t207 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 /--* t207 byref N004 ( 15, 9) [000209] -c---------- t209 = * LEA(b+1048) byref /--* t209 byref N005 ( 17, 11) [000210] ---XG------- t210 = * IND ref /--* t210 ref N007 ( 21, 14) [000300] DA-XG-----L- * STORE_LCL_VAR ref V24 tmp13 d:2 N010 ( 3, 2) [000301] ------------ t301 = LCL_VAR ref V24 tmp13 u:2 (last use) N011 ( 3, 2) [000217] ------------ t217 = LCL_VAR ref V18 tmp7 u:2 $34c N012 ( 3, 2) [000180] ------------ t180 = LCL_VAR ref V16 tmp5 u:2 (last use) $380 N013 ( 1, 4) [000211] ------------ t211 = CNS_INT int 0x7AA4 $49 /--* t301 ref arg1 in rsi +--* t217 ref this in rdi +--* t180 ref arg3 in rcx +--* t211 int arg2 in rdx N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void objp: ====== lowering arg : N001 ( 0, 0) [000302] ----------L- * ARGPLACE ref $149 args: ====== lowering arg : N007 ( 21, 14) [000300] DA-XG-----L- * STORE_LCL_VAR ref V24 tmp13 d:2 lowering arg : N008 ( 0, 0) [000304] ----------L- * ARGPLACE int lowering arg : N009 ( 0, 0) [000303] ----------L- * ARGPLACE ref $49 late: ====== lowering arg : N010 ( 3, 2) [000301] ------------ * LCL_VAR ref V24 tmp13 u:2 (last use) new node is : [000612] ------------ * PUTARG_REG ref REG rsi lowering arg : N011 ( 3, 2) [000217] ------------ * LCL_VAR ref V18 tmp7 u:2 $34c new node is : [000613] ------------ * PUTARG_REG ref REG rdi lowering arg : N012 ( 3, 2) [000180] ------------ * LCL_VAR ref V16 tmp5 u:2 (last use) $380 new node is : [000614] ------------ * PUTARG_REG ref REG rcx lowering arg : N013 ( 1, 4) [000211] ------------ * CNS_INT int 0x7AA4 $49 new node is : [000615] ------------ * PUTARG_REG int REG rdx results of lowering call: N001 ( 3, 10) [000616] ------------ t616 = CNS_INT(h) long 0xd1ffab1e ftn /--* t616 long N002 ( 5, 12) [000617] ------------ t617 = * IND long lowering call (after): N001 ( 3, 10) [000610] ------------ t610 = CNS_INT(h) long 0xd1ffab1e ftn /--* t610 long N002 ( 5, 12) [000611] -c---------- t611 = * IND long REG NA /--* t611 long control expr N002 ( 14, 5) [000207] H-CXG------- t207 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 /--* t207 byref N004 ( 15, 9) [000209] -c---------- t209 = * LEA(b+1048) byref /--* t209 byref N005 ( 17, 11) [000210] ---XG------- t210 = * IND ref /--* t210 ref N007 ( 21, 14) [000300] DA-XG-----L- * STORE_LCL_VAR ref V24 tmp13 d:2 N010 ( 3, 2) [000301] ------------ t301 = LCL_VAR ref V24 tmp13 u:2 (last use) /--* t301 ref [000612] ------------ t612 = * PUTARG_REG ref REG rsi N011 ( 3, 2) [000217] ------------ t217 = LCL_VAR ref V18 tmp7 u:2 $34c /--* t217 ref [000613] ------------ t613 = * PUTARG_REG ref REG rdi N012 ( 3, 2) [000180] ------------ t180 = LCL_VAR ref V16 tmp5 u:2 (last use) $380 /--* t180 ref [000614] ------------ t614 = * PUTARG_REG ref REG rcx N013 ( 1, 4) [000211] ------------ t211 = CNS_INT int 0x7AA4 $49 /--* t211 int [000615] ------------ t615 = * PUTARG_REG int REG rdx N001 ( 3, 10) [000616] ------------ t616 = CNS_INT(h) long 0xd1ffab1e ftn /--* t616 long N002 ( 5, 12) [000617] -c---------- t617 = * IND long REG NA /--* t612 ref arg1 in rsi +--* t613 ref this in rdi +--* t614 ref arg3 in rcx +--* t615 int arg2 in rdx +--* t617 long control expr N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void lowering call (before): N004 ( 3, 3) [000189] ------------ t189 = LCL_VAR_ADDR byref V17 tmp6 $481 N005 ( 1, 1) [000174] ------------ t174 = LCL_VAR ref V02 arg2 u:1 $82 N006 ( 3, 2) [000219] ------------ t219 = LCL_VAR ref V18 tmp7 u:2 (last use) $34c /--* t189 byref this in rdi +--* t174 ref arg1 in rsi +--* t219 ref arg2 in rdx N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void objp: ====== lowering arg : N001 ( 0, 0) [000305] ----------L- * ARGPLACE byref $480 args: ====== lowering arg : N002 ( 0, 0) [000306] ----------L- * ARGPLACE ref $481 lowering arg : N003 ( 0, 0) [000307] ----------L- * ARGPLACE ref $82 late: ====== lowering arg : N004 ( 3, 3) [000189] ------------ * LCL_VAR_ADDR byref V17 tmp6 $481 new node is : [000618] ------------ * PUTARG_REG byref REG rdi lowering arg : N005 ( 1, 1) [000174] ------------ * LCL_VAR ref V02 arg2 u:1 $82 new node is : [000619] ------------ * PUTARG_REG ref REG rsi lowering arg : N006 ( 3, 2) [000219] ------------ * LCL_VAR ref V18 tmp7 u:2 (last use) $34c new node is : [000620] ------------ * PUTARG_REG ref REG rdx results of lowering call: N001 ( 3, 10) [000621] ------------ t621 = CNS_INT(h) long 0xd1ffab1e ftn /--* t621 long N002 ( 5, 12) [000622] ------------ t622 = * IND long lowering call (after): N004 ( 3, 3) [000189] ------------ t189 = LCL_VAR_ADDR byref V17 tmp6 $481 /--* t189 byref [000618] ------------ t618 = * PUTARG_REG byref REG rdi N005 ( 1, 1) [000174] ------------ t174 = LCL_VAR ref V02 arg2 u:1 $82 /--* t174 ref [000619] ------------ t619 = * PUTARG_REG ref REG rsi N006 ( 3, 2) [000219] ------------ t219 = LCL_VAR ref V18 tmp7 u:2 (last use) $34c /--* t219 ref [000620] ------------ t620 = * PUTARG_REG ref REG rdx N001 ( 3, 10) [000621] ------------ t621 = CNS_INT(h) long 0xd1ffab1e ftn /--* t621 long N002 ( 5, 12) [000622] -c---------- t622 = * IND long REG NA /--* t618 byref this in rdi +--* t619 ref arg1 in rsi +--* t620 ref arg2 in rdx +--* t622 long control expr N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void lowering call (before): N003 ( 3, 2) [000191] -c-----N---- t191 = LCL_VAR_ADDR byref V17 tmp6 /--* t191 byref N005 ( 9, 7) [000194] n---G------- t194 = * OBJ struct N006 ( 3, 2) [000173] ------------ t173 = LCL_VAR ref V04 arg4 u:1 $84 N007 ( 3, 10) [000308] ------------ t308 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t194 struct arg2 out+00 +--* t173 ref this in rdi +--* t308 long arg1 in r11 N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void objp: ====== lowering arg : N001 ( 0, 0) [000309] ----------L- * ARGPLACE ref $151 args: ====== lowering arg : N002 ( 0, 0) [000310] ----------L- * ARGPLACE long $84 lowering arg : N005 ( 9, 7) [000194] n---G------- * OBJ struct new node is : [000623] ----G------- * PUTARG_STK [+0x00] void (5 slots) late: ====== lowering arg : N006 ( 3, 2) [000173] ------------ * LCL_VAR ref V04 arg4 u:1 $84 new node is : [000624] ------------ * PUTARG_REG ref REG rdi lowering arg : N007 ( 3, 10) [000308] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 new node is : [000625] ------------ * PUTARG_REG long REG r11 results of lowering call: N001 ( 3, 10) [000626] ------------ t626 = CNS_INT(h) long 0xd1ffab1e ftn /--* t626 long N002 ( 5, 12) [000627] ------------ t627 = * IND long lowering call (after): N003 ( 3, 2) [000191] -c-----N---- t191 = LCL_VAR_ADDR byref V17 tmp6 /--* t191 byref N005 ( 9, 7) [000194] nc--G------- t194 = * OBJ struct /--* t194 struct [000623] ----G------- * PUTARG_STK [+0x00] void (5 slots) (RepInstr) N006 ( 3, 2) [000173] ------------ t173 = LCL_VAR ref V04 arg4 u:1 $84 /--* t173 ref [000624] ------------ t624 = * PUTARG_REG ref REG rdi N007 ( 3, 10) [000308] ------------ t308 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t308 long [000625] ------------ t625 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000626] ------------ t626 = CNS_INT(h) long 0xd1ffab1e ftn /--* t626 long N002 ( 5, 12) [000627] -c---------- t627 = * IND long REG NA /--* t624 ref this in rdi +--* t625 long arg1 in r11 +--* t627 long control expr N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void lowering call (before): N001 ( 14, 5) [000505] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL objp: ====== args: ====== late: ====== lowering call (after): N001 ( 14, 5) [000505] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC LIR BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC LIR BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC LIR BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC LIR BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC LIR BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC LIR BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC LIR BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC LIR BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC LIR BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB19 (always) i gcsafe bwd LIR BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC LIR BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC LIR BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC LIR BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC LIR BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe LIR BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC LIR BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC LIR BB19 [0017] 2 BB14,BB10 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC LIR BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC LIR BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC LIR BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC LIR BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC LIR BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC LIR BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC LIR BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC LIR BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC LIR BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC LIR BB29 [0038] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} N003 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V03 arg3 u:1 $83 /--* t0 ref [000508] ------------ t508 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000279] ------------ t279 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t279 long [000509] ------------ t509 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000510] ------------ t510 = CNS_INT(h) long 0xd1ffab1e ftn /--* t510 long N002 ( 5, 12) [000511] -c---------- t511 = * IND long REG NA /--* t508 ref this in rdi +--* t509 long arg1 in r11 +--* t511 long control expr N005 ( 24, 21) [000198] --CXG------- t198 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 N006 ( 1, 1) [000199] -c---------- t199 = CNS_INT int 4 $44 /--* t198 int +--* t199 int N007 ( 26, 23) [000200] J--XG--N---- * EQ void $280 N008 ( 28, 25) [000006] ---XG------- * JTRUE void ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} [000472] ------------ IL_OFFSET void IL offset: 0xf N001 ( 1, 1) [000007] -c---------- t7 = CNS_INT int 1 $41 /--* t7 int N003 ( 5, 4) [000009] DA---------- * STORE_LCL_VAR int V07 loc1 d:2 N004 ( 1, 1) [000010] ------------ t10 = LCL_VAR ref V03 arg3 u:1 $83 /--* t10 ref [000512] ------------ t512 = * PUTARG_REG ref REG rdi N005 ( 3, 10) [000284] ------------ t284 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 /--* t284 long [000513] ------------ t513 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000514] ------------ t514 = CNS_INT(h) long 0xd1ffab1e ftn /--* t514 long N002 ( 5, 12) [000515] -c---------- t515 = * IND long REG NA /--* t512 ref this in rdi +--* t513 long arg1 in r11 +--* t515 long control expr N006 ( 24, 21) [000202] --CXG------- t202 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 /--* t202 int N007 ( 25, 23) [000203] ---XG------- t203 = * CAST int <- byte <- int $281 /--* t203 int [000516] ---XG------- t516 = * PUTARG_REG int REG rdi N001 ( 3, 10) [000517] ------------ t517 = CNS_INT(h) long 0xd1ffab1e ftn /--* t517 long N002 ( 5, 12) [000518] -c---------- t518 = * IND long REG NA /--* t516 int arg0 in rdi +--* t518 long control expr N008 ( 39, 29) [000204] --CXG------- t204 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N010 ( 1, 1) [000014] -c---------- t14 = CNS_INT bool 0 $40 /--* t204 bool +--* t14 bool N011 ( 42, 33) [000015] J--XG--N-U-- * NE void $283 N012 ( 44, 35) [000016] ---XG------- * JTRUE void ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} N001 ( 0, 0) [000450] ------------ t450 = PHI_ARG bool V07 loc1 u:3 $40 N002 ( 0, 0) [000449] ------------ t449 = PHI_ARG bool V07 loc1 u:2 $41 /--* t450 bool +--* t449 bool N003 ( 0, 0) [000446] ------------ t446 = * PHI bool /--* t446 bool N005 ( 0, 0) [000447] DA---------- * STORE_LCL_VAR bool V07 loc1 d:4 [000473] ------------ IL_OFFSET void IL offset: 0x40 N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR ref V02 arg2 u:1 $82 /--* t17 ref [000519] ------------ t519 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000312] ------------ t312 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca /--* t312 long [000520] ------------ t520 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000521] ------------ t521 = CNS_INT(h) long 0xd1ffab1e ftn /--* t521 long N002 ( 5, 12) [000522] -c---------- t522 = * IND long REG NA /--* t519 ref this in rdi +--* t520 long arg1 in r11 +--* t522 long control expr N005 ( 24, 21) [000018] --CXG------- t18 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 N007 ( 1, 1) [000020] -c---------- t20 = CNS_INT bool 0 $40 /--* t18 bool +--* t20 bool N008 ( 27, 25) [000021] J--XG--N-U-- * NE void $287 N009 ( 29, 27) [000022] ---XG------- * JTRUE void ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} N001 ( 0, 0) [000452] ------------ t452 = PHI_ARG bool V07 loc1 u:5 $40 N002 ( 0, 0) [000451] ------------ t451 = PHI_ARG bool V07 loc1 u:4 $580 /--* t452 bool +--* t451 bool N003 ( 0, 0) [000443] ------------ t443 = * PHI bool /--* t443 bool N005 ( 0, 0) [000444] DA---------- * STORE_LCL_VAR bool V07 loc1 d:6 [000474] ------------ IL_OFFSET void IL offset: 0x55 N003 ( 1, 1) [000023] ------------ t23 = LCL_VAR ref V02 arg2 u:1 $82 /--* t23 ref [000523] ------------ t523 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000319] ------------ t319 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc /--* t319 long [000524] ------------ t524 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000525] ------------ t525 = CNS_INT(h) long 0xd1ffab1e ftn /--* t525 long N002 ( 5, 12) [000526] -c---------- t526 = * IND long REG NA /--* t523 ref this in rdi +--* t524 long arg1 in r11 +--* t526 long control expr N005 ( 24, 21) [000024] --CXG------- t24 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N007 ( 1, 1) [000026] -c---------- t26 = CNS_INT bool 0 $40 /--* t24 bool +--* t26 bool N008 ( 27, 25) [000027] J--XG--N-U-- * NE void $28b N009 ( 29, 27) [000028] ---XG------- * JTRUE void ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} N001 ( 0, 0) [000454] ------------ t454 = PHI_ARG bool V07 loc1 u:7 $40 N002 ( 0, 0) [000453] ------------ t453 = PHI_ARG bool V07 loc1 u:6 $581 /--* t454 bool +--* t453 bool N003 ( 0, 0) [000440] ------------ t440 = * PHI bool /--* t440 bool N005 ( 0, 0) [000441] DA---------- * STORE_LCL_VAR bool V07 loc1 d:8 [000475] ------------ IL_OFFSET void IL offset: 0x6a N003 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V02 arg2 u:1 $82 /--* t29 ref [000527] ------------ t527 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000326] ------------ t326 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce /--* t326 long [000528] ------------ t528 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000529] ------------ t529 = CNS_INT(h) long 0xd1ffab1e ftn /--* t529 long N002 ( 5, 12) [000530] -c---------- t530 = * IND long REG NA /--* t527 ref this in rdi +--* t528 long arg1 in r11 +--* t530 long control expr N005 ( 24, 21) [000030] --CXG------- t30 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N007 ( 1, 1) [000032] -c---------- t32 = CNS_INT bool 0 $40 /--* t30 bool +--* t32 bool N008 ( 27, 25) [000033] J--XG--N-U-- * NE void $28f N009 ( 29, 27) [000034] ---XG------- * JTRUE void ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} N001 ( 0, 0) [000456] ------------ t456 = PHI_ARG bool V07 loc1 u:9 $40 N002 ( 0, 0) [000455] ------------ t455 = PHI_ARG bool V07 loc1 u:8 $582 /--* t456 bool +--* t455 bool N003 ( 0, 0) [000437] ------------ t437 = * PHI bool /--* t437 bool N005 ( 0, 0) [000438] DA---------- * STORE_LCL_VAR bool V07 loc1 d:10 N003 ( 1, 1) [000035] ------------ t35 = LCL_VAR ref V02 arg2 u:1 $82 /--* t35 ref [000531] ------------ t531 = * PUTARG_REG ref REG rdi N004 ( 1, 1) [000036] ------------ t36 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t36 byref [000532] ------------ t532 = * PUTARG_REG byref REG rsi N001 ( 3, 10) [000533] ------------ t533 = CNS_INT(h) long 0xd1ffab1e ftn /--* t533 long N002 ( 5, 12) [000534] -c---------- t534 = * IND long REG NA /--* t531 ref this in rdi +--* t532 byref arg1 in rsi +--* t534 long control expr N005 ( 16, 10) [000037] --CXG------- t37 = * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 /--* t37 ref N007 ( 20, 13) [000042] DA-XG------- * STORE_LCL_VAR ref (AX) V23 tmp12 [000476] ------------ IL_OFFSET void IL offset: 0x8b N003 ( 3, 10) [000046] ------------ t46 = CNS_INT(h) long 0xd1ffab1e class $1d0 /--* t46 long N004 ( 5, 12) [000047] n----------- t47 = * IND long /--* t47 long [000535] ------------ t535 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000043] -------N---- t43 = LCL_VAR_ADDR byref V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 /--* t43 byref [000536] ------------ t536 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000537] ------------ t537 = CNS_INT(h) long 0xd1ffab1e ftn /--* t537 long N002 ( 5, 12) [000538] -c---------- t538 = * IND long REG NA /--* t535 long arg1 in rsi +--* t536 byref this in rdi +--* t538 long control expr N007 ( 22, 23) [000045] --CXG------- t45 = * CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 /--* t45 struct N009 ( 26, 26) [000050] DA-XG------- * STORE_LCL_VAR struct(AX) V12 tmp1 N001 ( 3, 2) [000341] -------N---- t341 = LCL_VAR_ADDR byref V12 tmp1 /--* t341 byref N004 ( 3, 3) [000343] DA---------- * STORE_LCL_VAR byref V25 tmp14 d:2 N005 ( 1, 1) [000345] ------------ t345 = LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 /--* t345 byref N006 ( 3, 2) [000346] ---X-------- t346 = * IND ref /--* t346 ref N008 ( 7, 5) [000347] DA-XG------- * STORE_LCL_VAR ref (AX) V21 tmp10 N010 ( 1, 1) [000350] ------------ t350 = LCL_VAR byref V25 tmp14 u:2 (last use) $487 /--* t350 byref N012 ( 2, 2) [000352] -c---------- t352 = * LEA(b+8) byref /--* t352 byref N013 ( 4, 4) [000353] n----O------ t353 = * IND int /--* t353 int N015 ( 8, 7) [000354] DA--GO------ * STORE_LCL_VAR int (AX) V22 tmp11 [000477] ------------ IL_OFFSET void IL offset: 0xe1 N003 ( 3, 10) [000415] ------------ t415 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t415 long N004 ( 5, 12) [000414] n----------- t414 = * IND long /--* t414 long [000539] ------------ t539 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000417] ----G--N---- t417 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t417 byref [000540] ----G------- t540 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000541] ------------ t541 = CNS_INT(h) long 0xd1ffab1e ftn /--* t541 long N002 ( 5, 12) [000542] -c---------- t542 = * IND long REG NA /--* t539 long arg1 in rsi +--* t540 byref this in rdi +--* t542 long control expr N007 ( 22, 23) [000411] --CXG------- t411 = * CALL r2r_ind bool Enumerator[__Canon][System.__Canon].MoveNext $212 N009 ( 1, 1) [000418] -c---------- t418 = CNS_INT bool 0 $40 /--* t411 bool +--* t418 bool N010 ( 25, 27) [000409] J--XG--N-U-- * NE void $295 N011 ( 27, 29) [000419] ---XG------- * JTRUE void ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} N001 ( 0, 0) [000461] ------------ t461 = PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ t457 = PHI_ARG bool V07 loc1 u:10 $583 /--* t461 bool +--* t457 bool N003 ( 0, 0) [000431] ------------ t431 = * PHI bool /--* t431 bool N005 ( 0, 0) [000432] DA---------- * STORE_LCL_VAR bool V07 loc1 d:14 [000478] ------------ IL_OFFSET void IL offset: 0xea N001 ( 3, 2) [000125] ------------ t125 = LCL_VAR int V07 loc1 u:14 (last use) $584 /--* t125 int N003 ( 7, 5) [000127] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} N001 ( 0, 0) [000463] ------------ t463 = PHI_ARG bool V06 loc0 u:4 $584 N002 ( 0, 0) [000448] ------------ t448 = PHI_ARG bool V06 loc0 u:2 $41 /--* t463 bool +--* t448 bool N003 ( 0, 0) [000425] ------------ t425 = * PHI bool /--* t425 bool N005 ( 0, 0) [000426] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 [000479] ------------ IL_OFFSET void IL offset: 0xec N001 ( 3, 2) [000128] ------------ t128 = LCL_VAR int V06 loc0 u:3 (last use) $585 /--* t128 int N002 ( 4, 3) [000129] ------------ * RETURN int $214 ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} N001 ( 0, 0) [000460] ------------ t460 = PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ t458 = PHI_ARG bool V07 loc1 u:10 $583 /--* t460 bool +--* t458 bool N003 ( 0, 0) [000434] ------------ t434 = * PHI bool /--* t434 bool N005 ( 0, 0) [000435] DA---------- * STORE_LCL_VAR bool V07 loc1 d:11 [000480] ------------ IL_OFFSET void IL offset: 0x95 N003 ( 3, 10) [000067] ------------ t67 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t67 long N004 ( 5, 12) [000068] n----------- t68 = * IND long /--* t68 long [000543] ------------ t543 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000064] -------N---- t64 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t64 byref [000544] ------------ t544 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000545] ------------ t545 = CNS_INT(h) long 0xd1ffab1e ftn /--* t545 long N002 ( 5, 12) [000546] -c---------- t546 = * IND long REG NA /--* t543 long arg1 in rsi +--* t544 byref this in rdi +--* t546 long control expr N007 ( 22, 23) [000066] --CXG------- t66 = * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c /--* t66 ref N009 ( 26, 26) [000360] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp15 d:2 N012 ( 3, 2) [000361] ------------ t361 = LCL_VAR ref V26 tmp15 u:2 (last use) $16c /--* t361 ref [000547] ------------ t547 = * PUTARG_REG ref REG rdi N013 ( 3, 2) [000069] ------------ t69 = LCL_VAR ref V01 arg1 u:1 $81 /--* t69 ref [000548] ------------ t548 = * PUTARG_REG ref REG rsi N014 ( 3, 10) [000356] ------------ t356 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 /--* t356 long [000549] ------------ t549 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000550] ------------ t550 = CNS_INT(h) long 0xd1ffab1e ftn /--* t550 long N002 ( 5, 12) [000551] -c---------- t551 = * IND long REG NA /--* t547 ref this in rdi +--* t548 ref arg2 in rsi +--* t549 long arg1 in r11 +--* t551 long control expr N015 ( 55, 51) [000070] --CXG------- t70 = * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 /--* t70 struct N017 ( 59, 54) [000073] DA-XG------- * STORE_LCL_VAR struct V13 tmp2 d:2 N001 ( 3, 4) [000076] ------------ t76 = LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) $370 /--* t76 ref N003 ( 7, 7) [000078] DA---------- * STORE_LCL_VAR ref V10 loc4 d:2 [000481] ------------ IL_OFFSET void IL offset: 0xa9 N003 ( 3, 2) [000080] ------------ t80 = LCL_VAR ref V10 loc4 u:2 $370 /--* t80 ref [000552] ------------ t552 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000365] ------------ t365 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t365 long [000553] ------------ t553 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000554] ------------ t554 = CNS_INT(h) long 0xd1ffab1e ftn /--* t554 long N002 ( 5, 12) [000555] -c---------- t555 = * IND long REG NA /--* t552 ref this in rdi +--* t553 long arg1 in r11 +--* t555 long control expr N005 ( 26, 22) [000247] --CXG------- t247 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 N006 ( 1, 1) [000248] -c---------- t248 = CNS_INT int 4 $44 /--* t247 int +--* t248 int N007 ( 28, 24) [000249] J--XG--N---- * NE void $296 N008 ( 30, 26) [000228] ---XG------- * JTRUE void ------------ BB10 [0A9..0AA) -> BB19 (always), preds={BB09} succs={BB19} [000482] ------------ IL_OFFSET void IL offset: 0xa9 N003 ( 3, 2) [000237] ------------ t237 = LCL_VAR ref V10 loc4 u:2 $370 /--* t237 ref [000556] ------------ t556 = * PUTARG_REG ref REG rdi N004 ( 1, 1) [000238] ------------ t238 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t238 byref [000557] ------------ t557 = * PUTARG_REG byref REG rsi N001 ( 3, 10) [000558] ------------ t558 = CNS_INT(h) long 0xd1ffab1e ftn /--* t558 long N002 ( 5, 12) [000559] -c---------- t559 = * IND long REG NA /--* t556 ref arg0 in rdi +--* t557 byref arg1 in rsi +--* t559 long control expr N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void [000483] ------------ IL_OFFSET void IL offset: 0xa9 N001 ( 1, 1) [000240] ------------ t240 = CNS_INT int 0 $40 /--* t240 int N003 ( 5, 4) [000242] DA---------- * STORE_LCL_VAR int V19 tmp8 d:3 ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} [000484] ------------ IL_OFFSET void IL offset: 0x72 N006 ( 3, 2) [000130] ------------ t130 = LCL_VAR ref V00 arg0 u:1 (last use) $80 /--* t130 ref [000560] ------------ t560 = * PUTARG_REG ref REG rdi N007 ( 1, 1) [000131] ------------ t131 = LCL_VAR ref V02 arg2 u:1 $82 /--* t131 ref [000561] ------------ t561 = * PUTARG_REG ref REG rsi N008 ( 1, 1) [000132] ------------ t132 = LCL_VAR ref V03 arg3 u:1 $83 /--* t132 ref [000562] ------------ t562 = * PUTARG_REG ref REG rdx N009 ( 3, 2) [000133] ------------ t133 = LCL_VAR ref V04 arg4 u:1 $84 /--* t133 ref [000563] ------------ t563 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000134] ------------ t134 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t134 byref [000564] ------------ t564 = * PUTARG_REG byref REG r8 N001 ( 3, 10) [000565] ------------ t565 = CNS_INT(h) long 0xd1ffab1e ftn /--* t565 long N002 ( 5, 12) [000566] -c---------- t566 = * IND long REG NA /--* t560 ref arg0 in rdi +--* t561 ref arg1 in rsi +--* t562 ref arg2 in rdx +--* t563 ref arg3 in rcx +--* t564 byref arg4 in r8 +--* t566 long control expr N011 ( 23, 17) [000135] --CXG------- t135 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f N013 ( 1, 1) [000137] -c---------- t137 = CNS_INT bool 0 $40 /--* t135 bool +--* t137 bool N014 ( 26, 21) [000138] J--XG--N-U-- * EQ void $291 N015 ( 28, 23) [000139] ---XG------- * JTRUE void ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} [000485] ------------ IL_OFFSET void IL offset: 0xa9 N004 ( 1, 1) [000079] ------------ t79 = LCL_VAR ref V03 arg3 u:1 $83 /--* t79 ref [000567] ------------ t567 = * PUTARG_REG ref REG rdi N005 ( 3, 2) [000229] ------------ t229 = LCL_VAR ref V10 loc4 u:2 $370 /--* t229 ref [000568] ------------ t568 = * PUTARG_REG ref REG rsi N006 ( 1, 1) [000081] ------------ t81 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t81 byref [000569] ------------ t569 = * PUTARG_REG byref REG rdx N001 ( 3, 10) [000570] ------------ t570 = CNS_INT(h) long 0xd1ffab1e ftn /--* t570 long N002 ( 5, 12) [000571] -c---------- t571 = * IND long REG NA /--* t567 ref arg0 in rdi +--* t568 ref arg1 in rsi +--* t569 byref arg2 in rdx +--* t571 long control expr N007 ( 19, 12) [000230] --CXG------- t230 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 /--* t230 int N008 ( 20, 14) [000232] ---XG------- t232 = * CAST int <- bool <- int $297 /--* t232 int N010 ( 24, 17) [000234] DA-XG------- * STORE_LCL_VAR int V19 tmp8 d:2 N001 ( 3, 2) [000235] ------------ t235 = LCL_VAR int V19 tmp8 u:2 (last use) $297 N002 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 $40 /--* t235 int +--* t85 int N003 ( 5, 4) [000086] J------N---- * EQ void $298 N004 ( 7, 6) [000087] ------------ * JTRUE void ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB14,BB21} succs={BB16,BB09} N001 ( 0, 0) [000462] ------------ t462 = PHI_ARG bool V07 loc1 u:11 $586 N002 ( 0, 0) [000459] ------------ t459 = PHI_ARG bool V07 loc1 u:12 $40 /--* t462 bool +--* t459 bool N003 ( 0, 0) [000428] ------------ t428 = * PHI bool /--* t428 bool N005 ( 0, 0) [000429] DA---------- * STORE_LCL_VAR bool V07 loc1 d:13 [000486] ------------ IL_OFFSET void IL offset: 0xe1 N003 ( 3, 10) [000058] ------------ t58 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t58 long N004 ( 5, 12) [000059] n----------- t59 = * IND long /--* t59 long [000572] ------------ t572 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000055] -------N---- t55 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t55 byref [000573] ------------ t573 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000574] ------------ t574 = CNS_INT(h) long 0xd1ffab1e ftn /--* t574 long N002 ( 5, 12) [000575] -c---------- t575 = * IND long REG NA /--* t572 long arg1 in rsi +--* t573 byref this in rdi +--* t575 long control expr N007 ( 22, 23) [000057] --CXG------- t57 = * CALL r2r_ind bool Enumerator[__Canon][System.__Canon].MoveNext $21b N009 ( 1, 1) [000061] -c---------- t61 = CNS_INT bool 0 $40 /--* t57 bool +--* t61 bool N010 ( 25, 27) [000062] J--XG--N-U-- * NE void $29b N011 ( 27, 29) [000063] ---XG------- * JTRUE void ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} N004 ( 1, 1) [000143] ------------ t143 = LCL_VAR ref V02 arg2 u:1 $82 /--* t143 ref [000576] ------------ t576 = * PUTARG_REG ref REG rdi N005 ( 1, 1) [000144] ------------ t144 = LCL_VAR ref V03 arg3 u:1 $83 /--* t144 ref [000577] ------------ t577 = * PUTARG_REG ref REG rsi N006 ( 3, 2) [000145] ------------ t145 = LCL_VAR ref V04 arg4 u:1 $84 /--* t145 ref [000578] ------------ t578 = * PUTARG_REG ref REG rdx N001 ( 3, 10) [000579] ------------ t579 = CNS_INT(h) long 0xd1ffab1e ftn /--* t579 long N002 ( 5, 12) [000580] -c---------- t580 = * IND long REG NA /--* t576 ref arg0 in rdi +--* t577 ref arg1 in rsi +--* t578 ref arg2 in rdx +--* t580 long control expr N007 ( 19, 12) [000146] --CXG------- t146 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c N009 ( 1, 1) [000149] -c---------- t149 = CNS_INT bool 0 $40 /--* t146 bool +--* t149 bool N010 ( 22, 16) [000150] J--XG--N-U-- * NE void $28d N011 ( 24, 18) [000151] ---XG------- * JTRUE void ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} [000487] ------------ IL_OFFSET void IL offset: 0x68 N001 ( 1, 1) [000152] ------------ t152 = CNS_INT int 0 $40 /--* t152 int N003 ( 5, 4) [000154] DA---------- * STORE_LCL_VAR int V07 loc1 d:7 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB10} succs={BB20,BB21} [000488] ------------ IL_OFFSET void IL offset: 0xb5 N001 ( 3, 2) [000088] ------------ t88 = LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000089] -c---------- t89 = CNS_INT ref null $VN.Null /--* t88 ref +--* t89 ref N003 ( 5, 4) [000090] J------N---- * EQ void $284 N004 ( 7, 6) [000091] ------------ * JTRUE void ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} [000489] ------------ IL_OFFSET void IL offset: 0xb9 N002 ( 1, 1) [000098] ------------ t98 = CNS_INT long 2 $2c4 /--* t98 long [000581] ------------ t581 = * PUTARG_REG long REG rdi N001 ( 3, 10) [000582] ------------ t582 = CNS_INT(h) long 0xd1ffab1e ftn /--* t582 long N002 ( 5, 12) [000583] -c---------- t583 = * IND long REG NA /--* t581 long arg0 in rdi +--* t583 long control expr N003 ( 15, 7) [000099] --CXG------- t99 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 /--* t99 ref N005 ( 19, 10) [000101] DA-XG------- * STORE_LCL_VAR ref V14 tmp3 d:2 N001 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 0 $40 N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V14 tmp3 u:2 $385 /--* t103 ref [000504] -c---------- t504 = * LEA(b+8) ref /--* t504 ref N003 ( 5, 4) [000377] ---X-------- t377 = * IND int $299 /--* t377 int N005 ( 9, 7) [000465] DA-X-------- * STORE_LCL_VAR int V28 cse0 d:1 N006 ( 3, 2) [000466] ------------ t466 = LCL_VAR int V28 cse0 u:1 $299 /--* t104 int +--* t466 int N008 ( 17, 17) [000378] ---X-------- * ARR_BOUNDS_CHECK_Rng void $37c N009 ( 3, 2) [000375] ------------ t375 = LCL_VAR ref V14 tmp3 u:2 $385 /--* t375 ref N011 ( 4, 3) [000383] ------------ t383 = * LEA(b+16) byref N014 ( 1, 1) [000105] ------------ t105 = LCL_VAR ref V03 arg3 u:1 $83 /--* t383 byref +--* t105 ref [000490] -A-XG------- * STOREIND ref N001 ( 1, 1) [000109] -c---------- t109 = CNS_INT int 1 $41 N002 ( 3, 2) [000468] ------------ t468 = LCL_VAR int V28 cse0 u:1 $3c1 /--* t109 int +--* t468 int N003 ( 8, 10) [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void $645 N004 ( 3, 2) [000385] ------------ t385 = LCL_VAR ref V14 tmp3 u:2 $385 /--* t385 ref N006 ( 4, 3) [000393] ------------ t393 = * LEA(b+24) byref N009 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V10 loc4 u:2 (last use) $370 /--* t393 byref +--* t110 ref [000491] -A-XG------- * STOREIND ref N001 ( 3, 10) [000584] ------------ t584 = CNS_INT(h) long 0xd1ffab1e ftn /--* t584 long N002 ( 5, 12) [000585] -c---------- t585 = * IND long REG NA /--* t585 long control expr N001 ( 14, 5) [000259] --C--------- t259 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 /--* t259 ref N003 ( 18, 8) [000261] DA---------- * STORE_LCL_VAR ref V20 tmp9 d:2 N001 ( 3, 10) [000586] ------------ t586 = CNS_INT(h) long 0xd1ffab1e ftn /--* t586 long N002 ( 5, 12) [000587] -c---------- t587 = * IND long REG NA /--* t587 long control expr N002 ( 14, 5) [000252] H-CXG------- t252 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 /--* t252 byref N004 ( 15, 9) [000254] -c---------- t254 = * LEA(b+1048) byref /--* t254 byref N005 ( 17, 11) [000255] ---XG------- t255 = * IND ref /--* t255 ref N007 ( 21, 14) [000396] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp16 d:2 N010 ( 3, 2) [000397] ------------ t397 = LCL_VAR ref V27 tmp16 u:2 (last use) /--* t397 ref [000588] ------------ t588 = * PUTARG_REG ref REG rsi N011 ( 3, 2) [000262] ------------ t262 = LCL_VAR ref V20 tmp9 u:2 $647 /--* t262 ref [000589] ------------ t589 = * PUTARG_REG ref REG rdi N012 ( 3, 2) [000102] ------------ t102 = LCL_VAR ref V14 tmp3 u:2 (last use) $385 /--* t102 ref [000590] ------------ t590 = * PUTARG_REG ref REG rcx N013 ( 1, 4) [000256] ------------ t256 = CNS_INT int 0x7D2C $64 /--* t256 int [000591] ------------ t591 = * PUTARG_REG int REG rdx N001 ( 3, 10) [000592] ------------ t592 = CNS_INT(h) long 0xd1ffab1e ftn /--* t592 long N002 ( 5, 12) [000593] -c---------- t593 = * IND long REG NA /--* t588 ref arg1 in rsi +--* t589 ref this in rdi +--* t590 ref arg3 in rcx +--* t591 int arg2 in rdx +--* t593 long control expr N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N001 ( 1, 1) [000268] ------------ t268 = CNS_INT int 0 $40 [000594] Dc-----N---- t594 = LCL_VAR_ADDR byref V15 tmp4 /--* t594 byref +--* t268 int N003 ( 5, 4) [000269] sA---------- * STORE_BLK struct (init) (Unroll) N001 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V02 arg2 u:1 $82 /--* t96 ref N003 ( 5, 6) [000273] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:2->0[+0] Fseq[TypeParameter] N001 ( 3, 2) [000264] ------------ t264 = LCL_VAR ref V20 tmp9 u:2 (last use) $647 /--* t264 ref N003 ( 7, 7) [000277] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:3->0[+8] Fseq[DiagnosticInfo] [000492] ------------ IL_OFFSET void IL offset: 0xda N003 ( 3, 2) [000121] -c-----N---- t121 = LCL_VAR_ADDR byref V15 tmp4 u:4 (last use) /--* t121 byref N005 ( 9, 7) [000124] nc---------- t124 = * OBJ struct $507 /--* t124 struct [000595] ------------ * PUTARG_STK [+0x00] void (5 slots) (RepInstr) N006 ( 3, 2) [000095] ------------ t95 = LCL_VAR ref V04 arg4 u:1 $84 /--* t95 ref [000596] ------------ t596 = * PUTARG_REG ref REG rdi N007 ( 3, 10) [000401] ------------ t401 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t401 long [000597] ------------ t597 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000598] ------------ t598 = CNS_INT(h) long 0xd1ffab1e ftn /--* t598 long N002 ( 5, 12) [000599] -c---------- t599 = * IND long REG NA /--* t596 ref this in rdi +--* t597 long arg1 in r11 +--* t599 long control expr N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} [000493] ------------ IL_OFFSET void IL offset: 0xdf N001 ( 1, 1) [000092] ------------ t92 = CNS_INT int 0 $40 /--* t92 int N003 ( 5, 4) [000094] DA---------- * STORE_LCL_VAR int V07 loc1 d:12 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} [000494] ------------ IL_OFFSET void IL offset: 0x48 N004 ( 1, 1) [000155] ------------ t155 = LCL_VAR ref V02 arg2 u:1 $82 /--* t155 ref [000600] ------------ t600 = * PUTARG_REG ref REG rdi N005 ( 1, 1) [000156] ------------ t156 = LCL_VAR ref V03 arg3 u:1 $83 /--* t156 ref [000601] ------------ t601 = * PUTARG_REG ref REG rsi N006 ( 3, 2) [000157] ------------ t157 = LCL_VAR ref V04 arg4 u:1 $84 /--* t157 ref [000602] ------------ t602 = * PUTARG_REG ref REG rdx N001 ( 3, 10) [000603] ------------ t603 = CNS_INT(h) long 0xd1ffab1e ftn /--* t603 long N002 ( 5, 12) [000604] -c---------- t604 = * IND long REG NA /--* t600 ref arg0 in rdi +--* t601 ref arg1 in rsi +--* t602 ref arg2 in rdx +--* t604 long control expr N007 ( 19, 12) [000158] --CXG------- t158 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 N009 ( 1, 1) [000160] -c---------- t160 = CNS_INT bool 0 $40 /--* t158 bool +--* t160 bool N010 ( 22, 16) [000161] J--XG--N-U-- * NE void $289 N011 ( 24, 18) [000162] ---XG------- * JTRUE void ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} [000495] ------------ IL_OFFSET void IL offset: 0x53 N001 ( 1, 1) [000163] ------------ t163 = CNS_INT int 0 $40 /--* t163 int N003 ( 5, 4) [000165] DA---------- * STORE_LCL_VAR int V07 loc1 d:5 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} [000496] ------------ IL_OFFSET void IL offset: 0x8 N001 ( 1, 1) [000195] -c---------- t195 = CNS_INT int 1 $41 /--* t195 int N003 ( 5, 4) [000197] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} [000497] ------------ IL_OFFSET void IL offset: 0x19 N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000167] -c---------- t167 = CNS_INT ref null $VN.Null /--* t166 ref +--* t167 ref N003 ( 5, 4) [000168] J------N---- * EQ void $284 N004 ( 7, 6) [000169] ------------ * JTRUE void ------------ BB26 [01D..03E), preds={BB25} succs={BB27} [000498] ------------ IL_OFFSET void IL offset: 0x1d N002 ( 1, 1) [000176] ------------ t176 = CNS_INT long 1 $2c0 /--* t176 long [000605] ------------ t605 = * PUTARG_REG long REG rdi N001 ( 3, 10) [000606] ------------ t606 = CNS_INT(h) long 0xd1ffab1e ftn /--* t606 long N002 ( 5, 12) [000607] -c---------- t607 = * IND long REG NA /--* t605 long arg0 in rdi +--* t607 long control expr N003 ( 15, 7) [000177] --CXG------- t177 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 /--* t177 ref N005 ( 19, 10) [000179] DA-XG------- * STORE_LCL_VAR ref V16 tmp5 d:2 N001 ( 1, 1) [000182] -c---------- t182 = CNS_INT int 0 $40 N002 ( 3, 2) [000181] ------------ t181 = LCL_VAR ref V16 tmp5 u:2 $380 /--* t181 ref [000507] -c---------- t507 = * LEA(b+8) ref /--* t507 ref N003 ( 5, 4) [000291] -c-X-------- t291 = * IND int $285 /--* t182 int +--* t291 int N004 ( 10, 12) [000292] ---X-------- * ARR_BOUNDS_CHECK_Rng void $348 N005 ( 3, 2) [000289] ------------ t289 = LCL_VAR ref V16 tmp5 u:2 $380 /--* t289 ref N007 ( 4, 3) [000297] ------------ t297 = * LEA(b+16) byref N010 ( 1, 1) [000183] ------------ t183 = LCL_VAR ref V03 arg3 u:1 $83 /--* t297 byref +--* t183 ref [000499] -A-XG------- * STOREIND ref N001 ( 3, 10) [000608] ------------ t608 = CNS_INT(h) long 0xd1ffab1e ftn /--* t608 long N002 ( 5, 12) [000609] -c---------- t609 = * IND long REG NA /--* t609 long control expr N001 ( 14, 5) [000214] --C--------- t214 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c /--* t214 ref N003 ( 18, 8) [000216] DA---------- * STORE_LCL_VAR ref V18 tmp7 d:2 N001 ( 3, 10) [000610] ------------ t610 = CNS_INT(h) long 0xd1ffab1e ftn /--* t610 long N002 ( 5, 12) [000611] -c---------- t611 = * IND long REG NA /--* t611 long control expr N002 ( 14, 5) [000207] H-CXG------- t207 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 /--* t207 byref N004 ( 15, 9) [000209] -c---------- t209 = * LEA(b+1048) byref /--* t209 byref N005 ( 17, 11) [000210] ---XG------- t210 = * IND ref /--* t210 ref N007 ( 21, 14) [000300] DA-XG-----L- * STORE_LCL_VAR ref V24 tmp13 d:2 N010 ( 3, 2) [000301] ------------ t301 = LCL_VAR ref V24 tmp13 u:2 (last use) /--* t301 ref [000612] ------------ t612 = * PUTARG_REG ref REG rsi N011 ( 3, 2) [000217] ------------ t217 = LCL_VAR ref V18 tmp7 u:2 $34c /--* t217 ref [000613] ------------ t613 = * PUTARG_REG ref REG rdi N012 ( 3, 2) [000180] ------------ t180 = LCL_VAR ref V16 tmp5 u:2 (last use) $380 /--* t180 ref [000614] ------------ t614 = * PUTARG_REG ref REG rcx N013 ( 1, 4) [000211] ------------ t211 = CNS_INT int 0x7AA4 $49 /--* t211 int [000615] ------------ t615 = * PUTARG_REG int REG rdx N001 ( 3, 10) [000616] ------------ t616 = CNS_INT(h) long 0xd1ffab1e ftn /--* t616 long N002 ( 5, 12) [000617] -c---------- t617 = * IND long REG NA /--* t612 ref arg1 in rsi +--* t613 ref this in rdi +--* t614 ref arg3 in rcx +--* t615 int arg2 in rdx +--* t617 long control expr N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N004 ( 3, 3) [000189] ------------ t189 = LCL_VAR_ADDR byref V17 tmp6 $481 /--* t189 byref [000618] ------------ t618 = * PUTARG_REG byref REG rdi N005 ( 1, 1) [000174] ------------ t174 = LCL_VAR ref V02 arg2 u:1 $82 /--* t174 ref [000619] ------------ t619 = * PUTARG_REG ref REG rsi N006 ( 3, 2) [000219] ------------ t219 = LCL_VAR ref V18 tmp7 u:2 (last use) $34c /--* t219 ref [000620] ------------ t620 = * PUTARG_REG ref REG rdx N001 ( 3, 10) [000621] ------------ t621 = CNS_INT(h) long 0xd1ffab1e ftn /--* t621 long N002 ( 5, 12) [000622] -c---------- t622 = * IND long REG NA /--* t618 byref this in rdi +--* t619 ref arg1 in rsi +--* t620 ref arg2 in rdx +--* t622 long control expr N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void [000500] ------------ IL_OFFSET void IL offset: 0x39 N003 ( 3, 2) [000191] -c-----N---- t191 = LCL_VAR_ADDR byref V17 tmp6 /--* t191 byref N005 ( 9, 7) [000194] nc--G------- t194 = * OBJ struct /--* t194 struct [000623] ----G------- * PUTARG_STK [+0x00] void (5 slots) (RepInstr) N006 ( 3, 2) [000173] ------------ t173 = LCL_VAR ref V04 arg4 u:1 $84 /--* t173 ref [000624] ------------ t624 = * PUTARG_REG ref REG rdi N007 ( 3, 10) [000308] ------------ t308 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t308 long [000625] ------------ t625 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000626] ------------ t626 = CNS_INT(h) long 0xd1ffab1e ftn /--* t626 long N002 ( 5, 12) [000627] -c---------- t627 = * IND long REG NA /--* t624 ref this in rdi +--* t625 long arg1 in r11 +--* t627 long control expr N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} [000501] ------------ IL_OFFSET void IL offset: 0x3e N001 ( 1, 1) [000170] ------------ t170 = CNS_INT int 0 $40 /--* t170 int N003 ( 5, 4) [000172] DA---------- * STORE_LCL_VAR int V07 loc1 d:3 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} [000502] ------------ IL_OFFSET void IL offset: 0x80 N001 ( 1, 1) [000140] ------------ t140 = CNS_INT int 0 $40 /--* t140 int N003 ( 5, 4) [000142] DA---------- * STORE_LCL_VAR int V07 loc1 d:9 ------------ BB29 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [000505] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V07: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V02: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 2, refCntWtd = 2 New refCnts for V02: refCnt = 3, refCntWtd = 3 New refCnts for V02: refCnt = 4, refCntWtd = 4 New refCnts for V05: refCnt = 1, refCntWtd = 1 New refCnts for V09: refCnt = 1, refCntWtd = 1 New refCnts for V23: refCnt = 1, refCntWtd = 1 New refCnts for V23: refCnt = 2, refCntWtd = 2 New refCnts for V09: refCnt = 2, refCntWtd = 2 New refCnts for V12: refCnt = 1, refCntWtd = 2 New refCnts for V12: refCnt = 2, refCntWtd = 4 New refCnts for V25: refCnt = 1, refCntWtd = 2 New refCnts for V25: refCnt = 2, refCntWtd = 4 New refCnts for V08: refCnt = 1, refCntWtd = 1 New refCnts for V21: refCnt = 1, refCntWtd = 1 New refCnts for V25: refCnt = 3, refCntWtd = 6 New refCnts for V08: refCnt = 2, refCntWtd = 2 New refCnts for V22: refCnt = 1, refCntWtd = 1 New refCnts for V21: refCnt = 2, refCntWtd = 2 New refCnts for V22: refCnt = 2, refCntWtd = 2 New refCnts for V08: refCnt = 3, refCntWtd = 3 New refCnts for V07: refCnt = 2, refCntWtd = 2 New refCnts for V06: refCnt = 1, refCntWtd = 1 New refCnts for V06: refCnt = 2, refCntWtd = 2 New refCnts for V21: refCnt = 3, refCntWtd = 2.29 New refCnts for V22: refCnt = 3, refCntWtd = 2.29 New refCnts for V08: refCnt = 4, refCntWtd = 3.29 New refCnts for V26: refCnt = 1, refCntWtd = 0.58 New refCnts for V26: refCnt = 2, refCntWtd = 1.16 New refCnts for V01: refCnt = 1, refCntWtd = 0.29 New refCnts for V13: refCnt = 1, refCntWtd = 0.58 New refCnts for V13: refCnt = 2, refCntWtd = 1.16 New refCnts for V10: refCnt = 1, refCntWtd = 0.29 New refCnts for V10: refCnt = 2, refCntWtd = 0.58 New refCnts for V10: refCnt = 3, refCntWtd = 1.16 New refCnts for V05: refCnt = 2, refCntWtd = 1.58 New refCnts for V19: refCnt = 1, refCntWtd = 0.58 New refCnts for V00: refCnt = 1, refCntWtd = 0.01 New refCnts for V02: refCnt = 5, refCntWtd = 4.01 New refCnts for V03: refCnt = 3, refCntWtd = 2.01 New refCnts for V04: refCnt = 1, refCntWtd = 0.01 New refCnts for V05: refCnt = 3, refCntWtd = 1.59 New refCnts for V03: refCnt = 4, refCntWtd = 2.30 New refCnts for V10: refCnt = 4, refCntWtd = 1.45 New refCnts for V05: refCnt = 4, refCntWtd = 1.88 New refCnts for V19: refCnt = 2, refCntWtd = 0.87 New refCnts for V19: refCnt = 3, refCntWtd = 1.16 New refCnts for V21: refCnt = 4, refCntWtd = 2.58 New refCnts for V22: refCnt = 4, refCntWtd = 2.58 New refCnts for V08: refCnt = 5, refCntWtd = 3.58 New refCnts for V02: refCnt = 6, refCntWtd = 4.04 New refCnts for V03: refCnt = 5, refCntWtd = 2.33 New refCnts for V04: refCnt = 2, refCntWtd = 0.04 New refCnts for V07: refCnt = 3, refCntWtd = 2.01 New refCnts for V04: refCnt = 3, refCntWtd = 0.06 New refCnts for V14: refCnt = 1, refCntWtd = 0.04 New refCnts for V14: refCnt = 2, refCntWtd = 0.08 New refCnts for V28: refCnt = 1, refCntWtd = 0.02 New refCnts for V28: refCnt = 2, refCntWtd = 0.04 New refCnts for V14: refCnt = 3, refCntWtd = 0.12 New refCnts for V03: refCnt = 6, refCntWtd = 2.35 New refCnts for V28: refCnt = 3, refCntWtd = 0.06 New refCnts for V14: refCnt = 4, refCntWtd = 0.16 New refCnts for V10: refCnt = 5, refCntWtd = 1.47 New refCnts for V20: refCnt = 1, refCntWtd = 0.04 New refCnts for V27: refCnt = 1, refCntWtd = 0.04 New refCnts for V27: refCnt = 2, refCntWtd = 0.08 New refCnts for V20: refCnt = 2, refCntWtd = 0.08 New refCnts for V14: refCnt = 5, refCntWtd = 0.20 New refCnts for V15: refCnt = 1, refCntWtd = 0.04 New refCnts for V02: refCnt = 7, refCntWtd = 4.06 New refCnts for V15: refCnt = 2, refCntWtd = 0.08 New refCnts for V20: refCnt = 3, refCntWtd = 0.12 New refCnts for V15: refCnt = 3, refCntWtd = 0.12 New refCnts for V15: refCnt = 4, refCntWtd = 0.16 New refCnts for V04: refCnt = 4, refCntWtd = 0.08 New refCnts for V07: refCnt = 4, refCntWtd = 2.03 New refCnts for V02: refCnt = 8, refCntWtd = 4.07 New refCnts for V03: refCnt = 7, refCntWtd = 2.36 New refCnts for V04: refCnt = 5, refCntWtd = 0.09 New refCnts for V07: refCnt = 5, refCntWtd = 2.03 New refCnts for V06: refCnt = 3, refCntWtd = 2 New refCnts for V04: refCnt = 6, refCntWtd = 0.09 New refCnts for V16: refCnt = 1, refCntWtd = 0 New refCnts for V16: refCnt = 2, refCntWtd = 0 New refCnts for V16: refCnt = 3, refCntWtd = 0 New refCnts for V03: refCnt = 8, refCntWtd = 2.36 New refCnts for V18: refCnt = 1, refCntWtd = 0 New refCnts for V24: refCnt = 1, refCntWtd = 0 New refCnts for V24: refCnt = 2, refCntWtd = 0 New refCnts for V18: refCnt = 2, refCntWtd = 0 New refCnts for V16: refCnt = 4, refCntWtd = 0 New refCnts for V17: refCnt = 1, refCntWtd = 0 New refCnts for V02: refCnt = 9, refCntWtd = 4.07 New refCnts for V18: refCnt = 3, refCntWtd = 0 New refCnts for V17: refCnt = 2, refCntWtd = 0 New refCnts for V04: refCnt = 7, refCntWtd = 0.09 New refCnts for V07: refCnt = 6, refCntWtd = 2.03 New refCnts for V07: refCnt = 7, refCntWtd = 2.03 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 2, refCntWtd = 1.01 New refCnts for V00: refCnt = 3, refCntWtd = 2.01 New refCnts for V01: refCnt = 2, refCntWtd = 1.29 New refCnts for V01: refCnt = 3, refCntWtd = 2.29 New refCnts for V02: refCnt = 10, refCntWtd = 5.07 New refCnts for V02: refCnt = 11, refCntWtd = 6.07 New refCnts for V03: refCnt = 9, refCntWtd = 3.36 New refCnts for V03: refCnt = 10, refCntWtd = 4.36 New refCnts for V04: refCnt = 8, refCntWtd = 1.09 New refCnts for V04: refCnt = 9, refCntWtd = 2.09 New refCnts for V05: refCnt = 5, refCntWtd = 2.88 New refCnts for V05: refCnt = 6, refCntWtd = 3.88 *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 arg0 ref class-hnd ; V01 arg1 ref class-hnd ; V02 arg2 ref class-hnd ; V03 arg3 ref class-hnd ; V04 arg4 ref class-hnd ; V05 arg5 byref ; V06 loc0 bool ; V07 loc1 bool ; V08 loc2 struct do-not-enreg[XS] addr-exposed ld-addr-op ; V09 loc3 struct do-not-enreg[XS] addr-exposed ld-addr-op ; V10 loc4 ref class-hnd ; V11 OutArgs lclBlk <40> "OutgoingArgSpace" ; V12 tmp1 struct do-not-enreg[XSBR] multireg-ret addr-exposed "Return value temp for multireg return" ; V13 tmp2 struct do-not-enreg[SFR] multireg-ret "Return value temp for multireg return" ; V14 tmp3 ref class-hnd exact "dup spill" ; V15 tmp4 struct do-not-enreg[SFB] "NewObj constructor temp" ; V16 tmp5 ref class-hnd exact "dup spill" ; V17 tmp6 struct do-not-enreg[XS] addr-exposed "NewObj constructor temp" ; V18 tmp7 ref class-hnd exact "NewObj constructor temp" ; V19 tmp8 bool "Inline stloc first use temp" ; V20 tmp9 ref class-hnd exact "NewObj constructor temp" ; V21 tmp10 ref do-not-enreg[X] addr-exposed V08._array(offs=0x00) P-DEP "field V08._array (fldOffset=0x0)" ; V22 tmp11 int do-not-enreg[X] addr-exposed V08._index(offs=0x08) P-DEP "field V08._index (fldOffset=0x8)" ; V23 tmp12 ref do-not-enreg[X] addr-exposed V09.array(offs=0x00) P-DEP "field V09.array (fldOffset=0x0)" ; V24 tmp13 ref "argument with side effect" ; V25 tmp14 byref "BlockOp address local" ; V26 tmp15 ref "argument with side effect" ; V27 tmp16 ref "argument with side effect" ; V28 cse0 int "CSE - conservative" In fgLocalVarLivenessInit Local V13 should not be enregistered because: it is a struct Local V15 should not be enregistered because: it is a struct Tracked variable (21 out of 29) table: V02 arg2 [ ref]: refCnt = 11, refCntWtd = 6.07 V03 arg3 [ ref]: refCnt = 10, refCntWtd = 4.36 V25 tmp14 [ byref]: refCnt = 3, refCntWtd = 6 V05 arg5 [ byref]: refCnt = 6, refCntWtd = 3.88 V01 arg1 [ ref]: refCnt = 3, refCntWtd = 2.29 V04 arg4 [ ref]: refCnt = 9, refCntWtd = 2.09 V00 arg0 [ ref]: refCnt = 3, refCntWtd = 2.01 V07 loc1 [ bool]: refCnt = 7, refCntWtd = 2.03 V06 loc0 [ bool]: refCnt = 3, refCntWtd = 2 V10 loc4 [ ref]: refCnt = 5, refCntWtd = 1.47 V19 tmp8 [ bool]: refCnt = 3, refCntWtd = 1.16 V26 tmp15 [ ref]: refCnt = 2, refCntWtd = 1.16 V13 tmp2 [struct]: refCnt = 2, refCntWtd = 1.16 V14 tmp3 [ ref]: refCnt = 5, refCntWtd = 0.20 V15 tmp4 [struct]: refCnt = 4, refCntWtd = 0.16 V20 tmp9 [ ref]: refCnt = 3, refCntWtd = 0.12 V27 tmp16 [ ref]: refCnt = 2, refCntWtd = 0.08 V28 cse0 [ int]: refCnt = 3, refCntWtd = 0.06 V16 tmp5 [ ref]: refCnt = 4, refCntWtd = 0 V18 tmp7 [ ref]: refCnt = 3, refCntWtd = 0 V24 tmp13 [ ref]: refCnt = 2, refCntWtd = 0 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V03} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB02 USE(1)={V03 } + ByrefExposed + GcHeap DEF(1)={ V07} + ByrefExposed* + GcHeap* BB03 USE(1)={V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB04 USE(1)={V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB05 USE(1)={V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB06 USE(2)={V02 V05} + ByrefExposed + GcHeap DEF(1)={ V25 } + ByrefExposed* + GcHeap* BB07 USE(1)={V07 } DEF(1)={ V06} BB08 USE(1)={V06} DEF(0)={ } BB09 USE(1)={V01 } + ByrefExposed + GcHeap DEF(3)={ V10 V26 V13} + ByrefExposed* + GcHeap* BB10 USE(2)={V05 V10 } + ByrefExposed + GcHeap DEF(1)={ V19} + ByrefExposed* + GcHeap* BB12 USE(5)={V02 V03 V05 V04 V00} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB13 USE(0)={} DEF(0)={} BB14 USE(3)={V03 V05 V10 } + ByrefExposed + GcHeap DEF(1)={ V19} + ByrefExposed* + GcHeap* BB15 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB16 USE(0)={} DEF(0)={} BB17 USE(3)={V02 V03 V04} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB18 USE(0)={ } DEF(1)={V07} BB19 USE(1)={V04} DEF(0)={ } BB20 USE(4)={V02 V03 V04 V10 } + ByrefExposed + GcHeap DEF(5)={ V14 V15 V20 V27 V28} + ByrefExposed* + GcHeap* BB21 USE(0)={ } DEF(1)={V07} BB22 USE(3)={V02 V03 V04} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB23 USE(0)={ } DEF(1)={V07} BB24 USE(0)={ } DEF(1)={V06} BB25 USE(1)={V04} DEF(0)={ } BB26 USE(3)={V02 V03 V04 } + ByrefExposed + GcHeap DEF(3)={ V16 V18 V24} + ByrefExposed* + GcHeap* BB27 USE(0)={ } DEF(1)={V07} BB28 USE(0)={ } DEF(1)={V07} BB29 USE(0)={} DEF(0)={} ** Memory liveness computed, GcHeap states and ByrefExposed states diverge *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap BB02 IN (6)={V02 V03 V05 V01 V04 V00 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB03 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB04 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB05 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB06 IN (6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap BB07 IN (1)={V07 } OUT(1)={ V06} BB08 IN (1)={V06} OUT(0)={ } BB09 IN (6)={V02 V03 V05 V01 V04 V07 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V07 V10} + ByrefExposed + GcHeap BB10 IN (6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap BB12 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap BB13 IN (6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap BB14 IN (7)={V02 V03 V05 V01 V04 V07 V10} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V07 V10} + ByrefExposed + GcHeap BB15 IN (6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap BB16 IN (1)={V07} OUT(1)={V07} BB17 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB18 IN (6)={V02 V03 V05 V01 V04 V00 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB19 IN (6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap BB20 IN (6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap OUT(5)={V02 V03 V05 V01 V04 } + ByrefExposed + GcHeap BB21 IN (5)={V02 V03 V05 V01 V04 } + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap BB22 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB23 IN (6)={V02 V03 V05 V01 V04 V00 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB24 IN (0)={ } OUT(1)={V06} BB25 IN (6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap BB26 IN (6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap BB27 IN (6)={V02 V03 V05 V01 V04 V00 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap BB28 IN (5)={V02 V03 V05 V01 V04 } + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap BB29 IN (0)={} OUT(0)={} Removing dead store: N003 ( 5, 4) [000242] DA---------- * STORE_LCL_VAR int V19 tmp8 d:3 (last use) Removing dead node: N001 ( 1, 1) [000240] ------------ * CNS_INT int 0 $40 *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC LIR BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC LIR BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC LIR BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC LIR BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC LIR BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC LIR BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC LIR BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC LIR BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC LIR BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB19 (always) i gcsafe bwd LIR BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC LIR BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC LIR BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC LIR BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC LIR BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe LIR BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC LIR BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC LIR BB19 [0017] 2 BB14,BB10 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC LIR BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC LIR BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC LIR BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC LIR BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC LIR BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC LIR BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC LIR BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC LIR BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC LIR BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC LIR BB29 [0038] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V07: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V02: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 2, refCntWtd = 2 New refCnts for V02: refCnt = 3, refCntWtd = 3 New refCnts for V02: refCnt = 4, refCntWtd = 4 New refCnts for V05: refCnt = 1, refCntWtd = 1 New refCnts for V09: refCnt = 1, refCntWtd = 1 New refCnts for V23: refCnt = 1, refCntWtd = 1 New refCnts for V23: refCnt = 2, refCntWtd = 2 New refCnts for V09: refCnt = 2, refCntWtd = 2 New refCnts for V12: refCnt = 1, refCntWtd = 2 New refCnts for V12: refCnt = 2, refCntWtd = 4 New refCnts for V25: refCnt = 1, refCntWtd = 2 New refCnts for V25: refCnt = 2, refCntWtd = 4 New refCnts for V08: refCnt = 1, refCntWtd = 1 New refCnts for V21: refCnt = 1, refCntWtd = 1 New refCnts for V25: refCnt = 3, refCntWtd = 6 New refCnts for V08: refCnt = 2, refCntWtd = 2 New refCnts for V22: refCnt = 1, refCntWtd = 1 New refCnts for V21: refCnt = 2, refCntWtd = 2 New refCnts for V22: refCnt = 2, refCntWtd = 2 New refCnts for V08: refCnt = 3, refCntWtd = 3 New refCnts for V07: refCnt = 2, refCntWtd = 2 New refCnts for V06: refCnt = 1, refCntWtd = 1 New refCnts for V06: refCnt = 2, refCntWtd = 2 New refCnts for V21: refCnt = 3, refCntWtd = 2.29 New refCnts for V22: refCnt = 3, refCntWtd = 2.29 New refCnts for V08: refCnt = 4, refCntWtd = 3.29 New refCnts for V26: refCnt = 1, refCntWtd = 0.58 New refCnts for V26: refCnt = 2, refCntWtd = 1.16 New refCnts for V01: refCnt = 1, refCntWtd = 0.29 New refCnts for V13: refCnt = 1, refCntWtd = 0.58 New refCnts for V13: refCnt = 2, refCntWtd = 1.16 New refCnts for V10: refCnt = 1, refCntWtd = 0.29 New refCnts for V10: refCnt = 2, refCntWtd = 0.58 New refCnts for V10: refCnt = 3, refCntWtd = 1.16 New refCnts for V05: refCnt = 2, refCntWtd = 1.58 New refCnts for V00: refCnt = 1, refCntWtd = 0.01 New refCnts for V02: refCnt = 5, refCntWtd = 4.01 New refCnts for V03: refCnt = 3, refCntWtd = 2.01 New refCnts for V04: refCnt = 1, refCntWtd = 0.01 New refCnts for V05: refCnt = 3, refCntWtd = 1.59 New refCnts for V03: refCnt = 4, refCntWtd = 2.30 New refCnts for V10: refCnt = 4, refCntWtd = 1.45 New refCnts for V05: refCnt = 4, refCntWtd = 1.88 New refCnts for V19: refCnt = 1, refCntWtd = 0.29 New refCnts for V19: refCnt = 2, refCntWtd = 0.58 New refCnts for V21: refCnt = 4, refCntWtd = 2.58 New refCnts for V22: refCnt = 4, refCntWtd = 2.58 New refCnts for V08: refCnt = 5, refCntWtd = 3.58 New refCnts for V02: refCnt = 6, refCntWtd = 4.04 New refCnts for V03: refCnt = 5, refCntWtd = 2.33 New refCnts for V04: refCnt = 2, refCntWtd = 0.04 New refCnts for V07: refCnt = 3, refCntWtd = 2.01 New refCnts for V04: refCnt = 3, refCntWtd = 0.06 New refCnts for V14: refCnt = 1, refCntWtd = 0.04 New refCnts for V14: refCnt = 2, refCntWtd = 0.08 New refCnts for V28: refCnt = 1, refCntWtd = 0.02 New refCnts for V28: refCnt = 2, refCntWtd = 0.04 New refCnts for V14: refCnt = 3, refCntWtd = 0.12 New refCnts for V03: refCnt = 6, refCntWtd = 2.35 New refCnts for V28: refCnt = 3, refCntWtd = 0.06 New refCnts for V14: refCnt = 4, refCntWtd = 0.16 New refCnts for V10: refCnt = 5, refCntWtd = 1.47 New refCnts for V20: refCnt = 1, refCntWtd = 0.04 New refCnts for V27: refCnt = 1, refCntWtd = 0.04 New refCnts for V27: refCnt = 2, refCntWtd = 0.08 New refCnts for V20: refCnt = 2, refCntWtd = 0.08 New refCnts for V14: refCnt = 5, refCntWtd = 0.20 New refCnts for V15: refCnt = 1, refCntWtd = 0.04 New refCnts for V02: refCnt = 7, refCntWtd = 4.06 New refCnts for V15: refCnt = 2, refCntWtd = 0.08 New refCnts for V20: refCnt = 3, refCntWtd = 0.12 New refCnts for V15: refCnt = 3, refCntWtd = 0.12 New refCnts for V15: refCnt = 4, refCntWtd = 0.16 New refCnts for V04: refCnt = 4, refCntWtd = 0.08 New refCnts for V07: refCnt = 4, refCntWtd = 2.03 New refCnts for V02: refCnt = 8, refCntWtd = 4.07 New refCnts for V03: refCnt = 7, refCntWtd = 2.36 New refCnts for V04: refCnt = 5, refCntWtd = 0.09 New refCnts for V07: refCnt = 5, refCntWtd = 2.03 New refCnts for V06: refCnt = 3, refCntWtd = 2 New refCnts for V04: refCnt = 6, refCntWtd = 0.09 New refCnts for V16: refCnt = 1, refCntWtd = 0 New refCnts for V16: refCnt = 2, refCntWtd = 0 New refCnts for V16: refCnt = 3, refCntWtd = 0 New refCnts for V03: refCnt = 8, refCntWtd = 2.36 New refCnts for V18: refCnt = 1, refCntWtd = 0 New refCnts for V24: refCnt = 1, refCntWtd = 0 New refCnts for V24: refCnt = 2, refCntWtd = 0 New refCnts for V18: refCnt = 2, refCntWtd = 0 New refCnts for V16: refCnt = 4, refCntWtd = 0 New refCnts for V17: refCnt = 1, refCntWtd = 0 New refCnts for V02: refCnt = 9, refCntWtd = 4.07 New refCnts for V18: refCnt = 3, refCntWtd = 0 New refCnts for V17: refCnt = 2, refCntWtd = 0 New refCnts for V04: refCnt = 7, refCntWtd = 0.09 New refCnts for V07: refCnt = 6, refCntWtd = 2.03 New refCnts for V07: refCnt = 7, refCntWtd = 2.03 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 2, refCntWtd = 1.01 New refCnts for V00: refCnt = 3, refCntWtd = 2.01 New refCnts for V01: refCnt = 2, refCntWtd = 1.29 New refCnts for V01: refCnt = 3, refCntWtd = 2.29 New refCnts for V02: refCnt = 10, refCntWtd = 5.07 New refCnts for V02: refCnt = 11, refCntWtd = 6.07 New refCnts for V03: refCnt = 9, refCntWtd = 3.36 New refCnts for V03: refCnt = 10, refCntWtd = 4.36 New refCnts for V04: refCnt = 8, refCntWtd = 1.09 New refCnts for V04: refCnt = 9, refCntWtd = 2.09 New refCnts for V05: refCnt = 5, refCntWtd = 2.88 New refCnts for V05: refCnt = 6, refCntWtd = 3.88 *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC LIR BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC LIR BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC LIR BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC LIR BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC LIR BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC LIR BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC LIR BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC LIR BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC LIR BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB19 (always) i gcsafe bwd LIR BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC LIR BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC LIR BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC LIR BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC LIR BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe LIR BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC LIR BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC LIR BB19 [0017] 2 BB14,BB10 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC LIR BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC LIR BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC LIR BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC LIR BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC LIR BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC LIR BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC LIR BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC LIR BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC LIR BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC LIR BB29 [0038] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} N003 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V03 arg3 u:1 $83 /--* t0 ref [000508] ------------ t508 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000279] ------------ t279 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t279 long [000509] ------------ t509 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000510] ------------ t510 = CNS_INT(h) long 0xd1ffab1e ftn /--* t510 long N002 ( 5, 12) [000511] -c---------- t511 = * IND long REG NA /--* t508 ref this in rdi +--* t509 long arg1 in r11 +--* t511 long control expr N005 ( 24, 21) [000198] --CXG------- t198 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 N006 ( 1, 1) [000199] -c---------- t199 = CNS_INT int 4 $44 /--* t198 int +--* t199 int N007 ( 26, 23) [000200] J--XG--N---- * EQ void $280 N008 ( 28, 25) [000006] ---XG------- * JTRUE void ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} [000472] ------------ IL_OFFSET void IL offset: 0xf N001 ( 1, 1) [000007] -c---------- t7 = CNS_INT int 1 $41 /--* t7 int N003 ( 5, 4) [000009] DA---------- * STORE_LCL_VAR int V07 loc1 d:2 N004 ( 1, 1) [000010] ------------ t10 = LCL_VAR ref V03 arg3 u:1 $83 /--* t10 ref [000512] ------------ t512 = * PUTARG_REG ref REG rdi N005 ( 3, 10) [000284] ------------ t284 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 /--* t284 long [000513] ------------ t513 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000514] ------------ t514 = CNS_INT(h) long 0xd1ffab1e ftn /--* t514 long N002 ( 5, 12) [000515] -c---------- t515 = * IND long REG NA /--* t512 ref this in rdi +--* t513 long arg1 in r11 +--* t515 long control expr N006 ( 24, 21) [000202] --CXG------- t202 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 /--* t202 int N007 ( 25, 23) [000203] ---XG------- t203 = * CAST int <- byte <- int $281 /--* t203 int [000516] ---XG------- t516 = * PUTARG_REG int REG rdi N001 ( 3, 10) [000517] ------------ t517 = CNS_INT(h) long 0xd1ffab1e ftn /--* t517 long N002 ( 5, 12) [000518] -c---------- t518 = * IND long REG NA /--* t516 int arg0 in rdi +--* t518 long control expr N008 ( 39, 29) [000204] --CXG------- t204 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N010 ( 1, 1) [000014] -c---------- t14 = CNS_INT bool 0 $40 /--* t204 bool +--* t14 bool N011 ( 42, 33) [000015] J--XG--N-U-- * NE void $283 N012 ( 44, 35) [000016] ---XG------- * JTRUE void ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} N001 ( 0, 0) [000450] ------------ t450 = PHI_ARG bool V07 loc1 u:3 $40 N002 ( 0, 0) [000449] ------------ t449 = PHI_ARG bool V07 loc1 u:2 $41 /--* t450 bool +--* t449 bool N003 ( 0, 0) [000446] ------------ t446 = * PHI bool /--* t446 bool N005 ( 0, 0) [000447] DA---------- * STORE_LCL_VAR bool V07 loc1 d:4 [000473] ------------ IL_OFFSET void IL offset: 0x40 N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR ref V02 arg2 u:1 $82 /--* t17 ref [000519] ------------ t519 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000312] ------------ t312 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca /--* t312 long [000520] ------------ t520 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000521] ------------ t521 = CNS_INT(h) long 0xd1ffab1e ftn /--* t521 long N002 ( 5, 12) [000522] -c---------- t522 = * IND long REG NA /--* t519 ref this in rdi +--* t520 long arg1 in r11 +--* t522 long control expr N005 ( 24, 21) [000018] --CXG------- t18 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 N007 ( 1, 1) [000020] -c---------- t20 = CNS_INT bool 0 $40 /--* t18 bool +--* t20 bool N008 ( 27, 25) [000021] J--XG--N-U-- * NE void $287 N009 ( 29, 27) [000022] ---XG------- * JTRUE void ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} N001 ( 0, 0) [000452] ------------ t452 = PHI_ARG bool V07 loc1 u:5 $40 N002 ( 0, 0) [000451] ------------ t451 = PHI_ARG bool V07 loc1 u:4 $580 /--* t452 bool +--* t451 bool N003 ( 0, 0) [000443] ------------ t443 = * PHI bool /--* t443 bool N005 ( 0, 0) [000444] DA---------- * STORE_LCL_VAR bool V07 loc1 d:6 [000474] ------------ IL_OFFSET void IL offset: 0x55 N003 ( 1, 1) [000023] ------------ t23 = LCL_VAR ref V02 arg2 u:1 $82 /--* t23 ref [000523] ------------ t523 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000319] ------------ t319 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc /--* t319 long [000524] ------------ t524 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000525] ------------ t525 = CNS_INT(h) long 0xd1ffab1e ftn /--* t525 long N002 ( 5, 12) [000526] -c---------- t526 = * IND long REG NA /--* t523 ref this in rdi +--* t524 long arg1 in r11 +--* t526 long control expr N005 ( 24, 21) [000024] --CXG------- t24 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N007 ( 1, 1) [000026] -c---------- t26 = CNS_INT bool 0 $40 /--* t24 bool +--* t26 bool N008 ( 27, 25) [000027] J--XG--N-U-- * NE void $28b N009 ( 29, 27) [000028] ---XG------- * JTRUE void ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} N001 ( 0, 0) [000454] ------------ t454 = PHI_ARG bool V07 loc1 u:7 $40 N002 ( 0, 0) [000453] ------------ t453 = PHI_ARG bool V07 loc1 u:6 $581 /--* t454 bool +--* t453 bool N003 ( 0, 0) [000440] ------------ t440 = * PHI bool /--* t440 bool N005 ( 0, 0) [000441] DA---------- * STORE_LCL_VAR bool V07 loc1 d:8 [000475] ------------ IL_OFFSET void IL offset: 0x6a N003 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V02 arg2 u:1 $82 /--* t29 ref [000527] ------------ t527 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000326] ------------ t326 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce /--* t326 long [000528] ------------ t528 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000529] ------------ t529 = CNS_INT(h) long 0xd1ffab1e ftn /--* t529 long N002 ( 5, 12) [000530] -c---------- t530 = * IND long REG NA /--* t527 ref this in rdi +--* t528 long arg1 in r11 +--* t530 long control expr N005 ( 24, 21) [000030] --CXG------- t30 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N007 ( 1, 1) [000032] -c---------- t32 = CNS_INT bool 0 $40 /--* t30 bool +--* t32 bool N008 ( 27, 25) [000033] J--XG--N-U-- * NE void $28f N009 ( 29, 27) [000034] ---XG------- * JTRUE void ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} N001 ( 0, 0) [000456] ------------ t456 = PHI_ARG bool V07 loc1 u:9 $40 N002 ( 0, 0) [000455] ------------ t455 = PHI_ARG bool V07 loc1 u:8 $582 /--* t456 bool +--* t455 bool N003 ( 0, 0) [000437] ------------ t437 = * PHI bool /--* t437 bool N005 ( 0, 0) [000438] DA---------- * STORE_LCL_VAR bool V07 loc1 d:10 N003 ( 1, 1) [000035] ------------ t35 = LCL_VAR ref V02 arg2 u:1 $82 /--* t35 ref [000531] ------------ t531 = * PUTARG_REG ref REG rdi N004 ( 1, 1) [000036] ------------ t36 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t36 byref [000532] ------------ t532 = * PUTARG_REG byref REG rsi N001 ( 3, 10) [000533] ------------ t533 = CNS_INT(h) long 0xd1ffab1e ftn /--* t533 long N002 ( 5, 12) [000534] -c---------- t534 = * IND long REG NA /--* t531 ref this in rdi +--* t532 byref arg1 in rsi +--* t534 long control expr N005 ( 16, 10) [000037] --CXG------- t37 = * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 /--* t37 ref N007 ( 20, 13) [000042] DA-XG------- * STORE_LCL_VAR ref (AX) V23 tmp12 [000476] ------------ IL_OFFSET void IL offset: 0x8b N003 ( 3, 10) [000046] ------------ t46 = CNS_INT(h) long 0xd1ffab1e class $1d0 /--* t46 long N004 ( 5, 12) [000047] n----------- t47 = * IND long /--* t47 long [000535] ------------ t535 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000043] -------N---- t43 = LCL_VAR_ADDR byref V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 /--* t43 byref [000536] ------------ t536 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000537] ------------ t537 = CNS_INT(h) long 0xd1ffab1e ftn /--* t537 long N002 ( 5, 12) [000538] -c---------- t538 = * IND long REG NA /--* t535 long arg1 in rsi +--* t536 byref this in rdi +--* t538 long control expr N007 ( 22, 23) [000045] --CXG------- t45 = * CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 /--* t45 struct N009 ( 26, 26) [000050] DA-XG------- * STORE_LCL_VAR struct(AX) V12 tmp1 N001 ( 3, 2) [000341] -------N---- t341 = LCL_VAR_ADDR byref V12 tmp1 /--* t341 byref N004 ( 3, 3) [000343] DA---------- * STORE_LCL_VAR byref V25 tmp14 d:2 N005 ( 1, 1) [000345] ------------ t345 = LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 /--* t345 byref N006 ( 3, 2) [000346] ---X-------- t346 = * IND ref /--* t346 ref N008 ( 7, 5) [000347] DA-XG------- * STORE_LCL_VAR ref (AX) V21 tmp10 N010 ( 1, 1) [000350] ------------ t350 = LCL_VAR byref V25 tmp14 u:2 (last use) $487 /--* t350 byref N012 ( 2, 2) [000352] -c---------- t352 = * LEA(b+8) byref /--* t352 byref N013 ( 4, 4) [000353] n----O------ t353 = * IND int /--* t353 int N015 ( 8, 7) [000354] DA--GO------ * STORE_LCL_VAR int (AX) V22 tmp11 [000477] ------------ IL_OFFSET void IL offset: 0xe1 N003 ( 3, 10) [000415] ------------ t415 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t415 long N004 ( 5, 12) [000414] n----------- t414 = * IND long /--* t414 long [000539] ------------ t539 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000417] ----G--N---- t417 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t417 byref [000540] ----G------- t540 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000541] ------------ t541 = CNS_INT(h) long 0xd1ffab1e ftn /--* t541 long N002 ( 5, 12) [000542] -c---------- t542 = * IND long REG NA /--* t539 long arg1 in rsi +--* t540 byref this in rdi +--* t542 long control expr N007 ( 22, 23) [000411] --CXG------- t411 = * CALL r2r_ind bool Enumerator[__Canon][System.__Canon].MoveNext $212 N009 ( 1, 1) [000418] -c---------- t418 = CNS_INT bool 0 $40 /--* t411 bool +--* t418 bool N010 ( 25, 27) [000409] J--XG--N-U-- * NE void $295 N011 ( 27, 29) [000419] ---XG------- * JTRUE void ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} N001 ( 0, 0) [000461] ------------ t461 = PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ t457 = PHI_ARG bool V07 loc1 u:10 $583 /--* t461 bool +--* t457 bool N003 ( 0, 0) [000431] ------------ t431 = * PHI bool /--* t431 bool N005 ( 0, 0) [000432] DA---------- * STORE_LCL_VAR bool V07 loc1 d:14 [000478] ------------ IL_OFFSET void IL offset: 0xea N001 ( 3, 2) [000125] ------------ t125 = LCL_VAR int V07 loc1 u:14 (last use) $584 /--* t125 int N003 ( 7, 5) [000127] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} N001 ( 0, 0) [000463] ------------ t463 = PHI_ARG bool V06 loc0 u:4 $584 N002 ( 0, 0) [000448] ------------ t448 = PHI_ARG bool V06 loc0 u:2 $41 /--* t463 bool +--* t448 bool N003 ( 0, 0) [000425] ------------ t425 = * PHI bool /--* t425 bool N005 ( 0, 0) [000426] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 [000479] ------------ IL_OFFSET void IL offset: 0xec N001 ( 3, 2) [000128] ------------ t128 = LCL_VAR int V06 loc0 u:3 (last use) $585 /--* t128 int N002 ( 4, 3) [000129] ------------ * RETURN int $214 ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} N001 ( 0, 0) [000460] ------------ t460 = PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ t458 = PHI_ARG bool V07 loc1 u:10 $583 /--* t460 bool +--* t458 bool N003 ( 0, 0) [000434] ------------ t434 = * PHI bool /--* t434 bool N005 ( 0, 0) [000435] DA---------- * STORE_LCL_VAR bool V07 loc1 d:11 [000480] ------------ IL_OFFSET void IL offset: 0x95 N003 ( 3, 10) [000067] ------------ t67 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t67 long N004 ( 5, 12) [000068] n----------- t68 = * IND long /--* t68 long [000543] ------------ t543 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000064] -------N---- t64 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t64 byref [000544] ------------ t544 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000545] ------------ t545 = CNS_INT(h) long 0xd1ffab1e ftn /--* t545 long N002 ( 5, 12) [000546] -c---------- t546 = * IND long REG NA /--* t543 long arg1 in rsi +--* t544 byref this in rdi +--* t546 long control expr N007 ( 22, 23) [000066] --CXG------- t66 = * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c /--* t66 ref N009 ( 26, 26) [000360] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp15 d:2 N012 ( 3, 2) [000361] ------------ t361 = LCL_VAR ref V26 tmp15 u:2 (last use) $16c /--* t361 ref [000547] ------------ t547 = * PUTARG_REG ref REG rdi N013 ( 3, 2) [000069] ------------ t69 = LCL_VAR ref V01 arg1 u:1 $81 /--* t69 ref [000548] ------------ t548 = * PUTARG_REG ref REG rsi N014 ( 3, 10) [000356] ------------ t356 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 /--* t356 long [000549] ------------ t549 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000550] ------------ t550 = CNS_INT(h) long 0xd1ffab1e ftn /--* t550 long N002 ( 5, 12) [000551] -c---------- t551 = * IND long REG NA /--* t547 ref this in rdi +--* t548 ref arg2 in rsi +--* t549 long arg1 in r11 +--* t551 long control expr N015 ( 55, 51) [000070] --CXG------- t70 = * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 /--* t70 struct N017 ( 59, 54) [000073] DA-XG------- * STORE_LCL_VAR struct V13 tmp2 d:2 N001 ( 3, 4) [000076] ------------ t76 = LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) $370 /--* t76 ref N003 ( 7, 7) [000078] DA---------- * STORE_LCL_VAR ref V10 loc4 d:2 [000481] ------------ IL_OFFSET void IL offset: 0xa9 N003 ( 3, 2) [000080] ------------ t80 = LCL_VAR ref V10 loc4 u:2 $370 /--* t80 ref [000552] ------------ t552 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000365] ------------ t365 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t365 long [000553] ------------ t553 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000554] ------------ t554 = CNS_INT(h) long 0xd1ffab1e ftn /--* t554 long N002 ( 5, 12) [000555] -c---------- t555 = * IND long REG NA /--* t552 ref this in rdi +--* t553 long arg1 in r11 +--* t555 long control expr N005 ( 26, 22) [000247] --CXG------- t247 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 N006 ( 1, 1) [000248] -c---------- t248 = CNS_INT int 4 $44 /--* t247 int +--* t248 int N007 ( 28, 24) [000249] J--XG--N---- * NE void $296 N008 ( 30, 26) [000228] ---XG------- * JTRUE void ------------ BB10 [0A9..0AA) -> BB19 (always), preds={BB09} succs={BB19} [000482] ------------ IL_OFFSET void IL offset: 0xa9 N003 ( 3, 2) [000237] ------------ t237 = LCL_VAR ref V10 loc4 u:2 $370 /--* t237 ref [000556] ------------ t556 = * PUTARG_REG ref REG rdi N004 ( 1, 1) [000238] ------------ t238 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t238 byref [000557] ------------ t557 = * PUTARG_REG byref REG rsi N001 ( 3, 10) [000558] ------------ t558 = CNS_INT(h) long 0xd1ffab1e ftn /--* t558 long N002 ( 5, 12) [000559] -c---------- t559 = * IND long REG NA /--* t556 ref arg0 in rdi +--* t557 byref arg1 in rsi +--* t559 long control expr N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void [000483] ------------ IL_OFFSET void IL offset: 0xa9 ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} [000484] ------------ IL_OFFSET void IL offset: 0x72 N006 ( 3, 2) [000130] ------------ t130 = LCL_VAR ref V00 arg0 u:1 (last use) $80 /--* t130 ref [000560] ------------ t560 = * PUTARG_REG ref REG rdi N007 ( 1, 1) [000131] ------------ t131 = LCL_VAR ref V02 arg2 u:1 $82 /--* t131 ref [000561] ------------ t561 = * PUTARG_REG ref REG rsi N008 ( 1, 1) [000132] ------------ t132 = LCL_VAR ref V03 arg3 u:1 $83 /--* t132 ref [000562] ------------ t562 = * PUTARG_REG ref REG rdx N009 ( 3, 2) [000133] ------------ t133 = LCL_VAR ref V04 arg4 u:1 $84 /--* t133 ref [000563] ------------ t563 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000134] ------------ t134 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t134 byref [000564] ------------ t564 = * PUTARG_REG byref REG r8 N001 ( 3, 10) [000565] ------------ t565 = CNS_INT(h) long 0xd1ffab1e ftn /--* t565 long N002 ( 5, 12) [000566] -c---------- t566 = * IND long REG NA /--* t560 ref arg0 in rdi +--* t561 ref arg1 in rsi +--* t562 ref arg2 in rdx +--* t563 ref arg3 in rcx +--* t564 byref arg4 in r8 +--* t566 long control expr N011 ( 23, 17) [000135] --CXG------- t135 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f N013 ( 1, 1) [000137] -c---------- t137 = CNS_INT bool 0 $40 /--* t135 bool +--* t137 bool N014 ( 26, 21) [000138] J--XG--N-U-- * EQ void $291 N015 ( 28, 23) [000139] ---XG------- * JTRUE void ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} [000485] ------------ IL_OFFSET void IL offset: 0xa9 N004 ( 1, 1) [000079] ------------ t79 = LCL_VAR ref V03 arg3 u:1 $83 /--* t79 ref [000567] ------------ t567 = * PUTARG_REG ref REG rdi N005 ( 3, 2) [000229] ------------ t229 = LCL_VAR ref V10 loc4 u:2 $370 /--* t229 ref [000568] ------------ t568 = * PUTARG_REG ref REG rsi N006 ( 1, 1) [000081] ------------ t81 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t81 byref [000569] ------------ t569 = * PUTARG_REG byref REG rdx N001 ( 3, 10) [000570] ------------ t570 = CNS_INT(h) long 0xd1ffab1e ftn /--* t570 long N002 ( 5, 12) [000571] -c---------- t571 = * IND long REG NA /--* t567 ref arg0 in rdi +--* t568 ref arg1 in rsi +--* t569 byref arg2 in rdx +--* t571 long control expr N007 ( 19, 12) [000230] --CXG------- t230 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 /--* t230 int N008 ( 20, 14) [000232] ---XG------- t232 = * CAST int <- bool <- int $297 /--* t232 int N010 ( 24, 17) [000234] DA-XG------- * STORE_LCL_VAR int V19 tmp8 d:2 N001 ( 3, 2) [000235] ------------ t235 = LCL_VAR int V19 tmp8 u:2 (last use) $297 N002 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 $40 /--* t235 int +--* t85 int N003 ( 5, 4) [000086] J------N---- * EQ void $298 N004 ( 7, 6) [000087] ------------ * JTRUE void ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB14,BB21} succs={BB16,BB09} N001 ( 0, 0) [000462] ------------ t462 = PHI_ARG bool V07 loc1 u:11 $586 N002 ( 0, 0) [000459] ------------ t459 = PHI_ARG bool V07 loc1 u:12 $40 /--* t462 bool +--* t459 bool N003 ( 0, 0) [000428] ------------ t428 = * PHI bool /--* t428 bool N005 ( 0, 0) [000429] DA---------- * STORE_LCL_VAR bool V07 loc1 d:13 [000486] ------------ IL_OFFSET void IL offset: 0xe1 N003 ( 3, 10) [000058] ------------ t58 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t58 long N004 ( 5, 12) [000059] n----------- t59 = * IND long /--* t59 long [000572] ------------ t572 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000055] -------N---- t55 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t55 byref [000573] ------------ t573 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000574] ------------ t574 = CNS_INT(h) long 0xd1ffab1e ftn /--* t574 long N002 ( 5, 12) [000575] -c---------- t575 = * IND long REG NA /--* t572 long arg1 in rsi +--* t573 byref this in rdi +--* t575 long control expr N007 ( 22, 23) [000057] --CXG------- t57 = * CALL r2r_ind bool Enumerator[__Canon][System.__Canon].MoveNext $21b N009 ( 1, 1) [000061] -c---------- t61 = CNS_INT bool 0 $40 /--* t57 bool +--* t61 bool N010 ( 25, 27) [000062] J--XG--N-U-- * NE void $29b N011 ( 27, 29) [000063] ---XG------- * JTRUE void ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} N004 ( 1, 1) [000143] ------------ t143 = LCL_VAR ref V02 arg2 u:1 $82 /--* t143 ref [000576] ------------ t576 = * PUTARG_REG ref REG rdi N005 ( 1, 1) [000144] ------------ t144 = LCL_VAR ref V03 arg3 u:1 $83 /--* t144 ref [000577] ------------ t577 = * PUTARG_REG ref REG rsi N006 ( 3, 2) [000145] ------------ t145 = LCL_VAR ref V04 arg4 u:1 $84 /--* t145 ref [000578] ------------ t578 = * PUTARG_REG ref REG rdx N001 ( 3, 10) [000579] ------------ t579 = CNS_INT(h) long 0xd1ffab1e ftn /--* t579 long N002 ( 5, 12) [000580] -c---------- t580 = * IND long REG NA /--* t576 ref arg0 in rdi +--* t577 ref arg1 in rsi +--* t578 ref arg2 in rdx +--* t580 long control expr N007 ( 19, 12) [000146] --CXG------- t146 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c N009 ( 1, 1) [000149] -c---------- t149 = CNS_INT bool 0 $40 /--* t146 bool +--* t149 bool N010 ( 22, 16) [000150] J--XG--N-U-- * NE void $28d N011 ( 24, 18) [000151] ---XG------- * JTRUE void ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} [000487] ------------ IL_OFFSET void IL offset: 0x68 N001 ( 1, 1) [000152] ------------ t152 = CNS_INT int 0 $40 /--* t152 int N003 ( 5, 4) [000154] DA---------- * STORE_LCL_VAR int V07 loc1 d:7 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB10} succs={BB20,BB21} [000488] ------------ IL_OFFSET void IL offset: 0xb5 N001 ( 3, 2) [000088] ------------ t88 = LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000089] -c---------- t89 = CNS_INT ref null $VN.Null /--* t88 ref +--* t89 ref N003 ( 5, 4) [000090] J------N---- * EQ void $284 N004 ( 7, 6) [000091] ------------ * JTRUE void ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} [000489] ------------ IL_OFFSET void IL offset: 0xb9 N002 ( 1, 1) [000098] ------------ t98 = CNS_INT long 2 $2c4 /--* t98 long [000581] ------------ t581 = * PUTARG_REG long REG rdi N001 ( 3, 10) [000582] ------------ t582 = CNS_INT(h) long 0xd1ffab1e ftn /--* t582 long N002 ( 5, 12) [000583] -c---------- t583 = * IND long REG NA /--* t581 long arg0 in rdi +--* t583 long control expr N003 ( 15, 7) [000099] --CXG------- t99 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 /--* t99 ref N005 ( 19, 10) [000101] DA-XG------- * STORE_LCL_VAR ref V14 tmp3 d:2 N001 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 0 $40 N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V14 tmp3 u:2 $385 /--* t103 ref [000504] -c---------- t504 = * LEA(b+8) ref /--* t504 ref N003 ( 5, 4) [000377] ---X-------- t377 = * IND int $299 /--* t377 int N005 ( 9, 7) [000465] DA-X-------- * STORE_LCL_VAR int V28 cse0 d:1 N006 ( 3, 2) [000466] ------------ t466 = LCL_VAR int V28 cse0 u:1 $299 /--* t104 int +--* t466 int N008 ( 17, 17) [000378] ---X-------- * ARR_BOUNDS_CHECK_Rng void $37c N009 ( 3, 2) [000375] ------------ t375 = LCL_VAR ref V14 tmp3 u:2 $385 /--* t375 ref N011 ( 4, 3) [000383] ------------ t383 = * LEA(b+16) byref N014 ( 1, 1) [000105] ------------ t105 = LCL_VAR ref V03 arg3 u:1 $83 /--* t383 byref +--* t105 ref [000490] -A-XG------- * STOREIND ref N001 ( 1, 1) [000109] -c---------- t109 = CNS_INT int 1 $41 N002 ( 3, 2) [000468] ------------ t468 = LCL_VAR int V28 cse0 u:1 (last use) $3c1 /--* t109 int +--* t468 int N003 ( 8, 10) [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void $645 N004 ( 3, 2) [000385] ------------ t385 = LCL_VAR ref V14 tmp3 u:2 $385 /--* t385 ref N006 ( 4, 3) [000393] ------------ t393 = * LEA(b+24) byref N009 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V10 loc4 u:2 (last use) $370 /--* t393 byref +--* t110 ref [000491] -A-XG------- * STOREIND ref N001 ( 3, 10) [000584] ------------ t584 = CNS_INT(h) long 0xd1ffab1e ftn /--* t584 long N002 ( 5, 12) [000585] -c---------- t585 = * IND long REG NA /--* t585 long control expr N001 ( 14, 5) [000259] --C--------- t259 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 /--* t259 ref N003 ( 18, 8) [000261] DA---------- * STORE_LCL_VAR ref V20 tmp9 d:2 N001 ( 3, 10) [000586] ------------ t586 = CNS_INT(h) long 0xd1ffab1e ftn /--* t586 long N002 ( 5, 12) [000587] -c---------- t587 = * IND long REG NA /--* t587 long control expr N002 ( 14, 5) [000252] H-CXG------- t252 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 /--* t252 byref N004 ( 15, 9) [000254] -c---------- t254 = * LEA(b+1048) byref /--* t254 byref N005 ( 17, 11) [000255] ---XG------- t255 = * IND ref /--* t255 ref N007 ( 21, 14) [000396] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp16 d:2 N010 ( 3, 2) [000397] ------------ t397 = LCL_VAR ref V27 tmp16 u:2 (last use) /--* t397 ref [000588] ------------ t588 = * PUTARG_REG ref REG rsi N011 ( 3, 2) [000262] ------------ t262 = LCL_VAR ref V20 tmp9 u:2 $647 /--* t262 ref [000589] ------------ t589 = * PUTARG_REG ref REG rdi N012 ( 3, 2) [000102] ------------ t102 = LCL_VAR ref V14 tmp3 u:2 (last use) $385 /--* t102 ref [000590] ------------ t590 = * PUTARG_REG ref REG rcx N013 ( 1, 4) [000256] ------------ t256 = CNS_INT int 0x7D2C $64 /--* t256 int [000591] ------------ t591 = * PUTARG_REG int REG rdx N001 ( 3, 10) [000592] ------------ t592 = CNS_INT(h) long 0xd1ffab1e ftn /--* t592 long N002 ( 5, 12) [000593] -c---------- t593 = * IND long REG NA /--* t588 ref arg1 in rsi +--* t589 ref this in rdi +--* t590 ref arg3 in rcx +--* t591 int arg2 in rdx +--* t593 long control expr N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N001 ( 1, 1) [000268] ------------ t268 = CNS_INT int 0 $40 [000594] Dc-----N---- t594 = LCL_VAR_ADDR byref V15 tmp4 /--* t594 byref +--* t268 int N003 ( 5, 4) [000269] sA---------- * STORE_BLK struct (init) (Unroll) N001 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V02 arg2 u:1 $82 /--* t96 ref N003 ( 5, 6) [000273] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:2->0[+0] Fseq[TypeParameter] N001 ( 3, 2) [000264] ------------ t264 = LCL_VAR ref V20 tmp9 u:2 (last use) $647 /--* t264 ref N003 ( 7, 7) [000277] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:3->0[+8] Fseq[DiagnosticInfo] [000492] ------------ IL_OFFSET void IL offset: 0xda N003 ( 3, 2) [000121] -c-----N---- t121 = LCL_VAR_ADDR byref V15 tmp4 u:4 (last use) /--* t121 byref N005 ( 9, 7) [000124] nc---------- t124 = * OBJ struct $507 /--* t124 struct [000595] ------------ * PUTARG_STK [+0x00] void (5 slots) (RepInstr) N006 ( 3, 2) [000095] ------------ t95 = LCL_VAR ref V04 arg4 u:1 $84 /--* t95 ref [000596] ------------ t596 = * PUTARG_REG ref REG rdi N007 ( 3, 10) [000401] ------------ t401 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t401 long [000597] ------------ t597 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000598] ------------ t598 = CNS_INT(h) long 0xd1ffab1e ftn /--* t598 long N002 ( 5, 12) [000599] -c---------- t599 = * IND long REG NA /--* t596 ref this in rdi +--* t597 long arg1 in r11 +--* t599 long control expr N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} [000493] ------------ IL_OFFSET void IL offset: 0xdf N001 ( 1, 1) [000092] ------------ t92 = CNS_INT int 0 $40 /--* t92 int N003 ( 5, 4) [000094] DA---------- * STORE_LCL_VAR int V07 loc1 d:12 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} [000494] ------------ IL_OFFSET void IL offset: 0x48 N004 ( 1, 1) [000155] ------------ t155 = LCL_VAR ref V02 arg2 u:1 $82 /--* t155 ref [000600] ------------ t600 = * PUTARG_REG ref REG rdi N005 ( 1, 1) [000156] ------------ t156 = LCL_VAR ref V03 arg3 u:1 $83 /--* t156 ref [000601] ------------ t601 = * PUTARG_REG ref REG rsi N006 ( 3, 2) [000157] ------------ t157 = LCL_VAR ref V04 arg4 u:1 $84 /--* t157 ref [000602] ------------ t602 = * PUTARG_REG ref REG rdx N001 ( 3, 10) [000603] ------------ t603 = CNS_INT(h) long 0xd1ffab1e ftn /--* t603 long N002 ( 5, 12) [000604] -c---------- t604 = * IND long REG NA /--* t600 ref arg0 in rdi +--* t601 ref arg1 in rsi +--* t602 ref arg2 in rdx +--* t604 long control expr N007 ( 19, 12) [000158] --CXG------- t158 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 N009 ( 1, 1) [000160] -c---------- t160 = CNS_INT bool 0 $40 /--* t158 bool +--* t160 bool N010 ( 22, 16) [000161] J--XG--N-U-- * NE void $289 N011 ( 24, 18) [000162] ---XG------- * JTRUE void ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} [000495] ------------ IL_OFFSET void IL offset: 0x53 N001 ( 1, 1) [000163] ------------ t163 = CNS_INT int 0 $40 /--* t163 int N003 ( 5, 4) [000165] DA---------- * STORE_LCL_VAR int V07 loc1 d:5 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} [000496] ------------ IL_OFFSET void IL offset: 0x8 N001 ( 1, 1) [000195] -c---------- t195 = CNS_INT int 1 $41 /--* t195 int N003 ( 5, 4) [000197] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} [000497] ------------ IL_OFFSET void IL offset: 0x19 N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000167] -c---------- t167 = CNS_INT ref null $VN.Null /--* t166 ref +--* t167 ref N003 ( 5, 4) [000168] J------N---- * EQ void $284 N004 ( 7, 6) [000169] ------------ * JTRUE void ------------ BB26 [01D..03E), preds={BB25} succs={BB27} [000498] ------------ IL_OFFSET void IL offset: 0x1d N002 ( 1, 1) [000176] ------------ t176 = CNS_INT long 1 $2c0 /--* t176 long [000605] ------------ t605 = * PUTARG_REG long REG rdi N001 ( 3, 10) [000606] ------------ t606 = CNS_INT(h) long 0xd1ffab1e ftn /--* t606 long N002 ( 5, 12) [000607] -c---------- t607 = * IND long REG NA /--* t605 long arg0 in rdi +--* t607 long control expr N003 ( 15, 7) [000177] --CXG------- t177 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 /--* t177 ref N005 ( 19, 10) [000179] DA-XG------- * STORE_LCL_VAR ref V16 tmp5 d:2 N001 ( 1, 1) [000182] -c---------- t182 = CNS_INT int 0 $40 N002 ( 3, 2) [000181] ------------ t181 = LCL_VAR ref V16 tmp5 u:2 $380 /--* t181 ref [000507] -c---------- t507 = * LEA(b+8) ref /--* t507 ref N003 ( 5, 4) [000291] -c-X-------- t291 = * IND int $285 /--* t182 int +--* t291 int N004 ( 10, 12) [000292] ---X-------- * ARR_BOUNDS_CHECK_Rng void $348 N005 ( 3, 2) [000289] ------------ t289 = LCL_VAR ref V16 tmp5 u:2 $380 /--* t289 ref N007 ( 4, 3) [000297] ------------ t297 = * LEA(b+16) byref N010 ( 1, 1) [000183] ------------ t183 = LCL_VAR ref V03 arg3 u:1 $83 /--* t297 byref +--* t183 ref [000499] -A-XG------- * STOREIND ref N001 ( 3, 10) [000608] ------------ t608 = CNS_INT(h) long 0xd1ffab1e ftn /--* t608 long N002 ( 5, 12) [000609] -c---------- t609 = * IND long REG NA /--* t609 long control expr N001 ( 14, 5) [000214] --C--------- t214 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c /--* t214 ref N003 ( 18, 8) [000216] DA---------- * STORE_LCL_VAR ref V18 tmp7 d:2 N001 ( 3, 10) [000610] ------------ t610 = CNS_INT(h) long 0xd1ffab1e ftn /--* t610 long N002 ( 5, 12) [000611] -c---------- t611 = * IND long REG NA /--* t611 long control expr N002 ( 14, 5) [000207] H-CXG------- t207 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 /--* t207 byref N004 ( 15, 9) [000209] -c---------- t209 = * LEA(b+1048) byref /--* t209 byref N005 ( 17, 11) [000210] ---XG------- t210 = * IND ref /--* t210 ref N007 ( 21, 14) [000300] DA-XG-----L- * STORE_LCL_VAR ref V24 tmp13 d:2 N010 ( 3, 2) [000301] ------------ t301 = LCL_VAR ref V24 tmp13 u:2 (last use) /--* t301 ref [000612] ------------ t612 = * PUTARG_REG ref REG rsi N011 ( 3, 2) [000217] ------------ t217 = LCL_VAR ref V18 tmp7 u:2 $34c /--* t217 ref [000613] ------------ t613 = * PUTARG_REG ref REG rdi N012 ( 3, 2) [000180] ------------ t180 = LCL_VAR ref V16 tmp5 u:2 (last use) $380 /--* t180 ref [000614] ------------ t614 = * PUTARG_REG ref REG rcx N013 ( 1, 4) [000211] ------------ t211 = CNS_INT int 0x7AA4 $49 /--* t211 int [000615] ------------ t615 = * PUTARG_REG int REG rdx N001 ( 3, 10) [000616] ------------ t616 = CNS_INT(h) long 0xd1ffab1e ftn /--* t616 long N002 ( 5, 12) [000617] -c---------- t617 = * IND long REG NA /--* t612 ref arg1 in rsi +--* t613 ref this in rdi +--* t614 ref arg3 in rcx +--* t615 int arg2 in rdx +--* t617 long control expr N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N004 ( 3, 3) [000189] ------------ t189 = LCL_VAR_ADDR byref V17 tmp6 $481 /--* t189 byref [000618] ------------ t618 = * PUTARG_REG byref REG rdi N005 ( 1, 1) [000174] ------------ t174 = LCL_VAR ref V02 arg2 u:1 $82 /--* t174 ref [000619] ------------ t619 = * PUTARG_REG ref REG rsi N006 ( 3, 2) [000219] ------------ t219 = LCL_VAR ref V18 tmp7 u:2 (last use) $34c /--* t219 ref [000620] ------------ t620 = * PUTARG_REG ref REG rdx N001 ( 3, 10) [000621] ------------ t621 = CNS_INT(h) long 0xd1ffab1e ftn /--* t621 long N002 ( 5, 12) [000622] -c---------- t622 = * IND long REG NA /--* t618 byref this in rdi +--* t619 ref arg1 in rsi +--* t620 ref arg2 in rdx +--* t622 long control expr N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void [000500] ------------ IL_OFFSET void IL offset: 0x39 N003 ( 3, 2) [000191] -c-----N---- t191 = LCL_VAR_ADDR byref V17 tmp6 /--* t191 byref N005 ( 9, 7) [000194] nc--G------- t194 = * OBJ struct /--* t194 struct [000623] ----G------- * PUTARG_STK [+0x00] void (5 slots) (RepInstr) N006 ( 3, 2) [000173] ------------ t173 = LCL_VAR ref V04 arg4 u:1 $84 /--* t173 ref [000624] ------------ t624 = * PUTARG_REG ref REG rdi N007 ( 3, 10) [000308] ------------ t308 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t308 long [000625] ------------ t625 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000626] ------------ t626 = CNS_INT(h) long 0xd1ffab1e ftn /--* t626 long N002 ( 5, 12) [000627] -c---------- t627 = * IND long REG NA /--* t624 ref this in rdi +--* t625 long arg1 in r11 +--* t627 long control expr N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} [000501] ------------ IL_OFFSET void IL offset: 0x3e N001 ( 1, 1) [000170] ------------ t170 = CNS_INT int 0 $40 /--* t170 int N003 ( 5, 4) [000172] DA---------- * STORE_LCL_VAR int V07 loc1 d:3 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} [000502] ------------ IL_OFFSET void IL offset: 0x80 N001 ( 1, 1) [000140] ------------ t140 = CNS_INT int 0 $40 /--* t140 int N003 ( 5, 4) [000142] DA---------- * STORE_LCL_VAR int V07 loc1 d:9 ------------ BB29 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [000505] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Trees before Calculate stack level slots ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC LIR BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC LIR BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC LIR BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC LIR BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC LIR BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC LIR BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC LIR BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC LIR BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC LIR BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB19 (always) i gcsafe bwd LIR BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC LIR BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC LIR BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC LIR BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC LIR BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe LIR BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC LIR BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC LIR BB19 [0017] 2 BB14,BB10 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC LIR BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC LIR BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC LIR BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC LIR BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC LIR BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC LIR BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC LIR BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC LIR BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC LIR BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC LIR BB29 [0038] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} N003 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V03 arg3 u:1 $83 /--* t0 ref [000508] ------------ t508 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000279] ------------ t279 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t279 long [000509] ------------ t509 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000510] ------------ t510 = CNS_INT(h) long 0xd1ffab1e ftn /--* t510 long N002 ( 5, 12) [000511] -c---------- t511 = * IND long REG NA /--* t508 ref this in rdi +--* t509 long arg1 in r11 +--* t511 long control expr N005 ( 24, 21) [000198] --CXG------- t198 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $200 N006 ( 1, 1) [000199] -c---------- t199 = CNS_INT int 4 $44 /--* t198 int +--* t199 int N007 ( 26, 23) [000200] J--XG--N---- * EQ void $280 N008 ( 28, 25) [000006] ---XG------- * JTRUE void ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} [000472] ------------ IL_OFFSET void IL offset: 0xf N001 ( 1, 1) [000007] -c---------- t7 = CNS_INT int 1 $41 /--* t7 int N003 ( 5, 4) [000009] DA---------- * STORE_LCL_VAR int V07 loc1 d:2 N004 ( 1, 1) [000010] ------------ t10 = LCL_VAR ref V03 arg3 u:1 $83 /--* t10 ref [000512] ------------ t512 = * PUTARG_REG ref REG rdi N005 ( 3, 10) [000284] ------------ t284 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 /--* t284 long [000513] ------------ t513 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000514] ------------ t514 = CNS_INT(h) long 0xd1ffab1e ftn /--* t514 long N002 ( 5, 12) [000515] -c---------- t515 = * IND long REG NA /--* t512 ref this in rdi +--* t513 long arg1 in r11 +--* t515 long control expr N006 ( 24, 21) [000202] --CXG------- t202 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType $204 /--* t202 int N007 ( 25, 23) [000203] ---XG------- t203 = * CAST int <- byte <- int $281 /--* t203 int [000516] ---XG------- t516 = * PUTARG_REG int REG rdi N001 ( 3, 10) [000517] ------------ t517 = CNS_INT(h) long 0xd1ffab1e ftn /--* t517 long N002 ( 5, 12) [000518] -c---------- t518 = * IND long REG NA /--* t516 int arg0 in rdi +--* t518 long control expr N008 ( 39, 29) [000204] --CXG------- t204 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType $205 N010 ( 1, 1) [000014] -c---------- t14 = CNS_INT bool 0 $40 /--* t204 bool +--* t14 bool N011 ( 42, 33) [000015] J--XG--N-U-- * NE void $283 N012 ( 44, 35) [000016] ---XG------- * JTRUE void ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} N001 ( 0, 0) [000450] ------------ t450 = PHI_ARG bool V07 loc1 u:3 $40 N002 ( 0, 0) [000449] ------------ t449 = PHI_ARG bool V07 loc1 u:2 $41 /--* t450 bool +--* t449 bool N003 ( 0, 0) [000446] ------------ t446 = * PHI bool /--* t446 bool N005 ( 0, 0) [000447] DA---------- * STORE_LCL_VAR bool V07 loc1 d:4 [000473] ------------ IL_OFFSET void IL offset: 0x40 N003 ( 1, 1) [000017] ------------ t17 = LCL_VAR ref V02 arg2 u:1 $82 /--* t17 ref [000519] ------------ t519 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000312] ------------ t312 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca /--* t312 long [000520] ------------ t520 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000521] ------------ t521 = CNS_INT(h) long 0xd1ffab1e ftn /--* t521 long N002 ( 5, 12) [000522] -c---------- t522 = * IND long REG NA /--* t519 ref this in rdi +--* t520 long arg1 in r11 +--* t522 long control expr N005 ( 24, 21) [000018] --CXG------- t18 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint $208 N007 ( 1, 1) [000020] -c---------- t20 = CNS_INT bool 0 $40 /--* t18 bool +--* t20 bool N008 ( 27, 25) [000021] J--XG--N-U-- * NE void $287 N009 ( 29, 27) [000022] ---XG------- * JTRUE void ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} N001 ( 0, 0) [000452] ------------ t452 = PHI_ARG bool V07 loc1 u:5 $40 N002 ( 0, 0) [000451] ------------ t451 = PHI_ARG bool V07 loc1 u:4 $580 /--* t452 bool +--* t451 bool N003 ( 0, 0) [000443] ------------ t443 = * PHI bool /--* t443 bool N005 ( 0, 0) [000444] DA---------- * STORE_LCL_VAR bool V07 loc1 d:6 [000474] ------------ IL_OFFSET void IL offset: 0x55 N003 ( 1, 1) [000023] ------------ t23 = LCL_VAR ref V02 arg2 u:1 $82 /--* t23 ref [000523] ------------ t523 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000319] ------------ t319 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc /--* t319 long [000524] ------------ t524 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000525] ------------ t525 = CNS_INT(h) long 0xd1ffab1e ftn /--* t525 long N002 ( 5, 12) [000526] -c---------- t526 = * IND long REG NA /--* t523 ref this in rdi +--* t524 long arg1 in r11 +--* t526 long control expr N005 ( 24, 21) [000024] --CXG------- t24 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint $20b N007 ( 1, 1) [000026] -c---------- t26 = CNS_INT bool 0 $40 /--* t24 bool +--* t26 bool N008 ( 27, 25) [000027] J--XG--N-U-- * NE void $28b N009 ( 29, 27) [000028] ---XG------- * JTRUE void ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} N001 ( 0, 0) [000454] ------------ t454 = PHI_ARG bool V07 loc1 u:7 $40 N002 ( 0, 0) [000453] ------------ t453 = PHI_ARG bool V07 loc1 u:6 $581 /--* t454 bool +--* t453 bool N003 ( 0, 0) [000440] ------------ t440 = * PHI bool /--* t440 bool N005 ( 0, 0) [000441] DA---------- * STORE_LCL_VAR bool V07 loc1 d:8 [000475] ------------ IL_OFFSET void IL offset: 0x6a N003 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V02 arg2 u:1 $82 /--* t29 ref [000527] ------------ t527 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000326] ------------ t326 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce /--* t326 long [000528] ------------ t528 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000529] ------------ t529 = CNS_INT(h) long 0xd1ffab1e ftn /--* t529 long N002 ( 5, 12) [000530] -c---------- t530 = * IND long REG NA /--* t527 ref this in rdi +--* t528 long arg1 in r11 +--* t530 long control expr N005 ( 24, 21) [000030] --CXG------- t30 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint $20e N007 ( 1, 1) [000032] -c---------- t32 = CNS_INT bool 0 $40 /--* t30 bool +--* t32 bool N008 ( 27, 25) [000033] J--XG--N-U-- * NE void $28f N009 ( 29, 27) [000034] ---XG------- * JTRUE void ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} N001 ( 0, 0) [000456] ------------ t456 = PHI_ARG bool V07 loc1 u:9 $40 N002 ( 0, 0) [000455] ------------ t455 = PHI_ARG bool V07 loc1 u:8 $582 /--* t456 bool +--* t455 bool N003 ( 0, 0) [000437] ------------ t437 = * PHI bool /--* t437 bool N005 ( 0, 0) [000438] DA---------- * STORE_LCL_VAR bool V07 loc1 d:10 N003 ( 1, 1) [000035] ------------ t35 = LCL_VAR ref V02 arg2 u:1 $82 /--* t35 ref [000531] ------------ t531 = * PUTARG_REG ref REG rdi N004 ( 1, 1) [000036] ------------ t36 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t36 byref [000532] ------------ t532 = * PUTARG_REG byref REG rsi N001 ( 3, 10) [000533] ------------ t533 = CNS_INT(h) long 0xd1ffab1e ftn /--* t533 long N002 ( 5, 12) [000534] -c---------- t534 = * IND long REG NA /--* t531 ref this in rdi +--* t532 byref arg1 in rsi +--* t534 long control expr N005 ( 16, 10) [000037] --CXG------- t37 = * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics $167 /--* t37 ref N007 ( 20, 13) [000042] DA-XG------- * STORE_LCL_VAR ref (AX) V23 tmp12 [000476] ------------ IL_OFFSET void IL offset: 0x8b N003 ( 3, 10) [000046] ------------ t46 = CNS_INT(h) long 0xd1ffab1e class $1d0 /--* t46 long N004 ( 5, 12) [000047] n----------- t47 = * IND long /--* t47 long [000535] ------------ t535 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000043] -------N---- t43 = LCL_VAR_ADDR byref V09 loc3 * ref V09.array (offs=0x00) -> V23 tmp12 /--* t43 byref [000536] ------------ t536 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000537] ------------ t537 = CNS_INT(h) long 0xd1ffab1e ftn /--* t537 long N002 ( 5, 12) [000538] -c---------- t538 = * IND long REG NA /--* t535 long arg1 in rsi +--* t536 byref this in rdi +--* t538 long control expr N007 ( 22, 23) [000045] --CXG------- t45 = * CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator,NA $501 /--* t45 struct N009 ( 26, 26) [000050] DA-XG------- * STORE_LCL_VAR struct(AX) V12 tmp1 N001 ( 3, 2) [000341] -------N---- t341 = LCL_VAR_ADDR byref V12 tmp1 /--* t341 byref N004 ( 3, 3) [000343] DA---------- * STORE_LCL_VAR byref V25 tmp14 d:2 N005 ( 1, 1) [000345] ------------ t345 = LCL_VAR byref V25 tmp14 u:2 Zero Fseq[_array] $487 /--* t345 byref N006 ( 3, 2) [000346] ---X-------- t346 = * IND ref /--* t346 ref N008 ( 7, 5) [000347] DA-XG------- * STORE_LCL_VAR ref (AX) V21 tmp10 N010 ( 1, 1) [000350] ------------ t350 = LCL_VAR byref V25 tmp14 u:2 (last use) $487 /--* t350 byref N012 ( 2, 2) [000352] -c---------- t352 = * LEA(b+8) byref /--* t352 byref N013 ( 4, 4) [000353] n----O------ t353 = * IND int /--* t353 int N015 ( 8, 7) [000354] DA--GO------ * STORE_LCL_VAR int (AX) V22 tmp11 [000477] ------------ IL_OFFSET void IL offset: 0xe1 N003 ( 3, 10) [000415] ------------ t415 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t415 long N004 ( 5, 12) [000414] n----------- t414 = * IND long /--* t414 long [000539] ------------ t539 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000417] ----G--N---- t417 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t417 byref [000540] ----G------- t540 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000541] ------------ t541 = CNS_INT(h) long 0xd1ffab1e ftn /--* t541 long N002 ( 5, 12) [000542] -c---------- t542 = * IND long REG NA /--* t539 long arg1 in rsi +--* t540 byref this in rdi +--* t542 long control expr N007 ( 22, 23) [000411] --CXG------- t411 = * CALL r2r_ind bool Enumerator[__Canon][System.__Canon].MoveNext $212 N009 ( 1, 1) [000418] -c---------- t418 = CNS_INT bool 0 $40 /--* t411 bool +--* t418 bool N010 ( 25, 27) [000409] J--XG--N-U-- * NE void $295 N011 ( 27, 29) [000419] ---XG------- * JTRUE void ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} N001 ( 0, 0) [000461] ------------ t461 = PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ t457 = PHI_ARG bool V07 loc1 u:10 $583 /--* t461 bool +--* t457 bool N003 ( 0, 0) [000431] ------------ t431 = * PHI bool /--* t431 bool N005 ( 0, 0) [000432] DA---------- * STORE_LCL_VAR bool V07 loc1 d:14 [000478] ------------ IL_OFFSET void IL offset: 0xea N001 ( 3, 2) [000125] ------------ t125 = LCL_VAR int V07 loc1 u:14 (last use) $584 /--* t125 int N003 ( 7, 5) [000127] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} N001 ( 0, 0) [000463] ------------ t463 = PHI_ARG bool V06 loc0 u:4 $584 N002 ( 0, 0) [000448] ------------ t448 = PHI_ARG bool V06 loc0 u:2 $41 /--* t463 bool +--* t448 bool N003 ( 0, 0) [000425] ------------ t425 = * PHI bool /--* t425 bool N005 ( 0, 0) [000426] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 [000479] ------------ IL_OFFSET void IL offset: 0xec N001 ( 3, 2) [000128] ------------ t128 = LCL_VAR int V06 loc0 u:3 (last use) $585 /--* t128 int N002 ( 4, 3) [000129] ------------ * RETURN int $214 ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} N001 ( 0, 0) [000460] ------------ t460 = PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ t458 = PHI_ARG bool V07 loc1 u:10 $583 /--* t460 bool +--* t458 bool N003 ( 0, 0) [000434] ------------ t434 = * PHI bool /--* t434 bool N005 ( 0, 0) [000435] DA---------- * STORE_LCL_VAR bool V07 loc1 d:11 [000480] ------------ IL_OFFSET void IL offset: 0x95 N003 ( 3, 10) [000067] ------------ t67 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t67 long N004 ( 5, 12) [000068] n----------- t68 = * IND long /--* t68 long [000543] ------------ t543 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000064] -------N---- t64 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t64 byref [000544] ------------ t544 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000545] ------------ t545 = CNS_INT(h) long 0xd1ffab1e ftn /--* t545 long N002 ( 5, 12) [000546] -c---------- t546 = * IND long REG NA /--* t543 long arg1 in rsi +--* t544 byref this in rdi +--* t546 long control expr N007 ( 22, 23) [000066] --CXG------- t66 = * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current $16c /--* t66 ref N009 ( 26, 26) [000360] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp15 d:2 N012 ( 3, 2) [000361] ------------ t361 = LCL_VAR ref V26 tmp15 u:2 (last use) $16c /--* t361 ref [000547] ------------ t547 = * PUTARG_REG ref REG rdi N013 ( 3, 2) [000069] ------------ t69 = LCL_VAR ref V01 arg1 u:1 $81 /--* t69 ref [000548] ------------ t548 = * PUTARG_REG ref REG rsi N014 ( 3, 10) [000356] ------------ t356 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 /--* t356 long [000549] ------------ t549 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000550] ------------ t550 = CNS_INT(h) long 0xd1ffab1e ftn /--* t550 long N002 ( 5, 12) [000551] -c---------- t551 = * IND long REG NA /--* t547 ref this in rdi +--* t548 ref arg2 in rsi +--* t549 long arg1 in r11 +--* t551 long control expr N015 ( 55, 51) [000070] --CXG------- t70 = * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters,NA $502 /--* t70 struct N017 ( 59, 54) [000073] DA-XG------- * STORE_LCL_VAR struct V13 tmp2 d:2 N001 ( 3, 4) [000076] ------------ t76 = LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] (last use) $370 /--* t76 ref N003 ( 7, 7) [000078] DA---------- * STORE_LCL_VAR ref V10 loc4 d:2 [000481] ------------ IL_OFFSET void IL offset: 0xa9 N003 ( 3, 2) [000080] ------------ t80 = LCL_VAR ref V10 loc4 u:2 $370 /--* t80 ref [000552] ------------ t552 = * PUTARG_REG ref REG rdi N004 ( 3, 10) [000365] ------------ t365 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t365 long [000553] ------------ t553 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000554] ------------ t554 = CNS_INT(h) long 0xd1ffab1e ftn /--* t554 long N002 ( 5, 12) [000555] -c---------- t555 = * IND long REG NA /--* t552 ref this in rdi +--* t553 long arg1 in r11 +--* t555 long control expr N005 ( 26, 22) [000247] --CXG------- t247 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind $215 N006 ( 1, 1) [000248] -c---------- t248 = CNS_INT int 4 $44 /--* t247 int +--* t248 int N007 ( 28, 24) [000249] J--XG--N---- * NE void $296 N008 ( 30, 26) [000228] ---XG------- * JTRUE void ------------ BB10 [0A9..0AA) -> BB19 (always), preds={BB09} succs={BB19} [000482] ------------ IL_OFFSET void IL offset: 0xa9 N003 ( 3, 2) [000237] ------------ t237 = LCL_VAR ref V10 loc4 u:2 $370 /--* t237 ref [000556] ------------ t556 = * PUTARG_REG ref REG rdi N004 ( 1, 1) [000238] ------------ t238 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t238 byref [000557] ------------ t557 = * PUTARG_REG byref REG rsi N001 ( 3, 10) [000558] ------------ t558 = CNS_INT(h) long 0xd1ffab1e ftn /--* t558 long N002 ( 5, 12) [000559] -c---------- t559 = * IND long REG NA /--* t556 ref arg0 in rdi +--* t557 byref arg1 in rsi +--* t559 long control expr N005 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics $VN.Void [000483] ------------ IL_OFFSET void IL offset: 0xa9 ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} [000484] ------------ IL_OFFSET void IL offset: 0x72 N006 ( 3, 2) [000130] ------------ t130 = LCL_VAR ref V00 arg0 u:1 (last use) $80 /--* t130 ref [000560] ------------ t560 = * PUTARG_REG ref REG rdi N007 ( 1, 1) [000131] ------------ t131 = LCL_VAR ref V02 arg2 u:1 $82 /--* t131 ref [000561] ------------ t561 = * PUTARG_REG ref REG rsi N008 ( 1, 1) [000132] ------------ t132 = LCL_VAR ref V03 arg3 u:1 $83 /--* t132 ref [000562] ------------ t562 = * PUTARG_REG ref REG rdx N009 ( 3, 2) [000133] ------------ t133 = LCL_VAR ref V04 arg4 u:1 $84 /--* t133 ref [000563] ------------ t563 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000134] ------------ t134 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t134 byref [000564] ------------ t564 = * PUTARG_REG byref REG r8 N001 ( 3, 10) [000565] ------------ t565 = CNS_INT(h) long 0xd1ffab1e ftn /--* t565 long N002 ( 5, 12) [000566] -c---------- t566 = * IND long REG NA /--* t560 ref arg0 in rdi +--* t561 ref arg1 in rsi +--* t562 ref arg2 in rdx +--* t563 ref arg3 in rcx +--* t564 byref arg4 in r8 +--* t566 long control expr N011 ( 23, 17) [000135] --CXG------- t135 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint $20f N013 ( 1, 1) [000137] -c---------- t137 = CNS_INT bool 0 $40 /--* t135 bool +--* t137 bool N014 ( 26, 21) [000138] J--XG--N-U-- * EQ void $291 N015 ( 28, 23) [000139] ---XG------- * JTRUE void ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} [000485] ------------ IL_OFFSET void IL offset: 0xa9 N004 ( 1, 1) [000079] ------------ t79 = LCL_VAR ref V03 arg3 u:1 $83 /--* t79 ref [000567] ------------ t567 = * PUTARG_REG ref REG rdi N005 ( 3, 2) [000229] ------------ t229 = LCL_VAR ref V10 loc4 u:2 $370 /--* t229 ref [000568] ------------ t568 = * PUTARG_REG ref REG rsi N006 ( 1, 1) [000081] ------------ t81 = LCL_VAR byref V05 arg5 u:1 $c0 /--* t81 byref [000569] ------------ t569 = * PUTARG_REG byref REG rdx N001 ( 3, 10) [000570] ------------ t570 = CNS_INT(h) long 0xd1ffab1e ftn /--* t570 long N002 ( 5, 12) [000571] -c---------- t571 = * IND long REG NA /--* t567 ref arg0 in rdi +--* t568 ref arg1 in rsi +--* t569 byref arg2 in rdx +--* t571 long control expr N007 ( 19, 12) [000230] --CXG------- t230 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion $216 /--* t230 int N008 ( 20, 14) [000232] ---XG------- t232 = * CAST int <- bool <- int $297 /--* t232 int N010 ( 24, 17) [000234] DA-XG------- * STORE_LCL_VAR int V19 tmp8 d:2 N001 ( 3, 2) [000235] ------------ t235 = LCL_VAR int V19 tmp8 u:2 (last use) $297 N002 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 $40 /--* t235 int +--* t85 int N003 ( 5, 4) [000086] J------N---- * EQ void $298 N004 ( 7, 6) [000087] ------------ * JTRUE void ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB14,BB21} succs={BB16,BB09} N001 ( 0, 0) [000462] ------------ t462 = PHI_ARG bool V07 loc1 u:11 $586 N002 ( 0, 0) [000459] ------------ t459 = PHI_ARG bool V07 loc1 u:12 $40 /--* t462 bool +--* t459 bool N003 ( 0, 0) [000428] ------------ t428 = * PHI bool /--* t428 bool N005 ( 0, 0) [000429] DA---------- * STORE_LCL_VAR bool V07 loc1 d:13 [000486] ------------ IL_OFFSET void IL offset: 0xe1 N003 ( 3, 10) [000058] ------------ t58 = CNS_INT(h) long 0xd1ffab1e class $1d1 /--* t58 long N004 ( 5, 12) [000059] n----------- t59 = * IND long /--* t59 long [000572] ------------ t572 = * PUTARG_REG long REG rsi N005 ( 3, 2) [000055] -------N---- t55 = LCL_VAR_ADDR byref V08 loc2 * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 /--* t55 byref [000573] ------------ t573 = * PUTARG_REG byref REG rdi N001 ( 3, 10) [000574] ------------ t574 = CNS_INT(h) long 0xd1ffab1e ftn /--* t574 long N002 ( 5, 12) [000575] -c---------- t575 = * IND long REG NA /--* t572 long arg1 in rsi +--* t573 byref this in rdi +--* t575 long control expr N007 ( 22, 23) [000057] --CXG------- t57 = * CALL r2r_ind bool Enumerator[__Canon][System.__Canon].MoveNext $21b N009 ( 1, 1) [000061] -c---------- t61 = CNS_INT bool 0 $40 /--* t57 bool +--* t61 bool N010 ( 25, 27) [000062] J--XG--N-U-- * NE void $29b N011 ( 27, 29) [000063] ---XG------- * JTRUE void ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} N004 ( 1, 1) [000143] ------------ t143 = LCL_VAR ref V02 arg2 u:1 $82 /--* t143 ref [000576] ------------ t576 = * PUTARG_REG ref REG rdi N005 ( 1, 1) [000144] ------------ t144 = LCL_VAR ref V03 arg3 u:1 $83 /--* t144 ref [000577] ------------ t577 = * PUTARG_REG ref REG rsi N006 ( 3, 2) [000145] ------------ t145 = LCL_VAR ref V04 arg4 u:1 $84 /--* t145 ref [000578] ------------ t578 = * PUTARG_REG ref REG rdx N001 ( 3, 10) [000579] ------------ t579 = CNS_INT(h) long 0xd1ffab1e ftn /--* t579 long N002 ( 5, 12) [000580] -c---------- t580 = * IND long REG NA /--* t576 ref arg0 in rdi +--* t577 ref arg1 in rsi +--* t578 ref arg2 in rdx +--* t580 long control expr N007 ( 19, 12) [000146] --CXG------- t146 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint $20c N009 ( 1, 1) [000149] -c---------- t149 = CNS_INT bool 0 $40 /--* t146 bool +--* t149 bool N010 ( 22, 16) [000150] J--XG--N-U-- * NE void $28d N011 ( 24, 18) [000151] ---XG------- * JTRUE void ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} [000487] ------------ IL_OFFSET void IL offset: 0x68 N001 ( 1, 1) [000152] ------------ t152 = CNS_INT int 0 $40 /--* t152 int N003 ( 5, 4) [000154] DA---------- * STORE_LCL_VAR int V07 loc1 d:7 ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB10} succs={BB20,BB21} [000488] ------------ IL_OFFSET void IL offset: 0xb5 N001 ( 3, 2) [000088] ------------ t88 = LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000089] -c---------- t89 = CNS_INT ref null $VN.Null /--* t88 ref +--* t89 ref N003 ( 5, 4) [000090] J------N---- * EQ void $284 N004 ( 7, 6) [000091] ------------ * JTRUE void ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} [000489] ------------ IL_OFFSET void IL offset: 0xb9 N002 ( 1, 1) [000098] ------------ t98 = CNS_INT long 2 $2c4 /--* t98 long [000581] ------------ t581 = * PUTARG_REG long REG rdi N001 ( 3, 10) [000582] ------------ t582 = CNS_INT(h) long 0xd1ffab1e ftn /--* t582 long N002 ( 5, 12) [000583] -c---------- t583 = * IND long REG NA /--* t581 long arg0 in rdi +--* t583 long control expr N003 ( 15, 7) [000099] --CXG------- t99 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $376 /--* t99 ref N005 ( 19, 10) [000101] DA-XG------- * STORE_LCL_VAR ref V14 tmp3 d:2 N001 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 0 $40 N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V14 tmp3 u:2 $385 /--* t103 ref [000504] -c---------- t504 = * LEA(b+8) ref /--* t504 ref N003 ( 5, 4) [000377] ---X-------- t377 = * IND int $299 /--* t377 int N005 ( 9, 7) [000465] DA-X-------- * STORE_LCL_VAR int V28 cse0 d:1 N006 ( 3, 2) [000466] ------------ t466 = LCL_VAR int V28 cse0 u:1 $299 /--* t104 int +--* t466 int N008 ( 17, 17) [000378] ---X-------- * ARR_BOUNDS_CHECK_Rng void $37c N009 ( 3, 2) [000375] ------------ t375 = LCL_VAR ref V14 tmp3 u:2 $385 /--* t375 ref N011 ( 4, 3) [000383] ------------ t383 = * LEA(b+16) byref N014 ( 1, 1) [000105] ------------ t105 = LCL_VAR ref V03 arg3 u:1 $83 /--* t383 byref +--* t105 ref [000490] -A-XG------- * STOREIND ref N001 ( 1, 1) [000109] -c---------- t109 = CNS_INT int 1 $41 N002 ( 3, 2) [000468] ------------ t468 = LCL_VAR int V28 cse0 u:1 (last use) $3c1 /--* t109 int +--* t468 int N003 ( 8, 10) [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void $645 N004 ( 3, 2) [000385] ------------ t385 = LCL_VAR ref V14 tmp3 u:2 $385 /--* t385 ref N006 ( 4, 3) [000393] ------------ t393 = * LEA(b+24) byref N009 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V10 loc4 u:2 (last use) $370 /--* t393 byref +--* t110 ref [000491] -A-XG------- * STOREIND ref N001 ( 3, 10) [000584] ------------ t584 = CNS_INT(h) long 0xd1ffab1e ftn /--* t584 long N002 ( 5, 12) [000585] -c---------- t585 = * IND long REG NA /--* t585 long control expr N001 ( 14, 5) [000259] --C--------- t259 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $647 /--* t259 ref N003 ( 18, 8) [000261] DA---------- * STORE_LCL_VAR ref V20 tmp9 d:2 N001 ( 3, 10) [000586] ------------ t586 = CNS_INT(h) long 0xd1ffab1e ftn /--* t586 long N002 ( 5, 12) [000587] -c---------- t587 = * IND long REG NA /--* t587 long control expr N002 ( 14, 5) [000252] H-CXG------- t252 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 /--* t252 byref N004 ( 15, 9) [000254] -c---------- t254 = * LEA(b+1048) byref /--* t254 byref N005 ( 17, 11) [000255] ---XG------- t255 = * IND ref /--* t255 ref N007 ( 21, 14) [000396] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp16 d:2 N010 ( 3, 2) [000397] ------------ t397 = LCL_VAR ref V27 tmp16 u:2 (last use) /--* t397 ref [000588] ------------ t588 = * PUTARG_REG ref REG rsi N011 ( 3, 2) [000262] ------------ t262 = LCL_VAR ref V20 tmp9 u:2 $647 /--* t262 ref [000589] ------------ t589 = * PUTARG_REG ref REG rdi N012 ( 3, 2) [000102] ------------ t102 = LCL_VAR ref V14 tmp3 u:2 (last use) $385 /--* t102 ref [000590] ------------ t590 = * PUTARG_REG ref REG rcx N013 ( 1, 4) [000256] ------------ t256 = CNS_INT int 0x7D2C $64 /--* t256 int [000591] ------------ t591 = * PUTARG_REG int REG rdx N001 ( 3, 10) [000592] ------------ t592 = CNS_INT(h) long 0xd1ffab1e ftn /--* t592 long N002 ( 5, 12) [000593] -c---------- t593 = * IND long REG NA /--* t588 ref arg1 in rsi +--* t589 ref this in rdi +--* t590 ref arg3 in rcx +--* t591 int arg2 in rdx +--* t593 long control expr N014 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N001 ( 1, 1) [000268] ------------ t268 = CNS_INT int 0 $40 [000594] Dc-----N---- t594 = LCL_VAR_ADDR byref V15 tmp4 /--* t594 byref +--* t268 int N003 ( 5, 4) [000269] sA---------- * STORE_BLK struct (init) (Unroll) N001 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V02 arg2 u:1 $82 /--* t96 ref N003 ( 5, 6) [000273] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:2->0[+0] Fseq[TypeParameter] N001 ( 3, 2) [000264] ------------ t264 = LCL_VAR ref V20 tmp9 u:2 (last use) $647 /--* t264 ref N003 ( 7, 7) [000277] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:3->0[+8] Fseq[DiagnosticInfo] [000492] ------------ IL_OFFSET void IL offset: 0xda N003 ( 3, 2) [000121] -c-----N---- t121 = LCL_VAR_ADDR byref V15 tmp4 u:4 (last use) /--* t121 byref N005 ( 9, 7) [000124] nc---------- t124 = * OBJ struct $507 /--* t124 struct [000595] ------------ * PUTARG_STK [+0x00] void (5 slots) (RepInstr) N006 ( 3, 2) [000095] ------------ t95 = LCL_VAR ref V04 arg4 u:1 $84 /--* t95 ref [000596] ------------ t596 = * PUTARG_REG ref REG rdi N007 ( 3, 10) [000401] ------------ t401 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t401 long [000597] ------------ t597 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000598] ------------ t598 = CNS_INT(h) long 0xd1ffab1e ftn /--* t598 long N002 ( 5, 12) [000599] -c---------- t599 = * IND long REG NA /--* t596 ref this in rdi +--* t597 long arg1 in r11 +--* t599 long control expr N008 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} [000493] ------------ IL_OFFSET void IL offset: 0xdf N001 ( 1, 1) [000092] ------------ t92 = CNS_INT int 0 $40 /--* t92 int N003 ( 5, 4) [000094] DA---------- * STORE_LCL_VAR int V07 loc1 d:12 ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} [000494] ------------ IL_OFFSET void IL offset: 0x48 N004 ( 1, 1) [000155] ------------ t155 = LCL_VAR ref V02 arg2 u:1 $82 /--* t155 ref [000600] ------------ t600 = * PUTARG_REG ref REG rdi N005 ( 1, 1) [000156] ------------ t156 = LCL_VAR ref V03 arg3 u:1 $83 /--* t156 ref [000601] ------------ t601 = * PUTARG_REG ref REG rsi N006 ( 3, 2) [000157] ------------ t157 = LCL_VAR ref V04 arg4 u:1 $84 /--* t157 ref [000602] ------------ t602 = * PUTARG_REG ref REG rdx N001 ( 3, 10) [000603] ------------ t603 = CNS_INT(h) long 0xd1ffab1e ftn /--* t603 long N002 ( 5, 12) [000604] -c---------- t604 = * IND long REG NA /--* t600 ref arg0 in rdi +--* t601 ref arg1 in rsi +--* t602 ref arg2 in rdx +--* t604 long control expr N007 ( 19, 12) [000158] --CXG------- t158 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint $209 N009 ( 1, 1) [000160] -c---------- t160 = CNS_INT bool 0 $40 /--* t158 bool +--* t160 bool N010 ( 22, 16) [000161] J--XG--N-U-- * NE void $289 N011 ( 24, 18) [000162] ---XG------- * JTRUE void ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} [000495] ------------ IL_OFFSET void IL offset: 0x53 N001 ( 1, 1) [000163] ------------ t163 = CNS_INT int 0 $40 /--* t163 int N003 ( 5, 4) [000165] DA---------- * STORE_LCL_VAR int V07 loc1 d:5 ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} [000496] ------------ IL_OFFSET void IL offset: 0x8 N001 ( 1, 1) [000195] -c---------- t195 = CNS_INT int 1 $41 /--* t195 int N003 ( 5, 4) [000197] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} [000497] ------------ IL_OFFSET void IL offset: 0x19 N001 ( 3, 2) [000166] ------------ t166 = LCL_VAR ref V04 arg4 u:1 $84 N002 ( 1, 1) [000167] -c---------- t167 = CNS_INT ref null $VN.Null /--* t166 ref +--* t167 ref N003 ( 5, 4) [000168] J------N---- * EQ void $284 N004 ( 7, 6) [000169] ------------ * JTRUE void ------------ BB26 [01D..03E), preds={BB25} succs={BB27} [000498] ------------ IL_OFFSET void IL offset: 0x1d N002 ( 1, 1) [000176] ------------ t176 = CNS_INT long 1 $2c0 /--* t176 long [000605] ------------ t605 = * PUTARG_REG long REG rdi N001 ( 3, 10) [000606] ------------ t606 = CNS_INT(h) long 0xd1ffab1e ftn /--* t606 long N002 ( 5, 12) [000607] -c---------- t607 = * IND long REG NA /--* t605 long arg0 in rdi +--* t607 long control expr N003 ( 15, 7) [000177] --CXG------- t177 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 $342 /--* t177 ref N005 ( 19, 10) [000179] DA-XG------- * STORE_LCL_VAR ref V16 tmp5 d:2 N001 ( 1, 1) [000182] -c---------- t182 = CNS_INT int 0 $40 N002 ( 3, 2) [000181] ------------ t181 = LCL_VAR ref V16 tmp5 u:2 $380 /--* t181 ref [000507] -c---------- t507 = * LEA(b+8) ref /--* t507 ref N003 ( 5, 4) [000291] -c-X-------- t291 = * IND int $285 /--* t182 int +--* t291 int N004 ( 10, 12) [000292] ---X-------- * ARR_BOUNDS_CHECK_Rng void $348 N005 ( 3, 2) [000289] ------------ t289 = LCL_VAR ref V16 tmp5 u:2 $380 /--* t289 ref N007 ( 4, 3) [000297] ------------ t297 = * LEA(b+16) byref N010 ( 1, 1) [000183] ------------ t183 = LCL_VAR ref V03 arg3 u:1 $83 /--* t297 byref +--* t183 ref [000499] -A-XG------- * STOREIND ref N001 ( 3, 10) [000608] ------------ t608 = CNS_INT(h) long 0xd1ffab1e ftn /--* t608 long N002 ( 5, 12) [000609] -c---------- t609 = * IND long REG NA /--* t609 long control expr N001 ( 14, 5) [000214] --C--------- t214 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW $34c /--* t214 ref N003 ( 18, 8) [000216] DA---------- * STORE_LCL_VAR ref V18 tmp7 d:2 N001 ( 3, 10) [000610] ------------ t610 = CNS_INT(h) long 0xd1ffab1e ftn /--* t610 long N002 ( 5, 12) [000611] -c---------- t611 = * IND long REG NA /--* t611 long control expr N002 ( 14, 5) [000207] H-CXG------- t207 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE $401 /--* t207 byref N004 ( 15, 9) [000209] -c---------- t209 = * LEA(b+1048) byref /--* t209 byref N005 ( 17, 11) [000210] ---XG------- t210 = * IND ref /--* t210 ref N007 ( 21, 14) [000300] DA-XG-----L- * STORE_LCL_VAR ref V24 tmp13 d:2 N010 ( 3, 2) [000301] ------------ t301 = LCL_VAR ref V24 tmp13 u:2 (last use) /--* t301 ref [000612] ------------ t612 = * PUTARG_REG ref REG rsi N011 ( 3, 2) [000217] ------------ t217 = LCL_VAR ref V18 tmp7 u:2 $34c /--* t217 ref [000613] ------------ t613 = * PUTARG_REG ref REG rdi N012 ( 3, 2) [000180] ------------ t180 = LCL_VAR ref V16 tmp5 u:2 (last use) $380 /--* t180 ref [000614] ------------ t614 = * PUTARG_REG ref REG rcx N013 ( 1, 4) [000211] ------------ t211 = CNS_INT int 0x7AA4 $49 /--* t211 int [000615] ------------ t615 = * PUTARG_REG int REG rdx N001 ( 3, 10) [000616] ------------ t616 = CNS_INT(h) long 0xd1ffab1e ftn /--* t616 long N002 ( 5, 12) [000617] -c---------- t617 = * IND long REG NA /--* t612 ref arg1 in rsi +--* t613 ref this in rdi +--* t614 ref arg3 in rcx +--* t615 int arg2 in rdx +--* t617 long control expr N014 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor $VN.Void N004 ( 3, 3) [000189] ------------ t189 = LCL_VAR_ADDR byref V17 tmp6 $481 /--* t189 byref [000618] ------------ t618 = * PUTARG_REG byref REG rdi N005 ( 1, 1) [000174] ------------ t174 = LCL_VAR ref V02 arg2 u:1 $82 /--* t174 ref [000619] ------------ t619 = * PUTARG_REG ref REG rsi N006 ( 3, 2) [000219] ------------ t219 = LCL_VAR ref V18 tmp7 u:2 (last use) $34c /--* t219 ref [000620] ------------ t620 = * PUTARG_REG ref REG rdx N001 ( 3, 10) [000621] ------------ t621 = CNS_INT(h) long 0xd1ffab1e ftn /--* t621 long N002 ( 5, 12) [000622] -c---------- t622 = * IND long REG NA /--* t618 byref this in rdi +--* t619 ref arg1 in rsi +--* t620 ref arg2 in rdx +--* t622 long control expr N007 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor $VN.Void [000500] ------------ IL_OFFSET void IL offset: 0x39 N003 ( 3, 2) [000191] -c-----N---- t191 = LCL_VAR_ADDR byref V17 tmp6 /--* t191 byref N005 ( 9, 7) [000194] nc--G------- t194 = * OBJ struct /--* t194 struct [000623] ----G------- * PUTARG_STK [+0x00] void (5 slots) (RepInstr) N006 ( 3, 2) [000173] ------------ t173 = LCL_VAR ref V04 arg4 u:1 $84 /--* t173 ref [000624] ------------ t624 = * PUTARG_REG ref REG rdi N007 ( 3, 10) [000308] ------------ t308 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t308 long [000625] ------------ t625 = * PUTARG_REG long REG r11 N001 ( 3, 10) [000626] ------------ t626 = CNS_INT(h) long 0xd1ffab1e ftn /--* t626 long N002 ( 5, 12) [000627] -c---------- t627 = * IND long REG NA /--* t624 ref this in rdi +--* t625 long arg1 in r11 +--* t627 long control expr N008 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add $VN.Void ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} [000501] ------------ IL_OFFSET void IL offset: 0x3e N001 ( 1, 1) [000170] ------------ t170 = CNS_INT int 0 $40 /--* t170 int N003 ( 5, 4) [000172] DA---------- * STORE_LCL_VAR int V07 loc1 d:3 ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} [000502] ------------ IL_OFFSET void IL offset: 0x80 N001 ( 1, 1) [000140] ------------ t140 = CNS_INT int 0 $40 /--* t140 int N003 ( 5, 4) [000142] DA---------- * STORE_LCL_VAR int V07 loc1 d:9 ------------ BB29 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [000505] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Calculate stack level slots Too many pushed arguments for an ESP based encoding, forcing an EBP frame *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {V03} {} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05} BB02 use def in out {V03} {V07} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05 V07} BB03 use def in out {V02} {} {V00 V01 V02 V03 V04 V05 V07} {V00 V01 V02 V03 V04 V05 V07} BB04 use def in out {V02} {} {V00 V01 V02 V03 V04 V05 V07} {V00 V01 V02 V03 V04 V05 V07} BB05 use def in out {V02} {} {V00 V01 V02 V03 V04 V05 V07} {V00 V01 V02 V03 V04 V05 V07} BB06 use def in out {V02 V05} {V25} {V01 V02 V03 V04 V05 V07} {V01 V02 V03 V04 V05 V07} BB07 use def in out {V07} {V06} {V07} {V06} BB08 use def in out {V06} {} {V06} {} BB09 use def in out {V01} {V10 V13 V26} {V01 V02 V03 V04 V05 V07} {V01 V02 V03 V04 V05 V07 V10} BB10 use def in out {V05 V10} {V19} {V01 V02 V03 V04 V05 V10} {V01 V02 V03 V04 V05 V10} BB12 use def in out {V00 V02 V03 V04 V05} {} {V00 V01 V02 V03 V04 V05 V07} {V01 V02 V03 V04 V05 V07} BB13 use def in out {} {} {V01 V02 V03 V04 V05 V07} {V01 V02 V03 V04 V05 V07} BB14 use def in out {V03 V05 V10} {V19} {V01 V02 V03 V04 V05 V07 V10} {V01 V02 V03 V04 V05 V07 V10} BB15 use def in out {} {} {V01 V02 V03 V04 V05 V07} {V01 V02 V03 V04 V05 V07} BB16 use def in out {} {} {V07} {V07} BB17 use def in out {V02 V03 V04} {} {V00 V01 V02 V03 V04 V05 V07} {V00 V01 V02 V03 V04 V05 V07} BB18 use def in out {} {V07} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05 V07} BB19 use def in out {V04} {} {V01 V02 V03 V04 V05 V10} {V01 V02 V03 V04 V05 V10} BB20 use def in out {V02 V03 V04 V10} {V14 V15 V20 V27 V28} {V01 V02 V03 V04 V05 V10} {V01 V02 V03 V04 V05} BB21 use def in out {} {V07} {V01 V02 V03 V04 V05} {V01 V02 V03 V04 V05 V07} BB22 use def in out {V02 V03 V04} {} {V00 V01 V02 V03 V04 V05 V07} {V00 V01 V02 V03 V04 V05 V07} BB23 use def in out {} {V07} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05 V07} BB24 use def in out {} {V06} {} {V06} BB25 use def in out {V04} {} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05} BB26 use def in out {V02 V03 V04} {V16 V18 V24} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05} BB27 use def in out {} {V07} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05 V07} BB28 use def in out {} {V07} {V01 V02 V03 V04 V05} {V01 V02 V03 V04 V05 V07} BB29 use def in out {} {} {} {} Interval 0: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 0: (V00) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: (V01) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: (V02) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 3: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 3: (V03) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 4: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 4: (V04) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 5: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 5: (V05) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 6: int RefPositions {} physReg:NA Preferences=[allInt] Interval 6: (V06) int RefPositions {} physReg:NA Preferences=[allInt] Interval 7: int RefPositions {} physReg:NA Preferences=[allInt] Interval 7: (V07) int RefPositions {} physReg:NA Preferences=[allInt] Interval 8: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 8: (V10) ref RefPositions {} physReg:NA Preferences=[allInt] Local V13 should not be enregistered because: it is a struct Interval 9: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 9: (V14) ref RefPositions {} physReg:NA Preferences=[allInt] Local V15 should not be enregistered because: it is a struct Interval 10: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 10: (V16) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 11: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 11: (V18) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 12: int RefPositions {} physReg:NA Preferences=[allInt] Interval 12: (V19) int RefPositions {} physReg:NA Preferences=[allInt] Interval 13: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 13: (V20) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 14: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 14: (V24) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 15: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 15: (V25) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 16: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 16: (V26) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 17: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 17: (V27) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 18: int RefPositions {} physReg:NA Preferences=[allInt] Interval 18: (V28) int RefPositions {} physReg:NA Preferences=[allInt] FP callee save candidate vars: None floatVarCount = 0; hasLoops = 1, singleExit = 1 TUPLE STYLE DUMP BEFORE LSRA New BlockSet epoch 5, # of blocks (including unused BB00): 30, bitset array size: 1 (short) LSRA Block Sequence: BB01( 1 ) BB02( 1 ) BB03( 1 ) BB04( 1 ) BB05( 1 ) BB06( 1 ) BB07( 1 ) BB08( 1 ) BB09( 0.29) BB10( 0.58) BB12( 0.01) BB13( 0.01) BB14( 0.29) BB15( 0.29) BB16( 0.15) BB17( 0.03) BB18( 0.01) BB19( 0.02) BB20( 0.02) BB21( 0.02) BB22( 0.01) BB23( 0 ) BB24( 0 ) BB25( 0 ) BB26( 0 ) BB27( 0 ) BB28( 0 ) BB29( 0 ) BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} ===== N003. V03(t0) N000. t508 = PUTARG_REG; t0 N004. t279 = CNS_INT(h) 0xd1ffab1e ftn N000. t509 = PUTARG_REG; t279 N001. t510 = CNS_INT(h) 0xd1ffab1e ftn N002. t511 = IND ; t510 N005. t198 = CALLV stub; t508,t509,t511 N006. CNS_INT 4 N007. EQ ; t198 N008. JTRUE BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} ===== N000. IL_OFFSET IL offset: 0xf N001. CNS_INT 1 N003. V07(t9) N004. V03(t10) N000. t512 = PUTARG_REG; t10 N005. t284 = CNS_INT(h) 0xd1ffab1e ftn N000. t513 = PUTARG_REG; t284 N001. t514 = CNS_INT(h) 0xd1ffab1e ftn N002. t515 = IND ; t514 N006. t202 = CALLV stub; t512,t513,t515 N007. t203 = CAST ; t202 N000. t516 = PUTARG_REG; t203 N001. t517 = CNS_INT(h) 0xd1ffab1e ftn N002. t518 = IND ; t517 N008. t204 = CALL r2r_ind; t516,t518 N010. CNS_INT 0 N011. NE ; t204 N012. JTRUE BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} ===== N000. IL_OFFSET IL offset: 0x40 N003. V02(t17) N000. t519 = PUTARG_REG; t17 N004. t312 = CNS_INT(h) 0xd1ffab1e ftn N000. t520 = PUTARG_REG; t312 N001. t521 = CNS_INT(h) 0xd1ffab1e ftn N002. t522 = IND ; t521 N005. t18 = CALLV stub; t519,t520,t522 N007. CNS_INT 0 N008. NE ; t18 N009. JTRUE BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} ===== N000. IL_OFFSET IL offset: 0x55 N003. V02(t23) N000. t523 = PUTARG_REG; t23 N004. t319 = CNS_INT(h) 0xd1ffab1e ftn N000. t524 = PUTARG_REG; t319 N001. t525 = CNS_INT(h) 0xd1ffab1e ftn N002. t526 = IND ; t525 N005. t24 = CALLV stub; t523,t524,t526 N007. CNS_INT 0 N008. NE ; t24 N009. JTRUE BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} ===== N000. IL_OFFSET IL offset: 0x6a N003. V02(t29) N000. t527 = PUTARG_REG; t29 N004. t326 = CNS_INT(h) 0xd1ffab1e ftn N000. t528 = PUTARG_REG; t326 N001. t529 = CNS_INT(h) 0xd1ffab1e ftn N002. t530 = IND ; t529 N005. t30 = CALLV stub; t527,t528,t530 N007. CNS_INT 0 N008. NE ; t30 N009. JTRUE BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} ===== N003. V02(t35) N000. t531 = PUTARG_REG; t35 N004. V05(t36) N000. t532 = PUTARG_REG; t36 N001. t533 = CNS_INT(h) 0xd1ffab1e ftn N002. t534 = IND ; t533 N005. t37 = CALL r2r_ind; t531,t532,t534 N007. V23 MEM; t37 N000. IL_OFFSET IL offset: 0x8b N003. t46 = CNS_INT(h) 0xd1ffab1e class N004. t47 = IND ; t46 N000. t535 = PUTARG_REG; t47 N005. t43 = LCL_VAR_ADDR V09 loc3 ref V09.array (offs=0x00) -> V23 tmp12 N000. t536 = PUTARG_REG; t43 N001. t537 = CNS_INT(h) 0xd1ffab1e ftn N002. t538 = IND ; t537 N007. t45 = CALL r2r_ind; t535,t536,t538 N009. V12 MEM; t45 N001. t341 = LCL_VAR_ADDR V12 tmp1 N004. V25(t343); t341 N005. V25(t345) N006. t346 = IND ; t345 N008. V21 MEM; t346 N010. V25(t350*) N012. t352 = LEA(b+8) ; t350* N013. t353 = IND ; t352 N015. V22 MEM; t353 N000. IL_OFFSET IL offset: 0xe1 N003. t415 = CNS_INT(h) 0xd1ffab1e class N004. t414 = IND ; t415 N000. t539 = PUTARG_REG; t414 N005. t417 = LCL_VAR_ADDR V08 loc2 ref V08._array (offs=0x00) -> V21 tmp10 int V08._index (offs=0x08) -> V22 tmp11 N000. t540 = PUTARG_REG; t417 N001. t541 = CNS_INT(h) 0xd1ffab1e ftn N002. t542 = IND ; t541 N007. t411 = CALL r2r_ind; t539,t540,t542 N009. CNS_INT 0 N010. NE ; t411 N011. JTRUE BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} ===== N000. IL_OFFSET IL offset: 0xea N001. V07(t125*) N003. V06(t127); t125* BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} ===== N000. IL_OFFSET IL offset: 0xec N001. V06(t128*) N002. RETURN ; t128* BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} ===== N000. IL_OFFSET IL offset: 0x95 N003. t67 = CNS_INT(h) 0xd1ffab1e class N004. t68 = IND ; t67 N000. t543 = PUTARG_REG; t68 N005. t64 = LCL_VAR_ADDR V08 loc2 ref V08._array (offs=0x00) -> V21 tmp10 int V08._index (offs=0x08) -> V22 tmp11 N000. t544 = PUTARG_REG; t64 N001. t545 = CNS_INT(h) 0xd1ffab1e ftn N002. t546 = IND ; t545 N007. t66 = CALL r2r_ind; t543,t544,t546 N009. V26(t360); t66 N012. V26(t361*) N000. t547 = PUTARG_REG; t361* N013. V01(t69) N000. t548 = PUTARG_REG; t69 N014. t356 = CNS_INT(h) 0xd1ffab1e ftn N000. t549 = PUTARG_REG; t356 N001. t550 = CNS_INT(h) 0xd1ffab1e ftn N002. t551 = IND ; t550 N015. t70 = CALLV stub; t547,t548,t549,t551 N017. V13 MEM; t70 N001. t76 = V13 MEM N003. V10(t78); t76 N000. IL_OFFSET IL offset: 0xa9 N003. V10(t80) N000. t552 = PUTARG_REG; t80 N004. t365 = CNS_INT(h) 0xd1ffab1e ftn N000. t553 = PUTARG_REG; t365 N001. t554 = CNS_INT(h) 0xd1ffab1e ftn N002. t555 = IND ; t554 N005. t247 = CALLV stub; t552,t553,t555 N006. CNS_INT 4 N007. NE ; t247 N008. JTRUE BB10 [0A9..0AA) -> BB19 (always), preds={BB09} succs={BB19} ===== N000. IL_OFFSET IL offset: 0xa9 N003. V10(t237) N000. t556 = PUTARG_REG; t237 N004. V05(t238) N000. t557 = PUTARG_REG; t238 N001. t558 = CNS_INT(h) 0xd1ffab1e ftn N002. t559 = IND ; t558 N005. CALL r2r_ind; t556,t557,t559 N000. IL_OFFSET IL offset: 0xa9 BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} ===== N000. IL_OFFSET IL offset: 0x72 N006. V00(t130*) N000. t560 = PUTARG_REG; t130* N007. V02(t131) N000. t561 = PUTARG_REG; t131 N008. V03(t132) N000. t562 = PUTARG_REG; t132 N009. V04(t133) N000. t563 = PUTARG_REG; t133 N010. V05(t134) N000. t564 = PUTARG_REG; t134 N001. t565 = CNS_INT(h) 0xd1ffab1e ftn N002. t566 = IND ; t565 N011. t135 = CALL r2r_ind; t560,t561,t562,t563,t564,t566 N013. CNS_INT 0 N014. EQ ; t135 N015. JTRUE BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ===== BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} ===== N000. IL_OFFSET IL offset: 0xa9 N004. V03(t79) N000. t567 = PUTARG_REG; t79 N005. V10(t229) N000. t568 = PUTARG_REG; t229 N006. V05(t81) N000. t569 = PUTARG_REG; t81 N001. t570 = CNS_INT(h) 0xd1ffab1e ftn N002. t571 = IND ; t570 N007. t230 = CALL r2r_ind; t567,t568,t569,t571 N008. t232 = CAST ; t230 N010. V19(t234); t232 N001. V19(t235*) N002. CNS_INT 0 N003. EQ ; t235* N004. JTRUE BB15 [0E1..0EA) -> BB09 (cond), preds={BB14,BB21} succs={BB16,BB09} ===== N000. IL_OFFSET IL offset: 0xe1 N003. t58 = CNS_INT(h) 0xd1ffab1e class N004. t59 = IND ; t58 N000. t572 = PUTARG_REG; t59 N005. t55 = LCL_VAR_ADDR V08 loc2 ref V08._array (offs=0x00) -> V21 tmp10 int V08._index (offs=0x08) -> V22 tmp11 N000. t573 = PUTARG_REG; t55 N001. t574 = CNS_INT(h) 0xd1ffab1e ftn N002. t575 = IND ; t574 N007. t57 = CALL r2r_ind; t572,t573,t575 N009. CNS_INT 0 N010. NE ; t57 N011. JTRUE BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ===== BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} ===== N004. V02(t143) N000. t576 = PUTARG_REG; t143 N005. V03(t144) N000. t577 = PUTARG_REG; t144 N006. V04(t145) N000. t578 = PUTARG_REG; t145 N001. t579 = CNS_INT(h) 0xd1ffab1e ftn N002. t580 = IND ; t579 N007. t146 = CALL r2r_ind; t576,t577,t578,t580 N009. CNS_INT 0 N010. NE ; t146 N011. JTRUE BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} ===== N000. IL_OFFSET IL offset: 0x68 N001. t152 = CNS_INT 0 N003. V07(t154); t152 BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB10} succs={BB20,BB21} ===== N000. IL_OFFSET IL offset: 0xb5 N001. V04(t88) N002. CNS_INT null N003. EQ ; t88 N004. JTRUE BB20 [0B9..0DF), preds={BB19} succs={BB21} ===== N000. IL_OFFSET IL offset: 0xb9 N002. t98 = CNS_INT 2 N000. t581 = PUTARG_REG; t98 N001. t582 = CNS_INT(h) 0xd1ffab1e ftn N002. t583 = IND ; t582 N003. t99 = CALL help r2r_ind; t581,t583 N005. V14(t101); t99 N001. CNS_INT 0 N002. V14(t103) N000. t504 = LEA(b+8) ; t103 N003. t377 = IND ; t504 N005. V28(t465); t377 N006. V28(t466) N008. ARR_BOUNDS_CHECK_Rng; t466 N009. V14(t375) N011. t383 = LEA(b+16); t375 N014. V03(t105) N000. STOREIND ; t383,t105 N001. CNS_INT 1 N002. V28(t468*) N003. ARR_BOUNDS_CHECK_Rng; t468* N004. V14(t385) N006. t393 = LEA(b+24); t385 N009. V10(t110*) N000. STOREIND ; t393,t110* N001. t584 = CNS_INT(h) 0xd1ffab1e ftn N002. t585 = IND ; t584 N001. t259 = CALL help r2r_ind; t585 N003. V20(t261); t259 N001. t586 = CNS_INT(h) 0xd1ffab1e ftn N002. t587 = IND ; t586 N002. t252 = CALL help r2r_ind; t587 N004. t254 = LEA(b+1048); t252 N005. t255 = IND ; t254 N007. V27(t396); t255 N010. V27(t397*) N000. t588 = PUTARG_REG; t397* N011. V20(t262) N000. t589 = PUTARG_REG; t262 N012. V14(t102*) N000. t590 = PUTARG_REG; t102* N013. t256 = CNS_INT 0x7D2C N000. t591 = PUTARG_REG; t256 N001. t592 = CNS_INT(h) 0xd1ffab1e ftn N002. t593 = IND ; t592 N014. CALL r2r_ind; t588,t589,t590,t591,t593 N001. t268 = CNS_INT 0 N000. LCL_VAR_ADDR V15 tmp4 N003. STORE_BLK; t268 N001. V02(t96) N003. V15 MEM; t96 N001. V20(t264*) N003. V15 MEM; t264* N000. IL_OFFSET IL offset: 0xda N003. LCL_VAR_ADDR V15 tmp4 u:4 (last use) N005. OBJ N000. PUTARG_STK [+0x00] N006. V04(t95) N000. t596 = PUTARG_REG; t95 N007. t401 = CNS_INT(h) 0xd1ffab1e ftn N000. t597 = PUTARG_REG; t401 N001. t598 = CNS_INT(h) 0xd1ffab1e ftn N002. t599 = IND ; t598 N008. CALLV stub; t596,t597,t599 BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} ===== N000. IL_OFFSET IL offset: 0xdf N001. t92 = CNS_INT 0 N003. V07(t94); t92 BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} ===== N000. IL_OFFSET IL offset: 0x48 N004. V02(t155) N000. t600 = PUTARG_REG; t155 N005. V03(t156) N000. t601 = PUTARG_REG; t156 N006. V04(t157) N000. t602 = PUTARG_REG; t157 N001. t603 = CNS_INT(h) 0xd1ffab1e ftn N002. t604 = IND ; t603 N007. t158 = CALL r2r_ind; t600,t601,t602,t604 N009. CNS_INT 0 N010. NE ; t158 N011. JTRUE BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} ===== N000. IL_OFFSET IL offset: 0x53 N001. t163 = CNS_INT 0 N003. V07(t165); t163 BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} ===== N000. IL_OFFSET IL offset: 0x8 N001. CNS_INT 1 N003. V06(t197) BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} ===== N000. IL_OFFSET IL offset: 0x19 N001. V04(t166) N002. CNS_INT null N003. EQ ; t166 N004. JTRUE BB26 [01D..03E), preds={BB25} succs={BB27} ===== N000. IL_OFFSET IL offset: 0x1d N002. t176 = CNS_INT 1 N000. t605 = PUTARG_REG; t176 N001. t606 = CNS_INT(h) 0xd1ffab1e ftn N002. t607 = IND ; t606 N003. t177 = CALL help r2r_ind; t605,t607 N005. V16(t179); t177 N001. CNS_INT 0 N002. V16(t181) N000. t507 = LEA(b+8) ; t181 N003. t291 = IND ; t507 N004. ARR_BOUNDS_CHECK_Rng; t291 N005. V16(t289) N007. t297 = LEA(b+16); t289 N010. V03(t183) N000. STOREIND ; t297,t183 N001. t608 = CNS_INT(h) 0xd1ffab1e ftn N002. t609 = IND ; t608 N001. t214 = CALL help r2r_ind; t609 N003. V18(t216); t214 N001. t610 = CNS_INT(h) 0xd1ffab1e ftn N002. t611 = IND ; t610 N002. t207 = CALL help r2r_ind; t611 N004. t209 = LEA(b+1048); t207 N005. t210 = IND ; t209 N007. V24(t300); t210 N010. V24(t301*) N000. t612 = PUTARG_REG; t301* N011. V18(t217) N000. t613 = PUTARG_REG; t217 N012. V16(t180*) N000. t614 = PUTARG_REG; t180* N013. t211 = CNS_INT 0x7AA4 N000. t615 = PUTARG_REG; t211 N001. t616 = CNS_INT(h) 0xd1ffab1e ftn N002. t617 = IND ; t616 N014. CALL r2r_ind; t612,t613,t614,t615,t617 N004. t189 = LCL_VAR_ADDR V17 tmp6 N000. t618 = PUTARG_REG; t189 N005. V02(t174) N000. t619 = PUTARG_REG; t174 N006. V18(t219*) N000. t620 = PUTARG_REG; t219* N001. t621 = CNS_INT(h) 0xd1ffab1e ftn N002. t622 = IND ; t621 N007. CALL r2r_ind; t618,t619,t620,t622 N000. IL_OFFSET IL offset: 0x39 N003. LCL_VAR_ADDR V17 tmp6 N005. OBJ N000. PUTARG_STK [+0x00] N006. V04(t173) N000. t624 = PUTARG_REG; t173 N007. t308 = CNS_INT(h) 0xd1ffab1e ftn N000. t625 = PUTARG_REG; t308 N001. t626 = CNS_INT(h) 0xd1ffab1e ftn N002. t627 = IND ; t626 N008. CALLV stub; t624,t625,t627 BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} ===== N000. IL_OFFSET IL offset: 0x3e N001. t170 = CNS_INT 0 N003. V07(t172); t170 BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} ===== N000. IL_OFFSET IL offset: 0x80 N001. t140 = CNS_INT 0 N003. V07(t142); t140 BB29 [???..???) (throw), preds={} succs={} ===== N001. CALL help buildIntervals second part ======== Int arg V02 in reg rdx BB00 regmask=[rdx] minReg=1 fixed> Int arg V03 in reg rcx BB00 regmask=[rcx] minReg=1 fixed> Int arg V05 in reg r9 BB00 regmask=[r9] minReg=1 fixed> Int arg V01 in reg rsi BB00 regmask=[rsi] minReg=1 fixed> Int arg V04 in reg r8 BB00 regmask=[r8] minReg=1 fixed> Int arg V00 in reg rdi BB00 regmask=[rdi] minReg=1 fixed> NEW BLOCK BB01 DefList: { } N003 ( 1, 1) [000000] ------------ * LCL_VAR ref V03 arg3 u:1 NA REG NA $83 DefList: { } N005 (???,???) [000508] ------------ * PUTARG_REG ref REG rdi BB01 regmask=[rdi] minReg=1> LCL_VAR BB01 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 19: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N005.t508. PUTARG_REG } N007 ( 3, 10) [000279] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 Interval 20: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[r11] minReg=1> CNS_INT BB01 regmask=[r11] minReg=1 fixed> DefList: { N005.t508. PUTARG_REG; N007.t279. CNS_INT } N009 (???,???) [000509] ------------ * PUTARG_REG long REG r11 BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> Interval 21: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[r11] minReg=1> PUTARG_REG BB01 regmask=[r11] minReg=1 fixed> DefList: { N005.t508. PUTARG_REG; N009.t509. PUTARG_REG } N011 ( 3, 10) [000510] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 22: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N005.t508. PUTARG_REG; N009.t509. PUTARG_REG; N011.t510. CNS_INT } N013 ( 5, 12) [000511] -c---------- * IND long REG NA Contained DefList: { N005.t508. PUTARG_REG; N009.t509. PUTARG_REG; N011.t510. CNS_INT } N015 ( 24, 21) [000198] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind REG NA $200 BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 23: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N015.t198. CALL } N017 ( 1, 1) [000199] -c---------- * CNS_INT int 4 REG NA $44 Contained DefList: { N015.t198. CALL } N019 ( 26, 23) [000200] J--XG--N---- * EQ void REG NA $280 BB01 regmask=[allInt] minReg=1 last> DefList: { } N021 ( 28, 25) [000006] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB01, liveout={V00 V01 V02 V03 V04 V05} ============================== use: {V03} def: {} NEW BLOCK BB02 Setting BB01 as the predecessor for determining incoming variable registers of BB02 DefList: { } N025 (???,???) [000472] ------------ * IL_OFFSET void IL offset: 0xf REG NA DefList: { } N027 ( 1, 1) [000007] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N029 ( 5, 4) [000009] DA---------- * STORE_LCL_VAR int V07 loc1 d:2 NA REG NA STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last> DefList: { } N031 ( 1, 1) [000010] ------------ * LCL_VAR ref V03 arg3 u:1 NA REG NA $83 DefList: { } N033 (???,???) [000512] ------------ * PUTARG_REG ref REG rdi BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 24: ref RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N033.t512. PUTARG_REG } N035 ( 3, 10) [000284] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 Interval 25: long RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[r11] minReg=1> CNS_INT BB02 regmask=[r11] minReg=1 fixed> DefList: { N033.t512. PUTARG_REG; N035.t284. CNS_INT } N037 (???,???) [000513] ------------ * PUTARG_REG long REG r11 BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> Interval 26: long RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[r11] minReg=1> PUTARG_REG BB02 regmask=[r11] minReg=1 fixed> DefList: { N033.t512. PUTARG_REG; N037.t513. PUTARG_REG } N039 ( 3, 10) [000514] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 27: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB02 regmask=[allInt] minReg=1> DefList: { N033.t512. PUTARG_REG; N037.t513. PUTARG_REG; N039.t514. CNS_INT } N041 ( 5, 12) [000515] -c---------- * IND long REG NA Contained DefList: { N033.t512. PUTARG_REG; N037.t513. PUTARG_REG; N039.t514. CNS_INT } N043 ( 24, 21) [000202] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType REG NA $204 BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[rax] minReg=1> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[r8] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r10] minReg=1> BB02 regmask=[r11] minReg=1> Interval 28: int RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> DefList: { N043.t202. CALL } N045 ( 25, 23) [000203] ---XG------- * CAST int <- byte <- int REG NA $281 BB02 regmask=[allInt] minReg=1 last> Interval 29: int RefPositions {} physReg:NA Preferences=[allInt] CAST BB02 regmask=[allInt] minReg=1> DefList: { N045.t203. CAST } N047 (???,???) [000516] ---XG------- * PUTARG_REG int REG rdi BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> Interval 30: int RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> DefList: { N047.t516. PUTARG_REG } N049 ( 3, 10) [000517] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 31: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB02 regmask=[allInt] minReg=1> DefList: { N047.t516. PUTARG_REG; N049.t517. CNS_INT } N051 ( 5, 12) [000518] -c---------- * IND long REG NA Contained DefList: { N047.t516. PUTARG_REG; N049.t517. CNS_INT } N053 ( 39, 29) [000204] --CXG------- * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType REG NA $205 BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[rax] minReg=1> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[r8] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r10] minReg=1> BB02 regmask=[r11] minReg=1> Interval 32: bool RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> DefList: { N053.t204. CALL } N055 ( 1, 1) [000014] -c---------- * CNS_INT bool 0 REG NA $40 Contained DefList: { N053.t204. CALL } N057 ( 42, 33) [000015] J--XG--N-U-- * NE void REG NA $283 BB02 regmask=[allInt] minReg=1 last> DefList: { } N059 ( 44, 35) [000016] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB02, liveout={V00 V01 V02 V03 V04 V05 V07} ============================== use: {V03} def: {V07} NEW BLOCK BB03 Setting BB02 as the predecessor for determining incoming variable registers of BB03 DefList: { } N063 (???,???) [000473] ------------ * IL_OFFSET void IL offset: 0x40 REG NA DefList: { } N065 ( 1, 1) [000017] ------------ * LCL_VAR ref V02 arg2 u:1 NA REG NA $82 DefList: { } N067 (???,???) [000519] ------------ * PUTARG_REG ref REG rdi BB03 regmask=[rdi] minReg=1> LCL_VAR BB03 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 33: ref RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rdi] minReg=1> PUTARG_REG BB03 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N067.t519. PUTARG_REG } N069 ( 3, 10) [000312] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca Interval 34: long RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[r11] minReg=1> CNS_INT BB03 regmask=[r11] minReg=1 fixed> DefList: { N067.t519. PUTARG_REG; N069.t312. CNS_INT } N071 (???,???) [000520] ------------ * PUTARG_REG long REG r11 BB03 regmask=[r11] minReg=1> BB03 regmask=[r11] minReg=1 last fixed> Interval 35: long RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[r11] minReg=1> PUTARG_REG BB03 regmask=[r11] minReg=1 fixed> DefList: { N067.t519. PUTARG_REG; N071.t520. PUTARG_REG } N073 ( 3, 10) [000521] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 36: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB03 regmask=[allInt] minReg=1> DefList: { N067.t519. PUTARG_REG; N071.t520. PUTARG_REG; N073.t521. CNS_INT } N075 ( 5, 12) [000522] -c---------- * IND long REG NA Contained DefList: { N067.t519. PUTARG_REG; N071.t520. PUTARG_REG; N073.t521. CNS_INT } N077 ( 24, 21) [000018] --CXG------- * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint REG NA $208 BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1 last fixed> BB03 regmask=[r11] minReg=1> BB03 regmask=[r11] minReg=1 last fixed> BB03 regmask=[allInt] minReg=1 last> BB03 regmask=[rax] minReg=1> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rsi] minReg=1> BB03 regmask=[rdi] minReg=1> BB03 regmask=[r8] minReg=1> BB03 regmask=[r9] minReg=1> BB03 regmask=[r10] minReg=1> BB03 regmask=[r11] minReg=1> Interval 37: bool RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> DefList: { N077.t18. CALL } N079 ( 1, 1) [000020] -c---------- * CNS_INT bool 0 REG NA $40 Contained DefList: { N077.t18. CALL } N081 ( 27, 25) [000021] J--XG--N-U-- * NE void REG NA $287 BB03 regmask=[allInt] minReg=1 last> DefList: { } N083 ( 29, 27) [000022] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB03, liveout={V00 V01 V02 V03 V04 V05 V07} ============================== use: {V02} def: {} NEW BLOCK BB04 Setting BB03 as the predecessor for determining incoming variable registers of BB04 DefList: { } N087 (???,???) [000474] ------------ * IL_OFFSET void IL offset: 0x55 REG NA DefList: { } N089 ( 1, 1) [000023] ------------ * LCL_VAR ref V02 arg2 u:1 NA REG NA $82 DefList: { } N091 (???,???) [000523] ------------ * PUTARG_REG ref REG rdi BB04 regmask=[rdi] minReg=1> LCL_VAR BB04 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 38: ref RefPositions {} physReg:NA Preferences=[allInt] BB04 regmask=[rdi] minReg=1> PUTARG_REG BB04 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N091.t523. PUTARG_REG } N093 ( 3, 10) [000319] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc Interval 39: long RefPositions {} physReg:NA Preferences=[allInt] BB04 regmask=[r11] minReg=1> CNS_INT BB04 regmask=[r11] minReg=1 fixed> DefList: { N091.t523. PUTARG_REG; N093.t319. CNS_INT } N095 (???,???) [000524] ------------ * PUTARG_REG long REG r11 BB04 regmask=[r11] minReg=1> BB04 regmask=[r11] minReg=1 last fixed> Interval 40: long RefPositions {} physReg:NA Preferences=[allInt] BB04 regmask=[r11] minReg=1> PUTARG_REG BB04 regmask=[r11] minReg=1 fixed> DefList: { N091.t523. PUTARG_REG; N095.t524. PUTARG_REG } N097 ( 3, 10) [000525] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 41: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB04 regmask=[allInt] minReg=1> DefList: { N091.t523. PUTARG_REG; N095.t524. PUTARG_REG; N097.t525. CNS_INT } N099 ( 5, 12) [000526] -c---------- * IND long REG NA Contained DefList: { N091.t523. PUTARG_REG; N095.t524. PUTARG_REG; N097.t525. CNS_INT } N101 ( 24, 21) [000024] --CXG------- * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint REG NA $20b BB04 regmask=[rdi] minReg=1> BB04 regmask=[rdi] minReg=1 last fixed> BB04 regmask=[r11] minReg=1> BB04 regmask=[r11] minReg=1 last fixed> BB04 regmask=[allInt] minReg=1 last> BB04 regmask=[rax] minReg=1> BB04 regmask=[rcx] minReg=1> BB04 regmask=[rdx] minReg=1> BB04 regmask=[rsi] minReg=1> BB04 regmask=[rdi] minReg=1> BB04 regmask=[r8] minReg=1> BB04 regmask=[r9] minReg=1> BB04 regmask=[r10] minReg=1> BB04 regmask=[r11] minReg=1> Interval 42: bool RefPositions {} physReg:NA Preferences=[allInt] BB04 regmask=[rax] minReg=1> CALL BB04 regmask=[rax] minReg=1 fixed> DefList: { N101.t24. CALL } N103 ( 1, 1) [000026] -c---------- * CNS_INT bool 0 REG NA $40 Contained DefList: { N101.t24. CALL } N105 ( 27, 25) [000027] J--XG--N-U-- * NE void REG NA $28b BB04 regmask=[allInt] minReg=1 last> DefList: { } N107 ( 29, 27) [000028] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB04, liveout={V00 V01 V02 V03 V04 V05 V07} ============================== use: {V02} def: {} NEW BLOCK BB05 Setting BB04 as the predecessor for determining incoming variable registers of BB05 DefList: { } N111 (???,???) [000475] ------------ * IL_OFFSET void IL offset: 0x6a REG NA DefList: { } N113 ( 1, 1) [000029] ------------ * LCL_VAR ref V02 arg2 u:1 NA REG NA $82 DefList: { } N115 (???,???) [000527] ------------ * PUTARG_REG ref REG rdi BB05 regmask=[rdi] minReg=1> LCL_VAR BB05 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 43: ref RefPositions {} physReg:NA Preferences=[allInt] BB05 regmask=[rdi] minReg=1> PUTARG_REG BB05 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N115.t527. PUTARG_REG } N117 ( 3, 10) [000326] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce Interval 44: long RefPositions {} physReg:NA Preferences=[allInt] BB05 regmask=[r11] minReg=1> CNS_INT BB05 regmask=[r11] minReg=1 fixed> DefList: { N115.t527. PUTARG_REG; N117.t326. CNS_INT } N119 (???,???) [000528] ------------ * PUTARG_REG long REG r11 BB05 regmask=[r11] minReg=1> BB05 regmask=[r11] minReg=1 last fixed> Interval 45: long RefPositions {} physReg:NA Preferences=[allInt] BB05 regmask=[r11] minReg=1> PUTARG_REG BB05 regmask=[r11] minReg=1 fixed> DefList: { N115.t527. PUTARG_REG; N119.t528. PUTARG_REG } N121 ( 3, 10) [000529] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 46: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB05 regmask=[allInt] minReg=1> DefList: { N115.t527. PUTARG_REG; N119.t528. PUTARG_REG; N121.t529. CNS_INT } N123 ( 5, 12) [000530] -c---------- * IND long REG NA Contained DefList: { N115.t527. PUTARG_REG; N119.t528. PUTARG_REG; N121.t529. CNS_INT } N125 ( 24, 21) [000030] --CXG------- * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint REG NA $20e BB05 regmask=[rdi] minReg=1> BB05 regmask=[rdi] minReg=1 last fixed> BB05 regmask=[r11] minReg=1> BB05 regmask=[r11] minReg=1 last fixed> BB05 regmask=[allInt] minReg=1 last> BB05 regmask=[rax] minReg=1> BB05 regmask=[rcx] minReg=1> BB05 regmask=[rdx] minReg=1> BB05 regmask=[rsi] minReg=1> BB05 regmask=[rdi] minReg=1> BB05 regmask=[r8] minReg=1> BB05 regmask=[r9] minReg=1> BB05 regmask=[r10] minReg=1> BB05 regmask=[r11] minReg=1> Interval 47: bool RefPositions {} physReg:NA Preferences=[allInt] BB05 regmask=[rax] minReg=1> CALL BB05 regmask=[rax] minReg=1 fixed> DefList: { N125.t30. CALL } N127 ( 1, 1) [000032] -c---------- * CNS_INT bool 0 REG NA $40 Contained DefList: { N125.t30. CALL } N129 ( 27, 25) [000033] J--XG--N-U-- * NE void REG NA $28f BB05 regmask=[allInt] minReg=1 last> DefList: { } N131 ( 29, 27) [000034] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB05, liveout={V00 V01 V02 V03 V04 V05 V07} ============================== use: {V02} def: {} NEW BLOCK BB06 Setting BB05 as the predecessor for determining incoming variable registers of BB06 DefList: { } N135 ( 1, 1) [000035] ------------ * LCL_VAR ref V02 arg2 u:1 NA REG NA $82 DefList: { } N137 (???,???) [000531] ------------ * PUTARG_REG ref REG rdi BB06 regmask=[rdi] minReg=1> LCL_VAR BB06 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 48: ref RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[rdi] minReg=1> PUTARG_REG BB06 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N137.t531. PUTARG_REG } N139 ( 1, 1) [000036] ------------ * LCL_VAR byref V05 arg5 u:1 NA REG NA $c0 DefList: { N137.t531. PUTARG_REG } N141 (???,???) [000532] ------------ * PUTARG_REG byref REG rsi BB06 regmask=[rsi] minReg=1> LCL_VAR BB06 regmask=[rsi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 49: byref RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[rsi] minReg=1> PUTARG_REG BB06 regmask=[rsi] minReg=1 fixed> Assigning related to DefList: { N137.t531. PUTARG_REG; N141.t532. PUTARG_REG } N143 ( 3, 10) [000533] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 50: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB06 regmask=[allInt] minReg=1> DefList: { N137.t531. PUTARG_REG; N141.t532. PUTARG_REG; N143.t533. CNS_INT } N145 ( 5, 12) [000534] -c---------- * IND long REG NA Contained DefList: { N137.t531. PUTARG_REG; N141.t532. PUTARG_REG; N143.t533. CNS_INT } N147 ( 16, 10) [000037] --CXG------- * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics REG NA $167 BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[rax] minReg=1> BB06 regmask=[rcx] minReg=1> BB06 regmask=[rdx] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rdi] minReg=1> BB06 regmask=[r8] minReg=1> BB06 regmask=[r9] minReg=1> BB06 regmask=[r10] minReg=1> BB06 regmask=[r11] minReg=1> Interval 51: ref RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[rax] minReg=1> CALL BB06 regmask=[rax] minReg=1 fixed> DefList: { N147.t37. CALL } N149 ( 20, 13) [000042] DA-XG------- * STORE_LCL_VAR ref (AX) V23 tmp12 NA REG NA BB06 regmask=[allInt] minReg=1 last> DefList: { } N151 (???,???) [000476] ------------ * IL_OFFSET void IL offset: 0x8b REG NA DefList: { } N153 ( 3, 10) [000046] ------------ * CNS_INT(h) long 0xd1ffab1e class REG NA $1d0 Interval 52: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB06 regmask=[allInt] minReg=1> DefList: { N153.t46. CNS_INT } N155 ( 5, 12) [000047] n----------- * IND long REG NA BB06 regmask=[allInt] minReg=1 last> Interval 53: long RefPositions {} physReg:NA Preferences=[allInt] IND BB06 regmask=[allInt] minReg=1> DefList: { N155.t47. IND } N157 (???,???) [000535] ------------ * PUTARG_REG long REG rsi BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> Interval 54: long RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[rsi] minReg=1> PUTARG_REG BB06 regmask=[rsi] minReg=1 fixed> DefList: { N157.t535. PUTARG_REG } N159 ( 3, 2) [000043] -------N---- * LCL_VAR_ADDR byref V09 loc3 NA * ref V09.array (offs=0x00) -> V23 tmp12 REG NA Interval 55: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB06 regmask=[allInt] minReg=1> DefList: { N157.t535. PUTARG_REG; N159.t43. LCL_VAR_ADDR } N161 (???,???) [000536] ------------ * PUTARG_REG byref REG rdi BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> Interval 56: byref RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[rdi] minReg=1> PUTARG_REG BB06 regmask=[rdi] minReg=1 fixed> DefList: { N157.t535. PUTARG_REG; N161.t536. PUTARG_REG } N163 ( 3, 10) [000537] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 57: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB06 regmask=[allInt] minReg=1> DefList: { N157.t535. PUTARG_REG; N161.t536. PUTARG_REG; N163.t537. CNS_INT } N165 ( 5, 12) [000538] -c---------- * IND long REG NA Contained DefList: { N157.t535. PUTARG_REG; N161.t536. PUTARG_REG; N163.t537. CNS_INT } N167 ( 22, 23) [000045] --CXG------- * CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator REG NA,NA $501 BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[rax] minReg=1> BB06 regmask=[rcx] minReg=1> BB06 regmask=[rdx] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rdi] minReg=1> BB06 regmask=[r8] minReg=1> BB06 regmask=[r9] minReg=1> BB06 regmask=[r10] minReg=1> BB06 regmask=[r11] minReg=1> Interval 58: ref RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[rax] minReg=1> CALL BB06 regmask=[rax] minReg=1 fixed> Interval 59: long RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[rdx] minReg=1> CALL BB06 regmask=[rdx] minReg=1 fixed> DefList: { N167.t45. CALL; N167.t45. CALL } N169 ( 26, 26) [000050] DA-XG------- * STORE_LCL_VAR struct(AX) V12 tmp1 NA REG NA BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[allInt] minReg=1 last> DefList: { } N171 ( 3, 2) [000341] -------N---- * LCL_VAR_ADDR byref V12 tmp1 NA REG NA Interval 60: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB06 regmask=[allInt] minReg=1> DefList: { N171.t341. LCL_VAR_ADDR } N173 ( 3, 3) [000343] DA---------- * STORE_LCL_VAR byref V25 tmp14 d:2 NA REG NA BB06 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last> DefList: { } N175 ( 1, 1) [000345] ------------ * LCL_VAR byref V25 tmp14 u:2 NA Zero Fseq[_array] REG NA $487 DefList: { } N177 ( 3, 2) [000346] ---X-------- * IND ref REG NA LCL_VAR BB06 regmask=[allInt] minReg=1 last> Interval 61: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB06 regmask=[allInt] minReg=1> DefList: { N177.t346. IND } N179 ( 7, 5) [000347] DA-XG------- * STORE_LCL_VAR ref (AX) V21 tmp10 NA REG NA BB06 regmask=[allInt] minReg=1 last> DefList: { } N181 ( 1, 1) [000350] ------------ * LCL_VAR byref V25 tmp14 u:2 NA (last use) REG NA $487 DefList: { } N183 ( 2, 2) [000352] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N185 ( 4, 4) [000353] n----O------ * IND int REG NA LCL_VAR BB06 regmask=[allInt] minReg=1 last> Interval 62: int RefPositions {} physReg:NA Preferences=[allInt] IND BB06 regmask=[allInt] minReg=1> DefList: { N185.t353. IND } N187 ( 8, 7) [000354] DA--GO------ * STORE_LCL_VAR int (AX) V22 tmp11 NA REG NA BB06 regmask=[allInt] minReg=1 last> DefList: { } N189 (???,???) [000477] ------------ * IL_OFFSET void IL offset: 0xe1 REG NA DefList: { } N191 ( 3, 10) [000415] ------------ * CNS_INT(h) long 0xd1ffab1e class REG NA $1d1 Interval 63: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB06 regmask=[allInt] minReg=1> DefList: { N191.t415. CNS_INT } N193 ( 5, 12) [000414] n----------- * IND long REG NA BB06 regmask=[allInt] minReg=1 last> Interval 64: long RefPositions {} physReg:NA Preferences=[allInt] IND BB06 regmask=[allInt] minReg=1> DefList: { N193.t414. IND } N195 (???,???) [000539] ------------ * PUTARG_REG long REG rsi BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> Interval 65: long RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[rsi] minReg=1> PUTARG_REG BB06 regmask=[rsi] minReg=1 fixed> DefList: { N195.t539. PUTARG_REG } N197 ( 3, 2) [000417] ----G--N---- * LCL_VAR_ADDR byref V08 loc2 NA * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 REG NA Interval 66: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB06 regmask=[allInt] minReg=1> DefList: { N195.t539. PUTARG_REG; N197.t417. LCL_VAR_ADDR } N199 (???,???) [000540] ----G------- * PUTARG_REG byref REG rdi BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> Interval 67: byref RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[rdi] minReg=1> PUTARG_REG BB06 regmask=[rdi] minReg=1 fixed> DefList: { N195.t539. PUTARG_REG; N199.t540. PUTARG_REG } N201 ( 3, 10) [000541] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 68: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB06 regmask=[allInt] minReg=1> DefList: { N195.t539. PUTARG_REG; N199.t540. PUTARG_REG; N201.t541. CNS_INT } N203 ( 5, 12) [000542] -c---------- * IND long REG NA Contained DefList: { N195.t539. PUTARG_REG; N199.t540. PUTARG_REG; N201.t541. CNS_INT } N205 ( 22, 23) [000411] --CXG------- * CALL r2r_ind bool Enumerator[__Canon][System.__Canon].MoveNext REG NA $212 BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[rax] minReg=1> BB06 regmask=[rcx] minReg=1> BB06 regmask=[rdx] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rdi] minReg=1> BB06 regmask=[r8] minReg=1> BB06 regmask=[r9] minReg=1> BB06 regmask=[r10] minReg=1> BB06 regmask=[r11] minReg=1> Interval 69: bool RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[rax] minReg=1> CALL BB06 regmask=[rax] minReg=1 fixed> DefList: { N205.t411. CALL } N207 ( 1, 1) [000418] -c---------- * CNS_INT bool 0 REG NA $40 Contained DefList: { N205.t411. CALL } N209 ( 25, 27) [000409] J--XG--N-U-- * NE void REG NA $295 BB06 regmask=[allInt] minReg=1 last> DefList: { } N211 ( 27, 29) [000419] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB06, liveout={V01 V02 V03 V04 V05 V07} ============================== use: {V02 V05} def: {V25} NEW BLOCK BB07 Setting BB06 as the predecessor for determining incoming variable registers of BB07 DefList: { } N215 (???,???) [000478] ------------ * IL_OFFSET void IL offset: 0xea REG NA DefList: { } N217 ( 3, 2) [000125] ------------ * LCL_VAR int V07 loc1 u:14 NA (last use) REG NA $584 DefList: { } N219 ( 7, 5) [000127] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 NA REG NA LCL_VAR BB07 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB07 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB07, liveout={V06} ============================== use: {V07} def: {V06} NEW BLOCK BB08 Setting BB07 as the predecessor for determining incoming variable registers of BB08 DefList: { } N223 (???,???) [000479] ------------ * IL_OFFSET void IL offset: 0xec REG NA DefList: { } N225 ( 3, 2) [000128] ------------ * LCL_VAR int V06 loc0 u:3 NA (last use) REG NA $585 DefList: { } N227 ( 4, 3) [000129] ------------ * RETURN int REG NA $214 BB08 regmask=[rax] minReg=1> LCL_VAR BB08 regmask=[rax] minReg=1 last fixed> CHECKING LAST USES for BB08, liveout={} ============================== use: {V06} def: {} NEW BLOCK BB09 Setting BB06 as the predecessor for determining incoming variable registers of BB09 DefList: { } N231 (???,???) [000480] ------------ * IL_OFFSET void IL offset: 0x95 REG NA DefList: { } N233 ( 3, 10) [000067] ------------ * CNS_INT(h) long 0xd1ffab1e class REG NA $1d1 Interval 70: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB09 regmask=[allInt] minReg=1> DefList: { N233.t67. CNS_INT } N235 ( 5, 12) [000068] n----------- * IND long REG NA BB09 regmask=[allInt] minReg=1 last> Interval 71: long RefPositions {} physReg:NA Preferences=[allInt] IND BB09 regmask=[allInt] minReg=1> DefList: { N235.t68. IND } N237 (???,???) [000543] ------------ * PUTARG_REG long REG rsi BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last fixed> Interval 72: long RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[rsi] minReg=1> PUTARG_REG BB09 regmask=[rsi] minReg=1 fixed> DefList: { N237.t543. PUTARG_REG } N239 ( 3, 2) [000064] -------N---- * LCL_VAR_ADDR byref V08 loc2 NA * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 REG NA Interval 73: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB09 regmask=[allInt] minReg=1> DefList: { N237.t543. PUTARG_REG; N239.t64. LCL_VAR_ADDR } N241 (???,???) [000544] ------------ * PUTARG_REG byref REG rdi BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> Interval 74: byref RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[rdi] minReg=1> PUTARG_REG BB09 regmask=[rdi] minReg=1 fixed> DefList: { N237.t543. PUTARG_REG; N241.t544. PUTARG_REG } N243 ( 3, 10) [000545] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 75: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB09 regmask=[allInt] minReg=1> DefList: { N237.t543. PUTARG_REG; N241.t544. PUTARG_REG; N243.t545. CNS_INT } N245 ( 5, 12) [000546] -c---------- * IND long REG NA Contained DefList: { N237.t543. PUTARG_REG; N241.t544. PUTARG_REG; N243.t545. CNS_INT } N247 ( 22, 23) [000066] --CXG------- * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current REG NA $16c BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last fixed> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[allInt] minReg=1 last> BB09 regmask=[rax] minReg=1> BB09 regmask=[rcx] minReg=1> BB09 regmask=[rdx] minReg=1> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rdi] minReg=1> BB09 regmask=[r8] minReg=1> BB09 regmask=[r9] minReg=1> BB09 regmask=[r10] minReg=1> BB09 regmask=[r11] minReg=1> Interval 76: ref RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> DefList: { N247.t66. CALL } N249 ( 26, 26) [000360] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp15 d:2 NA REG NA BB09 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB09 regmask=[allInt] minReg=1 last> DefList: { } N251 ( 3, 2) [000361] ------------ * LCL_VAR ref V26 tmp15 u:2 NA (last use) REG NA $16c DefList: { } N253 (???,???) [000547] ------------ * PUTARG_REG ref REG rdi BB09 regmask=[rdi] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 last fixed> Interval 77: ref RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[rdi] minReg=1> PUTARG_REG BB09 regmask=[rdi] minReg=1 fixed> DefList: { N253.t547. PUTARG_REG } N255 ( 3, 2) [000069] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $81 DefList: { N253.t547. PUTARG_REG } N257 (???,???) [000548] ------------ * PUTARG_REG ref REG rsi BB09 regmask=[rsi] minReg=1> LCL_VAR BB09 regmask=[rsi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 78: ref RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[rsi] minReg=1> PUTARG_REG BB09 regmask=[rsi] minReg=1 fixed> Assigning related to DefList: { N253.t547. PUTARG_REG; N257.t548. PUTARG_REG } N259 ( 3, 10) [000356] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 Interval 79: long RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[r11] minReg=1> CNS_INT BB09 regmask=[r11] minReg=1 fixed> DefList: { N253.t547. PUTARG_REG; N257.t548. PUTARG_REG; N259.t356. CNS_INT } N261 (???,???) [000549] ------------ * PUTARG_REG long REG r11 BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> Interval 80: long RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[r11] minReg=1> PUTARG_REG BB09 regmask=[r11] minReg=1 fixed> DefList: { N253.t547. PUTARG_REG; N257.t548. PUTARG_REG; N261.t549. PUTARG_REG } N263 ( 3, 10) [000550] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 81: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB09 regmask=[allInt] minReg=1> DefList: { N253.t547. PUTARG_REG; N257.t548. PUTARG_REG; N261.t549. PUTARG_REG; N263.t550. CNS_INT } N265 ( 5, 12) [000551] -c---------- * IND long REG NA Contained DefList: { N253.t547. PUTARG_REG; N257.t548. PUTARG_REG; N261.t549. PUTARG_REG; N263.t550. CNS_INT } N267 ( 55, 51) [000070] --CXG------- * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters REG NA,NA $502 BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[allInt] minReg=1 last> BB09 regmask=[rax] minReg=1> BB09 regmask=[rcx] minReg=1> BB09 regmask=[rdx] minReg=1> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rdi] minReg=1> BB09 regmask=[r8] minReg=1> BB09 regmask=[r9] minReg=1> BB09 regmask=[r10] minReg=1> BB09 regmask=[r11] minReg=1> Interval 82: ref RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> Interval 83: ref RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[rdx] minReg=1> CALL BB09 regmask=[rdx] minReg=1 fixed> DefList: { N267.t70. CALL; N267.t70. CALL } N269 ( 59, 54) [000073] DA-XG------- * STORE_LCL_VAR struct V13 tmp2 d:2 NA REG NA BB09 regmask=[allInt] minReg=1 last> BB09 regmask=[allInt] minReg=1 last> DefList: { } N271 ( 3, 4) [000076] ------------ * LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] NA (last use) REG NA $370 Interval 84: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB09 regmask=[allInt] minReg=1> DefList: { N271.t76. LCL_FLD } N273 ( 7, 7) [000078] DA---------- * STORE_LCL_VAR ref V10 loc4 d:2 NA REG NA BB09 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB09 regmask=[allInt] minReg=1 last> DefList: { } N275 (???,???) [000481] ------------ * IL_OFFSET void IL offset: 0xa9 REG NA DefList: { } N277 ( 3, 2) [000080] ------------ * LCL_VAR ref V10 loc4 u:2 NA REG NA $370 DefList: { } N279 (???,???) [000552] ------------ * PUTARG_REG ref REG rdi BB09 regmask=[rdi] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 85: ref RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[rdi] minReg=1> PUTARG_REG BB09 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N279.t552. PUTARG_REG } N281 ( 3, 10) [000365] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 Interval 86: long RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[r11] minReg=1> CNS_INT BB09 regmask=[r11] minReg=1 fixed> DefList: { N279.t552. PUTARG_REG; N281.t365. CNS_INT } N283 (???,???) [000553] ------------ * PUTARG_REG long REG r11 BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> Interval 87: long RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[r11] minReg=1> PUTARG_REG BB09 regmask=[r11] minReg=1 fixed> DefList: { N279.t552. PUTARG_REG; N283.t553. PUTARG_REG } N285 ( 3, 10) [000554] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 88: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB09 regmask=[allInt] minReg=1> DefList: { N279.t552. PUTARG_REG; N283.t553. PUTARG_REG; N285.t554. CNS_INT } N287 ( 5, 12) [000555] -c---------- * IND long REG NA Contained DefList: { N279.t552. PUTARG_REG; N283.t553. PUTARG_REG; N285.t554. CNS_INT } N289 ( 26, 22) [000247] --CXG------- * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind REG NA $215 BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[allInt] minReg=1 last> BB09 regmask=[rax] minReg=1> BB09 regmask=[rcx] minReg=1> BB09 regmask=[rdx] minReg=1> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rdi] minReg=1> BB09 regmask=[r8] minReg=1> BB09 regmask=[r9] minReg=1> BB09 regmask=[r10] minReg=1> BB09 regmask=[r11] minReg=1> Interval 89: int RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> DefList: { N289.t247. CALL } N291 ( 1, 1) [000248] -c---------- * CNS_INT int 4 REG NA $44 Contained DefList: { N289.t247. CALL } N293 ( 28, 24) [000249] J--XG--N---- * NE void REG NA $296 BB09 regmask=[allInt] minReg=1 last> DefList: { } N295 ( 30, 26) [000228] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB09, liveout={V01 V02 V03 V04 V05 V07 V10} ============================== use: {V01} def: {V10 V13 V26} NEW BLOCK BB10 Setting BB09 as the predecessor for determining incoming variable registers of BB10 DefList: { } N299 (???,???) [000482] ------------ * IL_OFFSET void IL offset: 0xa9 REG NA DefList: { } N301 ( 3, 2) [000237] ------------ * LCL_VAR ref V10 loc4 u:2 NA REG NA $370 DefList: { } N303 (???,???) [000556] ------------ * PUTARG_REG ref REG rdi BB10 regmask=[rdi] minReg=1> LCL_VAR BB10 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 90: ref RefPositions {} physReg:NA Preferences=[allInt] BB10 regmask=[rdi] minReg=1> PUTARG_REG BB10 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N303.t556. PUTARG_REG } N305 ( 1, 1) [000238] ------------ * LCL_VAR byref V05 arg5 u:1 NA REG NA $c0 DefList: { N303.t556. PUTARG_REG } N307 (???,???) [000557] ------------ * PUTARG_REG byref REG rsi BB10 regmask=[rsi] minReg=1> LCL_VAR BB10 regmask=[rsi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 91: byref RefPositions {} physReg:NA Preferences=[allInt] BB10 regmask=[rsi] minReg=1> PUTARG_REG BB10 regmask=[rsi] minReg=1 fixed> Assigning related to DefList: { N303.t556. PUTARG_REG; N307.t557. PUTARG_REG } N309 ( 3, 10) [000558] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 92: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB10 regmask=[allInt] minReg=1> DefList: { N303.t556. PUTARG_REG; N307.t557. PUTARG_REG; N309.t558. CNS_INT } N311 ( 5, 12) [000559] -c---------- * IND long REG NA Contained DefList: { N303.t556. PUTARG_REG; N307.t557. PUTARG_REG; N309.t558. CNS_INT } N313 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics REG NA $VN.Void BB10 regmask=[rdi] minReg=1> BB10 regmask=[rdi] minReg=1 last fixed> BB10 regmask=[rsi] minReg=1> BB10 regmask=[rsi] minReg=1 last fixed> BB10 regmask=[allInt] minReg=1 last> BB10 regmask=[rax] minReg=1> BB10 regmask=[rcx] minReg=1> BB10 regmask=[rdx] minReg=1> BB10 regmask=[rsi] minReg=1> BB10 regmask=[rdi] minReg=1> BB10 regmask=[r8] minReg=1> BB10 regmask=[r9] minReg=1> BB10 regmask=[r10] minReg=1> BB10 regmask=[r11] minReg=1> DefList: { } N315 (???,???) [000483] ------------ * IL_OFFSET void IL offset: 0xa9 REG NA CHECKING LAST USES for BB10, liveout={V01 V02 V03 V04 V05 V10} ============================== use: {V05 V10} def: {V19} NEW BLOCK BB12 Setting BB05 as the predecessor for determining incoming variable registers of BB12 DefList: { } N319 (???,???) [000484] ------------ * IL_OFFSET void IL offset: 0x72 REG NA DefList: { } N321 ( 3, 2) [000130] ------------ * LCL_VAR ref V00 arg0 u:1 NA (last use) REG NA $80 DefList: { } N323 (???,???) [000560] ------------ * PUTARG_REG ref REG rdi BB12 regmask=[rdi] minReg=1> LCL_VAR BB12 regmask=[rdi] minReg=1 last fixed> Interval 93: ref RefPositions {} physReg:NA Preferences=[allInt] BB12 regmask=[rdi] minReg=1> PUTARG_REG BB12 regmask=[rdi] minReg=1 fixed> DefList: { N323.t560. PUTARG_REG } N325 ( 1, 1) [000131] ------------ * LCL_VAR ref V02 arg2 u:1 NA REG NA $82 DefList: { N323.t560. PUTARG_REG } N327 (???,???) [000561] ------------ * PUTARG_REG ref REG rsi BB12 regmask=[rsi] minReg=1> LCL_VAR BB12 regmask=[rsi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 94: ref RefPositions {} physReg:NA Preferences=[allInt] BB12 regmask=[rsi] minReg=1> PUTARG_REG BB12 regmask=[rsi] minReg=1 fixed> Assigning related to DefList: { N323.t560. PUTARG_REG; N327.t561. PUTARG_REG } N329 ( 1, 1) [000132] ------------ * LCL_VAR ref V03 arg3 u:1 NA REG NA $83 DefList: { N323.t560. PUTARG_REG; N327.t561. PUTARG_REG } N331 (???,???) [000562] ------------ * PUTARG_REG ref REG rdx BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 95: ref RefPositions {} physReg:NA Preferences=[allInt] BB12 regmask=[rdx] minReg=1> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> Assigning related to DefList: { N323.t560. PUTARG_REG; N327.t561. PUTARG_REG; N331.t562. PUTARG_REG } N333 ( 3, 2) [000133] ------------ * LCL_VAR ref V04 arg4 u:1 NA REG NA $84 DefList: { N323.t560. PUTARG_REG; N327.t561. PUTARG_REG; N331.t562. PUTARG_REG } N335 (???,???) [000563] ------------ * PUTARG_REG ref REG rcx BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 96: ref RefPositions {} physReg:NA Preferences=[allInt] BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N323.t560. PUTARG_REG; N327.t561. PUTARG_REG; N331.t562. PUTARG_REG; N335.t563. PUTARG_REG } N337 ( 1, 1) [000134] ------------ * LCL_VAR byref V05 arg5 u:1 NA REG NA $c0 DefList: { N323.t560. PUTARG_REG; N327.t561. PUTARG_REG; N331.t562. PUTARG_REG; N335.t563. PUTARG_REG } N339 (???,???) [000564] ------------ * PUTARG_REG byref REG r8 BB12 regmask=[r8] minReg=1> LCL_VAR BB12 regmask=[r8] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 97: byref RefPositions {} physReg:NA Preferences=[allInt] BB12 regmask=[r8] minReg=1> PUTARG_REG BB12 regmask=[r8] minReg=1 fixed> Assigning related to DefList: { N323.t560. PUTARG_REG; N327.t561. PUTARG_REG; N331.t562. PUTARG_REG; N335.t563. PUTARG_REG; N339.t564. PUTARG_REG } N341 ( 3, 10) [000565] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 98: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB12 regmask=[allInt] minReg=1> DefList: { N323.t560. PUTARG_REG; N327.t561. PUTARG_REG; N331.t562. PUTARG_REG; N335.t563. PUTARG_REG; N339.t564. PUTARG_REG; N341.t565. CNS_INT } N343 ( 5, 12) [000566] -c---------- * IND long REG NA Contained DefList: { N323.t560. PUTARG_REG; N327.t561. PUTARG_REG; N331.t562. PUTARG_REG; N335.t563. PUTARG_REG; N339.t564. PUTARG_REG; N341.t565. CNS_INT } N345 ( 23, 17) [000135] --CXG------- * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint REG NA $20f BB12 regmask=[rdi] minReg=1> BB12 regmask=[rdi] minReg=1 last fixed> BB12 regmask=[rsi] minReg=1> BB12 regmask=[rsi] minReg=1 last fixed> BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[r8] minReg=1> BB12 regmask=[r8] minReg=1 last fixed> BB12 regmask=[allInt] minReg=1 last> BB12 regmask=[rax] minReg=1> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rdx] minReg=1> BB12 regmask=[rsi] minReg=1> BB12 regmask=[rdi] minReg=1> BB12 regmask=[r8] minReg=1> BB12 regmask=[r9] minReg=1> BB12 regmask=[r10] minReg=1> BB12 regmask=[r11] minReg=1> Interval 99: bool RefPositions {} physReg:NA Preferences=[allInt] BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> DefList: { N345.t135. CALL } N347 ( 1, 1) [000137] -c---------- * CNS_INT bool 0 REG NA $40 Contained DefList: { N345.t135. CALL } N349 ( 26, 21) [000138] J--XG--N-U-- * EQ void REG NA $291 BB12 regmask=[allInt] minReg=1 last> DefList: { } N351 ( 28, 23) [000139] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB12, liveout={V01 V02 V03 V04 V05 V07} ============================== use: {V00 V02 V03 V04 V05} def: {} NEW BLOCK BB13 Setting BB12 as the predecessor for determining incoming variable registers of BB13 CHECKING LAST USES for BB13, liveout={V01 V02 V03 V04 V05 V07} ============================== use: {} def: {} NEW BLOCK BB14 Setting BB09 as the predecessor for determining incoming variable registers of BB14 DefList: { } N357 (???,???) [000485] ------------ * IL_OFFSET void IL offset: 0xa9 REG NA DefList: { } N359 ( 1, 1) [000079] ------------ * LCL_VAR ref V03 arg3 u:1 NA REG NA $83 DefList: { } N361 (???,???) [000567] ------------ * PUTARG_REG ref REG rdi BB14 regmask=[rdi] minReg=1> LCL_VAR BB14 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 100: ref RefPositions {} physReg:NA Preferences=[allInt] BB14 regmask=[rdi] minReg=1> PUTARG_REG BB14 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N361.t567. PUTARG_REG } N363 ( 3, 2) [000229] ------------ * LCL_VAR ref V10 loc4 u:2 NA REG NA $370 DefList: { N361.t567. PUTARG_REG } N365 (???,???) [000568] ------------ * PUTARG_REG ref REG rsi BB14 regmask=[rsi] minReg=1> LCL_VAR BB14 regmask=[rsi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 101: ref RefPositions {} physReg:NA Preferences=[allInt] BB14 regmask=[rsi] minReg=1> PUTARG_REG BB14 regmask=[rsi] minReg=1 fixed> Assigning related to DefList: { N361.t567. PUTARG_REG; N365.t568. PUTARG_REG } N367 ( 1, 1) [000081] ------------ * LCL_VAR byref V05 arg5 u:1 NA REG NA $c0 DefList: { N361.t567. PUTARG_REG; N365.t568. PUTARG_REG } N369 (???,???) [000569] ------------ * PUTARG_REG byref REG rdx BB14 regmask=[rdx] minReg=1> LCL_VAR BB14 regmask=[rdx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 102: byref RefPositions {} physReg:NA Preferences=[allInt] BB14 regmask=[rdx] minReg=1> PUTARG_REG BB14 regmask=[rdx] minReg=1 fixed> Assigning related to DefList: { N361.t567. PUTARG_REG; N365.t568. PUTARG_REG; N369.t569. PUTARG_REG } N371 ( 3, 10) [000570] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 103: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB14 regmask=[allInt] minReg=1> DefList: { N361.t567. PUTARG_REG; N365.t568. PUTARG_REG; N369.t569. PUTARG_REG; N371.t570. CNS_INT } N373 ( 5, 12) [000571] -c---------- * IND long REG NA Contained DefList: { N361.t567. PUTARG_REG; N365.t568. PUTARG_REG; N369.t569. PUTARG_REG; N371.t570. CNS_INT } N375 ( 19, 12) [000230] --CXG------- * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion REG NA $216 BB14 regmask=[rdi] minReg=1> BB14 regmask=[rdi] minReg=1 last fixed> BB14 regmask=[rsi] minReg=1> BB14 regmask=[rsi] minReg=1 last fixed> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> BB14 regmask=[allInt] minReg=1 last> BB14 regmask=[rax] minReg=1> BB14 regmask=[rcx] minReg=1> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rsi] minReg=1> BB14 regmask=[rdi] minReg=1> BB14 regmask=[r8] minReg=1> BB14 regmask=[r9] minReg=1> BB14 regmask=[r10] minReg=1> BB14 regmask=[r11] minReg=1> Interval 104: int RefPositions {} physReg:NA Preferences=[allInt] BB14 regmask=[rax] minReg=1> CALL BB14 regmask=[rax] minReg=1 fixed> DefList: { N375.t230. CALL } N377 ( 20, 14) [000232] ---XG------- * CAST int <- bool <- int REG NA $297 BB14 regmask=[allInt] minReg=1 last> Interval 105: int RefPositions {} physReg:NA Preferences=[allInt] CAST BB14 regmask=[allInt] minReg=1> DefList: { N377.t232. CAST } N379 ( 24, 17) [000234] DA-XG------- * STORE_LCL_VAR int V19 tmp8 d:2 NA REG NA BB14 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N381 ( 3, 2) [000235] ------------ * LCL_VAR int V19 tmp8 u:2 NA (last use) REG NA $297 DefList: { } N383 ( 1, 1) [000085] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N385 ( 5, 4) [000086] J------N---- * EQ void REG NA $298 LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N387 ( 7, 6) [000087] ------------ * JTRUE void REG NA CHECKING LAST USES for BB14, liveout={V01 V02 V03 V04 V05 V07 V10} ============================== use: {V03 V05 V10} def: {V19} NEW BLOCK BB15 Setting BB14 as the predecessor for determining incoming variable registers of BB15 DefList: { } N391 (???,???) [000486] ------------ * IL_OFFSET void IL offset: 0xe1 REG NA DefList: { } N393 ( 3, 10) [000058] ------------ * CNS_INT(h) long 0xd1ffab1e class REG NA $1d1 Interval 106: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB15 regmask=[allInt] minReg=1> DefList: { N393.t58. CNS_INT } N395 ( 5, 12) [000059] n----------- * IND long REG NA BB15 regmask=[allInt] minReg=1 last> Interval 107: long RefPositions {} physReg:NA Preferences=[allInt] IND BB15 regmask=[allInt] minReg=1> DefList: { N395.t59. IND } N397 (???,???) [000572] ------------ * PUTARG_REG long REG rsi BB15 regmask=[rsi] minReg=1> BB15 regmask=[rsi] minReg=1 last fixed> Interval 108: long RefPositions {} physReg:NA Preferences=[allInt] BB15 regmask=[rsi] minReg=1> PUTARG_REG BB15 regmask=[rsi] minReg=1 fixed> DefList: { N397.t572. PUTARG_REG } N399 ( 3, 2) [000055] -------N---- * LCL_VAR_ADDR byref V08 loc2 NA * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 REG NA Interval 109: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB15 regmask=[allInt] minReg=1> DefList: { N397.t572. PUTARG_REG; N399.t55. LCL_VAR_ADDR } N401 (???,???) [000573] ------------ * PUTARG_REG byref REG rdi BB15 regmask=[rdi] minReg=1> BB15 regmask=[rdi] minReg=1 last fixed> Interval 110: byref RefPositions {} physReg:NA Preferences=[allInt] BB15 regmask=[rdi] minReg=1> PUTARG_REG BB15 regmask=[rdi] minReg=1 fixed> DefList: { N397.t572. PUTARG_REG; N401.t573. PUTARG_REG } N403 ( 3, 10) [000574] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 111: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB15 regmask=[allInt] minReg=1> DefList: { N397.t572. PUTARG_REG; N401.t573. PUTARG_REG; N403.t574. CNS_INT } N405 ( 5, 12) [000575] -c---------- * IND long REG NA Contained DefList: { N397.t572. PUTARG_REG; N401.t573. PUTARG_REG; N403.t574. CNS_INT } N407 ( 22, 23) [000057] --CXG------- * CALL r2r_ind bool Enumerator[__Canon][System.__Canon].MoveNext REG NA $21b BB15 regmask=[rsi] minReg=1> BB15 regmask=[rsi] minReg=1 last fixed> BB15 regmask=[rdi] minReg=1> BB15 regmask=[rdi] minReg=1 last fixed> BB15 regmask=[allInt] minReg=1 last> BB15 regmask=[rax] minReg=1> BB15 regmask=[rcx] minReg=1> BB15 regmask=[rdx] minReg=1> BB15 regmask=[rsi] minReg=1> BB15 regmask=[rdi] minReg=1> BB15 regmask=[r8] minReg=1> BB15 regmask=[r9] minReg=1> BB15 regmask=[r10] minReg=1> BB15 regmask=[r11] minReg=1> Interval 112: bool RefPositions {} physReg:NA Preferences=[allInt] BB15 regmask=[rax] minReg=1> CALL BB15 regmask=[rax] minReg=1 fixed> DefList: { N407.t57. CALL } N409 ( 1, 1) [000061] -c---------- * CNS_INT bool 0 REG NA $40 Contained DefList: { N407.t57. CALL } N411 ( 25, 27) [000062] J--XG--N-U-- * NE void REG NA $29b BB15 regmask=[allInt] minReg=1 last> DefList: { } N413 ( 27, 29) [000063] ---XG------- * JTRUE void REG NA Exposed uses: BB15 regmask=[allInt] minReg=1> V02 BB15 regmask=[allInt] minReg=1> V03 BB15 regmask=[allInt] minReg=1> V05 BB15 regmask=[allInt] minReg=1> V01 BB15 regmask=[allInt] minReg=1> V04 CHECKING LAST USES for BB15, liveout={V01 V02 V03 V04 V05 V07} ============================== use: {} def: {} NEW BLOCK BB16 Setting BB06 as the predecessor for determining incoming variable registers of BB16 CHECKING LAST USES for BB16, liveout={V07} ============================== use: {} def: {} NEW BLOCK BB17 Setting BB04 as the predecessor for determining incoming variable registers of BB17 DefList: { } N419 ( 1, 1) [000143] ------------ * LCL_VAR ref V02 arg2 u:1 NA REG NA $82 DefList: { } N421 (???,???) [000576] ------------ * PUTARG_REG ref REG rdi BB17 regmask=[rdi] minReg=1> LCL_VAR BB17 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 113: ref RefPositions {} physReg:NA Preferences=[allInt] BB17 regmask=[rdi] minReg=1> PUTARG_REG BB17 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N421.t576. PUTARG_REG } N423 ( 1, 1) [000144] ------------ * LCL_VAR ref V03 arg3 u:1 NA REG NA $83 DefList: { N421.t576. PUTARG_REG } N425 (???,???) [000577] ------------ * PUTARG_REG ref REG rsi BB17 regmask=[rsi] minReg=1> LCL_VAR BB17 regmask=[rsi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 114: ref RefPositions {} physReg:NA Preferences=[allInt] BB17 regmask=[rsi] minReg=1> PUTARG_REG BB17 regmask=[rsi] minReg=1 fixed> Assigning related to DefList: { N421.t576. PUTARG_REG; N425.t577. PUTARG_REG } N427 ( 3, 2) [000145] ------------ * LCL_VAR ref V04 arg4 u:1 NA REG NA $84 DefList: { N421.t576. PUTARG_REG; N425.t577. PUTARG_REG } N429 (???,???) [000578] ------------ * PUTARG_REG ref REG rdx BB17 regmask=[rdx] minReg=1> LCL_VAR BB17 regmask=[rdx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 115: ref RefPositions {} physReg:NA Preferences=[allInt] BB17 regmask=[rdx] minReg=1> PUTARG_REG BB17 regmask=[rdx] minReg=1 fixed> Assigning related to DefList: { N421.t576. PUTARG_REG; N425.t577. PUTARG_REG; N429.t578. PUTARG_REG } N431 ( 3, 10) [000579] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 116: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB17 regmask=[allInt] minReg=1> DefList: { N421.t576. PUTARG_REG; N425.t577. PUTARG_REG; N429.t578. PUTARG_REG; N431.t579. CNS_INT } N433 ( 5, 12) [000580] -c---------- * IND long REG NA Contained DefList: { N421.t576. PUTARG_REG; N425.t577. PUTARG_REG; N429.t578. PUTARG_REG; N431.t579. CNS_INT } N435 ( 19, 12) [000146] --CXG------- * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint REG NA $20c BB17 regmask=[rdi] minReg=1> BB17 regmask=[rdi] minReg=1 last fixed> BB17 regmask=[rsi] minReg=1> BB17 regmask=[rsi] minReg=1 last fixed> BB17 regmask=[rdx] minReg=1> BB17 regmask=[rdx] minReg=1 last fixed> BB17 regmask=[allInt] minReg=1 last> BB17 regmask=[rax] minReg=1> BB17 regmask=[rcx] minReg=1> BB17 regmask=[rdx] minReg=1> BB17 regmask=[rsi] minReg=1> BB17 regmask=[rdi] minReg=1> BB17 regmask=[r8] minReg=1> BB17 regmask=[r9] minReg=1> BB17 regmask=[r10] minReg=1> BB17 regmask=[r11] minReg=1> Interval 117: bool RefPositions {} physReg:NA Preferences=[allInt] BB17 regmask=[rax] minReg=1> CALL BB17 regmask=[rax] minReg=1 fixed> DefList: { N435.t146. CALL } N437 ( 1, 1) [000149] -c---------- * CNS_INT bool 0 REG NA $40 Contained DefList: { N435.t146. CALL } N439 ( 22, 16) [000150] J--XG--N-U-- * NE void REG NA $28d BB17 regmask=[allInt] minReg=1 last> DefList: { } N441 ( 24, 18) [000151] ---XG------- * JTRUE void REG NA Exposed uses: BB17 regmask=[allInt] minReg=1> V07 CHECKING LAST USES for BB17, liveout={V00 V01 V02 V03 V04 V05 V07} ============================== use: {V02 V03 V04} def: {} NEW BLOCK BB18 Setting BB04 as the predecessor for determining incoming variable registers of BB18 DefList: { } N445 (???,???) [000487] ------------ * IL_OFFSET void IL offset: 0x68 REG NA DefList: { } N447 ( 1, 1) [000152] ------------ * CNS_INT int 0 REG NA $40 Interval 118: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB18 regmask=[allInt] minReg=1> DefList: { N447.t152. CNS_INT } N449 ( 5, 4) [000154] DA---------- * STORE_LCL_VAR int V07 loc1 d:7 NA REG NA BB18 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB18 regmask=[allInt] minReg=1 last> Exposed uses: BB18 regmask=[allInt] minReg=1> V00 BB18 regmask=[allInt] minReg=1> V07 CHECKING LAST USES for BB18, liveout={V00 V01 V02 V03 V04 V05 V07} ============================== use: {} def: {V07} NEW BLOCK BB19 Setting BB10 as the predecessor for determining incoming variable registers of BB19 DefList: { } N453 (???,???) [000488] ------------ * IL_OFFSET void IL offset: 0xb5 REG NA DefList: { } N455 ( 3, 2) [000088] ------------ * LCL_VAR ref V04 arg4 u:1 NA REG NA $84 DefList: { } N457 ( 1, 1) [000089] -c---------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N459 ( 5, 4) [000090] J------N---- * EQ void REG NA $284 LCL_VAR BB19 regmask=[allInt] minReg=1 last> DefList: { } N461 ( 7, 6) [000091] ------------ * JTRUE void REG NA CHECKING LAST USES for BB19, liveout={V01 V02 V03 V04 V05 V10} ============================== use: {V04} def: {} NEW BLOCK BB20 Setting BB19 as the predecessor for determining incoming variable registers of BB20 DefList: { } N465 (???,???) [000489] ------------ * IL_OFFSET void IL offset: 0xb9 REG NA DefList: { } N467 ( 1, 1) [000098] ------------ * CNS_INT long 2 REG NA $2c4 Interval 119: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB20 regmask=[allInt] minReg=1> DefList: { N467.t98. CNS_INT } N469 (???,???) [000581] ------------ * PUTARG_REG long REG rdi BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> Interval 120: long RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[rdi] minReg=1> PUTARG_REG BB20 regmask=[rdi] minReg=1 fixed> DefList: { N469.t581. PUTARG_REG } N471 ( 3, 10) [000582] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 121: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB20 regmask=[allInt] minReg=1> DefList: { N469.t581. PUTARG_REG; N471.t582. CNS_INT } N473 ( 5, 12) [000583] -c---------- * IND long REG NA Contained DefList: { N469.t581. PUTARG_REG; N471.t582. CNS_INT } N475 ( 15, 7) [000099] --CXG------- * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 REG NA $376 BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1> BB20 regmask=[rcx] minReg=1> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rsi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[r8] minReg=1> BB20 regmask=[r9] minReg=1> BB20 regmask=[r10] minReg=1> BB20 regmask=[r11] minReg=1> Interval 122: ref RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[rax] minReg=1> CALL BB20 regmask=[rax] minReg=1 fixed> DefList: { N475.t99. CALL } N477 ( 19, 10) [000101] DA-XG------- * STORE_LCL_VAR ref V14 tmp3 d:2 NA REG NA BB20 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB20 regmask=[allInt] minReg=1 last> DefList: { } N479 ( 1, 1) [000104] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N481 ( 3, 2) [000103] ------------ * LCL_VAR ref V14 tmp3 u:2 NA REG NA $385 DefList: { } N483 (???,???) [000504] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N485 ( 5, 4) [000377] ---X-------- * IND int REG NA $299 LCL_VAR BB20 regmask=[allInt] minReg=1 last> Interval 123: int RefPositions {} physReg:NA Preferences=[allInt] IND BB20 regmask=[allInt] minReg=1> DefList: { N485.t377. IND } N487 ( 9, 7) [000465] DA-X-------- * STORE_LCL_VAR int V28 cse0 d:1 NA REG NA BB20 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB20 regmask=[allInt] minReg=1 last> DefList: { } N489 ( 3, 2) [000466] ------------ * LCL_VAR int V28 cse0 u:1 NA REG NA $299 DefList: { } N491 ( 17, 17) [000378] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA $37c LCL_VAR BB20 regmask=[allInt] minReg=1 last> DefList: { } N493 ( 3, 2) [000375] ------------ * LCL_VAR ref V14 tmp3 u:2 NA REG NA $385 DefList: { } N495 ( 4, 3) [000383] ------------ * LEA(b+16) byref REG NA LCL_VAR BB20 regmask=[allInt] minReg=1 last> Interval 124: byref RefPositions {} physReg:NA Preferences=[allInt] LEA BB20 regmask=[allInt] minReg=1> DefList: { N495.t383. LEA } N497 ( 1, 1) [000105] ------------ * LCL_VAR ref V03 arg3 u:1 NA REG NA $83 DefList: { N495.t383. LEA } N499 (???,???) [000490] -A-XG------- * STOREIND ref REG NA BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rax] minReg=1> BB20 regmask=[rcx] minReg=1> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rsi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[r8] minReg=1> BB20 regmask=[r9] minReg=1> BB20 regmask=[r10] minReg=1> BB20 regmask=[r11] minReg=1> BB20 regmask=[mm0] minReg=1> BB20 regmask=[mm1] minReg=1> BB20 regmask=[mm2] minReg=1> BB20 regmask=[mm3] minReg=1> BB20 regmask=[mm4] minReg=1> BB20 regmask=[mm5] minReg=1> BB20 regmask=[mm6] minReg=1> BB20 regmask=[mm7] minReg=1> BB20 regmask=[mm8] minReg=1> BB20 regmask=[mm9] minReg=1> BB20 regmask=[mm10] minReg=1> BB20 regmask=[mm11] minReg=1> BB20 regmask=[mm12] minReg=1> BB20 regmask=[mm13] minReg=1> BB20 regmask=[mm14] minReg=1> BB20 regmask=[mm15] minReg=1> DefList: { } N501 ( 1, 1) [000109] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N503 ( 3, 2) [000468] ------------ * LCL_VAR int V28 cse0 u:1 NA (last use) REG NA $3c1 DefList: { } N505 ( 8, 10) [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA $645 LCL_VAR BB20 regmask=[allInt] minReg=1 last> DefList: { } N507 ( 3, 2) [000385] ------------ * LCL_VAR ref V14 tmp3 u:2 NA REG NA $385 DefList: { } N509 ( 4, 3) [000393] ------------ * LEA(b+24) byref REG NA LCL_VAR BB20 regmask=[allInt] minReg=1 last> Interval 125: byref RefPositions {} physReg:NA Preferences=[allInt] LEA BB20 regmask=[allInt] minReg=1> DefList: { N509.t393. LEA } N511 ( 3, 2) [000110] ------------ * LCL_VAR ref V10 loc4 u:2 NA (last use) REG NA $370 DefList: { N509.t393. LEA } N513 (???,???) [000491] -A-XG------- * STOREIND ref REG NA BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rax] minReg=1> BB20 regmask=[rcx] minReg=1> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rsi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[r8] minReg=1> BB20 regmask=[r9] minReg=1> BB20 regmask=[r10] minReg=1> BB20 regmask=[r11] minReg=1> BB20 regmask=[mm0] minReg=1> BB20 regmask=[mm1] minReg=1> BB20 regmask=[mm2] minReg=1> BB20 regmask=[mm3] minReg=1> BB20 regmask=[mm4] minReg=1> BB20 regmask=[mm5] minReg=1> BB20 regmask=[mm6] minReg=1> BB20 regmask=[mm7] minReg=1> BB20 regmask=[mm8] minReg=1> BB20 regmask=[mm9] minReg=1> BB20 regmask=[mm10] minReg=1> BB20 regmask=[mm11] minReg=1> BB20 regmask=[mm12] minReg=1> BB20 regmask=[mm13] minReg=1> BB20 regmask=[mm14] minReg=1> BB20 regmask=[mm15] minReg=1> DefList: { } N515 ( 3, 10) [000584] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 126: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB20 regmask=[allInt] minReg=1> DefList: { N515.t584. CNS_INT } N517 ( 5, 12) [000585] -c---------- * IND long REG NA Contained DefList: { N515.t584. CNS_INT } N519 ( 14, 5) [000259] --C--------- * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW REG NA $647 BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1> BB20 regmask=[rcx] minReg=1> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rsi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[r8] minReg=1> BB20 regmask=[r9] minReg=1> BB20 regmask=[r10] minReg=1> BB20 regmask=[r11] minReg=1> Interval 127: ref RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[rax] minReg=1> CALL BB20 regmask=[rax] minReg=1 fixed> DefList: { N519.t259. CALL } N521 ( 18, 8) [000261] DA---------- * STORE_LCL_VAR ref V20 tmp9 d:2 NA REG NA BB20 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB20 regmask=[allInt] minReg=1 last> DefList: { } N523 ( 3, 10) [000586] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 128: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB20 regmask=[allInt] minReg=1> DefList: { N523.t586. CNS_INT } N525 ( 5, 12) [000587] -c---------- * IND long REG NA Contained DefList: { N523.t586. CNS_INT } N527 ( 14, 5) [000252] H-CXG------- * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE REG NA $401 BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1> BB20 regmask=[rcx] minReg=1> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rsi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[r8] minReg=1> BB20 regmask=[r9] minReg=1> BB20 regmask=[r10] minReg=1> BB20 regmask=[r11] minReg=1> Interval 129: byref RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[rax] minReg=1> CALL BB20 regmask=[rax] minReg=1 fixed> DefList: { N527.t252. CALL } N529 ( 15, 9) [000254] -c---------- * LEA(b+1048) byref REG NA Contained DefList: { N527.t252. CALL } N531 ( 17, 11) [000255] ---XG------- * IND ref REG NA BB20 regmask=[allInt] minReg=1 last> Interval 130: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB20 regmask=[allInt] minReg=1> DefList: { N531.t255. IND } N533 ( 21, 14) [000396] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp16 d:2 NA REG NA BB20 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB20 regmask=[allInt] minReg=1 last> DefList: { } N535 ( 3, 2) [000397] ------------ * LCL_VAR ref V27 tmp16 u:2 NA (last use) REG NA DefList: { } N537 (???,???) [000588] ------------ * PUTARG_REG ref REG rsi BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> Interval 131: ref RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[rsi] minReg=1> PUTARG_REG BB20 regmask=[rsi] minReg=1 fixed> DefList: { N537.t588. PUTARG_REG } N539 ( 3, 2) [000262] ------------ * LCL_VAR ref V20 tmp9 u:2 NA REG NA $647 DefList: { N537.t588. PUTARG_REG } N541 (???,???) [000589] ------------ * PUTARG_REG ref REG rdi BB20 regmask=[rdi] minReg=1> LCL_VAR BB20 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 132: ref RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[rdi] minReg=1> PUTARG_REG BB20 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N537.t588. PUTARG_REG; N541.t589. PUTARG_REG } N543 ( 3, 2) [000102] ------------ * LCL_VAR ref V14 tmp3 u:2 NA (last use) REG NA $385 DefList: { N537.t588. PUTARG_REG; N541.t589. PUTARG_REG } N545 (???,???) [000590] ------------ * PUTARG_REG ref REG rcx BB20 regmask=[rcx] minReg=1> LCL_VAR BB20 regmask=[rcx] minReg=1 last fixed> Interval 133: ref RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[rcx] minReg=1> PUTARG_REG BB20 regmask=[rcx] minReg=1 fixed> DefList: { N537.t588. PUTARG_REG; N541.t589. PUTARG_REG; N545.t590. PUTARG_REG } N547 ( 1, 4) [000256] ------------ * CNS_INT int 0x7D2C REG NA $64 Interval 134: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB20 regmask=[allInt] minReg=1> DefList: { N537.t588. PUTARG_REG; N541.t589. PUTARG_REG; N545.t590. PUTARG_REG; N547.t256. CNS_INT } N549 (???,???) [000591] ------------ * PUTARG_REG int REG rdx BB20 regmask=[rdx] minReg=1> BB20 regmask=[rdx] minReg=1 last fixed> Interval 135: int RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[rdx] minReg=1> PUTARG_REG BB20 regmask=[rdx] minReg=1 fixed> DefList: { N537.t588. PUTARG_REG; N541.t589. PUTARG_REG; N545.t590. PUTARG_REG; N549.t591. PUTARG_REG } N551 ( 3, 10) [000592] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 136: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB20 regmask=[allInt] minReg=1> DefList: { N537.t588. PUTARG_REG; N541.t589. PUTARG_REG; N545.t590. PUTARG_REG; N549.t591. PUTARG_REG; N551.t592. CNS_INT } N553 ( 5, 12) [000593] -c---------- * IND long REG NA Contained DefList: { N537.t588. PUTARG_REG; N541.t589. PUTARG_REG; N545.t590. PUTARG_REG; N549.t591. PUTARG_REG; N551.t592. CNS_INT } N555 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor REG NA $VN.Void BB20 regmask=[rsi] minReg=1> BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rcx] minReg=1> BB20 regmask=[rcx] minReg=1 last fixed> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rdx] minReg=1 last fixed> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1> BB20 regmask=[rcx] minReg=1> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rsi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[r8] minReg=1> BB20 regmask=[r9] minReg=1> BB20 regmask=[r10] minReg=1> BB20 regmask=[r11] minReg=1> DefList: { } N557 ( 1, 1) [000268] ------------ * CNS_INT int 0 REG NA $40 Interval 137: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB20 regmask=[allInt] minReg=1> DefList: { N557.t268. CNS_INT } N559 (???,???) [000594] Dc-----N---- * LCL_VAR_ADDR byref V15 tmp4 NA REG NA Contained DefList: { N557.t268. CNS_INT } N561 ( 5, 4) [000269] sA---------- * STORE_BLK struct (init) (Unroll) REG NA Interval 138: float RefPositions {} physReg:NA Preferences=[allFloat] STORE_BLK BB20 regmask=[allFloat] minReg=1> BB20 regmask=[allInt] minReg=1 last> STORE_BLK BB20 regmask=[allFloat] minReg=1 last> DefList: { } N563 ( 1, 1) [000096] ------------ * LCL_VAR ref V02 arg2 u:1 NA REG NA $82 DefList: { } N565 ( 5, 6) [000273] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:2->0[+0] Fseq[TypeParameter] NA REG NA LCL_VAR BB20 regmask=[allInt] minReg=1 last> DefList: { } N567 ( 3, 2) [000264] ------------ * LCL_VAR ref V20 tmp9 u:2 NA (last use) REG NA $647 DefList: { } N569 ( 7, 7) [000277] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:3->0[+8] Fseq[DiagnosticInfo] NA REG NA LCL_VAR BB20 regmask=[allInt] minReg=1 last> DefList: { } N571 (???,???) [000492] ------------ * IL_OFFSET void IL offset: 0xda REG NA DefList: { } N573 ( 3, 2) [000121] -c-----N---- * LCL_VAR_ADDR byref V15 tmp4 u:4 NA (last use) REG NA Contained DefList: { } N575 ( 9, 7) [000124] nc---------- * OBJ struct REG NA $507 Contained DefList: { } N577 (???,???) [000595] ------------ * PUTARG_STK [+0x00] void (5 slots) (RepInstr) REG NA Interval 139: int RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[rdi] minReg=1> PUTARG_STK BB20 regmask=[rdi] minReg=1 fixed> Interval 140: int RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[rcx] minReg=1> PUTARG_STK BB20 regmask=[rcx] minReg=1 fixed> Interval 141: int RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[rsi] minReg=1> PUTARG_STK BB20 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB20 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB20 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB20 regmask=[rsi] minReg=1 last fixed> DefList: { } N579 ( 3, 2) [000095] ------------ * LCL_VAR ref V04 arg4 u:1 NA REG NA $84 DefList: { } N581 (???,???) [000596] ------------ * PUTARG_REG ref REG rdi BB20 regmask=[rdi] minReg=1> LCL_VAR BB20 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 142: ref RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[rdi] minReg=1> PUTARG_REG BB20 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N581.t596. PUTARG_REG } N583 ( 3, 10) [000401] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 Interval 143: long RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[r11] minReg=1> CNS_INT BB20 regmask=[r11] minReg=1 fixed> DefList: { N581.t596. PUTARG_REG; N583.t401. CNS_INT } N585 (???,???) [000597] ------------ * PUTARG_REG long REG r11 BB20 regmask=[r11] minReg=1> BB20 regmask=[r11] minReg=1 last fixed> Interval 144: long RefPositions {} physReg:NA Preferences=[allInt] BB20 regmask=[r11] minReg=1> PUTARG_REG BB20 regmask=[r11] minReg=1 fixed> DefList: { N581.t596. PUTARG_REG; N585.t597. PUTARG_REG } N587 ( 3, 10) [000598] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 145: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB20 regmask=[allInt] minReg=1> DefList: { N581.t596. PUTARG_REG; N585.t597. PUTARG_REG; N587.t598. CNS_INT } N589 ( 5, 12) [000599] -c---------- * IND long REG NA Contained DefList: { N581.t596. PUTARG_REG; N585.t597. PUTARG_REG; N587.t598. CNS_INT } N591 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add REG NA $VN.Void BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[r11] minReg=1> BB20 regmask=[r11] minReg=1 last fixed> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1> BB20 regmask=[rcx] minReg=1> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rsi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[r8] minReg=1> BB20 regmask=[r9] minReg=1> BB20 regmask=[r10] minReg=1> BB20 regmask=[r11] minReg=1> CHECKING LAST USES for BB20, liveout={V01 V02 V03 V04 V05} ============================== use: {V02 V03 V04 V10} def: {V14 V15 V20 V27 V28} NEW BLOCK BB21 Setting BB19 as the predecessor for determining incoming variable registers of BB21 DefList: { } N595 (???,???) [000493] ------------ * IL_OFFSET void IL offset: 0xdf REG NA DefList: { } N597 ( 1, 1) [000092] ------------ * CNS_INT int 0 REG NA $40 Interval 146: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB21 regmask=[allInt] minReg=1> DefList: { N597.t92. CNS_INT } N599 ( 5, 4) [000094] DA---------- * STORE_LCL_VAR int V07 loc1 d:12 NA REG NA BB21 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB21 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB21, liveout={V01 V02 V03 V04 V05 V07} ============================== use: {} def: {V07} NEW BLOCK BB22 Setting BB03 as the predecessor for determining incoming variable registers of BB22 DefList: { } N603 (???,???) [000494] ------------ * IL_OFFSET void IL offset: 0x48 REG NA DefList: { } N605 ( 1, 1) [000155] ------------ * LCL_VAR ref V02 arg2 u:1 NA REG NA $82 DefList: { } N607 (???,???) [000600] ------------ * PUTARG_REG ref REG rdi BB22 regmask=[rdi] minReg=1> LCL_VAR BB22 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 147: ref RefPositions {} physReg:NA Preferences=[allInt] BB22 regmask=[rdi] minReg=1> PUTARG_REG BB22 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N607.t600. PUTARG_REG } N609 ( 1, 1) [000156] ------------ * LCL_VAR ref V03 arg3 u:1 NA REG NA $83 DefList: { N607.t600. PUTARG_REG } N611 (???,???) [000601] ------------ * PUTARG_REG ref REG rsi BB22 regmask=[rsi] minReg=1> LCL_VAR BB22 regmask=[rsi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 148: ref RefPositions {} physReg:NA Preferences=[allInt] BB22 regmask=[rsi] minReg=1> PUTARG_REG BB22 regmask=[rsi] minReg=1 fixed> Assigning related to DefList: { N607.t600. PUTARG_REG; N611.t601. PUTARG_REG } N613 ( 3, 2) [000157] ------------ * LCL_VAR ref V04 arg4 u:1 NA REG NA $84 DefList: { N607.t600. PUTARG_REG; N611.t601. PUTARG_REG } N615 (???,???) [000602] ------------ * PUTARG_REG ref REG rdx BB22 regmask=[rdx] minReg=1> LCL_VAR BB22 regmask=[rdx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 149: ref RefPositions {} physReg:NA Preferences=[allInt] BB22 regmask=[rdx] minReg=1> PUTARG_REG BB22 regmask=[rdx] minReg=1 fixed> Assigning related to DefList: { N607.t600. PUTARG_REG; N611.t601. PUTARG_REG; N615.t602. PUTARG_REG } N617 ( 3, 10) [000603] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 150: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB22 regmask=[allInt] minReg=1> DefList: { N607.t600. PUTARG_REG; N611.t601. PUTARG_REG; N615.t602. PUTARG_REG; N617.t603. CNS_INT } N619 ( 5, 12) [000604] -c---------- * IND long REG NA Contained DefList: { N607.t600. PUTARG_REG; N611.t601. PUTARG_REG; N615.t602. PUTARG_REG; N617.t603. CNS_INT } N621 ( 19, 12) [000158] --CXG------- * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint REG NA $209 BB22 regmask=[rdi] minReg=1> BB22 regmask=[rdi] minReg=1 last fixed> BB22 regmask=[rsi] minReg=1> BB22 regmask=[rsi] minReg=1 last fixed> BB22 regmask=[rdx] minReg=1> BB22 regmask=[rdx] minReg=1 last fixed> BB22 regmask=[allInt] minReg=1 last> BB22 regmask=[rax] minReg=1> BB22 regmask=[rcx] minReg=1> BB22 regmask=[rdx] minReg=1> BB22 regmask=[rsi] minReg=1> BB22 regmask=[rdi] minReg=1> BB22 regmask=[r8] minReg=1> BB22 regmask=[r9] minReg=1> BB22 regmask=[r10] minReg=1> BB22 regmask=[r11] minReg=1> Interval 151: bool RefPositions {} physReg:NA Preferences=[allInt] BB22 regmask=[rax] minReg=1> CALL BB22 regmask=[rax] minReg=1 fixed> DefList: { N621.t158. CALL } N623 ( 1, 1) [000160] -c---------- * CNS_INT bool 0 REG NA $40 Contained DefList: { N621.t158. CALL } N625 ( 22, 16) [000161] J--XG--N-U-- * NE void REG NA $289 BB22 regmask=[allInt] minReg=1 last> DefList: { } N627 ( 24, 18) [000162] ---XG------- * JTRUE void REG NA Exposed uses: BB22 regmask=[allInt] minReg=1> V07 CHECKING LAST USES for BB22, liveout={V00 V01 V02 V03 V04 V05 V07} ============================== use: {V02 V03 V04} def: {} NEW BLOCK BB23 Setting BB03 as the predecessor for determining incoming variable registers of BB23 firstColdLoc = 631 DefList: { } N631 (???,???) [000495] ------------ * IL_OFFSET void IL offset: 0x53 REG NA DefList: { } N633 ( 1, 1) [000163] ------------ * CNS_INT int 0 REG NA $40 Interval 152: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB23 regmask=[allInt] minReg=1> DefList: { N633.t163. CNS_INT } N635 ( 5, 4) [000165] DA---------- * STORE_LCL_VAR int V07 loc1 d:5 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> Exposed uses: BB23 regmask=[allInt] minReg=1> V02 BB23 regmask=[allInt] minReg=1> V03 BB23 regmask=[allInt] minReg=1> V05 BB23 regmask=[allInt] minReg=1> V01 BB23 regmask=[allInt] minReg=1> V04 BB23 regmask=[allInt] minReg=1> V00 BB23 regmask=[allInt] minReg=1> V07 CHECKING LAST USES for BB23, liveout={V00 V01 V02 V03 V04 V05 V07} ============================== use: {} def: {V07} NEW BLOCK BB24 Setting BB01 as the predecessor for determining incoming variable registers of BB24 DefList: { } N639 (???,???) [000496] ------------ * IL_OFFSET void IL offset: 0x8 REG NA DefList: { } N641 ( 1, 1) [000195] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N643 ( 5, 4) [000197] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 NA REG NA STORE_LCL_VAR BB24 regmask=[allInt] minReg=1 last> Exposed uses: BB24 regmask=[allInt] minReg=1> V06 CHECKING LAST USES for BB24, liveout={V06} ============================== use: {} def: {V06} NEW BLOCK BB25 Setting BB02 as the predecessor for determining incoming variable registers of BB25 DefList: { } N647 (???,???) [000497] ------------ * IL_OFFSET void IL offset: 0x19 REG NA DefList: { } N649 ( 3, 2) [000166] ------------ * LCL_VAR ref V04 arg4 u:1 NA REG NA $84 DefList: { } N651 ( 1, 1) [000167] -c---------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N653 ( 5, 4) [000168] J------N---- * EQ void REG NA $284 LCL_VAR BB25 regmask=[allInt] minReg=1 last> DefList: { } N655 ( 7, 6) [000169] ------------ * JTRUE void REG NA CHECKING LAST USES for BB25, liveout={V00 V01 V02 V03 V04 V05} ============================== use: {V04} def: {} NEW BLOCK BB26 Setting BB25 as the predecessor for determining incoming variable registers of BB26 DefList: { } N659 (???,???) [000498] ------------ * IL_OFFSET void IL offset: 0x1d REG NA DefList: { } N661 ( 1, 1) [000176] ------------ * CNS_INT long 1 REG NA $2c0 Interval 153: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB26 regmask=[allInt] minReg=1> DefList: { N661.t176. CNS_INT } N663 (???,???) [000605] ------------ * PUTARG_REG long REG rdi BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> Interval 154: long RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> DefList: { N663.t605. PUTARG_REG } N665 ( 3, 10) [000606] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 155: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB26 regmask=[allInt] minReg=1> DefList: { N663.t605. PUTARG_REG; N665.t606. CNS_INT } N667 ( 5, 12) [000607] -c---------- * IND long REG NA Contained DefList: { N663.t605. PUTARG_REG; N665.t606. CNS_INT } N669 ( 15, 7) [000177] --CXG------- * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 REG NA $342 BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1> BB26 regmask=[rcx] minReg=1> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[r8] minReg=1> BB26 regmask=[r9] minReg=1> BB26 regmask=[r10] minReg=1> BB26 regmask=[r11] minReg=1> Interval 156: ref RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rax] minReg=1> CALL BB26 regmask=[rax] minReg=1 fixed> DefList: { N669.t177. CALL } N671 ( 19, 10) [000179] DA-XG------- * STORE_LCL_VAR ref V16 tmp5 d:2 NA REG NA BB26 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB26 regmask=[allInt] minReg=1 last> DefList: { } N673 ( 1, 1) [000182] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N675 ( 3, 2) [000181] ------------ * LCL_VAR ref V16 tmp5 u:2 NA REG NA $380 DefList: { } N677 (???,???) [000507] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N679 ( 5, 4) [000291] -c-X-------- * IND int REG NA $285 Contained DefList: { } N681 ( 10, 12) [000292] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA $348 LCL_VAR BB26 regmask=[allInt] minReg=1 last> DefList: { } N683 ( 3, 2) [000289] ------------ * LCL_VAR ref V16 tmp5 u:2 NA REG NA $380 DefList: { } N685 ( 4, 3) [000297] ------------ * LEA(b+16) byref REG NA LCL_VAR BB26 regmask=[allInt] minReg=1 last> Interval 157: byref RefPositions {} physReg:NA Preferences=[allInt] LEA BB26 regmask=[allInt] minReg=1> DefList: { N685.t297. LEA } N687 ( 1, 1) [000183] ------------ * LCL_VAR ref V03 arg3 u:1 NA REG NA $83 DefList: { N685.t297. LEA } N689 (???,???) [000499] -A-XG------- * STOREIND ref REG NA BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rax] minReg=1> BB26 regmask=[rcx] minReg=1> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[r8] minReg=1> BB26 regmask=[r9] minReg=1> BB26 regmask=[r10] minReg=1> BB26 regmask=[r11] minReg=1> BB26 regmask=[mm0] minReg=1> BB26 regmask=[mm1] minReg=1> BB26 regmask=[mm2] minReg=1> BB26 regmask=[mm3] minReg=1> BB26 regmask=[mm4] minReg=1> BB26 regmask=[mm5] minReg=1> BB26 regmask=[mm6] minReg=1> BB26 regmask=[mm7] minReg=1> BB26 regmask=[mm8] minReg=1> BB26 regmask=[mm9] minReg=1> BB26 regmask=[mm10] minReg=1> BB26 regmask=[mm11] minReg=1> BB26 regmask=[mm12] minReg=1> BB26 regmask=[mm13] minReg=1> BB26 regmask=[mm14] minReg=1> BB26 regmask=[mm15] minReg=1> DefList: { } N691 ( 3, 10) [000608] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 158: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB26 regmask=[allInt] minReg=1> DefList: { N691.t608. CNS_INT } N693 ( 5, 12) [000609] -c---------- * IND long REG NA Contained DefList: { N691.t608. CNS_INT } N695 ( 14, 5) [000214] --C--------- * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW REG NA $34c BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1> BB26 regmask=[rcx] minReg=1> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[r8] minReg=1> BB26 regmask=[r9] minReg=1> BB26 regmask=[r10] minReg=1> BB26 regmask=[r11] minReg=1> Interval 159: ref RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rax] minReg=1> CALL BB26 regmask=[rax] minReg=1 fixed> DefList: { N695.t214. CALL } N697 ( 18, 8) [000216] DA---------- * STORE_LCL_VAR ref V18 tmp7 d:2 NA REG NA BB26 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB26 regmask=[allInt] minReg=1 last> DefList: { } N699 ( 3, 10) [000610] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 160: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB26 regmask=[allInt] minReg=1> DefList: { N699.t610. CNS_INT } N701 ( 5, 12) [000611] -c---------- * IND long REG NA Contained DefList: { N699.t610. CNS_INT } N703 ( 14, 5) [000207] H-CXG------- * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE REG NA $401 BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1> BB26 regmask=[rcx] minReg=1> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[r8] minReg=1> BB26 regmask=[r9] minReg=1> BB26 regmask=[r10] minReg=1> BB26 regmask=[r11] minReg=1> Interval 161: byref RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rax] minReg=1> CALL BB26 regmask=[rax] minReg=1 fixed> DefList: { N703.t207. CALL } N705 ( 15, 9) [000209] -c---------- * LEA(b+1048) byref REG NA Contained DefList: { N703.t207. CALL } N707 ( 17, 11) [000210] ---XG------- * IND ref REG NA BB26 regmask=[allInt] minReg=1 last> Interval 162: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB26 regmask=[allInt] minReg=1> DefList: { N707.t210. IND } N709 ( 21, 14) [000300] DA-XG-----L- * STORE_LCL_VAR ref V24 tmp13 d:2 NA REG NA BB26 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB26 regmask=[allInt] minReg=1 last> DefList: { } N711 ( 3, 2) [000301] ------------ * LCL_VAR ref V24 tmp13 u:2 NA (last use) REG NA DefList: { } N713 (???,???) [000612] ------------ * PUTARG_REG ref REG rsi BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 last fixed> Interval 163: ref RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rsi] minReg=1> PUTARG_REG BB26 regmask=[rsi] minReg=1 fixed> DefList: { N713.t612. PUTARG_REG } N715 ( 3, 2) [000217] ------------ * LCL_VAR ref V18 tmp7 u:2 NA REG NA $34c DefList: { N713.t612. PUTARG_REG } N717 (???,???) [000613] ------------ * PUTARG_REG ref REG rdi BB26 regmask=[rdi] minReg=1> LCL_VAR BB26 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 164: ref RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N713.t612. PUTARG_REG; N717.t613. PUTARG_REG } N719 ( 3, 2) [000180] ------------ * LCL_VAR ref V16 tmp5 u:2 NA (last use) REG NA $380 DefList: { N713.t612. PUTARG_REG; N717.t613. PUTARG_REG } N721 (???,???) [000614] ------------ * PUTARG_REG ref REG rcx BB26 regmask=[rcx] minReg=1> LCL_VAR BB26 regmask=[rcx] minReg=1 last fixed> Interval 165: ref RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rcx] minReg=1> PUTARG_REG BB26 regmask=[rcx] minReg=1 fixed> DefList: { N713.t612. PUTARG_REG; N717.t613. PUTARG_REG; N721.t614. PUTARG_REG } N723 ( 1, 4) [000211] ------------ * CNS_INT int 0x7AA4 REG NA $49 Interval 166: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB26 regmask=[allInt] minReg=1> DefList: { N713.t612. PUTARG_REG; N717.t613. PUTARG_REG; N721.t614. PUTARG_REG; N723.t211. CNS_INT } N725 (???,???) [000615] ------------ * PUTARG_REG int REG rdx BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1 last fixed> Interval 167: int RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rdx] minReg=1> PUTARG_REG BB26 regmask=[rdx] minReg=1 fixed> DefList: { N713.t612. PUTARG_REG; N717.t613. PUTARG_REG; N721.t614. PUTARG_REG; N725.t615. PUTARG_REG } N727 ( 3, 10) [000616] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 168: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB26 regmask=[allInt] minReg=1> DefList: { N713.t612. PUTARG_REG; N717.t613. PUTARG_REG; N721.t614. PUTARG_REG; N725.t615. PUTARG_REG; N727.t616. CNS_INT } N729 ( 5, 12) [000617] -c---------- * IND long REG NA Contained DefList: { N713.t612. PUTARG_REG; N717.t613. PUTARG_REG; N721.t614. PUTARG_REG; N725.t615. PUTARG_REG; N727.t616. CNS_INT } N731 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor REG NA $VN.Void BB26 regmask=[rsi] minReg=1> BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rcx] minReg=1> BB26 regmask=[rcx] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1> BB26 regmask=[rcx] minReg=1> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[r8] minReg=1> BB26 regmask=[r9] minReg=1> BB26 regmask=[r10] minReg=1> BB26 regmask=[r11] minReg=1> DefList: { } N733 ( 3, 3) [000189] ------------ * LCL_VAR_ADDR byref V17 tmp6 NA REG NA $481 Interval 169: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB26 regmask=[allInt] minReg=1> DefList: { N733.t189. LCL_VAR_ADDR } N735 (???,???) [000618] ------------ * PUTARG_REG byref REG rdi BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> Interval 170: byref RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> DefList: { N735.t618. PUTARG_REG } N737 ( 1, 1) [000174] ------------ * LCL_VAR ref V02 arg2 u:1 NA REG NA $82 DefList: { N735.t618. PUTARG_REG } N739 (???,???) [000619] ------------ * PUTARG_REG ref REG rsi BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 171: ref RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rsi] minReg=1> PUTARG_REG BB26 regmask=[rsi] minReg=1 fixed> Assigning related to DefList: { N735.t618. PUTARG_REG; N739.t619. PUTARG_REG } N741 ( 3, 2) [000219] ------------ * LCL_VAR ref V18 tmp7 u:2 NA (last use) REG NA $34c DefList: { N735.t618. PUTARG_REG; N739.t619. PUTARG_REG } N743 (???,???) [000620] ------------ * PUTARG_REG ref REG rdx BB26 regmask=[rdx] minReg=1> LCL_VAR BB26 regmask=[rdx] minReg=1 last fixed> Interval 172: ref RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rdx] minReg=1> PUTARG_REG BB26 regmask=[rdx] minReg=1 fixed> DefList: { N735.t618. PUTARG_REG; N739.t619. PUTARG_REG; N743.t620. PUTARG_REG } N745 ( 3, 10) [000621] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 173: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB26 regmask=[allInt] minReg=1> DefList: { N735.t618. PUTARG_REG; N739.t619. PUTARG_REG; N743.t620. PUTARG_REG; N745.t621. CNS_INT } N747 ( 5, 12) [000622] -c---------- * IND long REG NA Contained DefList: { N735.t618. PUTARG_REG; N739.t619. PUTARG_REG; N743.t620. PUTARG_REG; N745.t621. CNS_INT } N749 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor REG NA $VN.Void BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1> BB26 regmask=[rcx] minReg=1> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[r8] minReg=1> BB26 regmask=[r9] minReg=1> BB26 regmask=[r10] minReg=1> BB26 regmask=[r11] minReg=1> DefList: { } N751 (???,???) [000500] ------------ * IL_OFFSET void IL offset: 0x39 REG NA DefList: { } N753 ( 3, 2) [000191] -c-----N---- * LCL_VAR_ADDR byref V17 tmp6 NA REG NA Contained DefList: { } N755 ( 9, 7) [000194] nc--G------- * OBJ struct REG NA Contained DefList: { } N757 (???,???) [000623] ----G------- * PUTARG_STK [+0x00] void (5 slots) (RepInstr) REG NA Interval 174: int RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rdi] minReg=1> PUTARG_STK BB26 regmask=[rdi] minReg=1 fixed> Interval 175: int RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rcx] minReg=1> PUTARG_STK BB26 regmask=[rcx] minReg=1 fixed> Interval 176: int RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rsi] minReg=1> PUTARG_STK BB26 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB26 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB26 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB26 regmask=[rsi] minReg=1 last fixed> DefList: { } N759 ( 3, 2) [000173] ------------ * LCL_VAR ref V04 arg4 u:1 NA REG NA $84 DefList: { } N761 (???,???) [000624] ------------ * PUTARG_REG ref REG rdi BB26 regmask=[rdi] minReg=1> LCL_VAR BB26 regmask=[rdi] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 177: ref RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> Assigning related to DefList: { N761.t624. PUTARG_REG } N763 ( 3, 10) [000308] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 Interval 178: long RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[r11] minReg=1> CNS_INT BB26 regmask=[r11] minReg=1 fixed> DefList: { N761.t624. PUTARG_REG; N763.t308. CNS_INT } N765 (???,???) [000625] ------------ * PUTARG_REG long REG r11 BB26 regmask=[r11] minReg=1> BB26 regmask=[r11] minReg=1 last fixed> Interval 179: long RefPositions {} physReg:NA Preferences=[allInt] BB26 regmask=[r11] minReg=1> PUTARG_REG BB26 regmask=[r11] minReg=1 fixed> DefList: { N761.t624. PUTARG_REG; N765.t625. PUTARG_REG } N767 ( 3, 10) [000626] ------------ * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 180: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB26 regmask=[allInt] minReg=1> DefList: { N761.t624. PUTARG_REG; N765.t625. PUTARG_REG; N767.t626. CNS_INT } N769 ( 5, 12) [000627] -c---------- * IND long REG NA Contained DefList: { N761.t624. PUTARG_REG; N765.t625. PUTARG_REG; N767.t626. CNS_INT } N771 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add REG NA $VN.Void BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[r11] minReg=1> BB26 regmask=[r11] minReg=1 last fixed> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1> BB26 regmask=[rcx] minReg=1> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[r8] minReg=1> BB26 regmask=[r9] minReg=1> BB26 regmask=[r10] minReg=1> BB26 regmask=[r11] minReg=1> CHECKING LAST USES for BB26, liveout={V00 V01 V02 V03 V04 V05} ============================== use: {V02 V03 V04} def: {V16 V18 V24} NEW BLOCK BB27 Setting BB25 as the predecessor for determining incoming variable registers of BB27 DefList: { } N775 (???,???) [000501] ------------ * IL_OFFSET void IL offset: 0x3e REG NA DefList: { } N777 ( 1, 1) [000170] ------------ * CNS_INT int 0 REG NA $40 Interval 181: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB27 regmask=[allInt] minReg=1> DefList: { N777.t170. CNS_INT } N779 ( 5, 4) [000172] DA---------- * STORE_LCL_VAR int V07 loc1 d:3 NA REG NA BB27 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB27 regmask=[allInt] minReg=1 last> Exposed uses: BB27 regmask=[allInt] minReg=1> V00 BB27 regmask=[allInt] minReg=1> V07 CHECKING LAST USES for BB27, liveout={V00 V01 V02 V03 V04 V05 V07} ============================== use: {} def: {V07} NEW BLOCK BB28 Setting BB12 as the predecessor for determining incoming variable registers of BB28 DefList: { } N783 (???,???) [000502] ------------ * IL_OFFSET void IL offset: 0x80 REG NA DefList: { } N785 ( 1, 1) [000140] ------------ * CNS_INT int 0 REG NA $40 Interval 182: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB28 regmask=[allInt] minReg=1> DefList: { N785.t140. CNS_INT } N787 ( 5, 4) [000142] DA---------- * STORE_LCL_VAR int V07 loc1 d:9 NA REG NA BB28 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB28 regmask=[allInt] minReg=1 last> Exposed uses: BB28 regmask=[allInt] minReg=1> V02 BB28 regmask=[allInt] minReg=1> V03 BB28 regmask=[allInt] minReg=1> V05 BB28 regmask=[allInt] minReg=1> V01 BB28 regmask=[allInt] minReg=1> V04 BB28 regmask=[allInt] minReg=1> V07 CHECKING LAST USES for BB28, liveout={V01 V02 V03 V04 V05 V07} ============================== use: {} def: {V07} NEW BLOCK BB29 No predecessor; Setting BB28 as the predecessor for determining incoming variable registers of BB29 DefList: { } N791 ( 14, 5) [000505] --CXG------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL REG NA BB29 regmask=[rax] minReg=1> BB29 regmask=[rcx] minReg=1> BB29 regmask=[rdx] minReg=1> BB29 regmask=[rsi] minReg=1> BB29 regmask=[rdi] minReg=1> BB29 regmask=[r8] minReg=1> BB29 regmask=[r9] minReg=1> BB29 regmask=[r10] minReg=1> BB29 regmask=[r11] minReg=1> CHECKING LAST USES for BB29, liveout={} ============================== use: {} def: {} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) ref RefPositions {#5@0 #404@323 #560@451 #810@637 #1008@781} physReg:rdi Preferences=[rbx r12-r15] Interval 1: (V01) ref RefPositions {#3@0 #315@257 #519@415 #808@637 #1017@789} physReg:rsi Preferences=[rbx r12-r15] Interval 2: (V02) ref RefPositions {#0@0 #88@67 #117@91 #146@115 #175@137 #408@327 #516@415 #524@421 #727@565 #769@607 #805@637 #946@739 #1014@789} physReg:rdx Preferences=[rbx r12-r15] Interval 3: (V03) ref RefPositions {#1@0 #8@5 #38@33 #412@331 #450@361 #517@415 #528@425 #597@499 #773@611 #806@637 #846@689 #1015@789} physReg:rcx Preferences=[rbx r12-r15] Interval 4: (V04) ref RefPositions {#4@0 #416@335 #520@415 #532@429 #563@459 #739@581 #777@615 #809@637 #816@653 #980@761 #1018@789} physReg:r8 Preferences=[rbx r12-r15] Interval 5: (V05) byref RefPositions {#2@0 #179@141 #384@307 #420@339 #458@369 #518@415 #807@637 #1016@789} physReg:r9 Preferences=[rbx r12-r15] Interval 6: (V06) int RefPositions {#274@220 #277@227 #813@644 #814@645} physReg:NA Preferences=[rax] Interval 7: (V07) int RefPositions {#36@30 #273@219 #555@443 #559@450 #561@451 #766@600 #800@629 #804@636 #811@637 #1007@780 #1009@781 #1013@788 #1019@789} physReg:NA Preferences=[rbx r12-r15] RelatedInterval Interval 8: (V10) ref RefPositions {#349@274 #351@279 #380@303 #454@365 #629@513} physReg:NA Preferences=[rbx r12-r15] Interval 9: (V14) ref RefPositions {#586@478 #587@485 #592@495 #624@509 #696@545} physReg:NA Preferences=[rbx r12-r15] Interval 10: (V16) ref RefPositions {#839@672 #840@681 #841@685 #913@721} physReg:NA Preferences=[rbx r12-r15] Interval 11: (V18) ref RefPositions {#886@698 #909@717 #950@743} physReg:NA Preferences=[rbx r12-r15] Interval 12: (V19) int RefPositions {#483@380 #484@385} physReg:NA Preferences=[allInt] Interval 13: (V20) ref RefPositions {#669@522 #692@541 #728@569} physReg:NA Preferences=[rbx r12-r15] Interval 14: (V24) ref RefPositions {#903@710 #905@713} physReg:NA Preferences=[rsi] Interval 15: (V25) byref RefPositions {#235@174 #236@177 #239@185} physReg:NA Preferences=[allInt] Interval 16: (V26) ref RefPositions {#309@250 #311@253} physReg:NA Preferences=[rdi] Interval 17: (V27) ref RefPositions {#686@534 #688@537} physReg:NA Preferences=[rsi] Interval 18: (V28) int RefPositions {#590@488 #591@491 #623@505} physReg:NA Preferences=[rbx r12-r15] Interval 19: ref (specialPutArg) RefPositions {#10@6 #19@15} physReg:NA Preferences=[rdi] RelatedInterval Interval 20: long (constant) RefPositions {#12@8 #14@9} physReg:NA Preferences=[r11] Interval 21: long RefPositions {#16@10 #21@15} physReg:NA Preferences=[r11] Interval 22: long (constant) RefPositions {#17@12 #22@15} physReg:NA Preferences=[allInt] Interval 23: int RefPositions {#33@16 #34@19} physReg:NA Preferences=[rax] Interval 24: ref (specialPutArg) RefPositions {#40@34 #49@43} physReg:NA Preferences=[rdi] RelatedInterval Interval 25: long (constant) RefPositions {#42@36 #44@37} physReg:NA Preferences=[r11] Interval 26: long RefPositions {#46@38 #51@43} physReg:NA Preferences=[r11] Interval 27: long (constant) RefPositions {#47@40 #52@43} physReg:NA Preferences=[allInt] Interval 28: int RefPositions {#63@44 #64@45} physReg:NA Preferences=[rax] Interval 29: int RefPositions {#65@46 #67@47} physReg:NA Preferences=[rdi] Interval 30: int RefPositions {#69@48 #72@53} physReg:NA Preferences=[rdi] Interval 31: long (constant) RefPositions {#70@50 #73@53} physReg:NA Preferences=[allInt] Interval 32: bool RefPositions {#84@54 #85@57} physReg:NA Preferences=[rax] Interval 33: ref (specialPutArg) RefPositions {#90@68 #99@77} physReg:NA Preferences=[rdi] RelatedInterval Interval 34: long (constant) RefPositions {#92@70 #94@71} physReg:NA Preferences=[r11] Interval 35: long RefPositions {#96@72 #101@77} physReg:NA Preferences=[r11] Interval 36: long (constant) RefPositions {#97@74 #102@77} physReg:NA Preferences=[allInt] Interval 37: bool RefPositions {#113@78 #114@81} physReg:NA Preferences=[rax] Interval 38: ref (specialPutArg) RefPositions {#119@92 #128@101} physReg:NA Preferences=[rdi] RelatedInterval Interval 39: long (constant) RefPositions {#121@94 #123@95} physReg:NA Preferences=[r11] Interval 40: long RefPositions {#125@96 #130@101} physReg:NA Preferences=[r11] Interval 41: long (constant) RefPositions {#126@98 #131@101} physReg:NA Preferences=[allInt] Interval 42: bool RefPositions {#142@102 #143@105} physReg:NA Preferences=[rax] Interval 43: ref (specialPutArg) RefPositions {#148@116 #157@125} physReg:NA Preferences=[rdi] RelatedInterval Interval 44: long (constant) RefPositions {#150@118 #152@119} physReg:NA Preferences=[r11] Interval 45: long RefPositions {#154@120 #159@125} physReg:NA Preferences=[r11] Interval 46: long (constant) RefPositions {#155@122 #160@125} physReg:NA Preferences=[allInt] Interval 47: bool RefPositions {#171@126 #172@129} physReg:NA Preferences=[rax] Interval 48: ref (specialPutArg) RefPositions {#177@138 #184@147} physReg:NA Preferences=[rdi] RelatedInterval Interval 49: byref (specialPutArg) RefPositions {#181@142 #186@147} physReg:NA Preferences=[rsi] RelatedInterval Interval 50: long (constant) RefPositions {#182@144 #187@147} physReg:NA Preferences=[allInt] Interval 51: ref RefPositions {#198@148 #199@149} physReg:NA Preferences=[rax] Interval 52: long (constant) RefPositions {#200@154 #201@155} physReg:NA Preferences=[allInt] Interval 53: long RefPositions {#202@156 #204@157} physReg:NA Preferences=[rsi] Interval 54: long RefPositions {#206@158 #214@167} physReg:NA Preferences=[rsi] Interval 55: byref RefPositions {#207@160 #209@161} physReg:NA Preferences=[rdi] Interval 56: byref RefPositions {#211@162 #216@167} physReg:NA Preferences=[rdi] Interval 57: long (constant) RefPositions {#212@164 #217@167} physReg:NA Preferences=[allInt] Interval 58: ref RefPositions {#228@168 #231@169} physReg:NA Preferences=[rax] Interval 59: long RefPositions {#230@168 #232@169} physReg:NA Preferences=[rdx] Interval 60: byref RefPositions {#233@172 #234@173} physReg:NA Preferences=[allInt] RelatedInterval Interval 61: ref RefPositions {#237@178 #238@179} physReg:NA Preferences=[allInt] Interval 62: int RefPositions {#240@186 #241@187} physReg:NA Preferences=[allInt] Interval 63: long (constant) RefPositions {#242@192 #243@193} physReg:NA Preferences=[allInt] Interval 64: long RefPositions {#244@194 #246@195} physReg:NA Preferences=[rsi] Interval 65: long RefPositions {#248@196 #256@205} physReg:NA Preferences=[rsi] Interval 66: byref RefPositions {#249@198 #251@199} physReg:NA Preferences=[rdi] Interval 67: byref RefPositions {#253@200 #258@205} physReg:NA Preferences=[rdi] Interval 68: long (constant) RefPositions {#254@202 #259@205} physReg:NA Preferences=[allInt] Interval 69: bool RefPositions {#270@206 #271@209} physReg:NA Preferences=[rax] Interval 70: long (constant) RefPositions {#279@234 #280@235} physReg:NA Preferences=[allInt] Interval 71: long RefPositions {#281@236 #283@237} physReg:NA Preferences=[rsi] Interval 72: long RefPositions {#285@238 #293@247} physReg:NA Preferences=[rsi] Interval 73: byref RefPositions {#286@240 #288@241} physReg:NA Preferences=[rdi] Interval 74: byref RefPositions {#290@242 #295@247} physReg:NA Preferences=[rdi] Interval 75: long (constant) RefPositions {#291@244 #296@247} physReg:NA Preferences=[allInt] Interval 76: ref RefPositions {#307@248 #308@249} physReg:NA Preferences=[rax] RelatedInterval Interval 77: ref RefPositions {#313@254 #326@267} physReg:NA Preferences=[rdi] Interval 78: ref (specialPutArg) RefPositions {#317@258 #328@267} physReg:NA Preferences=[rsi] RelatedInterval Interval 79: long (constant) RefPositions {#319@260 #321@261} physReg:NA Preferences=[r11] Interval 80: long RefPositions {#323@262 #330@267} physReg:NA Preferences=[r11] Interval 81: long (constant) RefPositions {#324@264 #331@267} physReg:NA Preferences=[allInt] Interval 82: ref RefPositions {#342@268 #345@269} physReg:NA Preferences=[rax] Interval 83: ref RefPositions {#344@268 #346@269} physReg:NA Preferences=[rdx] Interval 84: ref RefPositions {#347@272 #348@273} physReg:NA Preferences=[allInt] RelatedInterval Interval 85: ref (specialPutArg) RefPositions {#353@280 #362@289} physReg:NA Preferences=[rdi] RelatedInterval Interval 86: long (constant) RefPositions {#355@282 #357@283} physReg:NA Preferences=[r11] Interval 87: long RefPositions {#359@284 #364@289} physReg:NA Preferences=[r11] Interval 88: long (constant) RefPositions {#360@286 #365@289} physReg:NA Preferences=[allInt] Interval 89: int RefPositions {#376@290 #377@293} physReg:NA Preferences=[rax] Interval 90: ref (specialPutArg) RefPositions {#382@304 #389@313} physReg:NA Preferences=[rdi] RelatedInterval Interval 91: byref (specialPutArg) RefPositions {#386@308 #391@313} physReg:NA Preferences=[rsi] RelatedInterval Interval 92: long (constant) RefPositions {#387@310 #392@313} physReg:NA Preferences=[allInt] Interval 93: ref RefPositions {#406@324 #425@345} physReg:NA Preferences=[rdi] Interval 94: ref (specialPutArg) RefPositions {#410@328 #427@345} physReg:NA Preferences=[rsi] RelatedInterval Interval 95: ref (specialPutArg) RefPositions {#414@332 #429@345} physReg:NA Preferences=[rdx] RelatedInterval Interval 96: ref (specialPutArg) RefPositions {#418@336 #431@345} physReg:NA Preferences=[rcx] RelatedInterval Interval 97: byref (specialPutArg) RefPositions {#422@340 #433@345} physReg:NA Preferences=[r8] RelatedInterval Interval 98: long (constant) RefPositions {#423@342 #434@345} physReg:NA Preferences=[allInt] Interval 99: bool RefPositions {#445@346 #446@349} physReg:NA Preferences=[rax] Interval 100: ref (specialPutArg) RefPositions {#452@362 #463@375} physReg:NA Preferences=[rdi] RelatedInterval Interval 101: ref (specialPutArg) RefPositions {#456@366 #465@375} physReg:NA Preferences=[rsi] RelatedInterval Interval 102: byref (specialPutArg) RefPositions {#460@370 #467@375} physReg:NA Preferences=[rdx] RelatedInterval Interval 103: long (constant) RefPositions {#461@372 #468@375} physReg:NA Preferences=[allInt] Interval 104: int RefPositions {#479@376 #480@377} physReg:NA Preferences=[rax] Interval 105: int RefPositions {#481@378 #482@379} physReg:NA Preferences=[allInt] RelatedInterval Interval 106: long (constant) RefPositions {#486@394 #487@395} physReg:NA Preferences=[allInt] Interval 107: long RefPositions {#488@396 #490@397} physReg:NA Preferences=[rsi] Interval 108: long RefPositions {#492@398 #500@407} physReg:NA Preferences=[rsi] Interval 109: byref RefPositions {#493@400 #495@401} physReg:NA Preferences=[rdi] Interval 110: byref RefPositions {#497@402 #502@407} physReg:NA Preferences=[rdi] Interval 111: long (constant) RefPositions {#498@404 #503@407} physReg:NA Preferences=[allInt] Interval 112: bool RefPositions {#514@408 #515@411} physReg:NA Preferences=[rax] Interval 113: ref (specialPutArg) RefPositions {#526@422 #537@435} physReg:NA Preferences=[rdi] RelatedInterval Interval 114: ref (specialPutArg) RefPositions {#530@426 #539@435} physReg:NA Preferences=[rsi] RelatedInterval Interval 115: ref (specialPutArg) RefPositions {#534@430 #541@435} physReg:NA Preferences=[rdx] RelatedInterval Interval 116: long (constant) RefPositions {#535@432 #542@435} physReg:NA Preferences=[allInt] Interval 117: bool RefPositions {#553@436 #554@439} physReg:NA Preferences=[rax] Interval 118: int (constant) RefPositions {#557@448 #558@449} physReg:NA Preferences=[allInt] RelatedInterval Interval 119: long (constant) RefPositions {#565@468 #567@469} physReg:NA Preferences=[rdi] Interval 120: long RefPositions {#569@470 #572@475} physReg:NA Preferences=[rdi] Interval 121: long (constant) RefPositions {#570@472 #573@475} physReg:NA Preferences=[allInt] Interval 122: ref RefPositions {#584@476 #585@477} physReg:NA Preferences=[rax] RelatedInterval Interval 123: int RefPositions {#588@486 #589@487} physReg:NA Preferences=[allInt] RelatedInterval Interval 124: byref RefPositions {#593@496 #595@499} physReg:NA Preferences=[rdi] Interval 125: byref RefPositions {#625@510 #627@513} physReg:NA Preferences=[rdi] Interval 126: long (constant) RefPositions {#655@516 #656@519} physReg:NA Preferences=[allInt] Interval 127: ref RefPositions {#667@520 #668@521} physReg:NA Preferences=[rax] RelatedInterval Interval 128: long (constant) RefPositions {#670@524 #671@527} physReg:NA Preferences=[allInt] Interval 129: byref RefPositions {#682@528 #683@531} physReg:NA Preferences=[rax] Interval 130: ref RefPositions {#684@532 #685@533} physReg:NA Preferences=[allInt] RelatedInterval Interval 131: ref RefPositions {#690@538 #706@555} physReg:NA Preferences=[rsi] Interval 132: ref (specialPutArg) RefPositions {#694@542 #708@555} physReg:NA Preferences=[rdi] RelatedInterval Interval 133: ref RefPositions {#698@546 #710@555} physReg:NA Preferences=[rcx] Interval 134: int (constant) RefPositions {#699@548 #701@549} physReg:NA Preferences=[rdx] Interval 135: int RefPositions {#703@550 #712@555} physReg:NA Preferences=[rdx] Interval 136: long (constant) RefPositions {#704@552 #713@555} physReg:NA Preferences=[allInt] Interval 137: int (constant) RefPositions {#723@558 #725@561} physReg:NA Preferences=[allInt] Interval 138: float (INTERNAL) RefPositions {#724@561 #726@561} physReg:NA Preferences=[allFloat] Interval 139: int (INTERNAL) RefPositions {#730@577 #735@577} physReg:NA Preferences=[rdi] Interval 140: int (INTERNAL) RefPositions {#732@577 #736@577} physReg:NA Preferences=[rcx] Interval 141: int (INTERNAL) RefPositions {#734@577 #737@577} physReg:NA Preferences=[rsi] Interval 142: ref (specialPutArg) RefPositions {#741@582 #750@591} physReg:NA Preferences=[rdi] RelatedInterval Interval 143: long (constant) RefPositions {#743@584 #745@585} physReg:NA Preferences=[r11] Interval 144: long RefPositions {#747@586 #752@591} physReg:NA Preferences=[r11] Interval 145: long (constant) RefPositions {#748@588 #753@591} physReg:NA Preferences=[allInt] Interval 146: int (constant) RefPositions {#764@598 #765@599} physReg:NA Preferences=[allInt] RelatedInterval Interval 147: ref (specialPutArg) RefPositions {#771@608 #782@621} physReg:NA Preferences=[rdi] RelatedInterval Interval 148: ref (specialPutArg) RefPositions {#775@612 #784@621} physReg:NA Preferences=[rsi] RelatedInterval Interval 149: ref (specialPutArg) RefPositions {#779@616 #786@621} physReg:NA Preferences=[rdx] RelatedInterval Interval 150: long (constant) RefPositions {#780@618 #787@621} physReg:NA Preferences=[allInt] Interval 151: bool RefPositions {#798@622 #799@625} physReg:NA Preferences=[rax] Interval 152: int (constant) RefPositions {#802@634 #803@635} physReg:NA Preferences=[allInt] RelatedInterval Interval 153: long (constant) RefPositions {#818@662 #820@663} physReg:NA Preferences=[rdi] Interval 154: long RefPositions {#822@664 #825@669} physReg:NA Preferences=[rdi] Interval 155: long (constant) RefPositions {#823@666 #826@669} physReg:NA Preferences=[allInt] Interval 156: ref RefPositions {#837@670 #838@671} physReg:NA Preferences=[rax] RelatedInterval Interval 157: byref RefPositions {#842@686 #844@689} physReg:NA Preferences=[rdi] Interval 158: long (constant) RefPositions {#872@692 #873@695} physReg:NA Preferences=[allInt] Interval 159: ref RefPositions {#884@696 #885@697} physReg:NA Preferences=[rax] RelatedInterval Interval 160: long (constant) RefPositions {#887@700 #888@703} physReg:NA Preferences=[allInt] Interval 161: byref RefPositions {#899@704 #900@707} physReg:NA Preferences=[rax] Interval 162: ref RefPositions {#901@708 #902@709} physReg:NA Preferences=[allInt] RelatedInterval Interval 163: ref RefPositions {#907@714 #923@731} physReg:NA Preferences=[rsi] Interval 164: ref (specialPutArg) RefPositions {#911@718 #925@731} physReg:NA Preferences=[rdi] RelatedInterval Interval 165: ref RefPositions {#915@722 #927@731} physReg:NA Preferences=[rcx] Interval 166: int (constant) RefPositions {#916@724 #918@725} physReg:NA Preferences=[rdx] Interval 167: int RefPositions {#920@726 #929@731} physReg:NA Preferences=[rdx] Interval 168: long (constant) RefPositions {#921@728 #930@731} physReg:NA Preferences=[allInt] Interval 169: byref RefPositions {#940@734 #942@735} physReg:NA Preferences=[rdi] Interval 170: byref RefPositions {#944@736 #955@749} physReg:NA Preferences=[rdi] Interval 171: ref (specialPutArg) RefPositions {#948@740 #957@749} physReg:NA Preferences=[rsi] RelatedInterval Interval 172: ref RefPositions {#952@744 #959@749} physReg:NA Preferences=[rdx] Interval 173: long (constant) RefPositions {#953@746 #960@749} physReg:NA Preferences=[allInt] Interval 174: int (INTERNAL) RefPositions {#971@757 #976@757} physReg:NA Preferences=[rdi] Interval 175: int (INTERNAL) RefPositions {#973@757 #977@757} physReg:NA Preferences=[rcx] Interval 176: int (INTERNAL) RefPositions {#975@757 #978@757} physReg:NA Preferences=[rsi] Interval 177: ref (specialPutArg) RefPositions {#982@762 #991@771} physReg:NA Preferences=[rdi] RelatedInterval Interval 178: long (constant) RefPositions {#984@764 #986@765} physReg:NA Preferences=[r11] Interval 179: long RefPositions {#988@766 #993@771} physReg:NA Preferences=[r11] Interval 180: long (constant) RefPositions {#989@768 #994@771} physReg:NA Preferences=[allInt] Interval 181: int (constant) RefPositions {#1005@778 #1006@779} physReg:NA Preferences=[allInt] RelatedInterval Interval 182: int (constant) RefPositions {#1011@786 #1012@787} physReg:NA Preferences=[allInt] RelatedInterval ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ BB00 regmask=[rdx] minReg=1 fixed regOptional> BB00 regmask=[rcx] minReg=1 fixed regOptional> BB00 regmask=[r9] minReg=1 fixed regOptional> BB00 regmask=[rsi] minReg=1 fixed regOptional> BB00 regmask=[r8] minReg=1 fixed regOptional> BB00 regmask=[rdi] minReg=1 fixed regOptional> BB01 regmask=[rdi] minReg=1> LCL_VAR BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[r11] minReg=1> CNS_INT BB01 regmask=[r11] minReg=1 fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> PUTARG_REG BB01 regmask=[r11] minReg=1 fixed> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last regOptional> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[r11] minReg=1> CNS_INT BB02 regmask=[r11] minReg=1 fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> PUTARG_REG BB02 regmask=[r11] minReg=1 fixed> CNS_INT BB02 regmask=[allInt] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[allInt] minReg=1 last> CAST BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> CNS_INT BB02 regmask=[allInt] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[allInt] minReg=1 last regOptional> BB03 regmask=[rdi] minReg=1> LCL_VAR BB03 regmask=[rdi] minReg=1 fixed> BB03 regmask=[rdi] minReg=1> PUTARG_REG BB03 regmask=[rdi] minReg=1 fixed> BB03 regmask=[r11] minReg=1> CNS_INT BB03 regmask=[r11] minReg=1 fixed> BB03 regmask=[r11] minReg=1> BB03 regmask=[r11] minReg=1 last fixed> BB03 regmask=[r11] minReg=1> PUTARG_REG BB03 regmask=[r11] minReg=1 fixed> CNS_INT BB03 regmask=[allInt] minReg=1> BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1 last fixed> BB03 regmask=[r11] minReg=1> BB03 regmask=[r11] minReg=1 last fixed> BB03 regmask=[allInt] minReg=1 last> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[rsi] minReg=1 last> BB03 regmask=[rdi] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> BB03 regmask=[allInt] minReg=1 last regOptional> BB04 regmask=[rdi] minReg=1> LCL_VAR BB04 regmask=[rdi] minReg=1 fixed> BB04 regmask=[rdi] minReg=1> PUTARG_REG BB04 regmask=[rdi] minReg=1 fixed> BB04 regmask=[r11] minReg=1> CNS_INT BB04 regmask=[r11] minReg=1 fixed> BB04 regmask=[r11] minReg=1> BB04 regmask=[r11] minReg=1 last fixed> BB04 regmask=[r11] minReg=1> PUTARG_REG BB04 regmask=[r11] minReg=1 fixed> CNS_INT BB04 regmask=[allInt] minReg=1> BB04 regmask=[rdi] minReg=1> BB04 regmask=[rdi] minReg=1 last fixed> BB04 regmask=[r11] minReg=1> BB04 regmask=[r11] minReg=1 last fixed> BB04 regmask=[allInt] minReg=1 last> BB04 regmask=[rax] minReg=1 last> BB04 regmask=[rcx] minReg=1 last> BB04 regmask=[rdx] minReg=1 last> BB04 regmask=[rsi] minReg=1 last> BB04 regmask=[rdi] minReg=1 last> BB04 regmask=[r8] minReg=1 last> BB04 regmask=[r9] minReg=1 last> BB04 regmask=[r10] minReg=1 last> BB04 regmask=[r11] minReg=1 last> BB04 regmask=[rax] minReg=1> CALL BB04 regmask=[rax] minReg=1 fixed> BB04 regmask=[allInt] minReg=1 last regOptional> BB05 regmask=[rdi] minReg=1> LCL_VAR BB05 regmask=[rdi] minReg=1 fixed> BB05 regmask=[rdi] minReg=1> PUTARG_REG BB05 regmask=[rdi] minReg=1 fixed> BB05 regmask=[r11] minReg=1> CNS_INT BB05 regmask=[r11] minReg=1 fixed> BB05 regmask=[r11] minReg=1> BB05 regmask=[r11] minReg=1 last fixed> BB05 regmask=[r11] minReg=1> PUTARG_REG BB05 regmask=[r11] minReg=1 fixed> CNS_INT BB05 regmask=[allInt] minReg=1> BB05 regmask=[rdi] minReg=1> BB05 regmask=[rdi] minReg=1 last fixed> BB05 regmask=[r11] minReg=1> BB05 regmask=[r11] minReg=1 last fixed> BB05 regmask=[allInt] minReg=1 last> BB05 regmask=[rax] minReg=1 last> BB05 regmask=[rcx] minReg=1 last> BB05 regmask=[rdx] minReg=1 last> BB05 regmask=[rsi] minReg=1 last> BB05 regmask=[rdi] minReg=1 last> BB05 regmask=[r8] minReg=1 last> BB05 regmask=[r9] minReg=1 last> BB05 regmask=[r10] minReg=1 last> BB05 regmask=[r11] minReg=1 last> BB05 regmask=[rax] minReg=1> CALL BB05 regmask=[rax] minReg=1 fixed> BB05 regmask=[allInt] minReg=1 last regOptional> BB06 regmask=[rdi] minReg=1> LCL_VAR BB06 regmask=[rdi] minReg=1 fixed> BB06 regmask=[rdi] minReg=1> PUTARG_REG BB06 regmask=[rdi] minReg=1 fixed> BB06 regmask=[rsi] minReg=1> LCL_VAR BB06 regmask=[rsi] minReg=1 fixed> BB06 regmask=[rsi] minReg=1> PUTARG_REG BB06 regmask=[rsi] minReg=1 fixed> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rcx] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> BB06 regmask=[rsi] minReg=1 last> BB06 regmask=[rdi] minReg=1 last> BB06 regmask=[r8] minReg=1 last> BB06 regmask=[r9] minReg=1 last> BB06 regmask=[r10] minReg=1 last> BB06 regmask=[r11] minReg=1 last> BB06 regmask=[rax] minReg=1> CALL BB06 regmask=[rax] minReg=1 fixed> BB06 regmask=[allInt] minReg=1 last> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> IND BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rsi] minReg=1> PUTARG_REG BB06 regmask=[rsi] minReg=1 fixed> LCL_VAR_ADDR BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> PUTARG_REG BB06 regmask=[rdi] minReg=1 fixed> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rcx] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> BB06 regmask=[rsi] minReg=1 last> BB06 regmask=[rdi] minReg=1 last> BB06 regmask=[r8] minReg=1 last> BB06 regmask=[r9] minReg=1 last> BB06 regmask=[r10] minReg=1 last> BB06 regmask=[r11] minReg=1 last> BB06 regmask=[rax] minReg=1> CALL BB06 regmask=[rax] minReg=1 fixed> BB06 regmask=[rdx] minReg=1> CALL BB06 regmask=[rdx] minReg=1 fixed> BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> IND BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> LCL_VAR BB06 regmask=[allInt] minReg=1 last> IND BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> IND BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rsi] minReg=1> PUTARG_REG BB06 regmask=[rsi] minReg=1 fixed> LCL_VAR_ADDR BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> PUTARG_REG BB06 regmask=[rdi] minReg=1 fixed> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rcx] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> BB06 regmask=[rsi] minReg=1 last> BB06 regmask=[rdi] minReg=1 last> BB06 regmask=[r8] minReg=1 last> BB06 regmask=[r9] minReg=1 last> BB06 regmask=[r10] minReg=1 last> BB06 regmask=[r11] minReg=1 last> BB06 regmask=[rax] minReg=1> CALL BB06 regmask=[rax] minReg=1 fixed> BB06 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB07 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> BB08 regmask=[rax] minReg=1> LCL_VAR BB08 regmask=[rax] minReg=1 last fixed> CNS_INT BB09 regmask=[allInt] minReg=1> BB09 regmask=[allInt] minReg=1 last> IND BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last fixed> BB09 regmask=[rsi] minReg=1> PUTARG_REG BB09 regmask=[rsi] minReg=1 fixed> LCL_VAR_ADDR BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[rdi] minReg=1> PUTARG_REG BB09 regmask=[rdi] minReg=1 fixed> CNS_INT BB09 regmask=[allInt] minReg=1> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last fixed> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[allInt] minReg=1 last> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rcx] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> BB09 regmask=[rsi] minReg=1 last> BB09 regmask=[rdi] minReg=1 last> BB09 regmask=[r8] minReg=1 last> BB09 regmask=[r9] minReg=1 last> BB09 regmask=[r10] minReg=1 last> BB09 regmask=[r11] minReg=1 last> BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> BB09 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> BB09 regmask=[rdi] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[rdi] minReg=1> PUTARG_REG BB09 regmask=[rdi] minReg=1 fixed> BB09 regmask=[rsi] minReg=1> LCL_VAR BB09 regmask=[rsi] minReg=1 fixed> BB09 regmask=[rsi] minReg=1> PUTARG_REG BB09 regmask=[rsi] minReg=1 fixed> BB09 regmask=[r11] minReg=1> CNS_INT BB09 regmask=[r11] minReg=1 fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> PUTARG_REG BB09 regmask=[r11] minReg=1 fixed> CNS_INT BB09 regmask=[allInt] minReg=1> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[allInt] minReg=1 last> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rcx] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> BB09 regmask=[rsi] minReg=1 last> BB09 regmask=[rdi] minReg=1 last> BB09 regmask=[r8] minReg=1 last> BB09 regmask=[r9] minReg=1 last> BB09 regmask=[r10] minReg=1 last> BB09 regmask=[r11] minReg=1 last> BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> BB09 regmask=[rdx] minReg=1> CALL BB09 regmask=[rdx] minReg=1 fixed> BB09 regmask=[allInt] minReg=1 last> BB09 regmask=[allInt] minReg=1 last> LCL_FLD BB09 regmask=[allInt] minReg=1> BB09 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> BB09 regmask=[rdi] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 fixed> BB09 regmask=[rdi] minReg=1> PUTARG_REG BB09 regmask=[rdi] minReg=1 fixed> BB09 regmask=[r11] minReg=1> CNS_INT BB09 regmask=[r11] minReg=1 fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> PUTARG_REG BB09 regmask=[r11] minReg=1 fixed> CNS_INT BB09 regmask=[allInt] minReg=1> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[allInt] minReg=1 last> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rcx] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> BB09 regmask=[rsi] minReg=1 last> BB09 regmask=[rdi] minReg=1 last> BB09 regmask=[r8] minReg=1 last> BB09 regmask=[r9] minReg=1 last> BB09 regmask=[r10] minReg=1 last> BB09 regmask=[r11] minReg=1 last> BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> BB09 regmask=[allInt] minReg=1 last regOptional> BB10 regmask=[rdi] minReg=1> LCL_VAR BB10 regmask=[rdi] minReg=1 fixed> BB10 regmask=[rdi] minReg=1> PUTARG_REG BB10 regmask=[rdi] minReg=1 fixed> BB10 regmask=[rsi] minReg=1> LCL_VAR BB10 regmask=[rsi] minReg=1 fixed> BB10 regmask=[rsi] minReg=1> PUTARG_REG BB10 regmask=[rsi] minReg=1 fixed> CNS_INT BB10 regmask=[allInt] minReg=1> BB10 regmask=[rdi] minReg=1> BB10 regmask=[rdi] minReg=1 last fixed> BB10 regmask=[rsi] minReg=1> BB10 regmask=[rsi] minReg=1 last fixed> BB10 regmask=[allInt] minReg=1 last> BB10 regmask=[rax] minReg=1 last> BB10 regmask=[rcx] minReg=1 last> BB10 regmask=[rdx] minReg=1 last> BB10 regmask=[rsi] minReg=1 last> BB10 regmask=[rdi] minReg=1 last> BB10 regmask=[r8] minReg=1 last> BB10 regmask=[r9] minReg=1 last> BB10 regmask=[r10] minReg=1 last> BB10 regmask=[r11] minReg=1 last> BB12 regmask=[rdi] minReg=1> LCL_VAR BB12 regmask=[rdi] minReg=1 last fixed> BB12 regmask=[rdi] minReg=1> PUTARG_REG BB12 regmask=[rdi] minReg=1 fixed> BB12 regmask=[rsi] minReg=1> LCL_VAR BB12 regmask=[rsi] minReg=1 fixed> BB12 regmask=[rsi] minReg=1> PUTARG_REG BB12 regmask=[rsi] minReg=1 fixed> BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 fixed> BB12 regmask=[rdx] minReg=1> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> BB12 regmask=[r8] minReg=1> LCL_VAR BB12 regmask=[r8] minReg=1 fixed> BB12 regmask=[r8] minReg=1> PUTARG_REG BB12 regmask=[r8] minReg=1 fixed> CNS_INT BB12 regmask=[allInt] minReg=1> BB12 regmask=[rdi] minReg=1> BB12 regmask=[rdi] minReg=1 last fixed> BB12 regmask=[rsi] minReg=1> BB12 regmask=[rsi] minReg=1 last fixed> BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[r8] minReg=1> BB12 regmask=[r8] minReg=1 last fixed> BB12 regmask=[allInt] minReg=1 last> BB12 regmask=[rax] minReg=1 last> BB12 regmask=[rcx] minReg=1 last> BB12 regmask=[rdx] minReg=1 last> BB12 regmask=[rsi] minReg=1 last> BB12 regmask=[rdi] minReg=1 last> BB12 regmask=[r8] minReg=1 last> BB12 regmask=[r9] minReg=1 last> BB12 regmask=[r10] minReg=1 last> BB12 regmask=[r11] minReg=1 last> BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[allInt] minReg=1 last regOptional> BB14 regmask=[rdi] minReg=1> LCL_VAR BB14 regmask=[rdi] minReg=1 fixed> BB14 regmask=[rdi] minReg=1> PUTARG_REG BB14 regmask=[rdi] minReg=1 fixed> BB14 regmask=[rsi] minReg=1> LCL_VAR BB14 regmask=[rsi] minReg=1 fixed> BB14 regmask=[rsi] minReg=1> PUTARG_REG BB14 regmask=[rsi] minReg=1 fixed> BB14 regmask=[rdx] minReg=1> LCL_VAR BB14 regmask=[rdx] minReg=1 fixed> BB14 regmask=[rdx] minReg=1> PUTARG_REG BB14 regmask=[rdx] minReg=1 fixed> CNS_INT BB14 regmask=[allInt] minReg=1> BB14 regmask=[rdi] minReg=1> BB14 regmask=[rdi] minReg=1 last fixed> BB14 regmask=[rsi] minReg=1> BB14 regmask=[rsi] minReg=1 last fixed> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> BB14 regmask=[allInt] minReg=1 last> BB14 regmask=[rax] minReg=1 last> BB14 regmask=[rcx] minReg=1 last> BB14 regmask=[rdx] minReg=1 last> BB14 regmask=[rsi] minReg=1 last> BB14 regmask=[rdi] minReg=1 last> BB14 regmask=[r8] minReg=1 last> BB14 regmask=[r9] minReg=1 last> BB14 regmask=[r10] minReg=1 last> BB14 regmask=[r11] minReg=1 last> BB14 regmask=[rax] minReg=1> CALL BB14 regmask=[rax] minReg=1 fixed> BB14 regmask=[allInt] minReg=1 last> CAST BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last regOptional> CNS_INT BB15 regmask=[allInt] minReg=1> BB15 regmask=[allInt] minReg=1 last> IND BB15 regmask=[rsi] minReg=1> BB15 regmask=[rsi] minReg=1> BB15 regmask=[rsi] minReg=1 last fixed> BB15 regmask=[rsi] minReg=1> PUTARG_REG BB15 regmask=[rsi] minReg=1 fixed> LCL_VAR_ADDR BB15 regmask=[rdi] minReg=1> BB15 regmask=[rdi] minReg=1> BB15 regmask=[rdi] minReg=1 last fixed> BB15 regmask=[rdi] minReg=1> PUTARG_REG BB15 regmask=[rdi] minReg=1 fixed> CNS_INT BB15 regmask=[allInt] minReg=1> BB15 regmask=[rsi] minReg=1> BB15 regmask=[rsi] minReg=1 last fixed> BB15 regmask=[rdi] minReg=1> BB15 regmask=[rdi] minReg=1 last fixed> BB15 regmask=[allInt] minReg=1 last> BB15 regmask=[rax] minReg=1 last> BB15 regmask=[rcx] minReg=1 last> BB15 regmask=[rdx] minReg=1 last> BB15 regmask=[rsi] minReg=1 last> BB15 regmask=[rdi] minReg=1 last> BB15 regmask=[r8] minReg=1 last> BB15 regmask=[r9] minReg=1 last> BB15 regmask=[r10] minReg=1 last> BB15 regmask=[r11] minReg=1 last> BB15 regmask=[rax] minReg=1> CALL BB15 regmask=[rax] minReg=1 fixed> BB15 regmask=[allInt] minReg=1 last regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB17 regmask=[rdi] minReg=1> LCL_VAR BB17 regmask=[rdi] minReg=1 fixed> BB17 regmask=[rdi] minReg=1> PUTARG_REG BB17 regmask=[rdi] minReg=1 fixed> BB17 regmask=[rsi] minReg=1> LCL_VAR BB17 regmask=[rsi] minReg=1 fixed> BB17 regmask=[rsi] minReg=1> PUTARG_REG BB17 regmask=[rsi] minReg=1 fixed> BB17 regmask=[rdx] minReg=1> LCL_VAR BB17 regmask=[rdx] minReg=1 fixed> BB17 regmask=[rdx] minReg=1> PUTARG_REG BB17 regmask=[rdx] minReg=1 fixed> CNS_INT BB17 regmask=[allInt] minReg=1> BB17 regmask=[rdi] minReg=1> BB17 regmask=[rdi] minReg=1 last fixed> BB17 regmask=[rsi] minReg=1> BB17 regmask=[rsi] minReg=1 last fixed> BB17 regmask=[rdx] minReg=1> BB17 regmask=[rdx] minReg=1 last fixed> BB17 regmask=[allInt] minReg=1 last> BB17 regmask=[rax] minReg=1 last> BB17 regmask=[rcx] minReg=1 last> BB17 regmask=[rdx] minReg=1 last> BB17 regmask=[rsi] minReg=1 last> BB17 regmask=[rdi] minReg=1 last> BB17 regmask=[r8] minReg=1 last> BB17 regmask=[r9] minReg=1 last> BB17 regmask=[r10] minReg=1 last> BB17 regmask=[r11] minReg=1 last> BB17 regmask=[rax] minReg=1> CALL BB17 regmask=[rax] minReg=1 fixed> BB17 regmask=[allInt] minReg=1 last regOptional> BB17 regmask=[allInt] minReg=1 regOptional> CNS_INT BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 regOptional> BB18 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB19 regmask=[allInt] minReg=1 regOptional> CNS_INT BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rdi] minReg=1> PUTARG_REG BB20 regmask=[rdi] minReg=1 fixed> CNS_INT BB20 regmask=[allInt] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[rax] minReg=1> CALL BB20 regmask=[rax] minReg=1 fixed> BB20 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1> IND BB20 regmask=[allInt] minReg=1> BB20 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB20 regmask=[allInt] minReg=1> LEA BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 fixed> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[mm0] minReg=1 last> BB20 regmask=[mm1] minReg=1 last> BB20 regmask=[mm2] minReg=1 last> BB20 regmask=[mm3] minReg=1 last> BB20 regmask=[mm4] minReg=1 last> BB20 regmask=[mm5] minReg=1 last> BB20 regmask=[mm6] minReg=1 last> BB20 regmask=[mm7] minReg=1 last> BB20 regmask=[mm8] minReg=1 last> BB20 regmask=[mm9] minReg=1 last> BB20 regmask=[mm10] minReg=1 last> BB20 regmask=[mm11] minReg=1 last> BB20 regmask=[mm12] minReg=1 last> BB20 regmask=[mm13] minReg=1 last> BB20 regmask=[mm14] minReg=1 last> BB20 regmask=[mm15] minReg=1 last> LCL_VAR BB20 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB20 regmask=[allInt] minReg=1> LEA BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[mm0] minReg=1 last> BB20 regmask=[mm1] minReg=1 last> BB20 regmask=[mm2] minReg=1 last> BB20 regmask=[mm3] minReg=1 last> BB20 regmask=[mm4] minReg=1 last> BB20 regmask=[mm5] minReg=1 last> BB20 regmask=[mm6] minReg=1 last> BB20 regmask=[mm7] minReg=1 last> BB20 regmask=[mm8] minReg=1 last> BB20 regmask=[mm9] minReg=1 last> BB20 regmask=[mm10] minReg=1 last> BB20 regmask=[mm11] minReg=1 last> BB20 regmask=[mm12] minReg=1 last> BB20 regmask=[mm13] minReg=1 last> BB20 regmask=[mm14] minReg=1 last> BB20 regmask=[mm15] minReg=1 last> CNS_INT BB20 regmask=[allInt] minReg=1> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[rax] minReg=1> CALL BB20 regmask=[rax] minReg=1 fixed> BB20 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> CNS_INT BB20 regmask=[allInt] minReg=1> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[rax] minReg=1> CALL BB20 regmask=[rax] minReg=1 fixed> BB20 regmask=[allInt] minReg=1 last> IND BB20 regmask=[allInt] minReg=1> BB20 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rsi] minReg=1> PUTARG_REG BB20 regmask=[rsi] minReg=1 fixed> BB20 regmask=[rdi] minReg=1> LCL_VAR BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[rdi] minReg=1> PUTARG_REG BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[rcx] minReg=1> LCL_VAR BB20 regmask=[rcx] minReg=1 last fixed> BB20 regmask=[rcx] minReg=1> PUTARG_REG BB20 regmask=[rcx] minReg=1 fixed> CNS_INT BB20 regmask=[rdx] minReg=1> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rdx] minReg=1 last fixed> BB20 regmask=[rdx] minReg=1> PUTARG_REG BB20 regmask=[rdx] minReg=1 fixed> CNS_INT BB20 regmask=[allInt] minReg=1> BB20 regmask=[rsi] minReg=1> BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rcx] minReg=1> BB20 regmask=[rcx] minReg=1 last fixed> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rdx] minReg=1 last fixed> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> CNS_INT BB20 regmask=[allInt] minReg=1> STORE_BLK BB20 regmask=[allFloat] minReg=1> BB20 regmask=[allInt] minReg=1 last> STORE_BLK BB20 regmask=[allFloat] minReg=1 last> LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rdi] minReg=1> PUTARG_STK BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[rcx] minReg=1> PUTARG_STK BB20 regmask=[rcx] minReg=1 fixed> BB20 regmask=[rsi] minReg=1> PUTARG_STK BB20 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB20 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB20 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rdi] minReg=1> LCL_VAR BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[rdi] minReg=1> PUTARG_REG BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[r11] minReg=1> CNS_INT BB20 regmask=[r11] minReg=1 fixed> BB20 regmask=[r11] minReg=1> BB20 regmask=[r11] minReg=1 last fixed> BB20 regmask=[r11] minReg=1> PUTARG_REG BB20 regmask=[r11] minReg=1 fixed> CNS_INT BB20 regmask=[allInt] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[r11] minReg=1> BB20 regmask=[r11] minReg=1 last fixed> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> CNS_INT BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> BB22 regmask=[rdi] minReg=1> LCL_VAR BB22 regmask=[rdi] minReg=1 fixed> BB22 regmask=[rdi] minReg=1> PUTARG_REG BB22 regmask=[rdi] minReg=1 fixed> BB22 regmask=[rsi] minReg=1> LCL_VAR BB22 regmask=[rsi] minReg=1 fixed> BB22 regmask=[rsi] minReg=1> PUTARG_REG BB22 regmask=[rsi] minReg=1 fixed> BB22 regmask=[rdx] minReg=1> LCL_VAR BB22 regmask=[rdx] minReg=1 fixed> BB22 regmask=[rdx] minReg=1> PUTARG_REG BB22 regmask=[rdx] minReg=1 fixed> CNS_INT BB22 regmask=[allInt] minReg=1> BB22 regmask=[rdi] minReg=1> BB22 regmask=[rdi] minReg=1 last fixed> BB22 regmask=[rsi] minReg=1> BB22 regmask=[rsi] minReg=1 last fixed> BB22 regmask=[rdx] minReg=1> BB22 regmask=[rdx] minReg=1 last fixed> BB22 regmask=[allInt] minReg=1 last> BB22 regmask=[rax] minReg=1 last> BB22 regmask=[rcx] minReg=1 last> BB22 regmask=[rdx] minReg=1 last> BB22 regmask=[rsi] minReg=1 last> BB22 regmask=[rdi] minReg=1 last> BB22 regmask=[r8] minReg=1 last> BB22 regmask=[r9] minReg=1 last> BB22 regmask=[r10] minReg=1 last> BB22 regmask=[r11] minReg=1 last> BB22 regmask=[rax] minReg=1> CALL BB22 regmask=[rax] minReg=1 fixed> BB22 regmask=[allInt] minReg=1 last regOptional> BB22 regmask=[allInt] minReg=1 regOptional> CNS_INT BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> BB24 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB25 regmask=[allInt] minReg=1 regOptional> CNS_INT BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> CNS_INT BB26 regmask=[allInt] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[rax] minReg=1> CALL BB26 regmask=[rax] minReg=1 fixed> BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1> LEA BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 fixed> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[mm0] minReg=1 last> BB26 regmask=[mm1] minReg=1 last> BB26 regmask=[mm2] minReg=1 last> BB26 regmask=[mm3] minReg=1 last> BB26 regmask=[mm4] minReg=1 last> BB26 regmask=[mm5] minReg=1 last> BB26 regmask=[mm6] minReg=1 last> BB26 regmask=[mm7] minReg=1 last> BB26 regmask=[mm8] minReg=1 last> BB26 regmask=[mm9] minReg=1 last> BB26 regmask=[mm10] minReg=1 last> BB26 regmask=[mm11] minReg=1 last> BB26 regmask=[mm12] minReg=1 last> BB26 regmask=[mm13] minReg=1 last> BB26 regmask=[mm14] minReg=1 last> BB26 regmask=[mm15] minReg=1 last> CNS_INT BB26 regmask=[allInt] minReg=1> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[rax] minReg=1> CALL BB26 regmask=[rax] minReg=1 fixed> BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> CNS_INT BB26 regmask=[allInt] minReg=1> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[rax] minReg=1> CALL BB26 regmask=[rax] minReg=1 fixed> BB26 regmask=[allInt] minReg=1 last> IND BB26 regmask=[allInt] minReg=1> BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rsi] minReg=1> PUTARG_REG BB26 regmask=[rsi] minReg=1 fixed> BB26 regmask=[rdi] minReg=1> LCL_VAR BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rcx] minReg=1> LCL_VAR BB26 regmask=[rcx] minReg=1 last fixed> BB26 regmask=[rcx] minReg=1> PUTARG_REG BB26 regmask=[rcx] minReg=1 fixed> CNS_INT BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> PUTARG_REG BB26 regmask=[rdx] minReg=1 fixed> CNS_INT BB26 regmask=[allInt] minReg=1> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rcx] minReg=1> BB26 regmask=[rcx] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> LCL_VAR_ADDR BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 fixed> BB26 regmask=[rsi] minReg=1> PUTARG_REG BB26 regmask=[rsi] minReg=1 fixed> BB26 regmask=[rdx] minReg=1> LCL_VAR BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> PUTARG_REG BB26 regmask=[rdx] minReg=1 fixed> CNS_INT BB26 regmask=[allInt] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[rdi] minReg=1> PUTARG_STK BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rcx] minReg=1> PUTARG_STK BB26 regmask=[rcx] minReg=1 fixed> BB26 regmask=[rsi] minReg=1> PUTARG_STK BB26 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB26 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB26 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> LCL_VAR BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[r11] minReg=1> CNS_INT BB26 regmask=[r11] minReg=1 fixed> BB26 regmask=[r11] minReg=1> BB26 regmask=[r11] minReg=1 last fixed> BB26 regmask=[r11] minReg=1> PUTARG_REG BB26 regmask=[r11] minReg=1 fixed> CNS_INT BB26 regmask=[allInt] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[r11] minReg=1> BB26 regmask=[r11] minReg=1 last fixed> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> CNS_INT BB27 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB27 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> CNS_INT BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB29 regmask=[rax] minReg=1 last> BB29 regmask=[rcx] minReg=1 last> BB29 regmask=[rdx] minReg=1 last> BB29 regmask=[rsi] minReg=1 last> BB29 regmask=[rdi] minReg=1 last> BB29 regmask=[r8] minReg=1 last> BB29 regmask=[r9] minReg=1 last> BB29 regmask=[r10] minReg=1 last> BB29 regmask=[r11] minReg=1 last> ----------------- BB00 regmask=[rdx] minReg=1 fixed regOptional> LCL_VAR BB03 regmask=[rdi] minReg=1 fixed> LCL_VAR BB04 regmask=[rdi] minReg=1 fixed> LCL_VAR BB05 regmask=[rdi] minReg=1 fixed> LCL_VAR BB06 regmask=[rdi] minReg=1 fixed> LCL_VAR BB12 regmask=[rsi] minReg=1 fixed> BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB17 regmask=[rdi] minReg=1 fixed> LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB22 regmask=[rdi] minReg=1 fixed> BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB26 regmask=[rsi] minReg=1 fixed> BB28 regmask=[allInt] minReg=1 regOptional> ----------------- BB00 regmask=[rcx] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[rdi] minReg=1 fixed> LCL_VAR BB02 regmask=[rdi] minReg=1 fixed> LCL_VAR BB12 regmask=[rdx] minReg=1 fixed> LCL_VAR BB14 regmask=[rdi] minReg=1 fixed> BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB17 regmask=[rsi] minReg=1 fixed> LCL_VAR BB20 regmask=[rsi] minReg=1 fixed> LCL_VAR BB22 regmask=[rsi] minReg=1 fixed> BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB26 regmask=[rsi] minReg=1 fixed> BB28 regmask=[allInt] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last> ----------------- BB00 regmask=[r9] minReg=1 fixed regOptional> LCL_VAR BB06 regmask=[rsi] minReg=1 fixed> LCL_VAR BB10 regmask=[rsi] minReg=1 fixed> LCL_VAR BB12 regmask=[r8] minReg=1 fixed> LCL_VAR BB14 regmask=[rdx] minReg=1 fixed> BB15 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> ----------------- BB00 regmask=[rsi] minReg=1 fixed regOptional> LCL_VAR BB09 regmask=[rsi] minReg=1 fixed> BB15 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> ----------------- BB00 regmask=[r8] minReg=1 fixed regOptional> LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB17 regmask=[rdx] minReg=1 fixed> LCL_VAR BB19 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB20 regmask=[rdi] minReg=1 fixed> LCL_VAR BB22 regmask=[rdx] minReg=1 fixed> BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB25 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB26 regmask=[rdi] minReg=1 fixed> BB28 regmask=[allInt] minReg=1 regOptional> ----------------- BB00 regmask=[rdi] minReg=1 fixed regOptional> LCL_VAR BB12 regmask=[rdi] minReg=1 last fixed> BB18 regmask=[allInt] minReg=1 regOptional> CheckConstraints: LocalVar V00: undefined use at 451 BB23 regmask=[allInt] minReg=1 regOptional> CheckConstraints: LocalVar V00: undefined use at 637 BB27 regmask=[allInt] minReg=1 regOptional> CheckConstraints: LocalVar V00: undefined use at 781 ----------------- STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1 last> BB17 regmask=[allInt] minReg=1 regOptional> CheckConstraints: LocalVar V07: undefined use at 443 STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> BB22 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB27 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[rax] minReg=1 last fixed> STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> BB24 regmask=[allInt] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 fixed> LCL_VAR BB10 regmask=[rdi] minReg=1 fixed> LCL_VAR BB14 regmask=[rsi] minReg=1 fixed> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[rdi] minReg=1 fixed> LCL_VAR BB20 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB20 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[rdi] minReg=1 fixed> LCL_VAR BB26 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 last fixed> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V02 V03 V05 V01 V04 V00 BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} ===== N003. V03(L3) N005. PUTARG_REG Use:(#8) Fixed:rdi(#7) Def:(#10) rdi Pref: N007. CNS_INT(h) 0xd1ffab1e ftn Def:(#12) r11 N009. PUTARG_REG Use:(#14) Fixed:r11(#13) * Def:(#16) r11 N011. CNS_INT(h) 0xd1ffab1e ftn Def:(#17) N013. IND N015. CALLV stub Use:(#19) Fixed:rdi(#18) * Use:(#21) Fixed:r11(#20) * Use:(#22) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#33) rax N017. CNS_INT 4 N019. EQ Use:(#34) * N021. JTRUE BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} ===== N025. IL_OFFSET IL offset: 0xf N027. CNS_INT 1 N029. V07(L7) Def:(#36) Pref: N031. V03(L3) N033. PUTARG_REG Use:(#38) Fixed:rdi(#37) Def:(#40) rdi Pref: N035. CNS_INT(h) 0xd1ffab1e ftn Def:(#42) r11 N037. PUTARG_REG Use:(#44) Fixed:r11(#43) * Def:(#46) r11 N039. CNS_INT(h) 0xd1ffab1e ftn Def:(#47) N041. IND N043. CALLV stub Use:(#49) Fixed:rdi(#48) * Use:(#51) Fixed:r11(#50) * Use:(#52) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#63) rax N045. CAST Use:(#64) * Def:(#65) N047. PUTARG_REG Use:(#67) Fixed:rdi(#66) * Def:(#69) rdi N049. CNS_INT(h) 0xd1ffab1e ftn Def:(#70) N051. IND N053. CALL r2r_ind Use:(#72) Fixed:rdi(#71) * Use:(#73) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#84) rax N055. CNS_INT 0 N057. NE Use:(#85) * N059. JTRUE BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} ===== N063. IL_OFFSET IL offset: 0x40 N065. V02(L2) N067. PUTARG_REG Use:(#88) Fixed:rdi(#87) Def:(#90) rdi Pref: N069. CNS_INT(h) 0xd1ffab1e ftn Def:(#92) r11 N071. PUTARG_REG Use:(#94) Fixed:r11(#93) * Def:(#96) r11 N073. CNS_INT(h) 0xd1ffab1e ftn Def:(#97) N075. IND N077. CALLV stub Use:(#99) Fixed:rdi(#98) * Use:(#101) Fixed:r11(#100) * Use:(#102) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#113) rax N079. CNS_INT 0 N081. NE Use:(#114) * N083. JTRUE BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} ===== N087. IL_OFFSET IL offset: 0x55 N089. V02(L2) N091. PUTARG_REG Use:(#117) Fixed:rdi(#116) Def:(#119) rdi Pref: N093. CNS_INT(h) 0xd1ffab1e ftn Def:(#121) r11 N095. PUTARG_REG Use:(#123) Fixed:r11(#122) * Def:(#125) r11 N097. CNS_INT(h) 0xd1ffab1e ftn Def:(#126) N099. IND N101. CALLV stub Use:(#128) Fixed:rdi(#127) * Use:(#130) Fixed:r11(#129) * Use:(#131) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#142) rax N103. CNS_INT 0 N105. NE Use:(#143) * N107. JTRUE BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} ===== N111. IL_OFFSET IL offset: 0x6a N113. V02(L2) N115. PUTARG_REG Use:(#146) Fixed:rdi(#145) Def:(#148) rdi Pref: N117. CNS_INT(h) 0xd1ffab1e ftn Def:(#150) r11 N119. PUTARG_REG Use:(#152) Fixed:r11(#151) * Def:(#154) r11 N121. CNS_INT(h) 0xd1ffab1e ftn Def:(#155) N123. IND N125. CALLV stub Use:(#157) Fixed:rdi(#156) * Use:(#159) Fixed:r11(#158) * Use:(#160) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#171) rax N127. CNS_INT 0 N129. NE Use:(#172) * N131. JTRUE BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} ===== N135. V02(L2) N137. PUTARG_REG Use:(#175) Fixed:rdi(#174) Def:(#177) rdi Pref: N139. V05(L5) N141. PUTARG_REG Use:(#179) Fixed:rsi(#178) Def:(#181) rsi Pref: N143. CNS_INT(h) 0xd1ffab1e ftn Def:(#182) N145. IND N147. CALL r2r_ind Use:(#184) Fixed:rdi(#183) * Use:(#186) Fixed:rsi(#185) * Use:(#187) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#198) rax N149. V23 MEM Use:(#199) * N151. IL_OFFSET IL offset: 0x8b N153. CNS_INT(h) 0xd1ffab1e class Def:(#200) N155. IND Use:(#201) * Def:(#202) N157. PUTARG_REG Use:(#204) Fixed:rsi(#203) * Def:(#206) rsi N159. LCL_VAR_ADDR V09 loc3 NA ref V09.array (offs=0x00) -> V23 tmp12 Def:(#207) N161. PUTARG_REG Use:(#209) Fixed:rdi(#208) * Def:(#211) rdi N163. CNS_INT(h) 0xd1ffab1e ftn Def:(#212) N165. IND N167. CALL r2r_ind Use:(#214) Fixed:rsi(#213) * Use:(#216) Fixed:rdi(#215) * Use:(#217) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#228) rax Def:(#230) rdx N169. V12 MEM Use:(#231) * Use:(#232) * N171. LCL_VAR_ADDR V12 tmp1 NA Def:(#233) Pref: N173. V25(L15) Use:(#234) * Def:(#235) N175. V25(L15) N177. IND Use:(#236) Def:(#237) N179. V21 MEM Use:(#238) * N181. V25(L15) N183. LEA(b+8) N185. IND Use:(#239) * Def:(#240) N187. V22 MEM Use:(#241) * N189. IL_OFFSET IL offset: 0xe1 N191. CNS_INT(h) 0xd1ffab1e class Def:(#242) N193. IND Use:(#243) * Def:(#244) N195. PUTARG_REG Use:(#246) Fixed:rsi(#245) * Def:(#248) rsi N197. LCL_VAR_ADDR V08 loc2 NA ref V08._array (offs=0x00) -> V21 tmp10 int V08._index (offs=0x08) -> V22 tmp11 Def:(#249) N199. PUTARG_REG Use:(#251) Fixed:rdi(#250) * Def:(#253) rdi N201. CNS_INT(h) 0xd1ffab1e ftn Def:(#254) N203. IND N205. CALL r2r_ind Use:(#256) Fixed:rsi(#255) * Use:(#258) Fixed:rdi(#257) * Use:(#259) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#270) rax N207. CNS_INT 0 N209. NE Use:(#271) * N211. JTRUE BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} ===== N215. IL_OFFSET IL offset: 0xea N217. V07(L7) N219. V06(L6) Use:(#273) * Def:(#274) BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} ===== N223. IL_OFFSET IL offset: 0xec N225. V06(L6) N227. RETURN Use:(#277) Fixed:rax(#276) * BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} ===== N231. IL_OFFSET IL offset: 0x95 N233. CNS_INT(h) 0xd1ffab1e class Def:(#279) N235. IND Use:(#280) * Def:(#281) N237. PUTARG_REG Use:(#283) Fixed:rsi(#282) * Def:(#285) rsi N239. LCL_VAR_ADDR V08 loc2 NA ref V08._array (offs=0x00) -> V21 tmp10 int V08._index (offs=0x08) -> V22 tmp11 Def:(#286) N241. PUTARG_REG Use:(#288) Fixed:rdi(#287) * Def:(#290) rdi N243. CNS_INT(h) 0xd1ffab1e ftn Def:(#291) N245. IND N247. CALL r2r_ind Use:(#293) Fixed:rsi(#292) * Use:(#295) Fixed:rdi(#294) * Use:(#296) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#307) rax Pref: N249. V26(L16) Use:(#308) * Def:(#309) N251. V26(L16) N253. PUTARG_REG Use:(#311) Fixed:rdi(#310) * Def:(#313) rdi N255. V01(L1) N257. PUTARG_REG Use:(#315) Fixed:rsi(#314) Def:(#317) rsi Pref: N259. CNS_INT(h) 0xd1ffab1e ftn Def:(#319) r11 N261. PUTARG_REG Use:(#321) Fixed:r11(#320) * Def:(#323) r11 N263. CNS_INT(h) 0xd1ffab1e ftn Def:(#324) N265. IND N267. CALLV stub Use:(#326) Fixed:rdi(#325) * Use:(#328) Fixed:rsi(#327) * Use:(#330) Fixed:r11(#329) * Use:(#331) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#342) rax Def:(#344) rdx N269. V13 MEM Use:(#345) * Use:(#346) * N271. V13 MEM Def:(#347) Pref: N273. V10(L8) Use:(#348) * Def:(#349) N275. IL_OFFSET IL offset: 0xa9 N277. V10(L8) N279. PUTARG_REG Use:(#351) Fixed:rdi(#350) Def:(#353) rdi Pref: N281. CNS_INT(h) 0xd1ffab1e ftn Def:(#355) r11 N283. PUTARG_REG Use:(#357) Fixed:r11(#356) * Def:(#359) r11 N285. CNS_INT(h) 0xd1ffab1e ftn Def:(#360) N287. IND N289. CALLV stub Use:(#362) Fixed:rdi(#361) * Use:(#364) Fixed:r11(#363) * Use:(#365) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#376) rax N291. CNS_INT 4 N293. NE Use:(#377) * N295. JTRUE BB10 [0A9..0AA) -> BB19 (always), preds={BB09} succs={BB19} ===== N299. IL_OFFSET IL offset: 0xa9 N301. V10(L8) N303. PUTARG_REG Use:(#380) Fixed:rdi(#379) Def:(#382) rdi Pref: N305. V05(L5) N307. PUTARG_REG Use:(#384) Fixed:rsi(#383) Def:(#386) rsi Pref: N309. CNS_INT(h) 0xd1ffab1e ftn Def:(#387) N311. IND N313. CALL r2r_ind Use:(#389) Fixed:rdi(#388) * Use:(#391) Fixed:rsi(#390) * Use:(#392) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 N315. IL_OFFSET IL offset: 0xa9 BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} ===== N319. IL_OFFSET IL offset: 0x72 N321. V00(L0) N323. PUTARG_REG Use:(#404) Fixed:rdi(#403) * Def:(#406) rdi N325. V02(L2) N327. PUTARG_REG Use:(#408) Fixed:rsi(#407) Def:(#410) rsi Pref: N329. V03(L3) N331. PUTARG_REG Use:(#412) Fixed:rdx(#411) Def:(#414) rdx Pref: N333. V04(L4) N335. PUTARG_REG Use:(#416) Fixed:rcx(#415) Def:(#418) rcx Pref: N337. V05(L5) N339. PUTARG_REG Use:(#420) Fixed:r8(#419) Def:(#422) r8 Pref: N341. CNS_INT(h) 0xd1ffab1e ftn Def:(#423) N343. IND N345. CALL r2r_ind Use:(#425) Fixed:rdi(#424) * Use:(#427) Fixed:rsi(#426) * Use:(#429) Fixed:rdx(#428) * Use:(#431) Fixed:rcx(#430) * Use:(#433) Fixed:r8(#432) * Use:(#434) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#445) rax N347. CNS_INT 0 N349. EQ Use:(#446) * N351. JTRUE BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ===== BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} ===== N357. IL_OFFSET IL offset: 0xa9 N359. V03(L3) N361. PUTARG_REG Use:(#450) Fixed:rdi(#449) Def:(#452) rdi Pref: N363. V10(L8) N365. PUTARG_REG Use:(#454) Fixed:rsi(#453) Def:(#456) rsi Pref: N367. V05(L5) N369. PUTARG_REG Use:(#458) Fixed:rdx(#457) Def:(#460) rdx Pref: N371. CNS_INT(h) 0xd1ffab1e ftn Def:(#461) N373. IND N375. CALL r2r_ind Use:(#463) Fixed:rdi(#462) * Use:(#465) Fixed:rsi(#464) * Use:(#467) Fixed:rdx(#466) * Use:(#468) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#479) rax N377. CAST Use:(#480) * Def:(#481) Pref: N379. V19(L12) Use:(#482) * Def:(#483) N381. V19(L12) N383. CNS_INT 0 N385. EQ Use:(#484) * N387. JTRUE BB15 [0E1..0EA) -> BB09 (cond), preds={BB14,BB21} succs={BB16,BB09} ===== N391. IL_OFFSET IL offset: 0xe1 N393. CNS_INT(h) 0xd1ffab1e class Def:(#486) N395. IND Use:(#487) * Def:(#488) N397. PUTARG_REG Use:(#490) Fixed:rsi(#489) * Def:(#492) rsi N399. LCL_VAR_ADDR V08 loc2 NA ref V08._array (offs=0x00) -> V21 tmp10 int V08._index (offs=0x08) -> V22 tmp11 Def:(#493) N401. PUTARG_REG Use:(#495) Fixed:rdi(#494) * Def:(#497) rdi N403. CNS_INT(h) 0xd1ffab1e ftn Def:(#498) N405. IND N407. CALL r2r_ind Use:(#500) Fixed:rsi(#499) * Use:(#502) Fixed:rdi(#501) * Use:(#503) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#514) rax N409. CNS_INT 0 N411. NE Use:(#515) * N413. JTRUE Exposed use of V02 at #516 Exposed use of V03 at #517 Exposed use of V05 at #518 Exposed use of V01 at #519 Exposed use of V04 at #520 BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ===== BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} ===== N419. V02(L2) N421. PUTARG_REG Use:(#524) Fixed:rdi(#523) Def:(#526) rdi Pref: N423. V03(L3) N425. PUTARG_REG Use:(#528) Fixed:rsi(#527) Def:(#530) rsi Pref: N427. V04(L4) N429. PUTARG_REG Use:(#532) Fixed:rdx(#531) Def:(#534) rdx Pref: N431. CNS_INT(h) 0xd1ffab1e ftn Def:(#535) N433. IND N435. CALL r2r_ind Use:(#537) Fixed:rdi(#536) * Use:(#539) Fixed:rsi(#538) * Use:(#541) Fixed:rdx(#540) * Use:(#542) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#553) rax N437. CNS_INT 0 N439. NE Use:(#554) * N441. JTRUE Exposed use of V07 at #555 BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} ===== N445. IL_OFFSET IL offset: 0x68 N447. CNS_INT 0 Def:(#557) Pref: N449. V07(L7) Use:(#558) * Def:(#559) Pref: Exposed use of V00 at #560 Exposed use of V07 at #561 BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB10} succs={BB20,BB21} ===== N453. IL_OFFSET IL offset: 0xb5 N455. V04(L4) N457. CNS_INT null N459. EQ Use:(#563) N461. JTRUE BB20 [0B9..0DF), preds={BB19} succs={BB21} ===== N465. IL_OFFSET IL offset: 0xb9 N467. CNS_INT 2 Def:(#565) N469. PUTARG_REG Use:(#567) Fixed:rdi(#566) * Def:(#569) rdi N471. CNS_INT(h) 0xd1ffab1e ftn Def:(#570) N473. IND N475. CALL help r2r_ind Use:(#572) Fixed:rdi(#571) * Use:(#573) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#584) rax Pref: N477. V14(L9) Use:(#585) * Def:(#586) N479. CNS_INT 0 N481. V14(L9) N483. LEA(b+8) N485. IND Use:(#587) Def:(#588) Pref: N487. V28(L18) Use:(#589) * Def:(#590) N489. V28(L18) N491. ARR_BOUNDS_CHECK_Rng Use:(#591) N493. V14(L9) N495. LEA(b+16) Use:(#592) Def:(#593) N497. V03(L3) N499. STOREIND Use:(#595) Fixed:rdi(#594) * Use:(#597) Fixed:rsi(#596) Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7 mm8 mm9 mm10 mm11 mm12 mm13 mm14 mm15 N501. CNS_INT 1 N503. V28(L18) N505. ARR_BOUNDS_CHECK_Rng Use:(#623) * N507. V14(L9) N509. LEA(b+24) Use:(#624) Def:(#625) N511. V10(L8) N513. STOREIND Use:(#627) Fixed:rdi(#626) * Use:(#629) Fixed:rsi(#628) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7 mm8 mm9 mm10 mm11 mm12 mm13 mm14 mm15 N515. CNS_INT(h) 0xd1ffab1e ftn Def:(#655) N517. IND N519. CALL help r2r_ind Use:(#656) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#667) rax Pref: N521. V20(L13) Use:(#668) * Def:(#669) N523. CNS_INT(h) 0xd1ffab1e ftn Def:(#670) N525. IND N527. CALL help r2r_ind Use:(#671) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#682) rax N529. LEA(b+1048) N531. IND Use:(#683) * Def:(#684) Pref: N533. V27(L17) Use:(#685) * Def:(#686) N535. V27(L17) N537. PUTARG_REG Use:(#688) Fixed:rsi(#687) * Def:(#690) rsi N539. V20(L13) N541. PUTARG_REG Use:(#692) Fixed:rdi(#691) Def:(#694) rdi Pref: N543. V14(L9) N545. PUTARG_REG Use:(#696) Fixed:rcx(#695) * Def:(#698) rcx N547. CNS_INT 0x7D2C Def:(#699) N549. PUTARG_REG Use:(#701) Fixed:rdx(#700) * Def:(#703) rdx N551. CNS_INT(h) 0xd1ffab1e ftn Def:(#704) N553. IND N555. CALL r2r_ind Use:(#706) Fixed:rsi(#705) * Use:(#708) Fixed:rdi(#707) * Use:(#710) Fixed:rcx(#709) * Use:(#712) Fixed:rdx(#711) * Use:(#713) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 N557. CNS_INT 0 Def:(#723) N559. LCL_VAR_ADDR V15 tmp4 NA N561. STORE_BLK Def:(#724) Use:(#725) * Use:(#726) * N563. V02(L2) N565. V15 MEM Use:(#727) N567. V20(L13) N569. V15 MEM Use:(#728) * N571. IL_OFFSET IL offset: 0xda N573. LCL_VAR_ADDR V15 tmp4 u:4 NA (last use) N575. OBJ N577. PUTARG_STK [+0x00] Def:(#730) rdi Def:(#732) rcx Def:(#734) rsi Use:(#735) * Use:(#736) * Use:(#737) * N579. V04(L4) N581. PUTARG_REG Use:(#739) Fixed:rdi(#738) Def:(#741) rdi Pref: N583. CNS_INT(h) 0xd1ffab1e ftn Def:(#743) r11 N585. PUTARG_REG Use:(#745) Fixed:r11(#744) * Def:(#747) r11 N587. CNS_INT(h) 0xd1ffab1e ftn Def:(#748) N589. IND N591. CALLV stub Use:(#750) Fixed:rdi(#749) * Use:(#752) Fixed:r11(#751) * Use:(#753) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} ===== N595. IL_OFFSET IL offset: 0xdf N597. CNS_INT 0 Def:(#764) Pref: N599. V07(L7) Use:(#765) * Def:(#766) Pref: BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} ===== N603. IL_OFFSET IL offset: 0x48 N605. V02(L2) N607. PUTARG_REG Use:(#769) Fixed:rdi(#768) Def:(#771) rdi Pref: N609. V03(L3) N611. PUTARG_REG Use:(#773) Fixed:rsi(#772) Def:(#775) rsi Pref: N613. V04(L4) N615. PUTARG_REG Use:(#777) Fixed:rdx(#776) Def:(#779) rdx Pref: N617. CNS_INT(h) 0xd1ffab1e ftn Def:(#780) N619. IND N621. CALL r2r_ind Use:(#782) Fixed:rdi(#781) * Use:(#784) Fixed:rsi(#783) * Use:(#786) Fixed:rdx(#785) * Use:(#787) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#798) rax N623. CNS_INT 0 N625. NE Use:(#799) * N627. JTRUE Exposed use of V07 at #800 BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} ===== N631. IL_OFFSET IL offset: 0x53 N633. CNS_INT 0 Def:(#802) Pref: N635. V07(L7) Use:(#803) * Def:(#804) Pref: Exposed use of V02 at #805 Exposed use of V03 at #806 Exposed use of V05 at #807 Exposed use of V01 at #808 Exposed use of V04 at #809 Exposed use of V00 at #810 Exposed use of V07 at #811 BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} ===== N639. IL_OFFSET IL offset: 0x8 N641. CNS_INT 1 N643. V06(L6) Def:(#813) Exposed use of V06 at #814 BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} ===== N647. IL_OFFSET IL offset: 0x19 N649. V04(L4) N651. CNS_INT null N653. EQ Use:(#816) N655. JTRUE BB26 [01D..03E), preds={BB25} succs={BB27} ===== N659. IL_OFFSET IL offset: 0x1d N661. CNS_INT 1 Def:(#818) N663. PUTARG_REG Use:(#820) Fixed:rdi(#819) * Def:(#822) rdi N665. CNS_INT(h) 0xd1ffab1e ftn Def:(#823) N667. IND N669. CALL help r2r_ind Use:(#825) Fixed:rdi(#824) * Use:(#826) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#837) rax Pref: N671. V16(L10) Use:(#838) * Def:(#839) N673. CNS_INT 0 N675. V16(L10) N677. LEA(b+8) N679. IND N681. ARR_BOUNDS_CHECK_Rng Use:(#840) N683. V16(L10) N685. LEA(b+16) Use:(#841) Def:(#842) N687. V03(L3) N689. STOREIND Use:(#844) Fixed:rdi(#843) * Use:(#846) Fixed:rsi(#845) Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7 mm8 mm9 mm10 mm11 mm12 mm13 mm14 mm15 N691. CNS_INT(h) 0xd1ffab1e ftn Def:(#872) N693. IND N695. CALL help r2r_ind Use:(#873) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#884) rax Pref: N697. V18(L11) Use:(#885) * Def:(#886) N699. CNS_INT(h) 0xd1ffab1e ftn Def:(#887) N701. IND N703. CALL help r2r_ind Use:(#888) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#899) rax N705. LEA(b+1048) N707. IND Use:(#900) * Def:(#901) Pref: N709. V24(L14) Use:(#902) * Def:(#903) N711. V24(L14) N713. PUTARG_REG Use:(#905) Fixed:rsi(#904) * Def:(#907) rsi N715. V18(L11) N717. PUTARG_REG Use:(#909) Fixed:rdi(#908) Def:(#911) rdi Pref: N719. V16(L10) N721. PUTARG_REG Use:(#913) Fixed:rcx(#912) * Def:(#915) rcx N723. CNS_INT 0x7AA4 Def:(#916) N725. PUTARG_REG Use:(#918) Fixed:rdx(#917) * Def:(#920) rdx N727. CNS_INT(h) 0xd1ffab1e ftn Def:(#921) N729. IND N731. CALL r2r_ind Use:(#923) Fixed:rsi(#922) * Use:(#925) Fixed:rdi(#924) * Use:(#927) Fixed:rcx(#926) * Use:(#929) Fixed:rdx(#928) * Use:(#930) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 N733. LCL_VAR_ADDR V17 tmp6 NA Def:(#940) N735. PUTARG_REG Use:(#942) Fixed:rdi(#941) * Def:(#944) rdi N737. V02(L2) N739. PUTARG_REG Use:(#946) Fixed:rsi(#945) Def:(#948) rsi Pref: N741. V18(L11) N743. PUTARG_REG Use:(#950) Fixed:rdx(#949) * Def:(#952) rdx N745. CNS_INT(h) 0xd1ffab1e ftn Def:(#953) N747. IND N749. CALL r2r_ind Use:(#955) Fixed:rdi(#954) * Use:(#957) Fixed:rsi(#956) * Use:(#959) Fixed:rdx(#958) * Use:(#960) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 N751. IL_OFFSET IL offset: 0x39 N753. LCL_VAR_ADDR V17 tmp6 NA N755. OBJ N757. PUTARG_STK [+0x00] Def:(#971) rdi Def:(#973) rcx Def:(#975) rsi Use:(#976) * Use:(#977) * Use:(#978) * N759. V04(L4) N761. PUTARG_REG Use:(#980) Fixed:rdi(#979) Def:(#982) rdi Pref: N763. CNS_INT(h) 0xd1ffab1e ftn Def:(#984) r11 N765. PUTARG_REG Use:(#986) Fixed:r11(#985) * Def:(#988) r11 N767. CNS_INT(h) 0xd1ffab1e ftn Def:(#989) N769. IND N771. CALLV stub Use:(#991) Fixed:rdi(#990) * Use:(#993) Fixed:r11(#992) * Use:(#994) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} ===== N775. IL_OFFSET IL offset: 0x3e N777. CNS_INT 0 Def:(#1005) Pref: N779. V07(L7) Use:(#1006) * Def:(#1007) Pref: Exposed use of V00 at #1008 Exposed use of V07 at #1009 BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} ===== N783. IL_OFFSET IL offset: 0x80 N785. CNS_INT 0 Def:(#1011) Pref: N787. V07(L7) Use:(#1012) * Def:(#1013) Pref: Exposed use of V02 at #1014 Exposed use of V03 at #1015 Exposed use of V05 at #1016 Exposed use of V01 at #1017 Exposed use of V04 at #1018 Exposed use of V07 at #1019 BB29 [???..???) (throw), preds={} succs={} ===== N791. CALL help Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Linear scan intervals after buildIntervals: Interval 0: (V00) ref RefPositions {#5@0 #404@323 #560@451 #810@637 #1008@781} physReg:rdi Preferences=[rbx r12-r15] Interval 1: (V01) ref RefPositions {#3@0 #315@257 #519@415 #808@637 #1017@789} physReg:rsi Preferences=[rbx r12-r15] Interval 2: (V02) ref RefPositions {#0@0 #88@67 #117@91 #146@115 #175@137 #408@327 #516@415 #524@421 #727@565 #769@607 #805@637 #946@739 #1014@789} physReg:rdx Preferences=[rbx r12-r15] Interval 3: (V03) ref RefPositions {#1@0 #8@5 #38@33 #412@331 #450@361 #517@415 #528@425 #597@499 #773@611 #806@637 #846@689 #1015@789} physReg:rcx Preferences=[rbx r12-r15] Interval 4: (V04) ref RefPositions {#4@0 #416@335 #520@415 #532@429 #563@459 #739@581 #777@615 #809@637 #816@653 #980@761 #1018@789} physReg:r8 Preferences=[rbx r12-r15] Interval 5: (V05) byref RefPositions {#2@0 #179@141 #384@307 #420@339 #458@369 #518@415 #807@637 #1016@789} physReg:r9 Preferences=[rbx r12-r15] Interval 6: (V06) int RefPositions {#274@220 #277@227 #813@644 #814@645} physReg:NA Preferences=[rax] Interval 7: (V07) int RefPositions {#36@30 #273@219 #555@443 #559@450 #561@451 #766@600 #800@629 #804@636 #811@637 #1007@780 #1009@781 #1013@788 #1019@789} physReg:NA Preferences=[rbx r12-r15] RelatedInterval Interval 8: (V10) ref RefPositions {#349@274 #351@279 #380@303 #454@365 #629@513} physReg:NA Preferences=[rbx r12-r15] Interval 9: (V14) ref RefPositions {#586@478 #587@485 #592@495 #624@509 #696@545} physReg:NA Preferences=[rbx r12-r15] Interval 10: (V16) ref RefPositions {#839@672 #840@681 #841@685 #913@721} physReg:NA Preferences=[rbx r12-r15] Interval 11: (V18) ref RefPositions {#886@698 #909@717 #950@743} physReg:NA Preferences=[rbx r12-r15] Interval 12: (V19) int RefPositions {#483@380 #484@385} physReg:NA Preferences=[allInt] Interval 13: (V20) ref RefPositions {#669@522 #692@541 #728@569} physReg:NA Preferences=[rbx r12-r15] Interval 14: (V24) ref RefPositions {#903@710 #905@713} physReg:NA Preferences=[rsi] Interval 15: (V25) byref RefPositions {#235@174 #236@177 #239@185} physReg:NA Preferences=[allInt] Interval 16: (V26) ref RefPositions {#309@250 #311@253} physReg:NA Preferences=[rdi] Interval 17: (V27) ref RefPositions {#686@534 #688@537} physReg:NA Preferences=[rsi] Interval 18: (V28) int RefPositions {#590@488 #591@491 #623@505} physReg:NA Preferences=[rbx r12-r15] Interval 19: ref (specialPutArg) RefPositions {#10@6 #19@15} physReg:NA Preferences=[rdi] RelatedInterval Interval 20: long (constant) RefPositions {#12@8 #14@9} physReg:NA Preferences=[r11] Interval 21: long RefPositions {#16@10 #21@15} physReg:NA Preferences=[r11] Interval 22: long (constant) RefPositions {#17@12 #22@15} physReg:NA Preferences=[allInt] Interval 23: int RefPositions {#33@16 #34@19} physReg:NA Preferences=[rax] Interval 24: ref (specialPutArg) RefPositions {#40@34 #49@43} physReg:NA Preferences=[rdi] RelatedInterval Interval 25: long (constant) RefPositions {#42@36 #44@37} physReg:NA Preferences=[r11] Interval 26: long RefPositions {#46@38 #51@43} physReg:NA Preferences=[r11] Interval 27: long (constant) RefPositions {#47@40 #52@43} physReg:NA Preferences=[allInt] Interval 28: int RefPositions {#63@44 #64@45} physReg:NA Preferences=[rax] Interval 29: int RefPositions {#65@46 #67@47} physReg:NA Preferences=[rdi] Interval 30: int RefPositions {#69@48 #72@53} physReg:NA Preferences=[rdi] Interval 31: long (constant) RefPositions {#70@50 #73@53} physReg:NA Preferences=[allInt] Interval 32: bool RefPositions {#84@54 #85@57} physReg:NA Preferences=[rax] Interval 33: ref (specialPutArg) RefPositions {#90@68 #99@77} physReg:NA Preferences=[rdi] RelatedInterval Interval 34: long (constant) RefPositions {#92@70 #94@71} physReg:NA Preferences=[r11] Interval 35: long RefPositions {#96@72 #101@77} physReg:NA Preferences=[r11] Interval 36: long (constant) RefPositions {#97@74 #102@77} physReg:NA Preferences=[allInt] Interval 37: bool RefPositions {#113@78 #114@81} physReg:NA Preferences=[rax] Interval 38: ref (specialPutArg) RefPositions {#119@92 #128@101} physReg:NA Preferences=[rdi] RelatedInterval Interval 39: long (constant) RefPositions {#121@94 #123@95} physReg:NA Preferences=[r11] Interval 40: long RefPositions {#125@96 #130@101} physReg:NA Preferences=[r11] Interval 41: long (constant) RefPositions {#126@98 #131@101} physReg:NA Preferences=[allInt] Interval 42: bool RefPositions {#142@102 #143@105} physReg:NA Preferences=[rax] Interval 43: ref (specialPutArg) RefPositions {#148@116 #157@125} physReg:NA Preferences=[rdi] RelatedInterval Interval 44: long (constant) RefPositions {#150@118 #152@119} physReg:NA Preferences=[r11] Interval 45: long RefPositions {#154@120 #159@125} physReg:NA Preferences=[r11] Interval 46: long (constant) RefPositions {#155@122 #160@125} physReg:NA Preferences=[allInt] Interval 47: bool RefPositions {#171@126 #172@129} physReg:NA Preferences=[rax] Interval 48: ref (specialPutArg) RefPositions {#177@138 #184@147} physReg:NA Preferences=[rdi] RelatedInterval Interval 49: byref (specialPutArg) RefPositions {#181@142 #186@147} physReg:NA Preferences=[rsi] RelatedInterval Interval 50: long (constant) RefPositions {#182@144 #187@147} physReg:NA Preferences=[allInt] Interval 51: ref RefPositions {#198@148 #199@149} physReg:NA Preferences=[rax] Interval 52: long (constant) RefPositions {#200@154 #201@155} physReg:NA Preferences=[allInt] Interval 53: long RefPositions {#202@156 #204@157} physReg:NA Preferences=[rsi] Interval 54: long RefPositions {#206@158 #214@167} physReg:NA Preferences=[rsi] Interval 55: byref RefPositions {#207@160 #209@161} physReg:NA Preferences=[rdi] Interval 56: byref RefPositions {#211@162 #216@167} physReg:NA Preferences=[rdi] Interval 57: long (constant) RefPositions {#212@164 #217@167} physReg:NA Preferences=[allInt] Interval 58: ref RefPositions {#228@168 #231@169} physReg:NA Preferences=[rax] Interval 59: long RefPositions {#230@168 #232@169} physReg:NA Preferences=[rdx] Interval 60: byref RefPositions {#233@172 #234@173} physReg:NA Preferences=[allInt] RelatedInterval Interval 61: ref RefPositions {#237@178 #238@179} physReg:NA Preferences=[allInt] Interval 62: int RefPositions {#240@186 #241@187} physReg:NA Preferences=[allInt] Interval 63: long (constant) RefPositions {#242@192 #243@193} physReg:NA Preferences=[allInt] Interval 64: long RefPositions {#244@194 #246@195} physReg:NA Preferences=[rsi] Interval 65: long RefPositions {#248@196 #256@205} physReg:NA Preferences=[rsi] Interval 66: byref RefPositions {#249@198 #251@199} physReg:NA Preferences=[rdi] Interval 67: byref RefPositions {#253@200 #258@205} physReg:NA Preferences=[rdi] Interval 68: long (constant) RefPositions {#254@202 #259@205} physReg:NA Preferences=[allInt] Interval 69: bool RefPositions {#270@206 #271@209} physReg:NA Preferences=[rax] Interval 70: long (constant) RefPositions {#279@234 #280@235} physReg:NA Preferences=[allInt] Interval 71: long RefPositions {#281@236 #283@237} physReg:NA Preferences=[rsi] Interval 72: long RefPositions {#285@238 #293@247} physReg:NA Preferences=[rsi] Interval 73: byref RefPositions {#286@240 #288@241} physReg:NA Preferences=[rdi] Interval 74: byref RefPositions {#290@242 #295@247} physReg:NA Preferences=[rdi] Interval 75: long (constant) RefPositions {#291@244 #296@247} physReg:NA Preferences=[allInt] Interval 76: ref RefPositions {#307@248 #308@249} physReg:NA Preferences=[rax] RelatedInterval Interval 77: ref RefPositions {#313@254 #326@267} physReg:NA Preferences=[rdi] Interval 78: ref (specialPutArg) RefPositions {#317@258 #328@267} physReg:NA Preferences=[rsi] RelatedInterval Interval 79: long (constant) RefPositions {#319@260 #321@261} physReg:NA Preferences=[r11] Interval 80: long RefPositions {#323@262 #330@267} physReg:NA Preferences=[r11] Interval 81: long (constant) RefPositions {#324@264 #331@267} physReg:NA Preferences=[allInt] Interval 82: ref RefPositions {#342@268 #345@269} physReg:NA Preferences=[rax] Interval 83: ref RefPositions {#344@268 #346@269} physReg:NA Preferences=[rdx] Interval 84: ref RefPositions {#347@272 #348@273} physReg:NA Preferences=[allInt] RelatedInterval Interval 85: ref (specialPutArg) RefPositions {#353@280 #362@289} physReg:NA Preferences=[rdi] RelatedInterval Interval 86: long (constant) RefPositions {#355@282 #357@283} physReg:NA Preferences=[r11] Interval 87: long RefPositions {#359@284 #364@289} physReg:NA Preferences=[r11] Interval 88: long (constant) RefPositions {#360@286 #365@289} physReg:NA Preferences=[allInt] Interval 89: int RefPositions {#376@290 #377@293} physReg:NA Preferences=[rax] Interval 90: ref (specialPutArg) RefPositions {#382@304 #389@313} physReg:NA Preferences=[rdi] RelatedInterval Interval 91: byref (specialPutArg) RefPositions {#386@308 #391@313} physReg:NA Preferences=[rsi] RelatedInterval Interval 92: long (constant) RefPositions {#387@310 #392@313} physReg:NA Preferences=[allInt] Interval 93: ref RefPositions {#406@324 #425@345} physReg:NA Preferences=[rdi] Interval 94: ref (specialPutArg) RefPositions {#410@328 #427@345} physReg:NA Preferences=[rsi] RelatedInterval Interval 95: ref (specialPutArg) RefPositions {#414@332 #429@345} physReg:NA Preferences=[rdx] RelatedInterval Interval 96: ref (specialPutArg) RefPositions {#418@336 #431@345} physReg:NA Preferences=[rcx] RelatedInterval Interval 97: byref (specialPutArg) RefPositions {#422@340 #433@345} physReg:NA Preferences=[r8] RelatedInterval Interval 98: long (constant) RefPositions {#423@342 #434@345} physReg:NA Preferences=[allInt] Interval 99: bool RefPositions {#445@346 #446@349} physReg:NA Preferences=[rax] Interval 100: ref (specialPutArg) RefPositions {#452@362 #463@375} physReg:NA Preferences=[rdi] RelatedInterval Interval 101: ref (specialPutArg) RefPositions {#456@366 #465@375} physReg:NA Preferences=[rsi] RelatedInterval Interval 102: byref (specialPutArg) RefPositions {#460@370 #467@375} physReg:NA Preferences=[rdx] RelatedInterval Interval 103: long (constant) RefPositions {#461@372 #468@375} physReg:NA Preferences=[allInt] Interval 104: int RefPositions {#479@376 #480@377} physReg:NA Preferences=[rax] Interval 105: int RefPositions {#481@378 #482@379} physReg:NA Preferences=[allInt] RelatedInterval Interval 106: long (constant) RefPositions {#486@394 #487@395} physReg:NA Preferences=[allInt] Interval 107: long RefPositions {#488@396 #490@397} physReg:NA Preferences=[rsi] Interval 108: long RefPositions {#492@398 #500@407} physReg:NA Preferences=[rsi] Interval 109: byref RefPositions {#493@400 #495@401} physReg:NA Preferences=[rdi] Interval 110: byref RefPositions {#497@402 #502@407} physReg:NA Preferences=[rdi] Interval 111: long (constant) RefPositions {#498@404 #503@407} physReg:NA Preferences=[allInt] Interval 112: bool RefPositions {#514@408 #515@411} physReg:NA Preferences=[rax] Interval 113: ref (specialPutArg) RefPositions {#526@422 #537@435} physReg:NA Preferences=[rdi] RelatedInterval Interval 114: ref (specialPutArg) RefPositions {#530@426 #539@435} physReg:NA Preferences=[rsi] RelatedInterval Interval 115: ref (specialPutArg) RefPositions {#534@430 #541@435} physReg:NA Preferences=[rdx] RelatedInterval Interval 116: long (constant) RefPositions {#535@432 #542@435} physReg:NA Preferences=[allInt] Interval 117: bool RefPositions {#553@436 #554@439} physReg:NA Preferences=[rax] Interval 118: int (constant) RefPositions {#557@448 #558@449} physReg:NA Preferences=[allInt] RelatedInterval Interval 119: long (constant) RefPositions {#565@468 #567@469} physReg:NA Preferences=[rdi] Interval 120: long RefPositions {#569@470 #572@475} physReg:NA Preferences=[rdi] Interval 121: long (constant) RefPositions {#570@472 #573@475} physReg:NA Preferences=[allInt] Interval 122: ref RefPositions {#584@476 #585@477} physReg:NA Preferences=[rax] RelatedInterval Interval 123: int RefPositions {#588@486 #589@487} physReg:NA Preferences=[allInt] RelatedInterval Interval 124: byref RefPositions {#593@496 #595@499} physReg:NA Preferences=[rdi] Interval 125: byref RefPositions {#625@510 #627@513} physReg:NA Preferences=[rdi] Interval 126: long (constant) RefPositions {#655@516 #656@519} physReg:NA Preferences=[allInt] Interval 127: ref RefPositions {#667@520 #668@521} physReg:NA Preferences=[rax] RelatedInterval Interval 128: long (constant) RefPositions {#670@524 #671@527} physReg:NA Preferences=[allInt] Interval 129: byref RefPositions {#682@528 #683@531} physReg:NA Preferences=[rax] Interval 130: ref RefPositions {#684@532 #685@533} physReg:NA Preferences=[allInt] RelatedInterval Interval 131: ref RefPositions {#690@538 #706@555} physReg:NA Preferences=[rsi] Interval 132: ref (specialPutArg) RefPositions {#694@542 #708@555} physReg:NA Preferences=[rdi] RelatedInterval Interval 133: ref RefPositions {#698@546 #710@555} physReg:NA Preferences=[rcx] Interval 134: int (constant) RefPositions {#699@548 #701@549} physReg:NA Preferences=[rdx] Interval 135: int RefPositions {#703@550 #712@555} physReg:NA Preferences=[rdx] Interval 136: long (constant) RefPositions {#704@552 #713@555} physReg:NA Preferences=[allInt] Interval 137: int (constant) RefPositions {#723@558 #725@561} physReg:NA Preferences=[allInt] Interval 138: float (INTERNAL) RefPositions {#724@561 #726@561} physReg:NA Preferences=[allFloat] Interval 139: int (INTERNAL) RefPositions {#730@577 #735@577} physReg:NA Preferences=[rdi] Interval 140: int (INTERNAL) RefPositions {#732@577 #736@577} physReg:NA Preferences=[rcx] Interval 141: int (INTERNAL) RefPositions {#734@577 #737@577} physReg:NA Preferences=[rsi] Interval 142: ref (specialPutArg) RefPositions {#741@582 #750@591} physReg:NA Preferences=[rdi] RelatedInterval Interval 143: long (constant) RefPositions {#743@584 #745@585} physReg:NA Preferences=[r11] Interval 144: long RefPositions {#747@586 #752@591} physReg:NA Preferences=[r11] Interval 145: long (constant) RefPositions {#748@588 #753@591} physReg:NA Preferences=[allInt] Interval 146: int (constant) RefPositions {#764@598 #765@599} physReg:NA Preferences=[allInt] RelatedInterval Interval 147: ref (specialPutArg) RefPositions {#771@608 #782@621} physReg:NA Preferences=[rdi] RelatedInterval Interval 148: ref (specialPutArg) RefPositions {#775@612 #784@621} physReg:NA Preferences=[rsi] RelatedInterval Interval 149: ref (specialPutArg) RefPositions {#779@616 #786@621} physReg:NA Preferences=[rdx] RelatedInterval Interval 150: long (constant) RefPositions {#780@618 #787@621} physReg:NA Preferences=[allInt] Interval 151: bool RefPositions {#798@622 #799@625} physReg:NA Preferences=[rax] Interval 152: int (constant) RefPositions {#802@634 #803@635} physReg:NA Preferences=[allInt] RelatedInterval Interval 153: long (constant) RefPositions {#818@662 #820@663} physReg:NA Preferences=[rdi] Interval 154: long RefPositions {#822@664 #825@669} physReg:NA Preferences=[rdi] Interval 155: long (constant) RefPositions {#823@666 #826@669} physReg:NA Preferences=[allInt] Interval 156: ref RefPositions {#837@670 #838@671} physReg:NA Preferences=[rax] RelatedInterval Interval 157: byref RefPositions {#842@686 #844@689} physReg:NA Preferences=[rdi] Interval 158: long (constant) RefPositions {#872@692 #873@695} physReg:NA Preferences=[allInt] Interval 159: ref RefPositions {#884@696 #885@697} physReg:NA Preferences=[rax] RelatedInterval Interval 160: long (constant) RefPositions {#887@700 #888@703} physReg:NA Preferences=[allInt] Interval 161: byref RefPositions {#899@704 #900@707} physReg:NA Preferences=[rax] Interval 162: ref RefPositions {#901@708 #902@709} physReg:NA Preferences=[allInt] RelatedInterval Interval 163: ref RefPositions {#907@714 #923@731} physReg:NA Preferences=[rsi] Interval 164: ref (specialPutArg) RefPositions {#911@718 #925@731} physReg:NA Preferences=[rdi] RelatedInterval Interval 165: ref RefPositions {#915@722 #927@731} physReg:NA Preferences=[rcx] Interval 166: int (constant) RefPositions {#916@724 #918@725} physReg:NA Preferences=[rdx] Interval 167: int RefPositions {#920@726 #929@731} physReg:NA Preferences=[rdx] Interval 168: long (constant) RefPositions {#921@728 #930@731} physReg:NA Preferences=[allInt] Interval 169: byref RefPositions {#940@734 #942@735} physReg:NA Preferences=[rdi] Interval 170: byref RefPositions {#944@736 #955@749} physReg:NA Preferences=[rdi] Interval 171: ref (specialPutArg) RefPositions {#948@740 #957@749} physReg:NA Preferences=[rsi] RelatedInterval Interval 172: ref RefPositions {#952@744 #959@749} physReg:NA Preferences=[rdx] Interval 173: long (constant) RefPositions {#953@746 #960@749} physReg:NA Preferences=[allInt] Interval 174: int (INTERNAL) RefPositions {#971@757 #976@757} physReg:NA Preferences=[rdi] Interval 175: int (INTERNAL) RefPositions {#973@757 #977@757} physReg:NA Preferences=[rcx] Interval 176: int (INTERNAL) RefPositions {#975@757 #978@757} physReg:NA Preferences=[rsi] Interval 177: ref (specialPutArg) RefPositions {#982@762 #991@771} physReg:NA Preferences=[rdi] RelatedInterval Interval 178: long (constant) RefPositions {#984@764 #986@765} physReg:NA Preferences=[r11] Interval 179: long RefPositions {#988@766 #993@771} physReg:NA Preferences=[r11] Interval 180: long (constant) RefPositions {#989@768 #994@771} physReg:NA Preferences=[allInt] Interval 181: int (constant) RefPositions {#1005@778 #1006@779} physReg:NA Preferences=[allInt] RelatedInterval Interval 182: int (constant) RefPositions {#1011@786 #1012@787} physReg:NA Preferences=[allInt] RelatedInterval *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) ref RefPositions {#5@0 #404@323 #560@451 #810@637 #1008@781} physReg:rdi Preferences=[rbx r12-r15] Interval 1: (V01) ref RefPositions {#3@0 #315@257 #519@415 #808@637 #1017@789} physReg:rsi Preferences=[rbx r12-r15] Interval 2: (V02) ref RefPositions {#0@0 #88@67 #117@91 #146@115 #175@137 #408@327 #516@415 #524@421 #727@565 #769@607 #805@637 #946@739 #1014@789} physReg:rdx Preferences=[rbx r12-r15] Interval 3: (V03) ref RefPositions {#1@0 #8@5 #38@33 #412@331 #450@361 #517@415 #528@425 #597@499 #773@611 #806@637 #846@689 #1015@789} physReg:rcx Preferences=[rbx r12-r15] Interval 4: (V04) ref RefPositions {#4@0 #416@335 #520@415 #532@429 #563@459 #739@581 #777@615 #809@637 #816@653 #980@761 #1018@789} physReg:r8 Preferences=[rbx r12-r15] Interval 5: (V05) byref RefPositions {#2@0 #179@141 #384@307 #420@339 #458@369 #518@415 #807@637 #1016@789} physReg:r9 Preferences=[rbx r12-r15] Interval 6: (V06) int RefPositions {#274@220 #277@227 #813@644 #814@645} physReg:NA Preferences=[rax] Interval 7: (V07) int RefPositions {#36@30 #273@219 #555@443 #559@450 #561@451 #766@600 #800@629 #804@636 #811@637 #1007@780 #1009@781 #1013@788 #1019@789} physReg:NA Preferences=[rbx r12-r15] RelatedInterval Interval 8: (V10) ref RefPositions {#349@274 #351@279 #380@303 #454@365 #629@513} physReg:NA Preferences=[rbx r12-r15] Interval 9: (V14) ref RefPositions {#586@478 #587@485 #592@495 #624@509 #696@545} physReg:NA Preferences=[rbx r12-r15] Interval 10: (V16) ref RefPositions {#839@672 #840@681 #841@685 #913@721} physReg:NA Preferences=[rbx r12-r15] Interval 11: (V18) ref RefPositions {#886@698 #909@717 #950@743} physReg:NA Preferences=[rbx r12-r15] Interval 12: (V19) int RefPositions {#483@380 #484@385} physReg:NA Preferences=[allInt] Interval 13: (V20) ref RefPositions {#669@522 #692@541 #728@569} physReg:NA Preferences=[rbx r12-r15] Interval 14: (V24) ref RefPositions {#903@710 #905@713} physReg:NA Preferences=[rsi] Interval 15: (V25) byref RefPositions {#235@174 #236@177 #239@185} physReg:NA Preferences=[allInt] Interval 16: (V26) ref RefPositions {#309@250 #311@253} physReg:NA Preferences=[rdi] Interval 17: (V27) ref RefPositions {#686@534 #688@537} physReg:NA Preferences=[rsi] Interval 18: (V28) int RefPositions {#590@488 #591@491 #623@505} physReg:NA Preferences=[rbx r12-r15] Interval 19: ref (specialPutArg) RefPositions {#10@6 #19@15} physReg:NA Preferences=[rdi] RelatedInterval Interval 20: long (constant) RefPositions {#12@8 #14@9} physReg:NA Preferences=[r11] Interval 21: long RefPositions {#16@10 #21@15} physReg:NA Preferences=[r11] Interval 22: long (constant) RefPositions {#17@12 #22@15} physReg:NA Preferences=[allInt] Interval 23: int RefPositions {#33@16 #34@19} physReg:NA Preferences=[rax] Interval 24: ref (specialPutArg) RefPositions {#40@34 #49@43} physReg:NA Preferences=[rdi] RelatedInterval Interval 25: long (constant) RefPositions {#42@36 #44@37} physReg:NA Preferences=[r11] Interval 26: long RefPositions {#46@38 #51@43} physReg:NA Preferences=[r11] Interval 27: long (constant) RefPositions {#47@40 #52@43} physReg:NA Preferences=[allInt] Interval 28: int RefPositions {#63@44 #64@45} physReg:NA Preferences=[rax] Interval 29: int RefPositions {#65@46 #67@47} physReg:NA Preferences=[rdi] Interval 30: int RefPositions {#69@48 #72@53} physReg:NA Preferences=[rdi] Interval 31: long (constant) RefPositions {#70@50 #73@53} physReg:NA Preferences=[allInt] Interval 32: bool RefPositions {#84@54 #85@57} physReg:NA Preferences=[rax] Interval 33: ref (specialPutArg) RefPositions {#90@68 #99@77} physReg:NA Preferences=[rdi] RelatedInterval Interval 34: long (constant) RefPositions {#92@70 #94@71} physReg:NA Preferences=[r11] Interval 35: long RefPositions {#96@72 #101@77} physReg:NA Preferences=[r11] Interval 36: long (constant) RefPositions {#97@74 #102@77} physReg:NA Preferences=[allInt] Interval 37: bool RefPositions {#113@78 #114@81} physReg:NA Preferences=[rax] Interval 38: ref (specialPutArg) RefPositions {#119@92 #128@101} physReg:NA Preferences=[rdi] RelatedInterval Interval 39: long (constant) RefPositions {#121@94 #123@95} physReg:NA Preferences=[r11] Interval 40: long RefPositions {#125@96 #130@101} physReg:NA Preferences=[r11] Interval 41: long (constant) RefPositions {#126@98 #131@101} physReg:NA Preferences=[allInt] Interval 42: bool RefPositions {#142@102 #143@105} physReg:NA Preferences=[rax] Interval 43: ref (specialPutArg) RefPositions {#148@116 #157@125} physReg:NA Preferences=[rdi] RelatedInterval Interval 44: long (constant) RefPositions {#150@118 #152@119} physReg:NA Preferences=[r11] Interval 45: long RefPositions {#154@120 #159@125} physReg:NA Preferences=[r11] Interval 46: long (constant) RefPositions {#155@122 #160@125} physReg:NA Preferences=[allInt] Interval 47: bool RefPositions {#171@126 #172@129} physReg:NA Preferences=[rax] Interval 48: ref (specialPutArg) RefPositions {#177@138 #184@147} physReg:NA Preferences=[rdi] RelatedInterval Interval 49: byref (specialPutArg) RefPositions {#181@142 #186@147} physReg:NA Preferences=[rsi] RelatedInterval Interval 50: long (constant) RefPositions {#182@144 #187@147} physReg:NA Preferences=[allInt] Interval 51: ref RefPositions {#198@148 #199@149} physReg:NA Preferences=[rax] Interval 52: long (constant) RefPositions {#200@154 #201@155} physReg:NA Preferences=[allInt] Interval 53: long RefPositions {#202@156 #204@157} physReg:NA Preferences=[rsi] Interval 54: long RefPositions {#206@158 #214@167} physReg:NA Preferences=[rsi] Interval 55: byref RefPositions {#207@160 #209@161} physReg:NA Preferences=[rdi] Interval 56: byref RefPositions {#211@162 #216@167} physReg:NA Preferences=[rdi] Interval 57: long (constant) RefPositions {#212@164 #217@167} physReg:NA Preferences=[allInt] Interval 58: ref RefPositions {#228@168 #231@169} physReg:NA Preferences=[rax] Interval 59: long RefPositions {#230@168 #232@169} physReg:NA Preferences=[rdx] Interval 60: byref RefPositions {#233@172 #234@173} physReg:NA Preferences=[allInt] RelatedInterval Interval 61: ref RefPositions {#237@178 #238@179} physReg:NA Preferences=[allInt] Interval 62: int RefPositions {#240@186 #241@187} physReg:NA Preferences=[allInt] Interval 63: long (constant) RefPositions {#242@192 #243@193} physReg:NA Preferences=[allInt] Interval 64: long RefPositions {#244@194 #246@195} physReg:NA Preferences=[rsi] Interval 65: long RefPositions {#248@196 #256@205} physReg:NA Preferences=[rsi] Interval 66: byref RefPositions {#249@198 #251@199} physReg:NA Preferences=[rdi] Interval 67: byref RefPositions {#253@200 #258@205} physReg:NA Preferences=[rdi] Interval 68: long (constant) RefPositions {#254@202 #259@205} physReg:NA Preferences=[allInt] Interval 69: bool RefPositions {#270@206 #271@209} physReg:NA Preferences=[rax] Interval 70: long (constant) RefPositions {#279@234 #280@235} physReg:NA Preferences=[allInt] Interval 71: long RefPositions {#281@236 #283@237} physReg:NA Preferences=[rsi] Interval 72: long RefPositions {#285@238 #293@247} physReg:NA Preferences=[rsi] Interval 73: byref RefPositions {#286@240 #288@241} physReg:NA Preferences=[rdi] Interval 74: byref RefPositions {#290@242 #295@247} physReg:NA Preferences=[rdi] Interval 75: long (constant) RefPositions {#291@244 #296@247} physReg:NA Preferences=[allInt] Interval 76: ref RefPositions {#307@248 #308@249} physReg:NA Preferences=[rax] RelatedInterval Interval 77: ref RefPositions {#313@254 #326@267} physReg:NA Preferences=[rdi] Interval 78: ref (specialPutArg) RefPositions {#317@258 #328@267} physReg:NA Preferences=[rsi] RelatedInterval Interval 79: long (constant) RefPositions {#319@260 #321@261} physReg:NA Preferences=[r11] Interval 80: long RefPositions {#323@262 #330@267} physReg:NA Preferences=[r11] Interval 81: long (constant) RefPositions {#324@264 #331@267} physReg:NA Preferences=[allInt] Interval 82: ref RefPositions {#342@268 #345@269} physReg:NA Preferences=[rax] Interval 83: ref RefPositions {#344@268 #346@269} physReg:NA Preferences=[rdx] Interval 84: ref RefPositions {#347@272 #348@273} physReg:NA Preferences=[allInt] RelatedInterval Interval 85: ref (specialPutArg) RefPositions {#353@280 #362@289} physReg:NA Preferences=[rdi] RelatedInterval Interval 86: long (constant) RefPositions {#355@282 #357@283} physReg:NA Preferences=[r11] Interval 87: long RefPositions {#359@284 #364@289} physReg:NA Preferences=[r11] Interval 88: long (constant) RefPositions {#360@286 #365@289} physReg:NA Preferences=[allInt] Interval 89: int RefPositions {#376@290 #377@293} physReg:NA Preferences=[rax] Interval 90: ref (specialPutArg) RefPositions {#382@304 #389@313} physReg:NA Preferences=[rdi] RelatedInterval Interval 91: byref (specialPutArg) RefPositions {#386@308 #391@313} physReg:NA Preferences=[rsi] RelatedInterval Interval 92: long (constant) RefPositions {#387@310 #392@313} physReg:NA Preferences=[allInt] Interval 93: ref RefPositions {#406@324 #425@345} physReg:NA Preferences=[rdi] Interval 94: ref (specialPutArg) RefPositions {#410@328 #427@345} physReg:NA Preferences=[rsi] RelatedInterval Interval 95: ref (specialPutArg) RefPositions {#414@332 #429@345} physReg:NA Preferences=[rdx] RelatedInterval Interval 96: ref (specialPutArg) RefPositions {#418@336 #431@345} physReg:NA Preferences=[rcx] RelatedInterval Interval 97: byref (specialPutArg) RefPositions {#422@340 #433@345} physReg:NA Preferences=[r8] RelatedInterval Interval 98: long (constant) RefPositions {#423@342 #434@345} physReg:NA Preferences=[allInt] Interval 99: bool RefPositions {#445@346 #446@349} physReg:NA Preferences=[rax] Interval 100: ref (specialPutArg) RefPositions {#452@362 #463@375} physReg:NA Preferences=[rdi] RelatedInterval Interval 101: ref (specialPutArg) RefPositions {#456@366 #465@375} physReg:NA Preferences=[rsi] RelatedInterval Interval 102: byref (specialPutArg) RefPositions {#460@370 #467@375} physReg:NA Preferences=[rdx] RelatedInterval Interval 103: long (constant) RefPositions {#461@372 #468@375} physReg:NA Preferences=[allInt] Interval 104: int RefPositions {#479@376 #480@377} physReg:NA Preferences=[rax] Interval 105: int RefPositions {#481@378 #482@379} physReg:NA Preferences=[allInt] RelatedInterval Interval 106: long (constant) RefPositions {#486@394 #487@395} physReg:NA Preferences=[allInt] Interval 107: long RefPositions {#488@396 #490@397} physReg:NA Preferences=[rsi] Interval 108: long RefPositions {#492@398 #500@407} physReg:NA Preferences=[rsi] Interval 109: byref RefPositions {#493@400 #495@401} physReg:NA Preferences=[rdi] Interval 110: byref RefPositions {#497@402 #502@407} physReg:NA Preferences=[rdi] Interval 111: long (constant) RefPositions {#498@404 #503@407} physReg:NA Preferences=[allInt] Interval 112: bool RefPositions {#514@408 #515@411} physReg:NA Preferences=[rax] Interval 113: ref (specialPutArg) RefPositions {#526@422 #537@435} physReg:NA Preferences=[rdi] RelatedInterval Interval 114: ref (specialPutArg) RefPositions {#530@426 #539@435} physReg:NA Preferences=[rsi] RelatedInterval Interval 115: ref (specialPutArg) RefPositions {#534@430 #541@435} physReg:NA Preferences=[rdx] RelatedInterval Interval 116: long (constant) RefPositions {#535@432 #542@435} physReg:NA Preferences=[allInt] Interval 117: bool RefPositions {#553@436 #554@439} physReg:NA Preferences=[rax] Interval 118: int (constant) RefPositions {#557@448 #558@449} physReg:NA Preferences=[allInt] RelatedInterval Interval 119: long (constant) RefPositions {#565@468 #567@469} physReg:NA Preferences=[rdi] Interval 120: long RefPositions {#569@470 #572@475} physReg:NA Preferences=[rdi] Interval 121: long (constant) RefPositions {#570@472 #573@475} physReg:NA Preferences=[allInt] Interval 122: ref RefPositions {#584@476 #585@477} physReg:NA Preferences=[rax] RelatedInterval Interval 123: int RefPositions {#588@486 #589@487} physReg:NA Preferences=[allInt] RelatedInterval Interval 124: byref RefPositions {#593@496 #595@499} physReg:NA Preferences=[rdi] Interval 125: byref RefPositions {#625@510 #627@513} physReg:NA Preferences=[rdi] Interval 126: long (constant) RefPositions {#655@516 #656@519} physReg:NA Preferences=[allInt] Interval 127: ref RefPositions {#667@520 #668@521} physReg:NA Preferences=[rax] RelatedInterval Interval 128: long (constant) RefPositions {#670@524 #671@527} physReg:NA Preferences=[allInt] Interval 129: byref RefPositions {#682@528 #683@531} physReg:NA Preferences=[rax] Interval 130: ref RefPositions {#684@532 #685@533} physReg:NA Preferences=[allInt] RelatedInterval Interval 131: ref RefPositions {#690@538 #706@555} physReg:NA Preferences=[rsi] Interval 132: ref (specialPutArg) RefPositions {#694@542 #708@555} physReg:NA Preferences=[rdi] RelatedInterval Interval 133: ref RefPositions {#698@546 #710@555} physReg:NA Preferences=[rcx] Interval 134: int (constant) RefPositions {#699@548 #701@549} physReg:NA Preferences=[rdx] Interval 135: int RefPositions {#703@550 #712@555} physReg:NA Preferences=[rdx] Interval 136: long (constant) RefPositions {#704@552 #713@555} physReg:NA Preferences=[allInt] Interval 137: int (constant) RefPositions {#723@558 #725@561} physReg:NA Preferences=[allInt] Interval 138: float (INTERNAL) RefPositions {#724@561 #726@561} physReg:NA Preferences=[allFloat] Interval 139: int (INTERNAL) RefPositions {#730@577 #735@577} physReg:NA Preferences=[rdi] Interval 140: int (INTERNAL) RefPositions {#732@577 #736@577} physReg:NA Preferences=[rcx] Interval 141: int (INTERNAL) RefPositions {#734@577 #737@577} physReg:NA Preferences=[rsi] Interval 142: ref (specialPutArg) RefPositions {#741@582 #750@591} physReg:NA Preferences=[rdi] RelatedInterval Interval 143: long (constant) RefPositions {#743@584 #745@585} physReg:NA Preferences=[r11] Interval 144: long RefPositions {#747@586 #752@591} physReg:NA Preferences=[r11] Interval 145: long (constant) RefPositions {#748@588 #753@591} physReg:NA Preferences=[allInt] Interval 146: int (constant) RefPositions {#764@598 #765@599} physReg:NA Preferences=[allInt] RelatedInterval Interval 147: ref (specialPutArg) RefPositions {#771@608 #782@621} physReg:NA Preferences=[rdi] RelatedInterval Interval 148: ref (specialPutArg) RefPositions {#775@612 #784@621} physReg:NA Preferences=[rsi] RelatedInterval Interval 149: ref (specialPutArg) RefPositions {#779@616 #786@621} physReg:NA Preferences=[rdx] RelatedInterval Interval 150: long (constant) RefPositions {#780@618 #787@621} physReg:NA Preferences=[allInt] Interval 151: bool RefPositions {#798@622 #799@625} physReg:NA Preferences=[rax] Interval 152: int (constant) RefPositions {#802@634 #803@635} physReg:NA Preferences=[allInt] RelatedInterval Interval 153: long (constant) RefPositions {#818@662 #820@663} physReg:NA Preferences=[rdi] Interval 154: long RefPositions {#822@664 #825@669} physReg:NA Preferences=[rdi] Interval 155: long (constant) RefPositions {#823@666 #826@669} physReg:NA Preferences=[allInt] Interval 156: ref RefPositions {#837@670 #838@671} physReg:NA Preferences=[rax] RelatedInterval Interval 157: byref RefPositions {#842@686 #844@689} physReg:NA Preferences=[rdi] Interval 158: long (constant) RefPositions {#872@692 #873@695} physReg:NA Preferences=[allInt] Interval 159: ref RefPositions {#884@696 #885@697} physReg:NA Preferences=[rax] RelatedInterval Interval 160: long (constant) RefPositions {#887@700 #888@703} physReg:NA Preferences=[allInt] Interval 161: byref RefPositions {#899@704 #900@707} physReg:NA Preferences=[rax] Interval 162: ref RefPositions {#901@708 #902@709} physReg:NA Preferences=[allInt] RelatedInterval Interval 163: ref RefPositions {#907@714 #923@731} physReg:NA Preferences=[rsi] Interval 164: ref (specialPutArg) RefPositions {#911@718 #925@731} physReg:NA Preferences=[rdi] RelatedInterval Interval 165: ref RefPositions {#915@722 #927@731} physReg:NA Preferences=[rcx] Interval 166: int (constant) RefPositions {#916@724 #918@725} physReg:NA Preferences=[rdx] Interval 167: int RefPositions {#920@726 #929@731} physReg:NA Preferences=[rdx] Interval 168: long (constant) RefPositions {#921@728 #930@731} physReg:NA Preferences=[allInt] Interval 169: byref RefPositions {#940@734 #942@735} physReg:NA Preferences=[rdi] Interval 170: byref RefPositions {#944@736 #955@749} physReg:NA Preferences=[rdi] Interval 171: ref (specialPutArg) RefPositions {#948@740 #957@749} physReg:NA Preferences=[rsi] RelatedInterval Interval 172: ref RefPositions {#952@744 #959@749} physReg:NA Preferences=[rdx] Interval 173: long (constant) RefPositions {#953@746 #960@749} physReg:NA Preferences=[allInt] Interval 174: int (INTERNAL) RefPositions {#971@757 #976@757} physReg:NA Preferences=[rdi] Interval 175: int (INTERNAL) RefPositions {#973@757 #977@757} physReg:NA Preferences=[rcx] Interval 176: int (INTERNAL) RefPositions {#975@757 #978@757} physReg:NA Preferences=[rsi] Interval 177: ref (specialPutArg) RefPositions {#982@762 #991@771} physReg:NA Preferences=[rdi] RelatedInterval Interval 178: long (constant) RefPositions {#984@764 #986@765} physReg:NA Preferences=[r11] Interval 179: long RefPositions {#988@766 #993@771} physReg:NA Preferences=[r11] Interval 180: long (constant) RefPositions {#989@768 #994@771} physReg:NA Preferences=[allInt] Interval 181: int (constant) RefPositions {#1005@778 #1006@779} physReg:NA Preferences=[allInt] RelatedInterval Interval 182: int (constant) RefPositions {#1011@786 #1012@787} physReg:NA Preferences=[allInt] RelatedInterval ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ BB00 regmask=[rdx] minReg=1 fixed regOptional> BB00 regmask=[rcx] minReg=1 fixed regOptional> BB00 regmask=[r9] minReg=1 fixed regOptional> BB00 regmask=[rsi] minReg=1 fixed regOptional> BB00 regmask=[r8] minReg=1 fixed regOptional> BB00 regmask=[rdi] minReg=1 fixed regOptional> BB01 regmask=[rdi] minReg=1> LCL_VAR BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[r11] minReg=1> CNS_INT BB01 regmask=[r11] minReg=1 fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> PUTARG_REG BB01 regmask=[r11] minReg=1 fixed> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last regOptional> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[r11] minReg=1> CNS_INT BB02 regmask=[r11] minReg=1 fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> PUTARG_REG BB02 regmask=[r11] minReg=1 fixed> CNS_INT BB02 regmask=[allInt] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[allInt] minReg=1 last> CAST BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> CNS_INT BB02 regmask=[allInt] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[allInt] minReg=1 last regOptional> BB03 regmask=[rdi] minReg=1> LCL_VAR BB03 regmask=[rdi] minReg=1 fixed> BB03 regmask=[rdi] minReg=1> PUTARG_REG BB03 regmask=[rdi] minReg=1 fixed> BB03 regmask=[r11] minReg=1> CNS_INT BB03 regmask=[r11] minReg=1 fixed> BB03 regmask=[r11] minReg=1> BB03 regmask=[r11] minReg=1 last fixed> BB03 regmask=[r11] minReg=1> PUTARG_REG BB03 regmask=[r11] minReg=1 fixed> CNS_INT BB03 regmask=[allInt] minReg=1> BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1 last fixed> BB03 regmask=[r11] minReg=1> BB03 regmask=[r11] minReg=1 last fixed> BB03 regmask=[allInt] minReg=1 last> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[rsi] minReg=1 last> BB03 regmask=[rdi] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> BB03 regmask=[allInt] minReg=1 last regOptional> BB04 regmask=[rdi] minReg=1> LCL_VAR BB04 regmask=[rdi] minReg=1 fixed> BB04 regmask=[rdi] minReg=1> PUTARG_REG BB04 regmask=[rdi] minReg=1 fixed> BB04 regmask=[r11] minReg=1> CNS_INT BB04 regmask=[r11] minReg=1 fixed> BB04 regmask=[r11] minReg=1> BB04 regmask=[r11] minReg=1 last fixed> BB04 regmask=[r11] minReg=1> PUTARG_REG BB04 regmask=[r11] minReg=1 fixed> CNS_INT BB04 regmask=[allInt] minReg=1> BB04 regmask=[rdi] minReg=1> BB04 regmask=[rdi] minReg=1 last fixed> BB04 regmask=[r11] minReg=1> BB04 regmask=[r11] minReg=1 last fixed> BB04 regmask=[allInt] minReg=1 last> BB04 regmask=[rax] minReg=1 last> BB04 regmask=[rcx] minReg=1 last> BB04 regmask=[rdx] minReg=1 last> BB04 regmask=[rsi] minReg=1 last> BB04 regmask=[rdi] minReg=1 last> BB04 regmask=[r8] minReg=1 last> BB04 regmask=[r9] minReg=1 last> BB04 regmask=[r10] minReg=1 last> BB04 regmask=[r11] minReg=1 last> BB04 regmask=[rax] minReg=1> CALL BB04 regmask=[rax] minReg=1 fixed> BB04 regmask=[allInt] minReg=1 last regOptional> BB05 regmask=[rdi] minReg=1> LCL_VAR BB05 regmask=[rdi] minReg=1 fixed> BB05 regmask=[rdi] minReg=1> PUTARG_REG BB05 regmask=[rdi] minReg=1 fixed> BB05 regmask=[r11] minReg=1> CNS_INT BB05 regmask=[r11] minReg=1 fixed> BB05 regmask=[r11] minReg=1> BB05 regmask=[r11] minReg=1 last fixed> BB05 regmask=[r11] minReg=1> PUTARG_REG BB05 regmask=[r11] minReg=1 fixed> CNS_INT BB05 regmask=[allInt] minReg=1> BB05 regmask=[rdi] minReg=1> BB05 regmask=[rdi] minReg=1 last fixed> BB05 regmask=[r11] minReg=1> BB05 regmask=[r11] minReg=1 last fixed> BB05 regmask=[allInt] minReg=1 last> BB05 regmask=[rax] minReg=1 last> BB05 regmask=[rcx] minReg=1 last> BB05 regmask=[rdx] minReg=1 last> BB05 regmask=[rsi] minReg=1 last> BB05 regmask=[rdi] minReg=1 last> BB05 regmask=[r8] minReg=1 last> BB05 regmask=[r9] minReg=1 last> BB05 regmask=[r10] minReg=1 last> BB05 regmask=[r11] minReg=1 last> BB05 regmask=[rax] minReg=1> CALL BB05 regmask=[rax] minReg=1 fixed> BB05 regmask=[allInt] minReg=1 last regOptional> BB06 regmask=[rdi] minReg=1> LCL_VAR BB06 regmask=[rdi] minReg=1 fixed> BB06 regmask=[rdi] minReg=1> PUTARG_REG BB06 regmask=[rdi] minReg=1 fixed> BB06 regmask=[rsi] minReg=1> LCL_VAR BB06 regmask=[rsi] minReg=1 fixed> BB06 regmask=[rsi] minReg=1> PUTARG_REG BB06 regmask=[rsi] minReg=1 fixed> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rcx] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> BB06 regmask=[rsi] minReg=1 last> BB06 regmask=[rdi] minReg=1 last> BB06 regmask=[r8] minReg=1 last> BB06 regmask=[r9] minReg=1 last> BB06 regmask=[r10] minReg=1 last> BB06 regmask=[r11] minReg=1 last> BB06 regmask=[rax] minReg=1> CALL BB06 regmask=[rax] minReg=1 fixed> BB06 regmask=[allInt] minReg=1 last> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> IND BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rsi] minReg=1> PUTARG_REG BB06 regmask=[rsi] minReg=1 fixed> LCL_VAR_ADDR BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> PUTARG_REG BB06 regmask=[rdi] minReg=1 fixed> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rcx] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> BB06 regmask=[rsi] minReg=1 last> BB06 regmask=[rdi] minReg=1 last> BB06 regmask=[r8] minReg=1 last> BB06 regmask=[r9] minReg=1 last> BB06 regmask=[r10] minReg=1 last> BB06 regmask=[r11] minReg=1 last> BB06 regmask=[rax] minReg=1> CALL BB06 regmask=[rax] minReg=1 fixed> BB06 regmask=[rdx] minReg=1> CALL BB06 regmask=[rdx] minReg=1 fixed> BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[allInt] minReg=1 last> LCL_VAR_ADDR BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> IND BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> LCL_VAR BB06 regmask=[allInt] minReg=1 last> IND BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> IND BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rsi] minReg=1> PUTARG_REG BB06 regmask=[rsi] minReg=1 fixed> LCL_VAR_ADDR BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> PUTARG_REG BB06 regmask=[rdi] minReg=1 fixed> CNS_INT BB06 regmask=[allInt] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rcx] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> BB06 regmask=[rsi] minReg=1 last> BB06 regmask=[rdi] minReg=1 last> BB06 regmask=[r8] minReg=1 last> BB06 regmask=[r9] minReg=1 last> BB06 regmask=[r10] minReg=1 last> BB06 regmask=[r11] minReg=1 last> BB06 regmask=[rax] minReg=1> CALL BB06 regmask=[rax] minReg=1 fixed> BB06 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB07 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> BB08 regmask=[rax] minReg=1> LCL_VAR BB08 regmask=[rax] minReg=1 last fixed> CNS_INT BB09 regmask=[allInt] minReg=1> BB09 regmask=[allInt] minReg=1 last> IND BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last fixed> BB09 regmask=[rsi] minReg=1> PUTARG_REG BB09 regmask=[rsi] minReg=1 fixed> LCL_VAR_ADDR BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[rdi] minReg=1> PUTARG_REG BB09 regmask=[rdi] minReg=1 fixed> CNS_INT BB09 regmask=[allInt] minReg=1> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last fixed> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[allInt] minReg=1 last> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rcx] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> BB09 regmask=[rsi] minReg=1 last> BB09 regmask=[rdi] minReg=1 last> BB09 regmask=[r8] minReg=1 last> BB09 regmask=[r9] minReg=1 last> BB09 regmask=[r10] minReg=1 last> BB09 regmask=[r11] minReg=1 last> BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> BB09 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> BB09 regmask=[rdi] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[rdi] minReg=1> PUTARG_REG BB09 regmask=[rdi] minReg=1 fixed> BB09 regmask=[rsi] minReg=1> LCL_VAR BB09 regmask=[rsi] minReg=1 fixed> BB09 regmask=[rsi] minReg=1> PUTARG_REG BB09 regmask=[rsi] minReg=1 fixed> BB09 regmask=[r11] minReg=1> CNS_INT BB09 regmask=[r11] minReg=1 fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> PUTARG_REG BB09 regmask=[r11] minReg=1 fixed> CNS_INT BB09 regmask=[allInt] minReg=1> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[allInt] minReg=1 last> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rcx] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> BB09 regmask=[rsi] minReg=1 last> BB09 regmask=[rdi] minReg=1 last> BB09 regmask=[r8] minReg=1 last> BB09 regmask=[r9] minReg=1 last> BB09 regmask=[r10] minReg=1 last> BB09 regmask=[r11] minReg=1 last> BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> BB09 regmask=[rdx] minReg=1> CALL BB09 regmask=[rdx] minReg=1 fixed> BB09 regmask=[allInt] minReg=1 last> BB09 regmask=[allInt] minReg=1 last> LCL_FLD BB09 regmask=[allInt] minReg=1> BB09 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> BB09 regmask=[rdi] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 fixed> BB09 regmask=[rdi] minReg=1> PUTARG_REG BB09 regmask=[rdi] minReg=1 fixed> BB09 regmask=[r11] minReg=1> CNS_INT BB09 regmask=[r11] minReg=1 fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> PUTARG_REG BB09 regmask=[r11] minReg=1 fixed> CNS_INT BB09 regmask=[allInt] minReg=1> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[allInt] minReg=1 last> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rcx] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> BB09 regmask=[rsi] minReg=1 last> BB09 regmask=[rdi] minReg=1 last> BB09 regmask=[r8] minReg=1 last> BB09 regmask=[r9] minReg=1 last> BB09 regmask=[r10] minReg=1 last> BB09 regmask=[r11] minReg=1 last> BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> BB09 regmask=[allInt] minReg=1 last regOptional> BB10 regmask=[rdi] minReg=1> LCL_VAR BB10 regmask=[rdi] minReg=1 fixed> BB10 regmask=[rdi] minReg=1> PUTARG_REG BB10 regmask=[rdi] minReg=1 fixed> BB10 regmask=[rsi] minReg=1> LCL_VAR BB10 regmask=[rsi] minReg=1 fixed> BB10 regmask=[rsi] minReg=1> PUTARG_REG BB10 regmask=[rsi] minReg=1 fixed> CNS_INT BB10 regmask=[allInt] minReg=1> BB10 regmask=[rdi] minReg=1> BB10 regmask=[rdi] minReg=1 last fixed> BB10 regmask=[rsi] minReg=1> BB10 regmask=[rsi] minReg=1 last fixed> BB10 regmask=[allInt] minReg=1 last> BB10 regmask=[rax] minReg=1 last> BB10 regmask=[rcx] minReg=1 last> BB10 regmask=[rdx] minReg=1 last> BB10 regmask=[rsi] minReg=1 last> BB10 regmask=[rdi] minReg=1 last> BB10 regmask=[r8] minReg=1 last> BB10 regmask=[r9] minReg=1 last> BB10 regmask=[r10] minReg=1 last> BB10 regmask=[r11] minReg=1 last> BB12 regmask=[rdi] minReg=1> LCL_VAR BB12 regmask=[rdi] minReg=1 last fixed> BB12 regmask=[rdi] minReg=1> PUTARG_REG BB12 regmask=[rdi] minReg=1 fixed> BB12 regmask=[rsi] minReg=1> LCL_VAR BB12 regmask=[rsi] minReg=1 fixed> BB12 regmask=[rsi] minReg=1> PUTARG_REG BB12 regmask=[rsi] minReg=1 fixed> BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 fixed> BB12 regmask=[rdx] minReg=1> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> BB12 regmask=[r8] minReg=1> LCL_VAR BB12 regmask=[r8] minReg=1 fixed> BB12 regmask=[r8] minReg=1> PUTARG_REG BB12 regmask=[r8] minReg=1 fixed> CNS_INT BB12 regmask=[allInt] minReg=1> BB12 regmask=[rdi] minReg=1> BB12 regmask=[rdi] minReg=1 last fixed> BB12 regmask=[rsi] minReg=1> BB12 regmask=[rsi] minReg=1 last fixed> BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[r8] minReg=1> BB12 regmask=[r8] minReg=1 last fixed> BB12 regmask=[allInt] minReg=1 last> BB12 regmask=[rax] minReg=1 last> BB12 regmask=[rcx] minReg=1 last> BB12 regmask=[rdx] minReg=1 last> BB12 regmask=[rsi] minReg=1 last> BB12 regmask=[rdi] minReg=1 last> BB12 regmask=[r8] minReg=1 last> BB12 regmask=[r9] minReg=1 last> BB12 regmask=[r10] minReg=1 last> BB12 regmask=[r11] minReg=1 last> BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[allInt] minReg=1 last regOptional> BB14 regmask=[rdi] minReg=1> LCL_VAR BB14 regmask=[rdi] minReg=1 fixed> BB14 regmask=[rdi] minReg=1> PUTARG_REG BB14 regmask=[rdi] minReg=1 fixed> BB14 regmask=[rsi] minReg=1> LCL_VAR BB14 regmask=[rsi] minReg=1 fixed> BB14 regmask=[rsi] minReg=1> PUTARG_REG BB14 regmask=[rsi] minReg=1 fixed> BB14 regmask=[rdx] minReg=1> LCL_VAR BB14 regmask=[rdx] minReg=1 fixed> BB14 regmask=[rdx] minReg=1> PUTARG_REG BB14 regmask=[rdx] minReg=1 fixed> CNS_INT BB14 regmask=[allInt] minReg=1> BB14 regmask=[rdi] minReg=1> BB14 regmask=[rdi] minReg=1 last fixed> BB14 regmask=[rsi] minReg=1> BB14 regmask=[rsi] minReg=1 last fixed> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> BB14 regmask=[allInt] minReg=1 last> BB14 regmask=[rax] minReg=1 last> BB14 regmask=[rcx] minReg=1 last> BB14 regmask=[rdx] minReg=1 last> BB14 regmask=[rsi] minReg=1 last> BB14 regmask=[rdi] minReg=1 last> BB14 regmask=[r8] minReg=1 last> BB14 regmask=[r9] minReg=1 last> BB14 regmask=[r10] minReg=1 last> BB14 regmask=[r11] minReg=1 last> BB14 regmask=[rax] minReg=1> CALL BB14 regmask=[rax] minReg=1 fixed> BB14 regmask=[allInt] minReg=1 last> CAST BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last regOptional> CNS_INT BB15 regmask=[allInt] minReg=1> BB15 regmask=[allInt] minReg=1 last> IND BB15 regmask=[rsi] minReg=1> BB15 regmask=[rsi] minReg=1> BB15 regmask=[rsi] minReg=1 last fixed> BB15 regmask=[rsi] minReg=1> PUTARG_REG BB15 regmask=[rsi] minReg=1 fixed> LCL_VAR_ADDR BB15 regmask=[rdi] minReg=1> BB15 regmask=[rdi] minReg=1> BB15 regmask=[rdi] minReg=1 last fixed> BB15 regmask=[rdi] minReg=1> PUTARG_REG BB15 regmask=[rdi] minReg=1 fixed> CNS_INT BB15 regmask=[allInt] minReg=1> BB15 regmask=[rsi] minReg=1> BB15 regmask=[rsi] minReg=1 last fixed> BB15 regmask=[rdi] minReg=1> BB15 regmask=[rdi] minReg=1 last fixed> BB15 regmask=[allInt] minReg=1 last> BB15 regmask=[rax] minReg=1 last> BB15 regmask=[rcx] minReg=1 last> BB15 regmask=[rdx] minReg=1 last> BB15 regmask=[rsi] minReg=1 last> BB15 regmask=[rdi] minReg=1 last> BB15 regmask=[r8] minReg=1 last> BB15 regmask=[r9] minReg=1 last> BB15 regmask=[r10] minReg=1 last> BB15 regmask=[r11] minReg=1 last> BB15 regmask=[rax] minReg=1> CALL BB15 regmask=[rax] minReg=1 fixed> BB15 regmask=[allInt] minReg=1 last regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB17 regmask=[rdi] minReg=1> LCL_VAR BB17 regmask=[rdi] minReg=1 fixed> BB17 regmask=[rdi] minReg=1> PUTARG_REG BB17 regmask=[rdi] minReg=1 fixed> BB17 regmask=[rsi] minReg=1> LCL_VAR BB17 regmask=[rsi] minReg=1 fixed> BB17 regmask=[rsi] minReg=1> PUTARG_REG BB17 regmask=[rsi] minReg=1 fixed> BB17 regmask=[rdx] minReg=1> LCL_VAR BB17 regmask=[rdx] minReg=1 fixed> BB17 regmask=[rdx] minReg=1> PUTARG_REG BB17 regmask=[rdx] minReg=1 fixed> CNS_INT BB17 regmask=[allInt] minReg=1> BB17 regmask=[rdi] minReg=1> BB17 regmask=[rdi] minReg=1 last fixed> BB17 regmask=[rsi] minReg=1> BB17 regmask=[rsi] minReg=1 last fixed> BB17 regmask=[rdx] minReg=1> BB17 regmask=[rdx] minReg=1 last fixed> BB17 regmask=[allInt] minReg=1 last> BB17 regmask=[rax] minReg=1 last> BB17 regmask=[rcx] minReg=1 last> BB17 regmask=[rdx] minReg=1 last> BB17 regmask=[rsi] minReg=1 last> BB17 regmask=[rdi] minReg=1 last> BB17 regmask=[r8] minReg=1 last> BB17 regmask=[r9] minReg=1 last> BB17 regmask=[r10] minReg=1 last> BB17 regmask=[r11] minReg=1 last> BB17 regmask=[rax] minReg=1> CALL BB17 regmask=[rax] minReg=1 fixed> BB17 regmask=[allInt] minReg=1 last regOptional> BB17 regmask=[allInt] minReg=1 regOptional> CNS_INT BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 regOptional> BB18 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB19 regmask=[allInt] minReg=1 regOptional> CNS_INT BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rdi] minReg=1> PUTARG_REG BB20 regmask=[rdi] minReg=1 fixed> CNS_INT BB20 regmask=[allInt] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[rax] minReg=1> CALL BB20 regmask=[rax] minReg=1 fixed> BB20 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1> IND BB20 regmask=[allInt] minReg=1> BB20 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB20 regmask=[allInt] minReg=1> LEA BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 fixed> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[mm0] minReg=1 last> BB20 regmask=[mm1] minReg=1 last> BB20 regmask=[mm2] minReg=1 last> BB20 regmask=[mm3] minReg=1 last> BB20 regmask=[mm4] minReg=1 last> BB20 regmask=[mm5] minReg=1 last> BB20 regmask=[mm6] minReg=1 last> BB20 regmask=[mm7] minReg=1 last> BB20 regmask=[mm8] minReg=1 last> BB20 regmask=[mm9] minReg=1 last> BB20 regmask=[mm10] minReg=1 last> BB20 regmask=[mm11] minReg=1 last> BB20 regmask=[mm12] minReg=1 last> BB20 regmask=[mm13] minReg=1 last> BB20 regmask=[mm14] minReg=1 last> BB20 regmask=[mm15] minReg=1 last> LCL_VAR BB20 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB20 regmask=[allInt] minReg=1> LEA BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[mm0] minReg=1 last> BB20 regmask=[mm1] minReg=1 last> BB20 regmask=[mm2] minReg=1 last> BB20 regmask=[mm3] minReg=1 last> BB20 regmask=[mm4] minReg=1 last> BB20 regmask=[mm5] minReg=1 last> BB20 regmask=[mm6] minReg=1 last> BB20 regmask=[mm7] minReg=1 last> BB20 regmask=[mm8] minReg=1 last> BB20 regmask=[mm9] minReg=1 last> BB20 regmask=[mm10] minReg=1 last> BB20 regmask=[mm11] minReg=1 last> BB20 regmask=[mm12] minReg=1 last> BB20 regmask=[mm13] minReg=1 last> BB20 regmask=[mm14] minReg=1 last> BB20 regmask=[mm15] minReg=1 last> CNS_INT BB20 regmask=[allInt] minReg=1> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[rax] minReg=1> CALL BB20 regmask=[rax] minReg=1 fixed> BB20 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> CNS_INT BB20 regmask=[allInt] minReg=1> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[rax] minReg=1> CALL BB20 regmask=[rax] minReg=1 fixed> BB20 regmask=[allInt] minReg=1 last> IND BB20 regmask=[allInt] minReg=1> BB20 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rsi] minReg=1> PUTARG_REG BB20 regmask=[rsi] minReg=1 fixed> BB20 regmask=[rdi] minReg=1> LCL_VAR BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[rdi] minReg=1> PUTARG_REG BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[rcx] minReg=1> LCL_VAR BB20 regmask=[rcx] minReg=1 last fixed> BB20 regmask=[rcx] minReg=1> PUTARG_REG BB20 regmask=[rcx] minReg=1 fixed> CNS_INT BB20 regmask=[rdx] minReg=1> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rdx] minReg=1 last fixed> BB20 regmask=[rdx] minReg=1> PUTARG_REG BB20 regmask=[rdx] minReg=1 fixed> CNS_INT BB20 regmask=[allInt] minReg=1> BB20 regmask=[rsi] minReg=1> BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rcx] minReg=1> BB20 regmask=[rcx] minReg=1 last fixed> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rdx] minReg=1 last fixed> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> CNS_INT BB20 regmask=[allInt] minReg=1> STORE_BLK BB20 regmask=[allFloat] minReg=1> BB20 regmask=[allInt] minReg=1 last> STORE_BLK BB20 regmask=[allFloat] minReg=1 last> LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rdi] minReg=1> PUTARG_STK BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[rcx] minReg=1> PUTARG_STK BB20 regmask=[rcx] minReg=1 fixed> BB20 regmask=[rsi] minReg=1> PUTARG_STK BB20 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB20 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB20 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rdi] minReg=1> LCL_VAR BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[rdi] minReg=1> PUTARG_REG BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[r11] minReg=1> CNS_INT BB20 regmask=[r11] minReg=1 fixed> BB20 regmask=[r11] minReg=1> BB20 regmask=[r11] minReg=1 last fixed> BB20 regmask=[r11] minReg=1> PUTARG_REG BB20 regmask=[r11] minReg=1 fixed> CNS_INT BB20 regmask=[allInt] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[r11] minReg=1> BB20 regmask=[r11] minReg=1 last fixed> BB20 regmask=[allInt] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> CNS_INT BB21 regmask=[allInt] minReg=1> BB21 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> BB22 regmask=[rdi] minReg=1> LCL_VAR BB22 regmask=[rdi] minReg=1 fixed> BB22 regmask=[rdi] minReg=1> PUTARG_REG BB22 regmask=[rdi] minReg=1 fixed> BB22 regmask=[rsi] minReg=1> LCL_VAR BB22 regmask=[rsi] minReg=1 fixed> BB22 regmask=[rsi] minReg=1> PUTARG_REG BB22 regmask=[rsi] minReg=1 fixed> BB22 regmask=[rdx] minReg=1> LCL_VAR BB22 regmask=[rdx] minReg=1 fixed> BB22 regmask=[rdx] minReg=1> PUTARG_REG BB22 regmask=[rdx] minReg=1 fixed> CNS_INT BB22 regmask=[allInt] minReg=1> BB22 regmask=[rdi] minReg=1> BB22 regmask=[rdi] minReg=1 last fixed> BB22 regmask=[rsi] minReg=1> BB22 regmask=[rsi] minReg=1 last fixed> BB22 regmask=[rdx] minReg=1> BB22 regmask=[rdx] minReg=1 last fixed> BB22 regmask=[allInt] minReg=1 last> BB22 regmask=[rax] minReg=1 last> BB22 regmask=[rcx] minReg=1 last> BB22 regmask=[rdx] minReg=1 last> BB22 regmask=[rsi] minReg=1 last> BB22 regmask=[rdi] minReg=1 last> BB22 regmask=[r8] minReg=1 last> BB22 regmask=[r9] minReg=1 last> BB22 regmask=[r10] minReg=1 last> BB22 regmask=[r11] minReg=1 last> BB22 regmask=[rax] minReg=1> CALL BB22 regmask=[rax] minReg=1 fixed> BB22 regmask=[allInt] minReg=1 last regOptional> BB22 regmask=[allInt] minReg=1 regOptional> CNS_INT BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> BB24 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB25 regmask=[allInt] minReg=1 regOptional> CNS_INT BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> CNS_INT BB26 regmask=[allInt] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[rax] minReg=1> CALL BB26 regmask=[rax] minReg=1 fixed> BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1> LEA BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 fixed> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[mm0] minReg=1 last> BB26 regmask=[mm1] minReg=1 last> BB26 regmask=[mm2] minReg=1 last> BB26 regmask=[mm3] minReg=1 last> BB26 regmask=[mm4] minReg=1 last> BB26 regmask=[mm5] minReg=1 last> BB26 regmask=[mm6] minReg=1 last> BB26 regmask=[mm7] minReg=1 last> BB26 regmask=[mm8] minReg=1 last> BB26 regmask=[mm9] minReg=1 last> BB26 regmask=[mm10] minReg=1 last> BB26 regmask=[mm11] minReg=1 last> BB26 regmask=[mm12] minReg=1 last> BB26 regmask=[mm13] minReg=1 last> BB26 regmask=[mm14] minReg=1 last> BB26 regmask=[mm15] minReg=1 last> CNS_INT BB26 regmask=[allInt] minReg=1> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[rax] minReg=1> CALL BB26 regmask=[rax] minReg=1 fixed> BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> CNS_INT BB26 regmask=[allInt] minReg=1> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[rax] minReg=1> CALL BB26 regmask=[rax] minReg=1 fixed> BB26 regmask=[allInt] minReg=1 last> IND BB26 regmask=[allInt] minReg=1> BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rsi] minReg=1> PUTARG_REG BB26 regmask=[rsi] minReg=1 fixed> BB26 regmask=[rdi] minReg=1> LCL_VAR BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rcx] minReg=1> LCL_VAR BB26 regmask=[rcx] minReg=1 last fixed> BB26 regmask=[rcx] minReg=1> PUTARG_REG BB26 regmask=[rcx] minReg=1 fixed> CNS_INT BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> PUTARG_REG BB26 regmask=[rdx] minReg=1 fixed> CNS_INT BB26 regmask=[allInt] minReg=1> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rcx] minReg=1> BB26 regmask=[rcx] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> LCL_VAR_ADDR BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 fixed> BB26 regmask=[rsi] minReg=1> PUTARG_REG BB26 regmask=[rsi] minReg=1 fixed> BB26 regmask=[rdx] minReg=1> LCL_VAR BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> PUTARG_REG BB26 regmask=[rdx] minReg=1 fixed> CNS_INT BB26 regmask=[allInt] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[rdi] minReg=1> PUTARG_STK BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rcx] minReg=1> PUTARG_STK BB26 regmask=[rcx] minReg=1 fixed> BB26 regmask=[rsi] minReg=1> PUTARG_STK BB26 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB26 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB26 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> LCL_VAR BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[r11] minReg=1> CNS_INT BB26 regmask=[r11] minReg=1 fixed> BB26 regmask=[r11] minReg=1> BB26 regmask=[r11] minReg=1 last fixed> BB26 regmask=[r11] minReg=1> PUTARG_REG BB26 regmask=[r11] minReg=1 fixed> CNS_INT BB26 regmask=[allInt] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[r11] minReg=1> BB26 regmask=[r11] minReg=1 last fixed> BB26 regmask=[allInt] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> CNS_INT BB27 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB27 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> CNS_INT BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB29 regmask=[rax] minReg=1 last> BB29 regmask=[rcx] minReg=1 last> BB29 regmask=[rdx] minReg=1 last> BB29 regmask=[rsi] minReg=1 last> BB29 regmask=[rdi] minReg=1 last> BB29 regmask=[r8] minReg=1 last> BB29 regmask=[r9] minReg=1 last> BB29 regmask=[r10] minReg=1 last> BB29 regmask=[r11] minReg=1 last> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 (Interval 0) BB00 regmask=[rdi] minReg=1 fixed regOptional> LCL_VAR BB12 regmask=[rdi] minReg=1 last fixed> BB18 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> --- V01 (Interval 1) BB00 regmask=[rsi] minReg=1 fixed regOptional> LCL_VAR BB09 regmask=[rsi] minReg=1 fixed> BB15 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> --- V02 (Interval 2) BB00 regmask=[rdx] minReg=1 fixed regOptional> LCL_VAR BB03 regmask=[rdi] minReg=1 fixed> LCL_VAR BB04 regmask=[rdi] minReg=1 fixed> LCL_VAR BB05 regmask=[rdi] minReg=1 fixed> LCL_VAR BB06 regmask=[rdi] minReg=1 fixed> LCL_VAR BB12 regmask=[rsi] minReg=1 fixed> BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB17 regmask=[rdi] minReg=1 fixed> LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB22 regmask=[rdi] minReg=1 fixed> BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB26 regmask=[rsi] minReg=1 fixed> BB28 regmask=[allInt] minReg=1 regOptional> --- V03 (Interval 3) BB00 regmask=[rcx] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[rdi] minReg=1 fixed> LCL_VAR BB02 regmask=[rdi] minReg=1 fixed> LCL_VAR BB12 regmask=[rdx] minReg=1 fixed> LCL_VAR BB14 regmask=[rdi] minReg=1 fixed> BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB17 regmask=[rsi] minReg=1 fixed> LCL_VAR BB20 regmask=[rsi] minReg=1 fixed> LCL_VAR BB22 regmask=[rsi] minReg=1 fixed> BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB26 regmask=[rsi] minReg=1 fixed> BB28 regmask=[allInt] minReg=1 regOptional> --- V04 (Interval 4) BB00 regmask=[r8] minReg=1 fixed regOptional> LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB17 regmask=[rdx] minReg=1 fixed> LCL_VAR BB19 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB20 regmask=[rdi] minReg=1 fixed> LCL_VAR BB22 regmask=[rdx] minReg=1 fixed> BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB25 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB26 regmask=[rdi] minReg=1 fixed> BB28 regmask=[allInt] minReg=1 regOptional> --- V05 (Interval 5) BB00 regmask=[r9] minReg=1 fixed regOptional> LCL_VAR BB06 regmask=[rsi] minReg=1 fixed> LCL_VAR BB10 regmask=[rsi] minReg=1 fixed> LCL_VAR BB12 regmask=[r8] minReg=1 fixed> LCL_VAR BB14 regmask=[rdx] minReg=1 fixed> BB15 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> --- V06 (Interval 6) STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[rax] minReg=1 last fixed> STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> BB24 regmask=[allInt] minReg=1 regOptional> --- V07 (Interval 7) STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1 last> BB17 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> BB22 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB27 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB28 regmask=[allInt] minReg=1> BB28 regmask=[allInt] minReg=1 regOptional> --- V08 --- V09 --- V10 (Interval 8) STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 fixed> LCL_VAR BB10 regmask=[rdi] minReg=1 fixed> LCL_VAR BB14 regmask=[rsi] minReg=1 fixed> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> --- V11 --- V12 --- V13 --- V14 (Interval 9) STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[rcx] minReg=1 last fixed> --- V15 --- V16 (Interval 10) STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[rcx] minReg=1 last fixed> --- V17 --- V18 (Interval 11) STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[rdi] minReg=1 fixed> LCL_VAR BB26 regmask=[rdx] minReg=1 last fixed> --- V19 (Interval 12) STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last regOptional> --- V20 (Interval 13) STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[rdi] minReg=1 fixed> LCL_VAR BB20 regmask=[allInt] minReg=1 last> --- V21 --- V22 --- V23 --- V24 (Interval 14) STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 last fixed> --- V25 (Interval 15) STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last> --- V26 (Interval 16) STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 last fixed> --- V27 (Interval 17) STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> --- V28 (Interval 18) STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> LCL_VAR BB20 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB20 regmask=[allInt] minReg=1 last regOptional> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ | |V3 a|V2 a| |V1 a|V0 a|V4 a|V5 a| | | 0.#0 V2 Parm Alloc rbx | |V3 a| |V2 a|V1 a|V0 a|V4 a|V5 a| | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 |r14 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#1 V3 Parm Alloc r14 | | | |V2 a|V1 a|V0 a|V4 a|V5 a| | |V3 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#2 V5 Parm Alloc r15 | | | |V2 a|V1 a|V0 a|V4 a| | | |V3 a|V5 a| 0.#3 V1 Parm Alloc r12 | | | |V2 a| |V0 a|V4 a| |V1 a| |V3 a|V5 a| 0.#4 V4 Parm Alloc r13 | | | |V2 a| |V0 a| | |V1 a|V4 a|V3 a|V5 a| 0.#5 V0 Parm Alloc rax |V0 a| | |V2 a| | | | |V1 a|V4 a|V3 a|V5 a| 1.#6 BB1 PredBB0 |V0 a| | |V2 a| | | | |V1 a|V4 a|V3 a|V5 a| 5.#7 rdi Fixd Keep rdi |V0 a| | |V2 a| | | | |V1 a|V4 a|V3 a|V5 a| 5.#8 V3 Use Copy rdi |V0 a| | |V2 a| |V3 a| | |V1 a|V4 a|V3 a|V5 a| 6.#9 rdi Fixd Keep rdi |V0 a| | |V2 a| |V3 a| | |V1 a|V4 a|V3 a|V5 a| 6.#10 I19 Def Alloc rdi |V0 a| | |V2 a| |I19 a| | |V1 a|V4 a|V3 a|V5 a| 8.#11 r11 Fixd Keep r11 |V0 a| | |V2 a| |I19 a| | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 8.#12 C20 Def Alloc r11 |V0 a| | |V2 a| |I19 a| | |C20 a|V1 a|V4 a|V3 a|V5 a| 9.#13 r11 Fixd Keep r11 |V0 a| | |V2 a| |I19 a| | |C20 a|V1 a|V4 a|V3 a|V5 a| 9.#14 C20 Use * Keep r11 |V0 a| | |V2 a| |I19 a| | |C20 a|V1 a|V4 a|V3 a|V5 a| 10.#15 r11 Fixd Keep r11 |V0 a| | |V2 a| |I19 a| | | |V1 a|V4 a|V3 a|V5 a| 10.#16 I21 Def Alloc r11 |V0 a| | |V2 a| |I19 a| | |I21 a|V1 a|V4 a|V3 a|V5 a| 12.#17 C22 Def Alloc rsi |V0 a| | |V2 a|C22 a|I19 a| | |I21 a|V1 a|V4 a|V3 a|V5 a| 15.#18 rdi Fixd Keep rdi |V0 a| | |V2 a|C22 a|I19 a| | |I21 a|V1 a|V4 a|V3 a|V5 a| 15.#19 I19 Use * Keep rdi |V0 a| | |V2 a|C22 a|I19 a| | |I21 a|V1 a|V4 a|V3 a|V5 a| 15.#20 r11 Fixd Keep r11 |V0 a| | |V2 a|C22 a|I19 a| | |I21 a|V1 a|V4 a|V3 a|V5 a| 15.#21 I21 Use * Keep r11 |V0 a| | |V2 a|C22 a|I19 a| | |I21 a|V1 a|V4 a|V3 a|V5 a| 15.#22 C22 Use * Keep rsi |V0 a| | |V2 a|C22 a|I19 a| | |I21 a|V1 a|V4 a|V3 a|V5 a| 16.#23 rax Kill Spill rax | | | |V2 a|C22 i| | | | |V1 a|V4 a|V3 a|V5 a| Keep rax | | | |V2 a|C22 i| | | | |V1 a|V4 a|V3 a|V5 a| 16.#24 rcx Kill Keep rcx | | | |V2 a|C22 i| | | | |V1 a|V4 a|V3 a|V5 a| 16.#25 rdx Kill Keep rdx | | | |V2 a|C22 i| | | | |V1 a|V4 a|V3 a|V5 a| 16.#26 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#27 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#28 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#29 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#30 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#31 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#32 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#33 I23 Def Alloc rax |I23 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 19.#34 I23 Use * Keep rax |I23 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 23.#35 BB2 PredBB1 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 30.#36 V7 Def Alloc rax |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 33.#37 rdi Fixd Keep rdi |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 33.#38 V3 Use Copy rdi |V7 a| | |V2 a| |V3 a| | | |V1 a|V4 a|V3 a|V5 a| 34.#39 rdi Fixd Keep rdi |V7 a| | |V2 a| |V3 a| | | |V1 a|V4 a|V3 a|V5 a| 34.#40 I24 Def Alloc rdi |V7 a| | |V2 a| |I24 a| | | |V1 a|V4 a|V3 a|V5 a| 36.#41 r11 Fixd Keep r11 |V7 a| | |V2 a| |I24 a| | | |V1 a|V4 a|V3 a|V5 a| 36.#42 C25 Def Alloc r11 |V7 a| | |V2 a| |I24 a| | |C25 a|V1 a|V4 a|V3 a|V5 a| 37.#43 r11 Fixd Keep r11 |V7 a| | |V2 a| |I24 a| | |C25 a|V1 a|V4 a|V3 a|V5 a| 37.#44 C25 Use * Keep r11 |V7 a| | |V2 a| |I24 a| | |C25 a|V1 a|V4 a|V3 a|V5 a| 38.#45 r11 Fixd Keep r11 |V7 a| | |V2 a| |I24 a| | | |V1 a|V4 a|V3 a|V5 a| 38.#46 I26 Def Alloc r11 |V7 a| | |V2 a| |I24 a| | |I26 a|V1 a|V4 a|V3 a|V5 a| 40.#47 C27 Def Alloc rsi |V7 a| | |V2 a|C27 a|I24 a| | |I26 a|V1 a|V4 a|V3 a|V5 a| 43.#48 rdi Fixd Keep rdi |V7 a| | |V2 a|C27 a|I24 a| | |I26 a|V1 a|V4 a|V3 a|V5 a| 43.#49 I24 Use * Keep rdi |V7 a| | |V2 a|C27 a|I24 a| | |I26 a|V1 a|V4 a|V3 a|V5 a| 43.#50 r11 Fixd Keep r11 |V7 a| | |V2 a|C27 a|I24 a| | |I26 a|V1 a|V4 a|V3 a|V5 a| 43.#51 I26 Use * Keep r11 |V7 a| | |V2 a|C27 a|I24 a| | |I26 a|V1 a|V4 a|V3 a|V5 a| 43.#52 C27 Use * Keep rsi |V7 a| | |V2 a|C27 a|I24 a| | |I26 a|V1 a|V4 a|V3 a|V5 a| 44.#53 rax Kill Spill rax | | | |V2 a|C27 i| | | | |V1 a|V4 a|V3 a|V5 a| Keep rax | | | |V2 a|C27 i| | | | |V1 a|V4 a|V3 a|V5 a| 44.#54 rcx Kill Keep rcx | | | |V2 a|C27 i| | | | |V1 a|V4 a|V3 a|V5 a| 44.#55 rdx Kill Keep rdx | | | |V2 a|C27 i| | | | |V1 a|V4 a|V3 a|V5 a| 44.#56 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#57 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#58 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#59 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#60 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#61 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#62 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#63 I28 Def Alloc rax |I28 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 45.#64 I28 Use * Keep rax |I28 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 46.#65 I29 Def Alloc rdi | | | |V2 a| |I29 a| | | |V1 a|V4 a|V3 a|V5 a| 47.#66 rdi Fixd Keep rdi | | | |V2 a| |I29 a| | | |V1 a|V4 a|V3 a|V5 a| 47.#67 I29 Use * Keep rdi | | | |V2 a| |I29 a| | | |V1 a|V4 a|V3 a|V5 a| 48.#68 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 48.#69 I30 Def Alloc rdi | | | |V2 a| |I30 a| | | |V1 a|V4 a|V3 a|V5 a| 50.#70 C31 Def Alloc rax |C31 a| | |V2 a| |I30 a| | | |V1 a|V4 a|V3 a|V5 a| 53.#71 rdi Fixd Keep rdi |C31 a| | |V2 a| |I30 a| | | |V1 a|V4 a|V3 a|V5 a| 53.#72 I30 Use * Keep rdi |C31 a| | |V2 a| |I30 a| | | |V1 a|V4 a|V3 a|V5 a| 53.#73 C31 Use * Keep rax |C31 a| | |V2 a| |I30 a| | | |V1 a|V4 a|V3 a|V5 a| 54.#74 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#75 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#76 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#77 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#78 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#79 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#80 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#81 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#82 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#83 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#84 I32 Def Alloc rax |I32 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 57.#85 I32 Use * Keep rax |I32 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 61.#86 BB3 PredBB2 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 67.#87 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 67.#88 V2 Use Copy rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 68.#89 rdi Fixd Keep rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 68.#90 I33 Def Alloc rdi | | | |V2 a| |I33 a| | | |V1 a|V4 a|V3 a|V5 a| 70.#91 r11 Fixd Keep r11 | | | |V2 a| |I33 a| | | |V1 a|V4 a|V3 a|V5 a| 70.#92 C34 Def Alloc r11 | | | |V2 a| |I33 a| | |C34 a|V1 a|V4 a|V3 a|V5 a| 71.#93 r11 Fixd Keep r11 | | | |V2 a| |I33 a| | |C34 a|V1 a|V4 a|V3 a|V5 a| 71.#94 C34 Use * Keep r11 | | | |V2 a| |I33 a| | |C34 a|V1 a|V4 a|V3 a|V5 a| 72.#95 r11 Fixd Keep r11 | | | |V2 a| |I33 a| | | |V1 a|V4 a|V3 a|V5 a| 72.#96 I35 Def Alloc r11 | | | |V2 a| |I33 a| | |I35 a|V1 a|V4 a|V3 a|V5 a| 74.#97 C36 Def Alloc rax |C36 a| | |V2 a| |I33 a| | |I35 a|V1 a|V4 a|V3 a|V5 a| 77.#98 rdi Fixd Keep rdi |C36 a| | |V2 a| |I33 a| | |I35 a|V1 a|V4 a|V3 a|V5 a| 77.#99 I33 Use * Keep rdi |C36 a| | |V2 a| |I33 a| | |I35 a|V1 a|V4 a|V3 a|V5 a| 77.#100 r11 Fixd Keep r11 |C36 a| | |V2 a| |I33 a| | |I35 a|V1 a|V4 a|V3 a|V5 a| 77.#101 I35 Use * Keep r11 |C36 a| | |V2 a| |I33 a| | |I35 a|V1 a|V4 a|V3 a|V5 a| 77.#102 C36 Use * Keep rax |C36 a| | |V2 a| |I33 a| | |I35 a|V1 a|V4 a|V3 a|V5 a| 78.#103 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#104 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#105 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#106 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#107 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#108 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#109 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#110 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#111 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#112 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#113 I37 Def Alloc rax |I37 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 81.#114 I37 Use * Keep rax |I37 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 85.#115 BB4 PredBB3 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 91.#116 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 91.#117 V2 Use Copy rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 92.#118 rdi Fixd Keep rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 92.#119 I38 Def Alloc rdi | | | |V2 a| |I38 a| | | |V1 a|V4 a|V3 a|V5 a| 94.#120 r11 Fixd Keep r11 | | | |V2 a| |I38 a| | | |V1 a|V4 a|V3 a|V5 a| 94.#121 C39 Def Alloc r11 | | | |V2 a| |I38 a| | |C39 a|V1 a|V4 a|V3 a|V5 a| 95.#122 r11 Fixd Keep r11 | | | |V2 a| |I38 a| | |C39 a|V1 a|V4 a|V3 a|V5 a| 95.#123 C39 Use * Keep r11 | | | |V2 a| |I38 a| | |C39 a|V1 a|V4 a|V3 a|V5 a| 96.#124 r11 Fixd Keep r11 | | | |V2 a| |I38 a| | | |V1 a|V4 a|V3 a|V5 a| 96.#125 I40 Def Alloc r11 | | | |V2 a| |I38 a| | |I40 a|V1 a|V4 a|V3 a|V5 a| 98.#126 C41 Def Alloc rax |C41 a| | |V2 a| |I38 a| | |I40 a|V1 a|V4 a|V3 a|V5 a| 101.#127 rdi Fixd Keep rdi |C41 a| | |V2 a| |I38 a| | |I40 a|V1 a|V4 a|V3 a|V5 a| 101.#128 I38 Use * Keep rdi |C41 a| | |V2 a| |I38 a| | |I40 a|V1 a|V4 a|V3 a|V5 a| 101.#129 r11 Fixd Keep r11 |C41 a| | |V2 a| |I38 a| | |I40 a|V1 a|V4 a|V3 a|V5 a| 101.#130 I40 Use * Keep r11 |C41 a| | |V2 a| |I38 a| | |I40 a|V1 a|V4 a|V3 a|V5 a| 101.#131 C41 Use * Keep rax |C41 a| | |V2 a| |I38 a| | |I40 a|V1 a|V4 a|V3 a|V5 a| 102.#132 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#133 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#134 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#135 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#136 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#137 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#138 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#139 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#140 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#141 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#142 I42 Def Alloc rax |I42 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 105.#143 I42 Use * Keep rax |I42 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 109.#144 BB5 PredBB4 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 115.#145 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 115.#146 V2 Use Copy rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 116.#147 rdi Fixd Keep rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 116.#148 I43 Def Alloc rdi | | | |V2 a| |I43 a| | | |V1 a|V4 a|V3 a|V5 a| 118.#149 r11 Fixd Keep r11 | | | |V2 a| |I43 a| | | |V1 a|V4 a|V3 a|V5 a| 118.#150 C44 Def Alloc r11 | | | |V2 a| |I43 a| | |C44 a|V1 a|V4 a|V3 a|V5 a| 119.#151 r11 Fixd Keep r11 | | | |V2 a| |I43 a| | |C44 a|V1 a|V4 a|V3 a|V5 a| 119.#152 C44 Use * Keep r11 | | | |V2 a| |I43 a| | |C44 a|V1 a|V4 a|V3 a|V5 a| 120.#153 r11 Fixd Keep r11 | | | |V2 a| |I43 a| | | |V1 a|V4 a|V3 a|V5 a| 120.#154 I45 Def Alloc r11 | | | |V2 a| |I43 a| | |I45 a|V1 a|V4 a|V3 a|V5 a| 122.#155 C46 Def Alloc rax |C46 a| | |V2 a| |I43 a| | |I45 a|V1 a|V4 a|V3 a|V5 a| 125.#156 rdi Fixd Keep rdi |C46 a| | |V2 a| |I43 a| | |I45 a|V1 a|V4 a|V3 a|V5 a| 125.#157 I43 Use * Keep rdi |C46 a| | |V2 a| |I43 a| | |I45 a|V1 a|V4 a|V3 a|V5 a| 125.#158 r11 Fixd Keep r11 |C46 a| | |V2 a| |I43 a| | |I45 a|V1 a|V4 a|V3 a|V5 a| 125.#159 I45 Use * Keep r11 |C46 a| | |V2 a| |I43 a| | |I45 a|V1 a|V4 a|V3 a|V5 a| 125.#160 C46 Use * Keep rax |C46 a| | |V2 a| |I43 a| | |I45 a|V1 a|V4 a|V3 a|V5 a| 126.#161 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#162 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#163 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#164 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#165 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#166 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#167 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#168 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#169 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#170 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#171 I47 Def Alloc rax |I47 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 129.#172 I47 Use * Keep rax |I47 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 133.#173 BB6 PredBB5 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 137.#174 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 137.#175 V2 Use Copy rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 138.#176 rdi Fixd Keep rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 138.#177 I48 Def Alloc rdi | | | |V2 a| |I48 a| | | |V1 a|V4 a|V3 a|V5 a| 141.#178 rsi Fixd Keep rsi | | | |V2 a| |I48 a| | | |V1 a|V4 a|V3 a|V5 a| 141.#179 V5 Use Copy rsi | | | |V2 a|V5 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 142.#180 rsi Fixd Keep rsi | | | |V2 a|V5 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 142.#181 I49 Def Alloc rsi | | | |V2 a|I49 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 144.#182 C50 Def Alloc rax |C50 a| | |V2 a|I49 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 147.#183 rdi Fixd Keep rdi |C50 a| | |V2 a|I49 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 147.#184 I48 Use * Keep rdi |C50 a| | |V2 a|I49 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 147.#185 rsi Fixd Keep rsi |C50 a| | |V2 a|I49 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 147.#186 I49 Use * Keep rsi |C50 a| | |V2 a|I49 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 147.#187 C50 Use * Keep rax |C50 a| | |V2 a|I49 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 148.#188 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#189 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#190 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#191 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#192 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#193 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#194 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#195 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#196 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#197 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#198 I51 Def Alloc rax |I51 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 149.#199 I51 Use * Keep rax |I51 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 154.#200 C52 Def Alloc rsi | | | |V2 a|C52 a| | | | |V1 a|V4 a|V3 a|V5 a| 155.#201 C52 Use * Keep rsi | | | |V2 a|C52 a| | | | |V1 a|V4 a|V3 a|V5 a| 156.#202 I53 Def Alloc rsi | | | |V2 a|I53 a| | | | |V1 a|V4 a|V3 a|V5 a| 157.#203 rsi Fixd Keep rsi | | | |V2 a|I53 a| | | | |V1 a|V4 a|V3 a|V5 a| 157.#204 I53 Use * Keep rsi | | | |V2 a|I53 a| | | | |V1 a|V4 a|V3 a|V5 a| 158.#205 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 158.#206 I54 Def Alloc rsi | | | |V2 a|I54 a| | | | |V1 a|V4 a|V3 a|V5 a| 160.#207 I55 Def Alloc rdi | | | |V2 a|I54 a|I55 a| | | |V1 a|V4 a|V3 a|V5 a| 161.#208 rdi Fixd Keep rdi | | | |V2 a|I54 a|I55 a| | | |V1 a|V4 a|V3 a|V5 a| 161.#209 I55 Use * Keep rdi | | | |V2 a|I54 a|I55 a| | | |V1 a|V4 a|V3 a|V5 a| 162.#210 rdi Fixd Keep rdi | | | |V2 a|I54 a| | | | |V1 a|V4 a|V3 a|V5 a| 162.#211 I56 Def Alloc rdi | | | |V2 a|I54 a|I56 a| | | |V1 a|V4 a|V3 a|V5 a| 164.#212 C57 Def Alloc rax |C57 a| | |V2 a|I54 a|I56 a| | | |V1 a|V4 a|V3 a|V5 a| 167.#213 rsi Fixd Keep rsi |C57 a| | |V2 a|I54 a|I56 a| | | |V1 a|V4 a|V3 a|V5 a| 167.#214 I54 Use * Keep rsi |C57 a| | |V2 a|I54 a|I56 a| | | |V1 a|V4 a|V3 a|V5 a| 167.#215 rdi Fixd Keep rdi |C57 a| | |V2 a|I54 a|I56 a| | | |V1 a|V4 a|V3 a|V5 a| 167.#216 I56 Use * Keep rdi |C57 a| | |V2 a|I54 a|I56 a| | | |V1 a|V4 a|V3 a|V5 a| 167.#217 C57 Use * Keep rax |C57 a| | |V2 a|I54 a|I56 a| | | |V1 a|V4 a|V3 a|V5 a| 168.#218 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#219 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#220 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#221 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#222 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#223 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#224 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#225 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#226 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#227 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 168.#228 I58 Def Alloc rax |I58 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#229 rdx Fixd Keep rdx |I58 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#230 I59 Def Alloc rdx |I58 a| |I59 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 169.#231 I58 Use * Keep rax |I58 a| |I59 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 169.#232 I59 Use * Keep rdx |I58 a| |I59 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 172.#233 I60 Def Alloc rsi | | | |V2 a|I60 a| | | | |V1 a|V4 a|V3 a|V5 a| 173.#234 I60 Use * Keep rsi | | | |V2 a|I60 a| | | | |V1 a|V4 a|V3 a|V5 a| 174.#235 V25 Def Alloc rsi | | | |V2 a|V25 a| | | | |V1 a|V4 a|V3 a|V5 a| 177.#236 V25 Use Keep rsi | | | |V2 a|V25 a| | | | |V1 a|V4 a|V3 a|V5 a| 178.#237 I61 Def Alloc rdi | | | |V2 a|V25 a|I61 a| | | |V1 a|V4 a|V3 a|V5 a| 179.#238 I61 Use * Keep rdi | | | |V2 a|V25 a|I61 a| | | |V1 a|V4 a|V3 a|V5 a| 185.#239 V25 Use * Keep rsi | | | |V2 a|V25 a| | | | |V1 a|V4 a|V3 a|V5 a| 186.#240 I62 Def Alloc rsi | | | |V2 a|I62 a| | | | |V1 a|V4 a|V3 a|V5 a| 187.#241 I62 Use * Keep rsi | | | |V2 a|I62 a| | | | |V1 a|V4 a|V3 a|V5 a| 192.#242 C63 Def Alloc rsi | | | |V2 a|C63 a| | | | |V1 a|V4 a|V3 a|V5 a| 193.#243 C63 Use * Keep rsi | | | |V2 a|C63 a| | | | |V1 a|V4 a|V3 a|V5 a| 194.#244 I64 Def Alloc rsi | | | |V2 a|I64 a| | | | |V1 a|V4 a|V3 a|V5 a| 195.#245 rsi Fixd Keep rsi | | | |V2 a|I64 a| | | | |V1 a|V4 a|V3 a|V5 a| 195.#246 I64 Use * Keep rsi | | | |V2 a|I64 a| | | | |V1 a|V4 a|V3 a|V5 a| 196.#247 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 196.#248 I65 Def Alloc rsi | | | |V2 a|I65 a| | | | |V1 a|V4 a|V3 a|V5 a| 198.#249 I66 Def Alloc rdi | | | |V2 a|I65 a|I66 a| | | |V1 a|V4 a|V3 a|V5 a| 199.#250 rdi Fixd Keep rdi | | | |V2 a|I65 a|I66 a| | | |V1 a|V4 a|V3 a|V5 a| 199.#251 I66 Use * Keep rdi | | | |V2 a|I65 a|I66 a| | | |V1 a|V4 a|V3 a|V5 a| 200.#252 rdi Fixd Keep rdi | | | |V2 a|I65 a| | | | |V1 a|V4 a|V3 a|V5 a| 200.#253 I67 Def Alloc rdi | | | |V2 a|I65 a|I67 a| | | |V1 a|V4 a|V3 a|V5 a| 202.#254 C68 Def Alloc rax |C68 a| | |V2 a|I65 a|I67 a| | | |V1 a|V4 a|V3 a|V5 a| 205.#255 rsi Fixd Keep rsi |C68 a| | |V2 a|I65 a|I67 a| | | |V1 a|V4 a|V3 a|V5 a| 205.#256 I65 Use * Keep rsi |C68 a| | |V2 a|I65 a|I67 a| | | |V1 a|V4 a|V3 a|V5 a| 205.#257 rdi Fixd Keep rdi |C68 a| | |V2 a|I65 a|I67 a| | | |V1 a|V4 a|V3 a|V5 a| 205.#258 I67 Use * Keep rdi |C68 a| | |V2 a|I65 a|I67 a| | | |V1 a|V4 a|V3 a|V5 a| 205.#259 C68 Use * Keep rax |C68 a| | |V2 a|I65 a|I67 a| | | |V1 a|V4 a|V3 a|V5 a| 206.#260 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#261 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#262 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#263 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#264 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#265 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#266 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#267 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#268 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#269 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#270 I69 Def Alloc rax |I69 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 209.#271 I69 Use * Keep rax |I69 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 213.#272 BB7 PredBB6 | | | |V2 i| | | | | |V1 i|V4 i|V3 i|V5 i| 219.#273 V7 Use * ReLod NA | | | |V2 i| | | | | |V1 i|V4 i|V3 i|V5 i| Alloc r13 | | | |V2 i| | | | | |V1 i|V7 i|V3 i|V5 i| 220.#274 V6 Def Alloc rax |V6 a| | |V2 i| | | | | |V1 i|V7 i|V3 i|V5 i| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 221.#275 BB8 PredBB7 |V6 a| | |V2 i| | | | | |V1 i|V7 i|V3 i|V5 i| 227.#276 rax Fixd Keep rax |V6 a| | |V2 i| | | | | |V1 i|V7 i|V3 i|V5 i| 227.#277 V6 Use * Keep rax |V6 i| | |V2 i| | | | | |V1 i|V7 i|V3 i|V5 i| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 229.#278 BB9 PredBB6 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 234.#279 C70 Def Alloc rsi |V6 i| | |V2 a|C70 a| | | | |V1 a|V4 a|V3 a|V5 a| 235.#280 C70 Use * Keep rsi |V6 i| | |V2 a|C70 a| | | | |V1 a|V4 a|V3 a|V5 a| 236.#281 I71 Def Alloc rsi |V6 i| | |V2 a|I71 a| | | | |V1 a|V4 a|V3 a|V5 a| 237.#282 rsi Fixd Keep rsi |V6 i| | |V2 a|I71 a| | | | |V1 a|V4 a|V3 a|V5 a| 237.#283 I71 Use * Keep rsi |V6 i| | |V2 a|I71 a| | | | |V1 a|V4 a|V3 a|V5 a| 238.#284 rsi Fixd Keep rsi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 238.#285 I72 Def Alloc rsi |V6 i| | |V2 a|I72 a| | | | |V1 a|V4 a|V3 a|V5 a| 240.#286 I73 Def Alloc rdi |V6 i| | |V2 a|I72 a|I73 a| | | |V1 a|V4 a|V3 a|V5 a| 241.#287 rdi Fixd Keep rdi |V6 i| | |V2 a|I72 a|I73 a| | | |V1 a|V4 a|V3 a|V5 a| 241.#288 I73 Use * Keep rdi |V6 i| | |V2 a|I72 a|I73 a| | | |V1 a|V4 a|V3 a|V5 a| 242.#289 rdi Fixd Keep rdi |V6 i| | |V2 a|I72 a| | | | |V1 a|V4 a|V3 a|V5 a| 242.#290 I74 Def Alloc rdi |V6 i| | |V2 a|I72 a|I74 a| | | |V1 a|V4 a|V3 a|V5 a| 244.#291 C75 Def Alloc rax |C75 a| | |V2 a|I72 a|I74 a| | | |V1 a|V4 a|V3 a|V5 a| 247.#292 rsi Fixd Keep rsi |C75 a| | |V2 a|I72 a|I74 a| | | |V1 a|V4 a|V3 a|V5 a| 247.#293 I72 Use * Keep rsi |C75 a| | |V2 a|I72 a|I74 a| | | |V1 a|V4 a|V3 a|V5 a| 247.#294 rdi Fixd Keep rdi |C75 a| | |V2 a|I72 a|I74 a| | | |V1 a|V4 a|V3 a|V5 a| 247.#295 I74 Use * Keep rdi |C75 a| | |V2 a|I72 a|I74 a| | | |V1 a|V4 a|V3 a|V5 a| 247.#296 C75 Use * Keep rax |C75 a| | |V2 a|I72 a|I74 a| | | |V1 a|V4 a|V3 a|V5 a| 248.#297 rax Kill Restr rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Keep rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#298 rcx Kill Keep rcx |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#299 rdx Kill Keep rdx |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#300 rsi Kill Keep rsi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#301 rdi Kill Keep rdi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#302 r8 Kill Keep r8 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#303 r9 Kill Keep r9 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#304 r10 Kill Keep r10 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#305 r11 Kill Keep r11 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#306 rax Fixd Keep rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#307 I76 Def Alloc rax |I76 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 249.#308 I76 Use * Keep rax |I76 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Restr rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 250.#309 V26 Def Alloc rdi |V6 i| | |V2 a| |V26 a| | | |V1 a|V4 a|V3 a|V5 a| 253.#310 rdi Fixd Keep rdi |V6 i| | |V2 a| |V26 a| | | |V1 a|V4 a|V3 a|V5 a| 253.#311 V26 Use * Keep rdi |V6 i| | |V2 a| |V26 a| | | |V1 a|V4 a|V3 a|V5 a| 254.#312 rdi Fixd Keep rdi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 254.#313 I77 Def Alloc rdi |V6 i| | |V2 a| |I77 a| | | |V1 a|V4 a|V3 a|V5 a| 257.#314 rsi Fixd Keep rsi |V6 i| | |V2 a| |I77 a| | | |V1 a|V4 a|V3 a|V5 a| 257.#315 V1 Use Copy rsi |V6 i| | |V2 a|V1 a|I77 a| | | |V1 a|V4 a|V3 a|V5 a| 258.#316 rsi Fixd Keep rsi |V6 i| | |V2 a|V1 a|I77 a| | | |V1 a|V4 a|V3 a|V5 a| 258.#317 I78 Def Alloc rsi |V6 i| | |V2 a|I78 a|I77 a| | | |V1 a|V4 a|V3 a|V5 a| 260.#318 r11 Fixd Keep r11 |V6 i| | |V2 a|I78 a|I77 a| | | |V1 a|V4 a|V3 a|V5 a| 260.#319 C79 Def Alloc r11 |V6 i| | |V2 a|I78 a|I77 a| | |C79 a|V1 a|V4 a|V3 a|V5 a| 261.#320 r11 Fixd Keep r11 |V6 i| | |V2 a|I78 a|I77 a| | |C79 a|V1 a|V4 a|V3 a|V5 a| 261.#321 C79 Use * Keep r11 |V6 i| | |V2 a|I78 a|I77 a| | |C79 a|V1 a|V4 a|V3 a|V5 a| 262.#322 r11 Fixd Keep r11 |V6 i| | |V2 a|I78 a|I77 a| | | |V1 a|V4 a|V3 a|V5 a| 262.#323 I80 Def Alloc r11 |V6 i| | |V2 a|I78 a|I77 a| | |I80 a|V1 a|V4 a|V3 a|V5 a| 264.#324 C81 Def Alloc rax |C81 a| | |V2 a|I78 a|I77 a| | |I80 a|V1 a|V4 a|V3 a|V5 a| 267.#325 rdi Fixd Keep rdi |C81 a| | |V2 a|I78 a|I77 a| | |I80 a|V1 a|V4 a|V3 a|V5 a| 267.#326 I77 Use * Keep rdi |C81 a| | |V2 a|I78 a|I77 a| | |I80 a|V1 a|V4 a|V3 a|V5 a| 267.#327 rsi Fixd Keep rsi |C81 a| | |V2 a|I78 a|I77 a| | |I80 a|V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 267.#328 I78 Use * Keep rsi |C81 a| | |V2 a|I78 a|I77 a| | |I80 a|V1 a|V4 a|V3 a|V5 a| 267.#329 r11 Fixd Keep r11 |C81 a| | |V2 a|I78 a|I77 a| | |I80 a|V1 a|V4 a|V3 a|V5 a| 267.#330 I80 Use * Keep r11 |C81 a| | |V2 a|I78 a|I77 a| | |I80 a|V1 a|V4 a|V3 a|V5 a| 267.#331 C81 Use * Keep rax |C81 a| | |V2 a|I78 a|I77 a| | |I80 a|V1 a|V4 a|V3 a|V5 a| 268.#332 rax Kill Restr rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Keep rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#333 rcx Kill Keep rcx |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#334 rdx Kill Keep rdx |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#335 rsi Kill Keep rsi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#336 rdi Kill Keep rdi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#337 r8 Kill Keep r8 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#338 r9 Kill Keep r9 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#339 r10 Kill Keep r10 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#340 r11 Kill Keep r11 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#341 rax Fixd Keep rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#342 I82 Def Alloc rax |I82 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#343 rdx Fixd Keep rdx |I82 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#344 I83 Def Alloc rdx |I82 a| |I83 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 269.#345 I82 Use * Keep rax |I82 a| |I83 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 269.#346 I83 Use * Keep rdx |I82 a| |I83 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Restr rax |V6 i| |I83 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 272.#347 I84 Def Alloc rax |I84 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 273.#348 I84 Use * Keep rax |I84 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Restr rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 274.#349 V10 Def Alloc rax |V10 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 279.#350 rdi Fixd Keep rdi |V10 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 279.#351 V10 Use Copy rdi |V10 a| | |V2 a| |V10 a| | | |V1 a|V4 a|V3 a|V5 a| 280.#352 rdi Fixd Keep rdi |V10 a| | |V2 a| |V10 a| | | |V1 a|V4 a|V3 a|V5 a| 280.#353 I85 Def Alloc rdi |V10 a| | |V2 a| |I85 a| | | |V1 a|V4 a|V3 a|V5 a| 282.#354 r11 Fixd Keep r11 |V10 a| | |V2 a| |I85 a| | | |V1 a|V4 a|V3 a|V5 a| 282.#355 C86 Def Alloc r11 |V10 a| | |V2 a| |I85 a| | |C86 a|V1 a|V4 a|V3 a|V5 a| 283.#356 r11 Fixd Keep r11 |V10 a| | |V2 a| |I85 a| | |C86 a|V1 a|V4 a|V3 a|V5 a| 283.#357 C86 Use * Keep r11 |V10 a| | |V2 a| |I85 a| | |C86 a|V1 a|V4 a|V3 a|V5 a| 284.#358 r11 Fixd Keep r11 |V10 a| | |V2 a| |I85 a| | | |V1 a|V4 a|V3 a|V5 a| 284.#359 I87 Def Alloc r11 |V10 a| | |V2 a| |I85 a| | |I87 a|V1 a|V4 a|V3 a|V5 a| 286.#360 C88 Def Alloc rsi |V10 a| | |V2 a|C88 a|I85 a| | |I87 a|V1 a|V4 a|V3 a|V5 a| 289.#361 rdi Fixd Keep rdi |V10 a| | |V2 a|C88 a|I85 a| | |I87 a|V1 a|V4 a|V3 a|V5 a| 289.#362 I85 Use * Keep rdi |V10 a| | |V2 a|C88 a|I85 a| | |I87 a|V1 a|V4 a|V3 a|V5 a| 289.#363 r11 Fixd Keep r11 |V10 a| | |V2 a|C88 a|I85 a| | |I87 a|V1 a|V4 a|V3 a|V5 a| 289.#364 I87 Use * Keep r11 |V10 a| | |V2 a|C88 a|I85 a| | |I87 a|V1 a|V4 a|V3 a|V5 a| 289.#365 C88 Use * Keep rsi |V10 a| | |V2 a|C88 a|I85 a| | |I87 a|V1 a|V4 a|V3 a|V5 a| 290.#366 rax Kill Spill rax | | | |V2 a|C88 i| | | | |V1 a|V4 a|V3 a|V5 a| Keep rax | | | |V2 a|C88 i| | | | |V1 a|V4 a|V3 a|V5 a| 290.#367 rcx Kill Keep rcx | | | |V2 a|C88 i| | | | |V1 a|V4 a|V3 a|V5 a| 290.#368 rdx Kill Keep rdx | | | |V2 a|C88 i| | | | |V1 a|V4 a|V3 a|V5 a| 290.#369 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#370 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#371 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#372 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#373 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#374 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#375 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 290.#376 I89 Def Alloc rax |I89 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 293.#377 I89 Use * Keep rax |I89 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Restr rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 297.#378 BB10 PredBB9 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 303.#379 rdi Fixd Keep rdi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 303.#380 V10 Use ReLod NA |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Alloc rdi |V6 i| | |V2 a| |V10 a| | | |V1 a|V4 a|V3 a|V5 a| 304.#381 rdi Fixd Keep rdi |V6 i| | |V2 a| |V10 a| | | |V1 a|V4 a|V3 a|V5 a| 304.#382 I90 Def PtArg rdi |V6 i| | |V2 a| |V10 a| | | |V1 a|V4 a|V3 a|V5 a| 307.#383 rsi Fixd Keep rsi |V6 i| | |V2 a| |V10 a| | | |V1 a|V4 a|V3 a|V5 a| 307.#384 V5 Use Copy rsi |V6 i| | |V2 a|V5 a|V10 a| | | |V1 a|V4 a|V3 a|V5 a| 308.#385 rsi Fixd Keep rsi |V6 i| | |V2 a|V5 a|V10 a| | | |V1 a|V4 a|V3 a|V5 a| 308.#386 I91 Def Alloc rsi |V6 i| | |V2 a|I91 a|V10 a| | | |V1 a|V4 a|V3 a|V5 a| 310.#387 C92 Def Alloc rax |C92 a| | |V2 a|I91 a|V10 a| | | |V1 a|V4 a|V3 a|V5 a| 313.#388 rdi Fixd Keep rdi |C92 a| | |V2 a|I91 a|V10 a| | | |V1 a|V4 a|V3 a|V5 a| 313.#389 I90 Use * PtArg rdi |C92 a| | |V2 a|I91 a|V10 a| | | |V1 a|V4 a|V3 a|V5 a| 313.#390 rsi Fixd Keep rsi |C92 a| | |V2 a|I91 a|V10 a| | | |V1 a|V4 a|V3 a|V5 a| 313.#391 I91 Use * Keep rsi |C92 a| | |V2 a|I91 a|V10 a| | | |V1 a|V4 a|V3 a|V5 a| 313.#392 C92 Use * Keep rax |C92 a| | |V2 a|I91 a|V10 a| | | |V1 a|V4 a|V3 a|V5 a| 314.#393 rax Kill Restr rax |V6 i| | |V2 a| |V10 a| | | |V1 a|V4 a|V3 a|V5 a| Keep rax |V6 i| | |V2 a| |V10 a| | | |V1 a|V4 a|V3 a|V5 a| 314.#394 rcx Kill Keep rcx |V6 i| | |V2 a| |V10 a| | | |V1 a|V4 a|V3 a|V5 a| 314.#395 rdx Kill Keep rdx |V6 i| | |V2 a| |V10 a| | | |V1 a|V4 a|V3 a|V5 a| 314.#396 rsi Kill Keep rsi |V6 i| | |V2 a| |V10 a| | | |V1 a|V4 a|V3 a|V5 a| 314.#397 rdi Kill Spill rdi |V6 i| | |V2 a| |Busy | | | |V1 a|V4 a|V3 a|V5 a| Keep rdi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#398 r8 Kill Keep r8 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#399 r9 Kill Keep r9 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#400 r10 Kill Keep r10 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#401 r11 Kill Keep r11 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 317.#402 BB12 PredBB5 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 323.#403 rdi Fixd Keep rdi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 323.#404 V0 Use * ReLod NA |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Alloc rdi |V6 i| | |V2 a| |V0 i| | | |V1 a|V4 a|V3 a|V5 a| 324.#405 rdi Fixd Keep rdi |V6 i| | |V2 a| |V0 i| | | |V1 a|V4 a|V3 a|V5 a| 324.#406 I93 Def Alloc rdi |V6 i| | |V2 a| |I93 a| | | |V1 a|V4 a|V3 a|V5 a| 327.#407 rsi Fixd Keep rsi |V6 i| | |V2 a| |I93 a| | | |V1 a|V4 a|V3 a|V5 a| 327.#408 V2 Use Copy rsi |V6 i| | |V2 a|V2 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 328.#409 rsi Fixd Keep rsi |V6 i| | |V2 a|V2 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 328.#410 I94 Def Alloc rsi |V6 i| | |V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 331.#411 rdx Fixd Keep rdx |V6 i| | |V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 331.#412 V3 Use Copy rdx |V6 i| |V3 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 332.#413 rdx Fixd Keep rdx |V6 i| |V3 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 332.#414 I95 Def Alloc rdx |V6 i| |I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 335.#415 rcx Fixd Keep rcx |V6 i| |I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 335.#416 V4 Use Copy rcx |V6 i|V4 a|I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 336.#417 rcx Fixd Keep rcx |V6 i|V4 a|I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 336.#418 I96 Def Alloc rcx |V6 i|I96 a|I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 339.#419 r8 Fixd Keep r8 |V6 i|I96 a|I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 339.#420 V5 Use Copy r8 |V6 i|I96 a|I95 a|V2 a|I94 a|I93 a|V5 a| | |V1 a|V4 a|V3 a|V5 a| 340.#421 r8 Fixd Keep r8 |V6 i|I96 a|I95 a|V2 a|I94 a|I93 a|V5 a| | |V1 a|V4 a|V3 a|V5 a| 340.#422 I97 Def Alloc r8 |V6 i|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 342.#423 C98 Def Alloc rax |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#424 rdi Fixd Keep rdi |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#425 I93 Use * Keep rdi |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#426 rsi Fixd Keep rsi |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#427 I94 Use * Keep rsi |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#428 rdx Fixd Keep rdx |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#429 I95 Use * Keep rdx |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#430 rcx Fixd Keep rcx |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#431 I96 Use * Keep rcx |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#432 r8 Fixd Keep r8 |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#433 I97 Use * Keep r8 |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#434 C98 Use * Keep rax |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| Restr rdi |C98 i| | |V2 a| |V0 i|I97 a| | |V1 a|V4 a|V3 a|V5 a| 346.#435 rax Kill Restr rax |V6 i| | |V2 a| |V0 i| | | |V1 a|V4 a|V3 a|V5 a| Keep rax |V6 i| | |V2 a| |V0 i| | | |V1 a|V4 a|V3 a|V5 a| 346.#436 rcx Kill Keep rcx |V6 i| | |V2 a| |V0 i| | | |V1 a|V4 a|V3 a|V5 a| 346.#437 rdx Kill Keep rdx |V6 i| | |V2 a| |V0 i| | | |V1 a|V4 a|V3 a|V5 a| 346.#438 rsi Kill Keep rsi |V6 i| | |V2 a| |V0 i| | | |V1 a|V4 a|V3 a|V5 a| 346.#439 rdi Kill Keep rdi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#440 r8 Kill Keep r8 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#441 r9 Kill Keep r9 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#442 r10 Kill Keep r10 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#443 r11 Kill Keep r11 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#444 rax Fixd Keep rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#445 I99 Def Alloc rax |I99 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 349.#446 I99 Use * Keep rax |I99 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Restr rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 353.#447 BB13 PredBB12 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 355.#448 BB14 PredBB9 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 361.#449 rdi Fixd Keep rdi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 361.#450 V3 Use Copy rdi |V6 i| | |V2 a| |V3 a| | | |V1 a|V4 a|V3 a|V5 a| 362.#451 rdi Fixd Keep rdi |V6 i| | |V2 a| |V3 a| | | |V1 a|V4 a|V3 a|V5 a| 362.#452 I100 Def Alloc rdi |V6 i| | |V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| 365.#453 rsi Fixd Keep rsi |V6 i| | |V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| 365.#454 V10 Use ReLod NA |V6 i| | |V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| Alloc rsi |V6 i| | |V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 366.#455 rsi Fixd Keep rsi |V6 i| | |V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 366.#456 I101 Def PtArg rsi |V6 i| | |V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 369.#457 rdx Fixd Keep rdx |V6 i| | |V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 369.#458 V5 Use Copy rdx |V6 i| |V5 a|V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 370.#459 rdx Fixd Keep rdx |V6 i| |V5 a|V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 370.#460 I102 Def Alloc rdx |V6 i| |I102a|V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 372.#461 C103 Def Alloc rax |C103a| |I102a|V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 375.#462 rdi Fixd Keep rdi |C103a| |I102a|V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 375.#463 I100 Use * Keep rdi |C103a| |I102a|V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 375.#464 rsi Fixd Keep rsi |C103a| |I102a|V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 375.#465 I101 Use * PtArg rsi |C103a| |I102a|V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 375.#466 rdx Fixd Keep rdx |C103a| |I102a|V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 375.#467 I102 Use * Keep rdx |C103a| |I102a|V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 375.#468 C103 Use * Keep rax |C103a| |I102a|V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| 376.#469 rax Kill Restr rax |V6 i| | |V2 a|V10 a| | | | |V1 a|V4 a|V3 a|V5 a| Keep rax |V6 i| | |V2 a|V10 a| | | | |V1 a|V4 a|V3 a|V5 a| 376.#470 rcx Kill Keep rcx |V6 i| | |V2 a|V10 a| | | | |V1 a|V4 a|V3 a|V5 a| 376.#471 rdx Kill Keep rdx |V6 i| | |V2 a|V10 a| | | | |V1 a|V4 a|V3 a|V5 a| 376.#472 rsi Kill Spill rsi |V6 i| | |V2 a|Busy | | | | |V1 a|V4 a|V3 a|V5 a| Keep rsi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#473 rdi Kill Keep rdi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#474 r8 Kill Keep r8 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#475 r9 Kill Keep r9 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#476 r10 Kill Keep r10 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#477 r11 Kill Keep r11 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#478 rax Fixd Keep rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#479 I104 Def Alloc rax |I104a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 377.#480 I104 Use * Keep rax |I104a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Restr rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 378.#481 I105 Def Alloc rsi |V6 i| | |V2 a|I105a| | | | |V1 a|V4 a|V3 a|V5 a| 379.#482 I105 Use * Keep rsi |V6 i| | |V2 a|I105a| | | | |V1 a|V4 a|V3 a|V5 a| 380.#483 V19 Def Alloc rsi |V6 i| | |V2 a|V19 a| | | | |V1 a|V4 a|V3 a|V5 a| 385.#484 V19 Use * Keep rsi |V6 i| | |V2 a|V19 a| | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 389.#485 BB15 PredBB14 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 394.#486 C106 Def Alloc rsi |V6 i| | |V2 a|C106a| | | | |V1 a|V4 a|V3 a|V5 a| 395.#487 C106 Use * Keep rsi |V6 i| | |V2 a|C106a| | | | |V1 a|V4 a|V3 a|V5 a| 396.#488 I107 Def Alloc rsi |V6 i| | |V2 a|I107a| | | | |V1 a|V4 a|V3 a|V5 a| 397.#489 rsi Fixd Keep rsi |V6 i| | |V2 a|I107a| | | | |V1 a|V4 a|V3 a|V5 a| 397.#490 I107 Use * Keep rsi |V6 i| | |V2 a|I107a| | | | |V1 a|V4 a|V3 a|V5 a| 398.#491 rsi Fixd Keep rsi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 398.#492 I108 Def Alloc rsi |V6 i| | |V2 a|I108a| | | | |V1 a|V4 a|V3 a|V5 a| 400.#493 I109 Def Alloc rdi |V6 i| | |V2 a|I108a|I109a| | | |V1 a|V4 a|V3 a|V5 a| 401.#494 rdi Fixd Keep rdi |V6 i| | |V2 a|I108a|I109a| | | |V1 a|V4 a|V3 a|V5 a| 401.#495 I109 Use * Keep rdi |V6 i| | |V2 a|I108a|I109a| | | |V1 a|V4 a|V3 a|V5 a| 402.#496 rdi Fixd Keep rdi |V6 i| | |V2 a|I108a| | | | |V1 a|V4 a|V3 a|V5 a| 402.#497 I110 Def Alloc rdi |V6 i| | |V2 a|I108a|I110a| | | |V1 a|V4 a|V3 a|V5 a| 404.#498 C111 Def Alloc rax |C111a| | |V2 a|I108a|I110a| | | |V1 a|V4 a|V3 a|V5 a| 407.#499 rsi Fixd Keep rsi |C111a| | |V2 a|I108a|I110a| | | |V1 a|V4 a|V3 a|V5 a| 407.#500 I108 Use * Keep rsi |C111a| | |V2 a|I108a|I110a| | | |V1 a|V4 a|V3 a|V5 a| 407.#501 rdi Fixd Keep rdi |C111a| | |V2 a|I108a|I110a| | | |V1 a|V4 a|V3 a|V5 a| 407.#502 I110 Use * Keep rdi |C111a| | |V2 a|I108a|I110a| | | |V1 a|V4 a|V3 a|V5 a| 407.#503 C111 Use * Keep rax |C111a| | |V2 a|I108a|I110a| | | |V1 a|V4 a|V3 a|V5 a| 408.#504 rax Kill Restr rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Keep rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#505 rcx Kill Keep rcx |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#506 rdx Kill Keep rdx |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#507 rsi Kill Keep rsi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#508 rdi Kill Keep rdi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#509 r8 Kill Keep r8 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#510 r9 Kill Keep r9 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#511 r10 Kill Keep r10 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#512 r11 Kill Keep r11 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#513 rax Fixd Keep rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#514 I112 Def Alloc rax |I112a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 411.#515 I112 Use * Keep rax |I112a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Restr rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 415.#516 V2 ExpU Keep NA |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 415.#517 V3 ExpU Keep NA |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 415.#518 V5 ExpU Keep NA |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 415.#519 V1 ExpU Keep NA |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 415.#520 V4 ExpU Keep NA |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 415.#521 BB16 PredBB6 |V6 i| | |V2 i| | | | | |V1 i|V4 i|V3 i|V5 i| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 417.#522 BB17 PredBB4 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 421.#523 rdi Fixd Keep rdi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 421.#524 V2 Use Copy rdi |V6 i| | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 422.#525 rdi Fixd Keep rdi |V6 i| | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 422.#526 I113 Def Alloc rdi |V6 i| | |V2 a| |I113a| | | |V1 a|V4 a|V3 a|V5 a| 425.#527 rsi Fixd Keep rsi |V6 i| | |V2 a| |I113a| | | |V1 a|V4 a|V3 a|V5 a| 425.#528 V3 Use Copy rsi |V6 i| | |V2 a|V3 a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 426.#529 rsi Fixd Keep rsi |V6 i| | |V2 a|V3 a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 426.#530 I114 Def Alloc rsi |V6 i| | |V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 429.#531 rdx Fixd Keep rdx |V6 i| | |V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 429.#532 V4 Use Copy rdx |V6 i| |V4 a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 430.#533 rdx Fixd Keep rdx |V6 i| |V4 a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 430.#534 I115 Def Alloc rdx |V6 i| |I115a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 432.#535 C116 Def Alloc rax |C116a| |I115a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 435.#536 rdi Fixd Keep rdi |C116a| |I115a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 435.#537 I113 Use * Keep rdi |C116a| |I115a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 435.#538 rsi Fixd Keep rsi |C116a| |I115a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 435.#539 I114 Use * Keep rsi |C116a| |I115a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 435.#540 rdx Fixd Keep rdx |C116a| |I115a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 435.#541 I115 Use * Keep rdx |C116a| |I115a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 435.#542 C116 Use * Keep rax |C116a| |I115a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 436.#543 rax Kill Restr rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Keep rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#544 rcx Kill Keep rcx |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#545 rdx Kill Keep rdx |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#546 rsi Kill Keep rsi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#547 rdi Kill Keep rdi |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#548 r8 Kill Keep r8 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#549 r9 Kill Keep r9 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#550 r10 Kill Keep r10 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#551 r11 Kill Keep r11 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#552 rax Fixd Keep rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#553 I117 Def Alloc rax |I117a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 439.#554 I117 Use * Keep rax |I117a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Restr rax |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 443.#555 V7 ExpU Keep NA |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 443.#556 BB18 PredBB4 |V6 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 448.#557 C118 Def Alloc rdi |V6 i| | |V2 a| |C118a| | | |V1 a|V4 a|V3 a|V5 a| 449.#558 C118 Use * Keep rdi |V6 i| | |V2 a| |C118a| | | |V1 a|V4 a|V3 a|V5 a| 450.#559 V7 Def Alloc rax |V7 a| | |V2 a| |C118i| | | |V1 a|V4 a|V3 a|V5 a| 451.#560 V0 ExpU Keep NA |V7 a| | |V2 a| |C118i| | | |V1 a|V4 a|V3 a|V5 a| 451.#561 V7 ExpU Keep NA |V7 a| | |V2 a| |C118i| | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 451.#562 BB19 PredBB10 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 459.#563 V4 Use Keep r13 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 463.#564 BB20 PredBB19 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 468.#565 C119 Def Alloc rdi |V7 i| | |V2 a| |C119a| | | |V1 a|V4 a|V3 a|V5 a| 469.#566 rdi Fixd Keep rdi |V7 i| | |V2 a| |C119a| | | |V1 a|V4 a|V3 a|V5 a| 469.#567 C119 Use * Keep rdi |V7 i| | |V2 a| |C119a| | | |V1 a|V4 a|V3 a|V5 a| 470.#568 rdi Fixd Keep rdi |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 470.#569 I120 Def Alloc rdi |V7 i| | |V2 a| |I120a| | | |V1 a|V4 a|V3 a|V5 a| 472.#570 C121 Def Alloc rax |C121a| | |V2 a| |I120a| | | |V1 a|V4 a|V3 a|V5 a| 475.#571 rdi Fixd Keep rdi |C121a| | |V2 a| |I120a| | | |V1 a|V4 a|V3 a|V5 a| 475.#572 I120 Use * Keep rdi |C121a| | |V2 a| |I120a| | | |V1 a|V4 a|V3 a|V5 a| 475.#573 C121 Use * Keep rax |C121a| | |V2 a| |I120a| | | |V1 a|V4 a|V3 a|V5 a| 476.#574 rax Kill Restr rax |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Keep rax |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#575 rcx Kill Keep rcx |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#576 rdx Kill Keep rdx |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#577 rsi Kill Keep rsi |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#578 rdi Kill Keep rdi |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#579 r8 Kill Keep r8 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#580 r9 Kill Keep r9 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#581 r10 Kill Keep r10 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#582 r11 Kill Keep r11 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#583 rax Fixd Keep rax |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#584 I122 Def Alloc rax |I122a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 477.#585 I122 Use * Keep rax |I122a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Restr rax |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 478.#586 V14 Def Alloc rax |V14 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 485.#587 V14 Use Keep rax |V14 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 486.#588 I123 Def Alloc rdx |V14 a| |I123a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 487.#589 I123 Use * Keep rdx |V14 a| |I123a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 488.#590 V28 Def Alloc rdx |V14 a| |V28 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 491.#591 V28 Use Keep rdx |V14 a| |V28 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 495.#592 V14 Use Keep rax |V14 a| |V28 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 496.#593 I124 Def Alloc rdi |V14 a| |V28 a|V2 a| |I124a| | | |V1 a|V4 a|V3 a|V5 a| 499.#594 rdi Fixd Keep rdi |V14 a| |V28 a|V2 a| |I124a| | | |V1 a|V4 a|V3 a|V5 a| 499.#595 I124 Use * Keep rdi |V14 a| |V28 a|V2 a| |I124a| | | |V1 a|V4 a|V3 a|V5 a| 499.#596 rsi Fixd Keep rsi |V14 a| |V28 a|V2 a| |I124a| | | |V1 a|V4 a|V3 a|V5 a| 499.#597 V3 Use Copy rsi |V14 a| |V28 a|V2 a|V3 a|I124a| | | |V1 a|V4 a|V3 a|V5 a| 500.#598 rax Kill Spill rax | | |V28 a|V2 a|V3 a| | | | |V1 a|V4 a|V3 a|V5 a| Keep rax | | |V28 a|V2 a|V3 a| | | | |V1 a|V4 a|V3 a|V5 a| 500.#599 rcx Kill Keep rcx | | |V28 a|V2 a|V3 a| | | | |V1 a|V4 a|V3 a|V5 a| 500.#600 rdx Kill Spill rdx | | | |V2 a|V3 a| | | | |V1 a|V4 a|V3 a|V5 a| Keep rdx | | | |V2 a|V3 a| | | | |V1 a|V4 a|V3 a|V5 a| 500.#601 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#602 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#603 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#604 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#605 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#606 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#607 mm0 Kill Keep mm0 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#608 mm1 Kill Keep mm1 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#609 mm2 Kill Keep mm2 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#610 mm3 Kill Keep mm3 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#611 mm4 Kill Keep mm4 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#612 mm5 Kill Keep mm5 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#613 mm6 Kill Keep mm6 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#614 mm7 Kill Keep mm7 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#615 mm8 Kill Keep mm8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#616 mm9 Kill Keep mm9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#617 mm10 Kill Keep mm10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#618 mm11 Kill Keep mm11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#619 mm12 Kill Keep mm12 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#620 mm13 Kill Keep mm13 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#621 mm14 Kill Keep mm14 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#622 mm15 Kill Keep mm15 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 505.#623 V28 Use * ReLod NA | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| NoReg | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 509.#624 V14 Use ReLod NA | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Alloc rax |V14 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 510.#625 I125 Def Alloc rdi |V14 a| | |V2 a| |I125a| | | |V1 a|V4 a|V3 a|V5 a| 513.#626 rdi Fixd Keep rdi |V14 a| | |V2 a| |I125a| | | |V1 a|V4 a|V3 a|V5 a| 513.#627 I125 Use * Keep rdi |V14 a| | |V2 a| |I125a| | | |V1 a|V4 a|V3 a|V5 a| 513.#628 rsi Fixd Keep rsi |V14 a| | |V2 a| |I125a| | | |V1 a|V4 a|V3 a|V5 a| 513.#629 V10 Use * ReLod NA |V14 a| | |V2 a| |I125a| | | |V1 a|V4 a|V3 a|V5 a| Alloc rsi |V14 a| | |V2 a|V10 a|I125a| | | |V1 a|V4 a|V3 a|V5 a| 514.#630 rax Kill Spill rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#631 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#632 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#633 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#634 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#635 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#636 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#637 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#638 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#639 mm0 Kill Keep mm0 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#640 mm1 Kill Keep mm1 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#641 mm2 Kill Keep mm2 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#642 mm3 Kill Keep mm3 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#643 mm4 Kill Keep mm4 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#644 mm5 Kill Keep mm5 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#645 mm6 Kill Keep mm6 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#646 mm7 Kill Keep mm7 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#647 mm8 Kill Keep mm8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#648 mm9 Kill Keep mm9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#649 mm10 Kill Keep mm10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#650 mm11 Kill Keep mm11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#651 mm12 Kill Keep mm12 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#652 mm13 Kill Keep mm13 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#653 mm14 Kill Keep mm14 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#654 mm15 Kill Keep mm15 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 516.#655 C126 Def Alloc rax |C126a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 519.#656 C126 Use * Keep rax |C126a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#657 rax Kill Restr rax |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Keep rax |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#658 rcx Kill Keep rcx |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#659 rdx Kill Keep rdx |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#660 rsi Kill Keep rsi |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#661 rdi Kill Keep rdi |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#662 r8 Kill Keep r8 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#663 r9 Kill Keep r9 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#664 r10 Kill Keep r10 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#665 r11 Kill Keep r11 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#666 rax Fixd Keep rax |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#667 I127 Def Alloc rax |I127a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 521.#668 I127 Use * Keep rax |I127a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Restr rax |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 522.#669 V20 Def Alloc rax |V20 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 524.#670 C128 Def Alloc rdi |V20 a| | |V2 a| |C128a| | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 527.#671 C128 Use * Keep rdi |V20 a| | |V2 a| |C128a| | | |V1 a|V4 a|V3 a|V5 a| 528.#672 rax Kill Spill rax | | | |V2 a| |C128i| | | |V1 a|V4 a|V3 a|V5 a| Keep rax | | | |V2 a| |C128i| | | |V1 a|V4 a|V3 a|V5 a| 528.#673 rcx Kill Keep rcx | | | |V2 a| |C128i| | | |V1 a|V4 a|V3 a|V5 a| 528.#674 rdx Kill Keep rdx | | | |V2 a| |C128i| | | |V1 a|V4 a|V3 a|V5 a| 528.#675 rsi Kill Keep rsi | | | |V2 a| |C128i| | | |V1 a|V4 a|V3 a|V5 a| 528.#676 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#677 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#678 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#679 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#680 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#681 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#682 I129 Def Alloc rax |I129a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 531.#683 I129 Use * Keep rax |I129a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Restr rax |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 532.#684 I130 Def Alloc rsi |V7 i| | |V2 a|I130a| | | | |V1 a|V4 a|V3 a|V5 a| 533.#685 I130 Use * Keep rsi |V7 i| | |V2 a|I130a| | | | |V1 a|V4 a|V3 a|V5 a| 534.#686 V27 Def Alloc rsi |V7 i| | |V2 a|V27 a| | | | |V1 a|V4 a|V3 a|V5 a| 537.#687 rsi Fixd Keep rsi |V7 i| | |V2 a|V27 a| | | | |V1 a|V4 a|V3 a|V5 a| 537.#688 V27 Use * Keep rsi |V7 i| | |V2 a|V27 a| | | | |V1 a|V4 a|V3 a|V5 a| 538.#689 rsi Fixd Keep rsi |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 538.#690 I131 Def Alloc rsi |V7 i| | |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 541.#691 rdi Fixd Keep rdi |V7 i| | |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 541.#692 V20 Use ReLod NA |V7 i| | |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| Alloc rdi |V7 i| | |V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 542.#693 rdi Fixd Keep rdi |V7 i| | |V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 542.#694 I132 Def PtArg rdi |V7 i| | |V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 545.#695 rcx Fixd Keep rcx |V7 i| | |V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 545.#696 V14 Use * ReLod NA |V7 i| | |V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| Alloc rcx |V7 i|V14 a| |V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 546.#697 rcx Fixd Keep rcx |V7 i| | |V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 546.#698 I133 Def Alloc rcx |V7 i|I133a| |V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 548.#699 C134 Def Alloc rdx |V7 i|I133a|C134a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 549.#700 rdx Fixd Keep rdx |V7 i|I133a|C134a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 549.#701 C134 Use * Keep rdx |V7 i|I133a|C134a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 550.#702 rdx Fixd Keep rdx |V7 i|I133a| |V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 550.#703 I135 Def Alloc rdx |V7 i|I133a|I135a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 552.#704 C136 Def Alloc rax |C136a|I133a|I135a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 555.#705 rsi Fixd Keep rsi |C136a|I133a|I135a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 555.#706 I131 Use * Keep rsi |C136a|I133a|I135a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 555.#707 rdi Fixd Keep rdi |C136a|I133a|I135a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 555.#708 I132 Use * PtArg rdi |C136a|I133a|I135a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 555.#709 rcx Fixd Keep rcx |C136a|I133a|I135a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 555.#710 I133 Use * Keep rcx |C136a|I133a|I135a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 555.#711 rdx Fixd Keep rdx |C136a|I133a|I135a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 555.#712 I135 Use * Keep rdx |C136a|I133a|I135a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 555.#713 C136 Use * Keep rax |C136a|I133a|I135a|V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| 556.#714 rax Kill Restr rax |V7 i| | |V2 a| |V20 a| | | |V1 a|V4 a|V3 a|V5 a| Keep rax |V7 i| | |V2 a| |V20 a| | | |V1 a|V4 a|V3 a|V5 a| 556.#715 rcx Kill Keep rcx |V7 i| | |V2 a| |V20 a| | | |V1 a|V4 a|V3 a|V5 a| 556.#716 rdx Kill Keep rdx |V7 i| | |V2 a| |V20 a| | | |V1 a|V4 a|V3 a|V5 a| 556.#717 rsi Kill Keep rsi |V7 i| | |V2 a| |V20 a| | | |V1 a|V4 a|V3 a|V5 a| 556.#718 rdi Kill Spill rdi |V7 i| | |V2 a| |Busy | | | |V1 a|V4 a|V3 a|V5 a| Keep rdi |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#719 r8 Kill Keep r8 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#720 r9 Kill Keep r9 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#721 r10 Kill Keep r10 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#722 r11 Kill Keep r11 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 558.#723 C137 Def Alloc rdi |V7 i| | |V2 a| |C137a| | | |V1 a|V4 a|V3 a|V5 a| 561.#724 I138 Def Alloc mm0 |V7 i| | |V2 a| |C137a| | | |V1 a|V4 a|V3 a|V5 a| 561.#725 C137 Use * Keep rdi |V7 i| | |V2 a| |C137a| | | |V1 a|V4 a|V3 a|V5 a| 561.#726 I138 Use * Keep mm0 |V7 i| | |V2 a| |C137a| | | |V1 a|V4 a|V3 a|V5 a| 565.#727 V2 Use Keep rbx |V7 i| | |V2 a| |C137i| | | |V1 a|V4 a|V3 a|V5 a| 569.#728 V20 Use * ReLod NA |V7 i| | |V2 a| |C137i| | | |V1 a|V4 a|V3 a|V5 a| Alloc rdi |V7 i| | |V2 a| |V20 a| | | |V1 a|V4 a|V3 a|V5 a| 577.#729 rdi Fixd Keep rdi |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 577.#730 I139 Def Alloc rdi |V7 i| | |V2 a| |I139a| | | |V1 a|V4 a|V3 a|V5 a| 577.#731 rcx Fixd Keep rcx |V7 i| | |V2 a| |I139a| | | |V1 a|V4 a|V3 a|V5 a| 577.#732 I140 Def Alloc rcx |V7 i|I140a| |V2 a| |I139a| | | |V1 a|V4 a|V3 a|V5 a| 577.#733 rsi Fixd Keep rsi |V7 i|I140a| |V2 a| |I139a| | | |V1 a|V4 a|V3 a|V5 a| 577.#734 I141 Def Alloc rsi |V7 i|I140a| |V2 a|I141a|I139a| | | |V1 a|V4 a|V3 a|V5 a| 577.#735 I139 Use * Keep rdi |V7 i|I140a| |V2 a|I141a|I139a| | | |V1 a|V4 a|V3 a|V5 a| 577.#736 I140 Use * Keep rcx |V7 i|I140a| |V2 a|I141a|I139a| | | |V1 a|V4 a|V3 a|V5 a| 577.#737 I141 Use * Keep rsi |V7 i|I140a| |V2 a|I141a|I139a| | | |V1 a|V4 a|V3 a|V5 a| 581.#738 rdi Fixd Keep rdi |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 581.#739 V4 Use Copy rdi |V7 i| | |V2 a| |V4 a| | | |V1 a|V4 a|V3 a|V5 a| 582.#740 rdi Fixd Keep rdi |V7 i| | |V2 a| |V4 a| | | |V1 a|V4 a|V3 a|V5 a| 582.#741 I142 Def Alloc rdi |V7 i| | |V2 a| |I142a| | | |V1 a|V4 a|V3 a|V5 a| 584.#742 r11 Fixd Keep r11 |V7 i| | |V2 a| |I142a| | | |V1 a|V4 a|V3 a|V5 a| 584.#743 C143 Def Alloc r11 |V7 i| | |V2 a| |I142a| | |C143a|V1 a|V4 a|V3 a|V5 a| 585.#744 r11 Fixd Keep r11 |V7 i| | |V2 a| |I142a| | |C143a|V1 a|V4 a|V3 a|V5 a| 585.#745 C143 Use * Keep r11 |V7 i| | |V2 a| |I142a| | |C143a|V1 a|V4 a|V3 a|V5 a| 586.#746 r11 Fixd Keep r11 |V7 i| | |V2 a| |I142a| | | |V1 a|V4 a|V3 a|V5 a| 586.#747 I144 Def Alloc r11 |V7 i| | |V2 a| |I142a| | |I144a|V1 a|V4 a|V3 a|V5 a| 588.#748 C145 Def Alloc rax |C145a| | |V2 a| |I142a| | |I144a|V1 a|V4 a|V3 a|V5 a| 591.#749 rdi Fixd Keep rdi |C145a| | |V2 a| |I142a| | |I144a|V1 a|V4 a|V3 a|V5 a| 591.#750 I142 Use * Keep rdi |C145a| | |V2 a| |I142a| | |I144a|V1 a|V4 a|V3 a|V5 a| 591.#751 r11 Fixd Keep r11 |C145a| | |V2 a| |I142a| | |I144a|V1 a|V4 a|V3 a|V5 a| 591.#752 I144 Use * Keep r11 |C145a| | |V2 a| |I142a| | |I144a|V1 a|V4 a|V3 a|V5 a| 591.#753 C145 Use * Keep rax |C145a| | |V2 a| |I142a| | |I144a|V1 a|V4 a|V3 a|V5 a| 592.#754 rax Kill Restr rax |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Keep rax |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#755 rcx Kill Keep rcx |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#756 rdx Kill Keep rdx |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#757 rsi Kill Keep rsi |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#758 rdi Kill Keep rdi |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#759 r8 Kill Keep r8 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#760 r9 Kill Keep r9 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#761 r10 Kill Keep r10 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#762 r11 Kill Keep r11 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 593.#763 BB21 PredBB19 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 598.#764 C146 Def Alloc rax |C146a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 599.#765 C146 Use * Keep rax |C146a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 600.#766 V7 Def Alloc rax |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 601.#767 BB22 PredBB3 |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 607.#768 rdi Fixd Keep rdi |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 607.#769 V2 Use Copy rdi |V7 a| | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 608.#770 rdi Fixd Keep rdi |V7 a| | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 608.#771 I147 Def Alloc rdi |V7 a| | |V2 a| |I147a| | | |V1 a|V4 a|V3 a|V5 a| 611.#772 rsi Fixd Keep rsi |V7 a| | |V2 a| |I147a| | | |V1 a|V4 a|V3 a|V5 a| 611.#773 V3 Use Copy rsi |V7 a| | |V2 a|V3 a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 612.#774 rsi Fixd Keep rsi |V7 a| | |V2 a|V3 a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 612.#775 I148 Def Alloc rsi |V7 a| | |V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 615.#776 rdx Fixd Keep rdx |V7 a| | |V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 615.#777 V4 Use Copy rdx |V7 a| |V4 a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 616.#778 rdx Fixd Keep rdx |V7 a| |V4 a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 616.#779 I149 Def Alloc rdx |V7 a| |I149a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 618.#780 C150 Def Alloc rcx |V7 a|C150a|I149a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 621.#781 rdi Fixd Keep rdi |V7 a|C150a|I149a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 621.#782 I147 Use * Keep rdi |V7 a|C150a|I149a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 621.#783 rsi Fixd Keep rsi |V7 a|C150a|I149a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 621.#784 I148 Use * Keep rsi |V7 a|C150a|I149a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 621.#785 rdx Fixd Keep rdx |V7 a|C150a|I149a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 621.#786 I149 Use * Keep rdx |V7 a|C150a|I149a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 621.#787 C150 Use * Keep rcx |V7 a|C150a|I149a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 622.#788 rax Kill Spill rax | |C150i| |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Keep rax | |C150i| |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#789 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#790 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#791 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#792 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#793 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#794 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#795 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#796 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#797 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#798 I151 Def Alloc rax |I151a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 625.#799 I151 Use * Keep rax |I151a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 629.#800 V7 ExpU Keep NA | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 629.#801 BB23 PredBB3 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 634.#802 C152 Def Alloc rax |C152a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 635.#803 C152 Use * Keep rax |C152a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 636.#804 V7 Def Alloc rax |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#805 V2 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#806 V3 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#807 V5 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#808 V1 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#809 V4 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#810 V0 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#811 V7 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 637.#812 BB24 PredBB1 |V7 i| | |V2 i| | | | | |V1 i|V4 i|V3 i|V5 i| 644.#813 V6 Def Alloc rax |V6 a| | |V2 i| | | | | |V1 i|V4 i|V3 i|V5 i| 645.#814 V6 ExpU Keep NA |V6 a| | |V2 i| | | | | |V1 i|V4 i|V3 i|V5 i| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 645.#815 BB25 PredBB2 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 653.#816 V4 Use Keep r13 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 657.#817 BB26 PredBB25 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 662.#818 C153 Def Alloc rdi | | | |V2 a| |C153a| | | |V1 a|V4 a|V3 a|V5 a| 663.#819 rdi Fixd Keep rdi | | | |V2 a| |C153a| | | |V1 a|V4 a|V3 a|V5 a| 663.#820 C153 Use * Keep rdi | | | |V2 a| |C153a| | | |V1 a|V4 a|V3 a|V5 a| 664.#821 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 664.#822 I154 Def Alloc rdi | | | |V2 a| |I154a| | | |V1 a|V4 a|V3 a|V5 a| 666.#823 C155 Def Alloc rax |C155a| | |V2 a| |I154a| | | |V1 a|V4 a|V3 a|V5 a| 669.#824 rdi Fixd Keep rdi |C155a| | |V2 a| |I154a| | | |V1 a|V4 a|V3 a|V5 a| 669.#825 I154 Use * Keep rdi |C155a| | |V2 a| |I154a| | | |V1 a|V4 a|V3 a|V5 a| 669.#826 C155 Use * Keep rax |C155a| | |V2 a| |I154a| | | |V1 a|V4 a|V3 a|V5 a| 670.#827 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#828 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#829 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#830 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#831 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#832 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#833 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#834 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#835 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#836 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#837 I156 Def Alloc rax |I156a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 671.#838 I156 Use * Keep rax |I156a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 672.#839 V16 Def Alloc rax |V16 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 681.#840 V16 Use Keep rax |V16 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 685.#841 V16 Use Keep rax |V16 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 686.#842 I157 Def Alloc rdi |V16 a| | |V2 a| |I157a| | | |V1 a|V4 a|V3 a|V5 a| 689.#843 rdi Fixd Keep rdi |V16 a| | |V2 a| |I157a| | | |V1 a|V4 a|V3 a|V5 a| 689.#844 I157 Use * Keep rdi |V16 a| | |V2 a| |I157a| | | |V1 a|V4 a|V3 a|V5 a| 689.#845 rsi Fixd Keep rsi |V16 a| | |V2 a| |I157a| | | |V1 a|V4 a|V3 a|V5 a| 689.#846 V3 Use Copy rsi |V16 a| | |V2 a|V3 a|I157a| | | |V1 a|V4 a|V3 a|V5 a| 690.#847 rax Kill Spill rax | | | |V2 a|V3 a| | | | |V1 a|V4 a|V3 a|V5 a| Keep rax | | | |V2 a|V3 a| | | | |V1 a|V4 a|V3 a|V5 a| 690.#848 rcx Kill Keep rcx | | | |V2 a|V3 a| | | | |V1 a|V4 a|V3 a|V5 a| 690.#849 rdx Kill Keep rdx | | | |V2 a|V3 a| | | | |V1 a|V4 a|V3 a|V5 a| 690.#850 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#851 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#852 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#853 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#854 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#855 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#856 mm0 Kill Keep mm0 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#857 mm1 Kill Keep mm1 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#858 mm2 Kill Keep mm2 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#859 mm3 Kill Keep mm3 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#860 mm4 Kill Keep mm4 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#861 mm5 Kill Keep mm5 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#862 mm6 Kill Keep mm6 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#863 mm7 Kill Keep mm7 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#864 mm8 Kill Keep mm8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#865 mm9 Kill Keep mm9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#866 mm10 Kill Keep mm10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#867 mm11 Kill Keep mm11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#868 mm12 Kill Keep mm12 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#869 mm13 Kill Keep mm13 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#870 mm14 Kill Keep mm14 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#871 mm15 Kill Keep mm15 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 692.#872 C158 Def Alloc rax |C158a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 695.#873 C158 Use * Keep rax |C158a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#874 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#875 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#876 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#877 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#878 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#879 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#880 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#881 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#882 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#883 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#884 I159 Def Alloc rax |I159a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 697.#885 I159 Use * Keep rax |I159a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 698.#886 V18 Def Alloc rax |V18 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 700.#887 C160 Def Alloc rdi |V18 a| | |V2 a| |C160a| | | |V1 a|V4 a|V3 a|V5 a| 703.#888 C160 Use * Keep rdi |V18 a| | |V2 a| |C160a| | | |V1 a|V4 a|V3 a|V5 a| 704.#889 rax Kill Spill rax | | | |V2 a| |C160i| | | |V1 a|V4 a|V3 a|V5 a| Keep rax | | | |V2 a| |C160i| | | |V1 a|V4 a|V3 a|V5 a| 704.#890 rcx Kill Keep rcx | | | |V2 a| |C160i| | | |V1 a|V4 a|V3 a|V5 a| 704.#891 rdx Kill Keep rdx | | | |V2 a| |C160i| | | |V1 a|V4 a|V3 a|V5 a| 704.#892 rsi Kill Keep rsi | | | |V2 a| |C160i| | | |V1 a|V4 a|V3 a|V5 a| 704.#893 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#894 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#895 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#896 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#897 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#898 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#899 I161 Def Alloc rax |I161a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 707.#900 I161 Use * Keep rax |I161a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 708.#901 I162 Def Alloc rsi | | | |V2 a|I162a| | | | |V1 a|V4 a|V3 a|V5 a| 709.#902 I162 Use * Keep rsi | | | |V2 a|I162a| | | | |V1 a|V4 a|V3 a|V5 a| 710.#903 V24 Def Alloc rsi | | | |V2 a|V24 a| | | | |V1 a|V4 a|V3 a|V5 a| 713.#904 rsi Fixd Keep rsi | | | |V2 a|V24 a| | | | |V1 a|V4 a|V3 a|V5 a| 713.#905 V24 Use * Keep rsi | | | |V2 a|V24 a| | | | |V1 a|V4 a|V3 a|V5 a| 714.#906 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 714.#907 I163 Def Alloc rsi | | | |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 717.#908 rdi Fixd Keep rdi | | | |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 717.#909 V18 Use ReLod NA | | | |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| Alloc rdi | | | |V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 718.#910 rdi Fixd Keep rdi | | | |V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 718.#911 I164 Def PtArg rdi | | | |V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 721.#912 rcx Fixd Keep rcx | | | |V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 721.#913 V16 Use * ReLod NA | | | |V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| Alloc rcx | |V16 a| |V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 722.#914 rcx Fixd Keep rcx | | | |V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 722.#915 I165 Def Alloc rcx | |I165a| |V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 724.#916 C166 Def Alloc rdx | |I165a|C166a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 725.#917 rdx Fixd Keep rdx | |I165a|C166a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 725.#918 C166 Use * Keep rdx | |I165a|C166a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 726.#919 rdx Fixd Keep rdx | |I165a| |V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 726.#920 I167 Def Alloc rdx | |I165a|I167a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 728.#921 C168 Def Alloc rax |C168a|I165a|I167a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 731.#922 rsi Fixd Keep rsi |C168a|I165a|I167a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 731.#923 I163 Use * Keep rsi |C168a|I165a|I167a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 731.#924 rdi Fixd Keep rdi |C168a|I165a|I167a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 731.#925 I164 Use * PtArg rdi |C168a|I165a|I167a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 731.#926 rcx Fixd Keep rcx |C168a|I165a|I167a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 731.#927 I165 Use * Keep rcx |C168a|I165a|I167a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 731.#928 rdx Fixd Keep rdx |C168a|I165a|I167a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 731.#929 I167 Use * Keep rdx |C168a|I165a|I167a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 731.#930 C168 Use * Keep rax |C168a|I165a|I167a|V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| 732.#931 rax Kill Keep rax | | | |V2 a| |V18 a| | | |V1 a|V4 a|V3 a|V5 a| 732.#932 rcx Kill Keep rcx | | | |V2 a| |V18 a| | | |V1 a|V4 a|V3 a|V5 a| 732.#933 rdx Kill Keep rdx | | | |V2 a| |V18 a| | | |V1 a|V4 a|V3 a|V5 a| 732.#934 rsi Kill Keep rsi | | | |V2 a| |V18 a| | | |V1 a|V4 a|V3 a|V5 a| 732.#935 rdi Kill Spill rdi | | | |V2 a| |Busy | | | |V1 a|V4 a|V3 a|V5 a| Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#936 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#937 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#938 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#939 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 734.#940 I169 Def Alloc rdi | | | |V2 a| |I169a| | | |V1 a|V4 a|V3 a|V5 a| 735.#941 rdi Fixd Keep rdi | | | |V2 a| |I169a| | | |V1 a|V4 a|V3 a|V5 a| 735.#942 I169 Use * Keep rdi | | | |V2 a| |I169a| | | |V1 a|V4 a|V3 a|V5 a| 736.#943 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 736.#944 I170 Def Alloc rdi | | | |V2 a| |I170a| | | |V1 a|V4 a|V3 a|V5 a| 739.#945 rsi Fixd Keep rsi | | | |V2 a| |I170a| | | |V1 a|V4 a|V3 a|V5 a| 739.#946 V2 Use Copy rsi | | | |V2 a|V2 a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 740.#947 rsi Fixd Keep rsi | | | |V2 a|V2 a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 740.#948 I171 Def Alloc rsi | | | |V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 743.#949 rdx Fixd Keep rdx | | | |V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 743.#950 V18 Use * ReLod NA | | | |V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| Alloc rdx | | |V18 a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 744.#951 rdx Fixd Keep rdx | | | |V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 744.#952 I172 Def Alloc rdx | | |I172a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 746.#953 C173 Def Alloc rax |C173a| |I172a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 749.#954 rdi Fixd Keep rdi |C173a| |I172a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 749.#955 I170 Use * Keep rdi |C173a| |I172a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 749.#956 rsi Fixd Keep rsi |C173a| |I172a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 749.#957 I171 Use * Keep rsi |C173a| |I172a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 749.#958 rdx Fixd Keep rdx |C173a| |I172a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 749.#959 I172 Use * Keep rdx |C173a| |I172a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 749.#960 C173 Use * Keep rax |C173a| |I172a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 750.#961 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#962 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#963 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#964 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#965 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#966 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#967 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#968 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#969 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 757.#970 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 757.#971 I174 Def Alloc rdi | | | |V2 a| |I174a| | | |V1 a|V4 a|V3 a|V5 a| 757.#972 rcx Fixd Keep rcx | | | |V2 a| |I174a| | | |V1 a|V4 a|V3 a|V5 a| 757.#973 I175 Def Alloc rcx | |I175a| |V2 a| |I174a| | | |V1 a|V4 a|V3 a|V5 a| 757.#974 rsi Fixd Keep rsi | |I175a| |V2 a| |I174a| | | |V1 a|V4 a|V3 a|V5 a| 757.#975 I176 Def Alloc rsi | |I175a| |V2 a|I176a|I174a| | | |V1 a|V4 a|V3 a|V5 a| 757.#976 I174 Use * Keep rdi | |I175a| |V2 a|I176a|I174a| | | |V1 a|V4 a|V3 a|V5 a| 757.#977 I175 Use * Keep rcx | |I175a| |V2 a|I176a|I174a| | | |V1 a|V4 a|V3 a|V5 a| 757.#978 I176 Use * Keep rsi | |I175a| |V2 a|I176a|I174a| | | |V1 a|V4 a|V3 a|V5 a| 761.#979 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 761.#980 V4 Use Copy rdi | | | |V2 a| |V4 a| | | |V1 a|V4 a|V3 a|V5 a| 762.#981 rdi Fixd Keep rdi | | | |V2 a| |V4 a| | | |V1 a|V4 a|V3 a|V5 a| 762.#982 I177 Def Alloc rdi | | | |V2 a| |I177a| | | |V1 a|V4 a|V3 a|V5 a| 764.#983 r11 Fixd Keep r11 | | | |V2 a| |I177a| | | |V1 a|V4 a|V3 a|V5 a| 764.#984 C178 Def Alloc r11 | | | |V2 a| |I177a| | |C178a|V1 a|V4 a|V3 a|V5 a| 765.#985 r11 Fixd Keep r11 | | | |V2 a| |I177a| | |C178a|V1 a|V4 a|V3 a|V5 a| 765.#986 C178 Use * Keep r11 | | | |V2 a| |I177a| | |C178a|V1 a|V4 a|V3 a|V5 a| 766.#987 r11 Fixd Keep r11 | | | |V2 a| |I177a| | | |V1 a|V4 a|V3 a|V5 a| 766.#988 I179 Def Alloc r11 | | | |V2 a| |I177a| | |I179a|V1 a|V4 a|V3 a|V5 a| 768.#989 C180 Def Alloc rax |C180a| | |V2 a| |I177a| | |I179a|V1 a|V4 a|V3 a|V5 a| 771.#990 rdi Fixd Keep rdi |C180a| | |V2 a| |I177a| | |I179a|V1 a|V4 a|V3 a|V5 a| 771.#991 I177 Use * Keep rdi |C180a| | |V2 a| |I177a| | |I179a|V1 a|V4 a|V3 a|V5 a| 771.#992 r11 Fixd Keep r11 |C180a| | |V2 a| |I177a| | |I179a|V1 a|V4 a|V3 a|V5 a| 771.#993 I179 Use * Keep r11 |C180a| | |V2 a| |I177a| | |I179a|V1 a|V4 a|V3 a|V5 a| 771.#994 C180 Use * Keep rax |C180a| | |V2 a| |I177a| | |I179a|V1 a|V4 a|V3 a|V5 a| 772.#995 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#996 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#997 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#998 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#999 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#1000 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#1001 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#1002 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#1003 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 773.#1004 BB27 PredBB25 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 778.#1005 C181 Def Alloc rax |C181a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 779.#1006 C181 Use * Keep rax |C181a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 780.#1007 V7 Def Alloc rax |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 781.#1008 V0 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 781.#1009 V7 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 781.#1010 BB28 PredBB12 |V7 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 786.#1011 C182 Def Alloc rax |C182a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 787.#1012 C182 Use * Keep rax |C182a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 788.#1013 V7 Def Alloc rax |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#1014 V2 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#1015 V3 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#1016 V5 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#1017 V1 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#1018 V4 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#1019 V7 ExpU Keep NA |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 789.#1020 BB29 PredBB28 | | | | | | | | | | | | | | 792.#1021 rax Kill Keep rax | | | | | | | | | | | | | | 792.#1022 rcx Kill Keep rcx | | | | | | | | | | | | | | 792.#1023 rdx Kill Keep rdx | | | | | | | | | | | | | | 792.#1024 rsi Kill Keep rsi | | | | | | | | | | | | | | 792.#1025 rdi Kill Keep rdi | | | | | | | | | | | | | | 792.#1026 r8 Kill Keep r8 | | | | | | | | | | | | | | 792.#1027 r9 Kill Keep r9 | | | | | | | | | | | | | | 792.#1028 r10 Kill Keep r10 | | | | | | | | | | | | | | 792.#1029 r11 Kill Keep r11 | | | | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ BB00 regmask=[rbx] minReg=1 fixed regOptional> BB00 regmask=[r14] minReg=1 fixed regOptional> BB00 regmask=[r15] minReg=1 fixed regOptional> BB00 regmask=[r12] minReg=1 fixed regOptional> BB00 regmask=[r13] minReg=1 fixed regOptional> BB00 regmask=[] minReg=1 fixed regOptional> BB01 regmask=[rdi] minReg=1> LCL_VAR BB01 regmask=[rdi] minReg=1 copy fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[r11] minReg=1> CNS_INT BB01 regmask=[r11] minReg=1 fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> PUTARG_REG BB01 regmask=[r11] minReg=1 fixed> CNS_INT BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last regOptional> STORE_LCL_VAR BB02 regmask=[rax] minReg=1 spillAfter> BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 copy fixed> BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[r11] minReg=1> CNS_INT BB02 regmask=[r11] minReg=1 fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> PUTARG_REG BB02 regmask=[r11] minReg=1 fixed> CNS_INT BB02 regmask=[rsi] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[rax] minReg=1 last> CAST BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> CNS_INT BB02 regmask=[rax] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[rax] minReg=1 last regOptional> BB03 regmask=[rdi] minReg=1> LCL_VAR BB03 regmask=[rdi] minReg=1 copy fixed> BB03 regmask=[rdi] minReg=1> PUTARG_REG BB03 regmask=[rdi] minReg=1 fixed> BB03 regmask=[r11] minReg=1> CNS_INT BB03 regmask=[r11] minReg=1 fixed> BB03 regmask=[r11] minReg=1> BB03 regmask=[r11] minReg=1 last fixed> BB03 regmask=[r11] minReg=1> PUTARG_REG BB03 regmask=[r11] minReg=1 fixed> CNS_INT BB03 regmask=[rax] minReg=1> BB03 regmask=[rdi] minReg=1> BB03 regmask=[rdi] minReg=1 last fixed> BB03 regmask=[r11] minReg=1> BB03 regmask=[r11] minReg=1 last fixed> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[rsi] minReg=1 last> BB03 regmask=[rdi] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> BB03 regmask=[rax] minReg=1 last regOptional> BB04 regmask=[rdi] minReg=1> LCL_VAR BB04 regmask=[rdi] minReg=1 copy fixed> BB04 regmask=[rdi] minReg=1> PUTARG_REG BB04 regmask=[rdi] minReg=1 fixed> BB04 regmask=[r11] minReg=1> CNS_INT BB04 regmask=[r11] minReg=1 fixed> BB04 regmask=[r11] minReg=1> BB04 regmask=[r11] minReg=1 last fixed> BB04 regmask=[r11] minReg=1> PUTARG_REG BB04 regmask=[r11] minReg=1 fixed> CNS_INT BB04 regmask=[rax] minReg=1> BB04 regmask=[rdi] minReg=1> BB04 regmask=[rdi] minReg=1 last fixed> BB04 regmask=[r11] minReg=1> BB04 regmask=[r11] minReg=1 last fixed> BB04 regmask=[rax] minReg=1 last> BB04 regmask=[rax] minReg=1 last> BB04 regmask=[rcx] minReg=1 last> BB04 regmask=[rdx] minReg=1 last> BB04 regmask=[rsi] minReg=1 last> BB04 regmask=[rdi] minReg=1 last> BB04 regmask=[r8] minReg=1 last> BB04 regmask=[r9] minReg=1 last> BB04 regmask=[r10] minReg=1 last> BB04 regmask=[r11] minReg=1 last> BB04 regmask=[rax] minReg=1> CALL BB04 regmask=[rax] minReg=1 fixed> BB04 regmask=[rax] minReg=1 last regOptional> BB05 regmask=[rdi] minReg=1> LCL_VAR BB05 regmask=[rdi] minReg=1 copy fixed> BB05 regmask=[rdi] minReg=1> PUTARG_REG BB05 regmask=[rdi] minReg=1 fixed> BB05 regmask=[r11] minReg=1> CNS_INT BB05 regmask=[r11] minReg=1 fixed> BB05 regmask=[r11] minReg=1> BB05 regmask=[r11] minReg=1 last fixed> BB05 regmask=[r11] minReg=1> PUTARG_REG BB05 regmask=[r11] minReg=1 fixed> CNS_INT BB05 regmask=[rax] minReg=1> BB05 regmask=[rdi] minReg=1> BB05 regmask=[rdi] minReg=1 last fixed> BB05 regmask=[r11] minReg=1> BB05 regmask=[r11] minReg=1 last fixed> BB05 regmask=[rax] minReg=1 last> BB05 regmask=[rax] minReg=1 last> BB05 regmask=[rcx] minReg=1 last> BB05 regmask=[rdx] minReg=1 last> BB05 regmask=[rsi] minReg=1 last> BB05 regmask=[rdi] minReg=1 last> BB05 regmask=[r8] minReg=1 last> BB05 regmask=[r9] minReg=1 last> BB05 regmask=[r10] minReg=1 last> BB05 regmask=[r11] minReg=1 last> BB05 regmask=[rax] minReg=1> CALL BB05 regmask=[rax] minReg=1 fixed> BB05 regmask=[rax] minReg=1 last regOptional> BB06 regmask=[rdi] minReg=1> LCL_VAR BB06 regmask=[rdi] minReg=1 copy fixed> BB06 regmask=[rdi] minReg=1> PUTARG_REG BB06 regmask=[rdi] minReg=1 fixed> BB06 regmask=[rsi] minReg=1> LCL_VAR BB06 regmask=[rsi] minReg=1 copy fixed> BB06 regmask=[rsi] minReg=1> PUTARG_REG BB06 regmask=[rsi] minReg=1 fixed> CNS_INT BB06 regmask=[rax] minReg=1> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rcx] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> BB06 regmask=[rsi] minReg=1 last> BB06 regmask=[rdi] minReg=1 last> BB06 regmask=[r8] minReg=1 last> BB06 regmask=[r9] minReg=1 last> BB06 regmask=[r10] minReg=1 last> BB06 regmask=[r11] minReg=1 last> BB06 regmask=[rax] minReg=1> CALL BB06 regmask=[rax] minReg=1 fixed> BB06 regmask=[rax] minReg=1 last> CNS_INT BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last> IND BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rsi] minReg=1> PUTARG_REG BB06 regmask=[rsi] minReg=1 fixed> LCL_VAR_ADDR BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> PUTARG_REG BB06 regmask=[rdi] minReg=1 fixed> CNS_INT BB06 regmask=[rax] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rcx] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> BB06 regmask=[rsi] minReg=1 last> BB06 regmask=[rdi] minReg=1 last> BB06 regmask=[r8] minReg=1 last> BB06 regmask=[r9] minReg=1 last> BB06 regmask=[r10] minReg=1 last> BB06 regmask=[r11] minReg=1 last> BB06 regmask=[rax] minReg=1> CALL BB06 regmask=[rax] minReg=1 fixed> BB06 regmask=[rdx] minReg=1> CALL BB06 regmask=[rdx] minReg=1 fixed> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> LCL_VAR_ADDR BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last> STORE_LCL_VAR BB06 regmask=[rsi] minReg=1> LCL_VAR BB06 regmask=[rsi] minReg=1> IND BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last> LCL_VAR BB06 regmask=[rsi] minReg=1 last> IND BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last> CNS_INT BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last> IND BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rsi] minReg=1> PUTARG_REG BB06 regmask=[rsi] minReg=1 fixed> LCL_VAR_ADDR BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> PUTARG_REG BB06 regmask=[rdi] minReg=1 fixed> CNS_INT BB06 regmask=[rax] minReg=1> BB06 regmask=[rsi] minReg=1> BB06 regmask=[rsi] minReg=1 last fixed> BB06 regmask=[rdi] minReg=1> BB06 regmask=[rdi] minReg=1 last fixed> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rcx] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> BB06 regmask=[rsi] minReg=1 last> BB06 regmask=[rdi] minReg=1 last> BB06 regmask=[r8] minReg=1 last> BB06 regmask=[r9] minReg=1 last> BB06 regmask=[r10] minReg=1 last> BB06 regmask=[r11] minReg=1 last> BB06 regmask=[rax] minReg=1> CALL BB06 regmask=[rax] minReg=1 fixed> BB06 regmask=[rax] minReg=1 last regOptional> LCL_VAR BB07 regmask=[r13] minReg=1 last reload> STORE_LCL_VAR BB07 regmask=[rax] minReg=1> BB08 regmask=[rax] minReg=1> LCL_VAR BB08 regmask=[rax] minReg=1 last fixed> CNS_INT BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last> IND BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last fixed> BB09 regmask=[rsi] minReg=1> PUTARG_REG BB09 regmask=[rsi] minReg=1 fixed> LCL_VAR_ADDR BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[rdi] minReg=1> PUTARG_REG BB09 regmask=[rdi] minReg=1 fixed> CNS_INT BB09 regmask=[rax] minReg=1> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last fixed> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rcx] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> BB09 regmask=[rsi] minReg=1 last> BB09 regmask=[rdi] minReg=1 last> BB09 regmask=[r8] minReg=1 last> BB09 regmask=[r9] minReg=1 last> BB09 regmask=[r10] minReg=1 last> BB09 regmask=[r11] minReg=1 last> BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> BB09 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[rdi] minReg=1> PUTARG_REG BB09 regmask=[rdi] minReg=1 fixed> BB09 regmask=[rsi] minReg=1> LCL_VAR BB09 regmask=[rsi] minReg=1 copy fixed> BB09 regmask=[rsi] minReg=1> PUTARG_REG BB09 regmask=[rsi] minReg=1 fixed> BB09 regmask=[r11] minReg=1> CNS_INT BB09 regmask=[r11] minReg=1 fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> PUTARG_REG BB09 regmask=[r11] minReg=1 fixed> CNS_INT BB09 regmask=[rax] minReg=1> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[rsi] minReg=1> BB09 regmask=[rsi] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rcx] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> BB09 regmask=[rsi] minReg=1 last> BB09 regmask=[rdi] minReg=1 last> BB09 regmask=[r8] minReg=1 last> BB09 regmask=[r9] minReg=1 last> BB09 regmask=[r10] minReg=1 last> BB09 regmask=[r11] minReg=1 last> BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> BB09 regmask=[rdx] minReg=1> CALL BB09 regmask=[rdx] minReg=1 fixed> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> LCL_FLD BB09 regmask=[rax] minReg=1> BB09 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB09 regmask=[rax] minReg=1> BB09 regmask=[rdi] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 spillAfter copy fixed> BB09 regmask=[rdi] minReg=1> PUTARG_REG BB09 regmask=[rdi] minReg=1 fixed> BB09 regmask=[r11] minReg=1> CNS_INT BB09 regmask=[r11] minReg=1 fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> PUTARG_REG BB09 regmask=[r11] minReg=1 fixed> CNS_INT BB09 regmask=[rsi] minReg=1> BB09 regmask=[rdi] minReg=1> BB09 regmask=[rdi] minReg=1 last fixed> BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last fixed> BB09 regmask=[rsi] minReg=1 last> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rcx] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> BB09 regmask=[rsi] minReg=1 last> BB09 regmask=[rdi] minReg=1 last> BB09 regmask=[r8] minReg=1 last> BB09 regmask=[r9] minReg=1 last> BB09 regmask=[r10] minReg=1 last> BB09 regmask=[r11] minReg=1 last> BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> BB09 regmask=[rax] minReg=1 last regOptional> BB10 regmask=[rdi] minReg=1> LCL_VAR BB10 regmask=[rdi] minReg=1 reload spillAfter fixed> BB10 regmask=[rdi] minReg=1> PUTARG_REG BB10 regmask=[rdi] minReg=1 fixed> BB10 regmask=[rsi] minReg=1> LCL_VAR BB10 regmask=[rsi] minReg=1 copy fixed> BB10 regmask=[rsi] minReg=1> PUTARG_REG BB10 regmask=[rsi] minReg=1 fixed> CNS_INT BB10 regmask=[rax] minReg=1> BB10 regmask=[rdi] minReg=1> BB10 regmask=[rdi] minReg=1 last fixed> BB10 regmask=[rsi] minReg=1> BB10 regmask=[rsi] minReg=1 last fixed> BB10 regmask=[rax] minReg=1 last> BB10 regmask=[rax] minReg=1 last> BB10 regmask=[rcx] minReg=1 last> BB10 regmask=[rdx] minReg=1 last> BB10 regmask=[rsi] minReg=1 last> BB10 regmask=[rdi] minReg=1 last> BB10 regmask=[r8] minReg=1 last> BB10 regmask=[r9] minReg=1 last> BB10 regmask=[r10] minReg=1 last> BB10 regmask=[r11] minReg=1 last> BB12 regmask=[rdi] minReg=1> LCL_VAR BB12 regmask=[rdi] minReg=1 last reload fixed> BB12 regmask=[rdi] minReg=1> PUTARG_REG BB12 regmask=[rdi] minReg=1 fixed> BB12 regmask=[rsi] minReg=1> LCL_VAR BB12 regmask=[rsi] minReg=1 copy fixed> BB12 regmask=[rsi] minReg=1> PUTARG_REG BB12 regmask=[rsi] minReg=1 fixed> BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 copy fixed> BB12 regmask=[rdx] minReg=1> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 copy fixed> BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> BB12 regmask=[r8] minReg=1> LCL_VAR BB12 regmask=[r8] minReg=1 copy fixed> BB12 regmask=[r8] minReg=1> PUTARG_REG BB12 regmask=[r8] minReg=1 fixed> CNS_INT BB12 regmask=[rax] minReg=1> BB12 regmask=[rdi] minReg=1> BB12 regmask=[rdi] minReg=1 last fixed> BB12 regmask=[rsi] minReg=1> BB12 regmask=[rsi] minReg=1 last fixed> BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[r8] minReg=1> BB12 regmask=[r8] minReg=1 last fixed> BB12 regmask=[rax] minReg=1 last> BB12 regmask=[rax] minReg=1 last> BB12 regmask=[rcx] minReg=1 last> BB12 regmask=[rdx] minReg=1 last> BB12 regmask=[rsi] minReg=1 last> BB12 regmask=[rdi] minReg=1 last> BB12 regmask=[r8] minReg=1 last> BB12 regmask=[r9] minReg=1 last> BB12 regmask=[r10] minReg=1 last> BB12 regmask=[r11] minReg=1 last> BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[rax] minReg=1 last regOptional> BB14 regmask=[rdi] minReg=1> LCL_VAR BB14 regmask=[rdi] minReg=1 copy fixed> BB14 regmask=[rdi] minReg=1> PUTARG_REG BB14 regmask=[rdi] minReg=1 fixed> BB14 regmask=[rsi] minReg=1> LCL_VAR BB14 regmask=[rsi] minReg=1 reload spillAfter fixed> BB14 regmask=[rsi] minReg=1> PUTARG_REG BB14 regmask=[rsi] minReg=1 fixed> BB14 regmask=[rdx] minReg=1> LCL_VAR BB14 regmask=[rdx] minReg=1 copy fixed> BB14 regmask=[rdx] minReg=1> PUTARG_REG BB14 regmask=[rdx] minReg=1 fixed> CNS_INT BB14 regmask=[rax] minReg=1> BB14 regmask=[rdi] minReg=1> BB14 regmask=[rdi] minReg=1 last fixed> BB14 regmask=[rsi] minReg=1> BB14 regmask=[rsi] minReg=1 last fixed> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> BB14 regmask=[rax] minReg=1 last> BB14 regmask=[rax] minReg=1 last> BB14 regmask=[rcx] minReg=1 last> BB14 regmask=[rdx] minReg=1 last> BB14 regmask=[rsi] minReg=1 last> BB14 regmask=[rdi] minReg=1 last> BB14 regmask=[r8] minReg=1 last> BB14 regmask=[r9] minReg=1 last> BB14 regmask=[r10] minReg=1 last> BB14 regmask=[r11] minReg=1 last> BB14 regmask=[rax] minReg=1> CALL BB14 regmask=[rax] minReg=1 fixed> BB14 regmask=[rax] minReg=1 last> CAST BB14 regmask=[rsi] minReg=1> BB14 regmask=[rsi] minReg=1 last> STORE_LCL_VAR BB14 regmask=[rsi] minReg=1> LCL_VAR BB14 regmask=[rsi] minReg=1 last regOptional> CNS_INT BB15 regmask=[rsi] minReg=1> BB15 regmask=[rsi] minReg=1 last> IND BB15 regmask=[rsi] minReg=1> BB15 regmask=[rsi] minReg=1> BB15 regmask=[rsi] minReg=1 last fixed> BB15 regmask=[rsi] minReg=1> PUTARG_REG BB15 regmask=[rsi] minReg=1 fixed> LCL_VAR_ADDR BB15 regmask=[rdi] minReg=1> BB15 regmask=[rdi] minReg=1> BB15 regmask=[rdi] minReg=1 last fixed> BB15 regmask=[rdi] minReg=1> PUTARG_REG BB15 regmask=[rdi] minReg=1 fixed> CNS_INT BB15 regmask=[rax] minReg=1> BB15 regmask=[rsi] minReg=1> BB15 regmask=[rsi] minReg=1 last fixed> BB15 regmask=[rdi] minReg=1> BB15 regmask=[rdi] minReg=1 last fixed> BB15 regmask=[rax] minReg=1 last> BB15 regmask=[rax] minReg=1 last> BB15 regmask=[rcx] minReg=1 last> BB15 regmask=[rdx] minReg=1 last> BB15 regmask=[rsi] minReg=1 last> BB15 regmask=[rdi] minReg=1 last> BB15 regmask=[r8] minReg=1 last> BB15 regmask=[r9] minReg=1 last> BB15 regmask=[r10] minReg=1 last> BB15 regmask=[r11] minReg=1 last> BB15 regmask=[rax] minReg=1> CALL BB15 regmask=[rax] minReg=1 fixed> BB15 regmask=[rax] minReg=1 last regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB15 regmask=[allInt] minReg=1 regOptional> BB17 regmask=[rdi] minReg=1> LCL_VAR BB17 regmask=[rdi] minReg=1 copy fixed outOfOrder> BB17 regmask=[rdi] minReg=1> PUTARG_REG BB17 regmask=[rdi] minReg=1 fixed> BB17 regmask=[rsi] minReg=1> LCL_VAR BB17 regmask=[rsi] minReg=1 copy fixed outOfOrder> BB17 regmask=[rsi] minReg=1> PUTARG_REG BB17 regmask=[rsi] minReg=1 fixed> BB17 regmask=[rdx] minReg=1> LCL_VAR BB17 regmask=[rdx] minReg=1 copy fixed outOfOrder> BB17 regmask=[rdx] minReg=1> PUTARG_REG BB17 regmask=[rdx] minReg=1 fixed> CNS_INT BB17 regmask=[rax] minReg=1> BB17 regmask=[rdi] minReg=1> BB17 regmask=[rdi] minReg=1 last fixed> BB17 regmask=[rsi] minReg=1> BB17 regmask=[rsi] minReg=1 last fixed> BB17 regmask=[rdx] minReg=1> BB17 regmask=[rdx] minReg=1 last fixed> BB17 regmask=[rax] minReg=1 last> BB17 regmask=[rax] minReg=1 last> BB17 regmask=[rcx] minReg=1 last> BB17 regmask=[rdx] minReg=1 last> BB17 regmask=[rsi] minReg=1 last> BB17 regmask=[rdi] minReg=1 last> BB17 regmask=[r8] minReg=1 last> BB17 regmask=[r9] minReg=1 last> BB17 regmask=[r10] minReg=1 last> BB17 regmask=[r11] minReg=1 last> BB17 regmask=[rax] minReg=1> CALL BB17 regmask=[rax] minReg=1 fixed> BB17 regmask=[rax] minReg=1 last regOptional> BB17 regmask=[allInt] minReg=1 regOptional> CNS_INT BB18 regmask=[rdi] minReg=1> BB18 regmask=[rdi] minReg=1 last> STORE_LCL_VAR BB18 regmask=[rax] minReg=1> BB18 regmask=[allInt] minReg=1 regOptional> BB18 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB19 regmask=[r13] minReg=1 regOptional> CNS_INT BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rdi] minReg=1> PUTARG_REG BB20 regmask=[rdi] minReg=1 fixed> CNS_INT BB20 regmask=[rax] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[rax] minReg=1> CALL BB20 regmask=[rax] minReg=1 fixed> BB20 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB20 regmask=[rax] minReg=1> LCL_VAR BB20 regmask=[rax] minReg=1> IND BB20 regmask=[rdx] minReg=1> BB20 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB20 regmask=[rdx] minReg=1> LCL_VAR BB20 regmask=[rdx] minReg=1 spillAfter regOptional> LCL_VAR BB20 regmask=[rax] minReg=1 spillAfter> LEA BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 copy fixed> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[mm0] minReg=1 last> BB20 regmask=[mm1] minReg=1 last> BB20 regmask=[mm2] minReg=1 last> BB20 regmask=[mm3] minReg=1 last> BB20 regmask=[mm4] minReg=1 last> BB20 regmask=[mm5] minReg=1 last> BB20 regmask=[mm6] minReg=1 last> BB20 regmask=[mm7] minReg=1 last> BB20 regmask=[mm8] minReg=1 last> BB20 regmask=[mm9] minReg=1 last> BB20 regmask=[mm10] minReg=1 last> BB20 regmask=[mm11] minReg=1 last> BB20 regmask=[mm12] minReg=1 last> BB20 regmask=[mm13] minReg=1 last> BB20 regmask=[mm14] minReg=1 last> BB20 regmask=[mm15] minReg=1 last> LCL_VAR BB20 regmask=[] minReg=1 last regOptional> LCL_VAR BB20 regmask=[rax] minReg=1 reload spillAfter> LEA BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 last reload fixed> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[mm0] minReg=1 last> BB20 regmask=[mm1] minReg=1 last> BB20 regmask=[mm2] minReg=1 last> BB20 regmask=[mm3] minReg=1 last> BB20 regmask=[mm4] minReg=1 last> BB20 regmask=[mm5] minReg=1 last> BB20 regmask=[mm6] minReg=1 last> BB20 regmask=[mm7] minReg=1 last> BB20 regmask=[mm8] minReg=1 last> BB20 regmask=[mm9] minReg=1 last> BB20 regmask=[mm10] minReg=1 last> BB20 regmask=[mm11] minReg=1 last> BB20 regmask=[mm12] minReg=1 last> BB20 regmask=[mm13] minReg=1 last> BB20 regmask=[mm14] minReg=1 last> BB20 regmask=[mm15] minReg=1 last> CNS_INT BB20 regmask=[rax] minReg=1> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[rax] minReg=1> CALL BB20 regmask=[rax] minReg=1 fixed> BB20 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB20 regmask=[rax] minReg=1 spillAfter> CNS_INT BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> BB20 regmask=[rax] minReg=1> CALL BB20 regmask=[rax] minReg=1 fixed> BB20 regmask=[rax] minReg=1 last> IND BB20 regmask=[rsi] minReg=1> BB20 regmask=[rsi] minReg=1 last> STORE_LCL_VAR BB20 regmask=[rsi] minReg=1> BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rsi] minReg=1> PUTARG_REG BB20 regmask=[rsi] minReg=1 fixed> BB20 regmask=[rdi] minReg=1> LCL_VAR BB20 regmask=[rdi] minReg=1 reload spillAfter fixed> BB20 regmask=[rdi] minReg=1> PUTARG_REG BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[rcx] minReg=1> LCL_VAR BB20 regmask=[rcx] minReg=1 last reload fixed> BB20 regmask=[rcx] minReg=1> PUTARG_REG BB20 regmask=[rcx] minReg=1 fixed> CNS_INT BB20 regmask=[rdx] minReg=1> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rdx] minReg=1 last fixed> BB20 regmask=[rdx] minReg=1> PUTARG_REG BB20 regmask=[rdx] minReg=1 fixed> CNS_INT BB20 regmask=[rax] minReg=1> BB20 regmask=[rsi] minReg=1> BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[rcx] minReg=1> BB20 regmask=[rcx] minReg=1 last fixed> BB20 regmask=[rdx] minReg=1> BB20 regmask=[rdx] minReg=1 last fixed> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> CNS_INT BB20 regmask=[rdi] minReg=1> STORE_BLK BB20 regmask=[mm0] minReg=1> BB20 regmask=[rdi] minReg=1 last> STORE_BLK BB20 regmask=[mm0] minReg=1 last> LCL_VAR BB20 regmask=[rbx] minReg=1> LCL_VAR BB20 regmask=[rdi] minReg=1 last reload> BB20 regmask=[rdi] minReg=1> PUTARG_STK BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[rcx] minReg=1> PUTARG_STK BB20 regmask=[rcx] minReg=1 fixed> BB20 regmask=[rsi] minReg=1> PUTARG_STK BB20 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB20 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB20 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB20 regmask=[rsi] minReg=1 last fixed> BB20 regmask=[rdi] minReg=1> LCL_VAR BB20 regmask=[rdi] minReg=1 copy fixed> BB20 regmask=[rdi] minReg=1> PUTARG_REG BB20 regmask=[rdi] minReg=1 fixed> BB20 regmask=[r11] minReg=1> CNS_INT BB20 regmask=[r11] minReg=1 fixed> BB20 regmask=[r11] minReg=1> BB20 regmask=[r11] minReg=1 last fixed> BB20 regmask=[r11] minReg=1> PUTARG_REG BB20 regmask=[r11] minReg=1 fixed> CNS_INT BB20 regmask=[rax] minReg=1> BB20 regmask=[rdi] minReg=1> BB20 regmask=[rdi] minReg=1 last fixed> BB20 regmask=[r11] minReg=1> BB20 regmask=[r11] minReg=1 last fixed> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rax] minReg=1 last> BB20 regmask=[rcx] minReg=1 last> BB20 regmask=[rdx] minReg=1 last> BB20 regmask=[rsi] minReg=1 last> BB20 regmask=[rdi] minReg=1 last> BB20 regmask=[r8] minReg=1 last> BB20 regmask=[r9] minReg=1 last> BB20 regmask=[r10] minReg=1 last> BB20 regmask=[r11] minReg=1 last> CNS_INT BB21 regmask=[rax] minReg=1> BB21 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB21 regmask=[rax] minReg=1 spillAfter> BB22 regmask=[rdi] minReg=1> LCL_VAR BB22 regmask=[rdi] minReg=1 copy fixed> BB22 regmask=[rdi] minReg=1> PUTARG_REG BB22 regmask=[rdi] minReg=1 fixed> BB22 regmask=[rsi] minReg=1> LCL_VAR BB22 regmask=[rsi] minReg=1 copy fixed> BB22 regmask=[rsi] minReg=1> PUTARG_REG BB22 regmask=[rsi] minReg=1 fixed> BB22 regmask=[rdx] minReg=1> LCL_VAR BB22 regmask=[rdx] minReg=1 copy fixed> BB22 regmask=[rdx] minReg=1> PUTARG_REG BB22 regmask=[rdx] minReg=1 fixed> CNS_INT BB22 regmask=[rcx] minReg=1> BB22 regmask=[rdi] minReg=1> BB22 regmask=[rdi] minReg=1 last fixed> BB22 regmask=[rsi] minReg=1> BB22 regmask=[rsi] minReg=1 last fixed> BB22 regmask=[rdx] minReg=1> BB22 regmask=[rdx] minReg=1 last fixed> BB22 regmask=[rcx] minReg=1 last> BB22 regmask=[rax] minReg=1 last> BB22 regmask=[rcx] minReg=1 last> BB22 regmask=[rdx] minReg=1 last> BB22 regmask=[rsi] minReg=1 last> BB22 regmask=[rdi] minReg=1 last> BB22 regmask=[r8] minReg=1 last> BB22 regmask=[r9] minReg=1 last> BB22 regmask=[r10] minReg=1 last> BB22 regmask=[r11] minReg=1 last> BB22 regmask=[rax] minReg=1> CALL BB22 regmask=[rax] minReg=1 fixed> BB22 regmask=[rax] minReg=1 last regOptional> BB22 regmask=[allInt] minReg=1 regOptional> CNS_INT BB23 regmask=[rax] minReg=1> BB23 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB23 regmask=[rax] minReg=1> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 outOfOrder regOptional> BB23 regmask=[allInt] minReg=1 outOfOrder regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB24 regmask=[rax] minReg=1> BB24 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB25 regmask=[r13] minReg=1 outOfOrder regOptional> CNS_INT BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> CNS_INT BB26 regmask=[rax] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[rax] minReg=1> CALL BB26 regmask=[rax] minReg=1 fixed> BB26 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB26 regmask=[rax] minReg=1> LCL_VAR BB26 regmask=[rax] minReg=1> LCL_VAR BB26 regmask=[rax] minReg=1 spillAfter> LEA BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 copy fixed outOfOrder> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[mm0] minReg=1 last> BB26 regmask=[mm1] minReg=1 last> BB26 regmask=[mm2] minReg=1 last> BB26 regmask=[mm3] minReg=1 last> BB26 regmask=[mm4] minReg=1 last> BB26 regmask=[mm5] minReg=1 last> BB26 regmask=[mm6] minReg=1 last> BB26 regmask=[mm7] minReg=1 last> BB26 regmask=[mm8] minReg=1 last> BB26 regmask=[mm9] minReg=1 last> BB26 regmask=[mm10] minReg=1 last> BB26 regmask=[mm11] minReg=1 last> BB26 regmask=[mm12] minReg=1 last> BB26 regmask=[mm13] minReg=1 last> BB26 regmask=[mm14] minReg=1 last> BB26 regmask=[mm15] minReg=1 last> CNS_INT BB26 regmask=[rax] minReg=1> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[rax] minReg=1> CALL BB26 regmask=[rax] minReg=1 fixed> BB26 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB26 regmask=[rax] minReg=1 spillAfter> CNS_INT BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[rax] minReg=1> CALL BB26 regmask=[rax] minReg=1 fixed> BB26 regmask=[rax] minReg=1 last> IND BB26 regmask=[rsi] minReg=1> BB26 regmask=[rsi] minReg=1 last> STORE_LCL_VAR BB26 regmask=[rsi] minReg=1> BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rsi] minReg=1> PUTARG_REG BB26 regmask=[rsi] minReg=1 fixed> BB26 regmask=[rdi] minReg=1> LCL_VAR BB26 regmask=[rdi] minReg=1 reload spillAfter fixed> BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rcx] minReg=1> LCL_VAR BB26 regmask=[rcx] minReg=1 last reload fixed> BB26 regmask=[rcx] minReg=1> PUTARG_REG BB26 regmask=[rcx] minReg=1 fixed> CNS_INT BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> PUTARG_REG BB26 regmask=[rdx] minReg=1 fixed> CNS_INT BB26 regmask=[rax] minReg=1> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rcx] minReg=1> BB26 regmask=[rcx] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> LCL_VAR_ADDR BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 copy fixed outOfOrder> BB26 regmask=[rsi] minReg=1> PUTARG_REG BB26 regmask=[rsi] minReg=1 fixed> BB26 regmask=[rdx] minReg=1> LCL_VAR BB26 regmask=[rdx] minReg=1 last reload fixed> BB26 regmask=[rdx] minReg=1> PUTARG_REG BB26 regmask=[rdx] minReg=1 fixed> CNS_INT BB26 regmask=[rax] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[rsi] minReg=1> BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rdx] minReg=1> BB26 regmask=[rdx] minReg=1 last fixed> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> BB26 regmask=[rdi] minReg=1> PUTARG_STK BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[rcx] minReg=1> PUTARG_STK BB26 regmask=[rcx] minReg=1 fixed> BB26 regmask=[rsi] minReg=1> PUTARG_STK BB26 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB26 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB26 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB26 regmask=[rsi] minReg=1 last fixed> BB26 regmask=[rdi] minReg=1> LCL_VAR BB26 regmask=[rdi] minReg=1 copy fixed> BB26 regmask=[rdi] minReg=1> PUTARG_REG BB26 regmask=[rdi] minReg=1 fixed> BB26 regmask=[r11] minReg=1> CNS_INT BB26 regmask=[r11] minReg=1 fixed> BB26 regmask=[r11] minReg=1> BB26 regmask=[r11] minReg=1 last fixed> BB26 regmask=[r11] minReg=1> PUTARG_REG BB26 regmask=[r11] minReg=1 fixed> CNS_INT BB26 regmask=[rax] minReg=1> BB26 regmask=[rdi] minReg=1> BB26 regmask=[rdi] minReg=1 last fixed> BB26 regmask=[r11] minReg=1> BB26 regmask=[r11] minReg=1 last fixed> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rax] minReg=1 last> BB26 regmask=[rcx] minReg=1 last> BB26 regmask=[rdx] minReg=1 last> BB26 regmask=[rsi] minReg=1 last> BB26 regmask=[rdi] minReg=1 last> BB26 regmask=[r8] minReg=1 last> BB26 regmask=[r9] minReg=1 last> BB26 regmask=[r10] minReg=1 last> BB26 regmask=[r11] minReg=1 last> CNS_INT BB27 regmask=[rax] minReg=1> BB27 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB27 regmask=[rax] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> CNS_INT BB28 regmask=[rax] minReg=1> BB28 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB28 regmask=[rax] minReg=1> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 outOfOrder regOptional> BB28 regmask=[allInt] minReg=1 outOfOrder regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB28 regmask=[allInt] minReg=1 regOptional> BB29 regmask=[rax] minReg=1 last> BB29 regmask=[rcx] minReg=1 last> BB29 regmask=[rdx] minReg=1 last> BB29 regmask=[rsi] minReg=1 last> BB29 regmask=[rdi] minReg=1 last> BB29 regmask=[r8] minReg=1 last> BB29 regmask=[r9] minReg=1 last> BB29 regmask=[r10] minReg=1 last> BB29 regmask=[r11] minReg=1 last> VAR REFPOSITIONS AFTER ALLOCATION --- V00 (Interval 0) BB00 regmask=[] minReg=1 fixed regOptional> LCL_VAR BB12 regmask=[rdi] minReg=1 last reload fixed> BB18 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> --- V01 (Interval 1) BB00 regmask=[r12] minReg=1 fixed regOptional> LCL_VAR BB09 regmask=[rsi] minReg=1 copy fixed> BB15 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 outOfOrder regOptional> BB28 regmask=[allInt] minReg=1 outOfOrder regOptional> --- V02 (Interval 2) BB00 regmask=[rbx] minReg=1 fixed regOptional> LCL_VAR BB03 regmask=[rdi] minReg=1 copy fixed> LCL_VAR BB04 regmask=[rdi] minReg=1 copy fixed> LCL_VAR BB05 regmask=[rdi] minReg=1 copy fixed> LCL_VAR BB06 regmask=[rdi] minReg=1 copy fixed> LCL_VAR BB12 regmask=[rsi] minReg=1 copy fixed> BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB17 regmask=[rdi] minReg=1 copy fixed outOfOrder> LCL_VAR BB20 regmask=[rbx] minReg=1> LCL_VAR BB22 regmask=[rdi] minReg=1 copy fixed> BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB26 regmask=[rsi] minReg=1 copy fixed outOfOrder> BB28 regmask=[allInt] minReg=1 regOptional> --- V03 (Interval 3) BB00 regmask=[r14] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[rdi] minReg=1 copy fixed> LCL_VAR BB02 regmask=[rdi] minReg=1 copy fixed> LCL_VAR BB12 regmask=[rdx] minReg=1 copy fixed> LCL_VAR BB14 regmask=[rdi] minReg=1 copy fixed> BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB17 regmask=[rsi] minReg=1 copy fixed outOfOrder> LCL_VAR BB20 regmask=[rsi] minReg=1 copy fixed> LCL_VAR BB22 regmask=[rsi] minReg=1 copy fixed> BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB26 regmask=[rsi] minReg=1 copy fixed outOfOrder> BB28 regmask=[allInt] minReg=1 regOptional> --- V04 (Interval 4) BB00 regmask=[r13] minReg=1 fixed regOptional> LCL_VAR BB12 regmask=[rcx] minReg=1 copy fixed> BB15 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB17 regmask=[rdx] minReg=1 copy fixed outOfOrder> LCL_VAR BB19 regmask=[r13] minReg=1 regOptional> LCL_VAR BB20 regmask=[rdi] minReg=1 copy fixed> LCL_VAR BB22 regmask=[rdx] minReg=1 copy fixed> BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB25 regmask=[r13] minReg=1 outOfOrder regOptional> LCL_VAR BB26 regmask=[rdi] minReg=1 copy fixed> BB28 regmask=[allInt] minReg=1 regOptional> --- V05 (Interval 5) BB00 regmask=[r15] minReg=1 fixed regOptional> LCL_VAR BB06 regmask=[rsi] minReg=1 copy fixed> LCL_VAR BB10 regmask=[rsi] minReg=1 copy fixed> LCL_VAR BB12 regmask=[r8] minReg=1 copy fixed> LCL_VAR BB14 regmask=[rdx] minReg=1 copy fixed> BB15 regmask=[allInt] minReg=1 regOptional> BB23 regmask=[allInt] minReg=1 outOfOrder regOptional> BB28 regmask=[allInt] minReg=1 outOfOrder regOptional> --- V06 (Interval 6) STORE_LCL_VAR BB07 regmask=[rax] minReg=1> LCL_VAR BB08 regmask=[rax] minReg=1 last fixed> STORE_LCL_VAR BB24 regmask=[rax] minReg=1> BB24 regmask=[allInt] minReg=1 regOptional> --- V07 (Interval 7) STORE_LCL_VAR BB02 regmask=[rax] minReg=1 spillAfter> LCL_VAR BB07 regmask=[r13] minReg=1 last reload> BB17 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB18 regmask=[rax] minReg=1> BB18 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB21 regmask=[rax] minReg=1 spillAfter> BB22 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB23 regmask=[rax] minReg=1> BB23 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB27 regmask=[rax] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB28 regmask=[rax] minReg=1> BB28 regmask=[allInt] minReg=1 regOptional> --- V08 --- V09 --- V10 (Interval 8) STORE_LCL_VAR BB09 regmask=[rax] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 spillAfter copy fixed> LCL_VAR BB10 regmask=[rdi] minReg=1 reload spillAfter fixed> LCL_VAR BB14 regmask=[rsi] minReg=1 reload spillAfter fixed> LCL_VAR BB20 regmask=[rsi] minReg=1 last reload fixed> --- V11 --- V12 --- V13 --- V14 (Interval 9) STORE_LCL_VAR BB20 regmask=[rax] minReg=1> LCL_VAR BB20 regmask=[rax] minReg=1> LCL_VAR BB20 regmask=[rax] minReg=1 spillAfter> LCL_VAR BB20 regmask=[rax] minReg=1 reload spillAfter> LCL_VAR BB20 regmask=[rcx] minReg=1 last reload fixed> --- V15 --- V16 (Interval 10) STORE_LCL_VAR BB26 regmask=[rax] minReg=1> LCL_VAR BB26 regmask=[rax] minReg=1> LCL_VAR BB26 regmask=[rax] minReg=1 spillAfter> LCL_VAR BB26 regmask=[rcx] minReg=1 last reload fixed> --- V17 --- V18 (Interval 11) STORE_LCL_VAR BB26 regmask=[rax] minReg=1 spillAfter> LCL_VAR BB26 regmask=[rdi] minReg=1 reload spillAfter fixed> LCL_VAR BB26 regmask=[rdx] minReg=1 last reload fixed> --- V19 (Interval 12) STORE_LCL_VAR BB14 regmask=[rsi] minReg=1> LCL_VAR BB14 regmask=[rsi] minReg=1 last regOptional> --- V20 (Interval 13) STORE_LCL_VAR BB20 regmask=[rax] minReg=1 spillAfter> LCL_VAR BB20 regmask=[rdi] minReg=1 reload spillAfter fixed> LCL_VAR BB20 regmask=[rdi] minReg=1 last reload> --- V21 --- V22 --- V23 --- V24 (Interval 14) STORE_LCL_VAR BB26 regmask=[rsi] minReg=1> LCL_VAR BB26 regmask=[rsi] minReg=1 last fixed> --- V25 (Interval 15) STORE_LCL_VAR BB06 regmask=[rsi] minReg=1> LCL_VAR BB06 regmask=[rsi] minReg=1> LCL_VAR BB06 regmask=[rsi] minReg=1 last> --- V26 (Interval 16) STORE_LCL_VAR BB09 regmask=[rdi] minReg=1> LCL_VAR BB09 regmask=[rdi] minReg=1 last fixed> --- V27 (Interval 17) STORE_LCL_VAR BB20 regmask=[rsi] minReg=1> LCL_VAR BB20 regmask=[rsi] minReg=1 last fixed> --- V28 (Interval 18) STORE_LCL_VAR BB20 regmask=[rdx] minReg=1> LCL_VAR BB20 regmask=[rdx] minReg=1 spillAfter regOptional> LCL_VAR BB20 regmask=[] minReg=1 last regOptional> Active intervals at end of allocation: ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00 V01 V02 V03 V04 V05 V06 V07 V10} Has Critical Edges Prior to Resolution BB01 use def in out {V03} {} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05} Var=Reg beg of BB01: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB01: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB02 use def in out {V03} {V07} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05 V07} Var=Reg beg of BB02: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB02: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB03 use def in out {V02} {} {V00 V01 V02 V03 V04 V05 V07} {V00 V01 V02 V03 V04 V05 V07} Var=Reg beg of BB03: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB03: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB04 use def in out {V02} {} {V00 V01 V02 V03 V04 V05 V07} {V00 V01 V02 V03 V04 V05 V07} Var=Reg beg of BB04: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB04: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB05 use def in out {V02} {} {V00 V01 V02 V03 V04 V05 V07} {V00 V01 V02 V03 V04 V05 V07} Var=Reg beg of BB05: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB05: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB06 use def in out {V02 V05} {V25} {V01 V02 V03 V04 V05 V07} {V01 V02 V03 V04 V05 V07} Var=Reg beg of BB06: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB06: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB07 use def in out {V07} {V06} {V07} {V06} Var=Reg beg of BB07: none Var=Reg end of BB07: V06=rax BB08 use def in out {V06} {} {V06} {} Var=Reg beg of BB08: V06=rax Var=Reg end of BB08: none BB09 use def in out {V01} {V10 V13 V26} {V01 V02 V03 V04 V05 V07} {V01 V02 V03 V04 V05 V07 V10} Var=Reg beg of BB09: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB09: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB10 use def in out {V05 V10} {V19} {V01 V02 V03 V04 V05 V10} {V01 V02 V03 V04 V05 V10} Var=Reg beg of BB10: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB10: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB12 use def in out {V00 V02 V03 V04 V05} {} {V00 V01 V02 V03 V04 V05 V07} {V01 V02 V03 V04 V05 V07} Var=Reg beg of BB12: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB12: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB13 use def in out {} {} {V01 V02 V03 V04 V05 V07} {V01 V02 V03 V04 V05 V07} Var=Reg beg of BB13: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB13: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB14 use def in out {V03 V05 V10} {V19} {V01 V02 V03 V04 V05 V07 V10} {V01 V02 V03 V04 V05 V07 V10} Var=Reg beg of BB14: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB14: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB15 use def in out {} {} {V01 V02 V03 V04 V05 V07} {V01 V02 V03 V04 V05 V07} Var=Reg beg of BB15: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB15: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB16 use def in out {} {} {V07} {V07} Var=Reg beg of BB16: none Var=Reg end of BB16: none BB17 use def in out {V02 V03 V04} {} {V00 V01 V02 V03 V04 V05 V07} {V00 V01 V02 V03 V04 V05 V07} Var=Reg beg of BB17: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB17: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB18 use def in out {} {V07} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05 V07} Var=Reg beg of BB18: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB18: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 V07=rax BB19 use def in out {V04} {} {V01 V02 V03 V04 V05 V10} {V01 V02 V03 V04 V05 V10} Var=Reg beg of BB19: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB19: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB20 use def in out {V02 V03 V04 V10} {V14 V15 V20 V27 V28} {V01 V02 V03 V04 V05 V10} {V01 V02 V03 V04 V05} Var=Reg beg of BB20: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB20: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB21 use def in out {} {V07} {V01 V02 V03 V04 V05} {V01 V02 V03 V04 V05 V07} Var=Reg beg of BB21: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB21: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB22 use def in out {V02 V03 V04} {} {V00 V01 V02 V03 V04 V05 V07} {V00 V01 V02 V03 V04 V05 V07} Var=Reg beg of BB22: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB22: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB23 use def in out {} {V07} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05 V07} Var=Reg beg of BB23: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB23: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 V07=rax BB24 use def in out {} {V06} {} {V06} Var=Reg beg of BB24: none Var=Reg end of BB24: V06=rax BB25 use def in out {V04} {} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05} Var=Reg beg of BB25: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB25: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB26 use def in out {V02 V03 V04} {V16 V18 V24} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05} Var=Reg beg of BB26: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB26: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB27 use def in out {} {V07} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V03 V04 V05 V07} Var=Reg beg of BB27: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB27: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 V07=rax BB28 use def in out {} {V07} {V01 V02 V03 V04 V05} {V01 V02 V03 V04 V05 V07} Var=Reg beg of BB28: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB28: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 V07=rax BB29 use def in out {} {} {} {} Var=Reg beg of BB29: none Var=Reg end of BB29: none RESOLVING EDGES BB18 bottom: move V07 from rax to STK (Join) BB23 bottom: move V07 from rax to STK (Join) BB27 bottom: move V07 from rax to STK (Join) BB28 bottom: move V07 from rax to STK (Join) Set V00 argument initial register to STK Set V01 argument initial register to r12 Set V02 argument initial register to rbx Set V03 argument initial register to r14 Set V04 argument initial register to r13 Set V05 argument initial register to r15 Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC LIR BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC LIR BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC LIR BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC LIR BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC LIR BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC LIR BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC LIR BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC LIR BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC LIR BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB19 (always) i gcsafe bwd LIR BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC LIR BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC LIR BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC LIR BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC LIR BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe LIR BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC LIR BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC LIR BB19 [0017] 2 BB14,BB10 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC LIR BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC LIR BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC LIR BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC LIR BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC LIR BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC LIR BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC LIR BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC LIR BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC LIR BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC LIR BB29 [0038] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} N003 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t0 ref N005 (???,???) [000508] ------------ t508 = * PUTARG_REG ref REG rdi N007 ( 3, 10) [000279] ------------ t279 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t279 long N009 (???,???) [000509] ------------ t509 = * PUTARG_REG long REG r11 N011 ( 3, 10) [000510] ------------ t510 = CNS_INT(h) long 0xd1ffab1e ftn REG rsi /--* t510 long N013 ( 5, 12) [000511] -c---------- t511 = * IND long REG NA /--* t508 ref this in rdi +--* t509 long arg1 in r11 +--* t511 long control expr N015 ( 24, 21) [000198] --CXG------- t198 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind REG rax $200 N017 ( 1, 1) [000199] -c---------- t199 = CNS_INT int 4 REG NA $44 /--* t198 int +--* t199 int N019 ( 26, 23) [000200] J--XG--N---- * EQ void REG NA $280 N021 ( 28, 25) [000006] ---XG------- * JTRUE void REG NA ------------ BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} N025 (???,???) [000472] ------------ IL_OFFSET void IL offset: 0xf REG NA N027 ( 1, 1) [000007] -c---------- t7 = CNS_INT int 1 REG NA $41 /--* t7 int N029 ( 5, 4) [000009] DA---------- * STORE_LCL_VAR int V07 loc1 d:2 NA REG NA N031 ( 1, 1) [000010] ------------ t10 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t10 ref N033 (???,???) [000512] ------------ t512 = * PUTARG_REG ref REG rdi N035 ( 3, 10) [000284] ------------ t284 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 /--* t284 long N037 (???,???) [000513] ------------ t513 = * PUTARG_REG long REG r11 N039 ( 3, 10) [000514] ------------ t514 = CNS_INT(h) long 0xd1ffab1e ftn REG rsi /--* t514 long N041 ( 5, 12) [000515] -c---------- t515 = * IND long REG NA /--* t512 ref this in rdi +--* t513 long arg1 in r11 +--* t515 long control expr N043 ( 24, 21) [000202] --CXG------- t202 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType REG rax $204 /--* t202 int N045 ( 25, 23) [000203] ---XG------- t203 = * CAST int <- byte <- int REG rdi $281 /--* t203 int N047 (???,???) [000516] ---XG------- t516 = * PUTARG_REG int REG rdi N049 ( 3, 10) [000517] ------------ t517 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t517 long N051 ( 5, 12) [000518] -c---------- t518 = * IND long REG NA /--* t516 int arg0 in rdi +--* t518 long control expr N053 ( 39, 29) [000204] --CXG------- t204 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType REG rax $205 N055 ( 1, 1) [000014] -c---------- t14 = CNS_INT bool 0 REG NA $40 /--* t204 bool +--* t14 bool N057 ( 42, 33) [000015] J--XG--N-U-- * NE void REG NA $283 N059 ( 44, 35) [000016] ---XG------- * JTRUE void REG NA ------------ BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} N001 ( 0, 0) [000450] ------------ t450 = PHI_ARG bool V07 loc1 u:3 $40 N002 ( 0, 0) [000449] ------------ t449 = PHI_ARG bool V07 loc1 u:2 $41 /--* t450 bool +--* t449 bool N003 ( 0, 0) [000446] ------------ t446 = * PHI bool /--* t446 bool N005 ( 0, 0) [000447] DA---------- * STORE_LCL_VAR bool V07 loc1 d:4 N063 (???,???) [000473] ------------ IL_OFFSET void IL offset: 0x40 REG NA N065 ( 1, 1) [000017] ------------ t17 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t17 ref N067 (???,???) [000519] ------------ t519 = * PUTARG_REG ref REG rdi N069 ( 3, 10) [000312] ------------ t312 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca /--* t312 long N071 (???,???) [000520] ------------ t520 = * PUTARG_REG long REG r11 N073 ( 3, 10) [000521] ------------ t521 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t521 long N075 ( 5, 12) [000522] -c---------- t522 = * IND long REG NA /--* t519 ref this in rdi +--* t520 long arg1 in r11 +--* t522 long control expr N077 ( 24, 21) [000018] --CXG------- t18 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint REG rax $208 N079 ( 1, 1) [000020] -c---------- t20 = CNS_INT bool 0 REG NA $40 /--* t18 bool +--* t20 bool N081 ( 27, 25) [000021] J--XG--N-U-- * NE void REG NA $287 N083 ( 29, 27) [000022] ---XG------- * JTRUE void REG NA ------------ BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} N001 ( 0, 0) [000452] ------------ t452 = PHI_ARG bool V07 loc1 u:5 $40 N002 ( 0, 0) [000451] ------------ t451 = PHI_ARG bool V07 loc1 u:4 $580 /--* t452 bool +--* t451 bool N003 ( 0, 0) [000443] ------------ t443 = * PHI bool /--* t443 bool N005 ( 0, 0) [000444] DA---------- * STORE_LCL_VAR bool V07 loc1 d:6 N087 (???,???) [000474] ------------ IL_OFFSET void IL offset: 0x55 REG NA N089 ( 1, 1) [000023] ------------ t23 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t23 ref N091 (???,???) [000523] ------------ t523 = * PUTARG_REG ref REG rdi N093 ( 3, 10) [000319] ------------ t319 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc /--* t319 long N095 (???,???) [000524] ------------ t524 = * PUTARG_REG long REG r11 N097 ( 3, 10) [000525] ------------ t525 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t525 long N099 ( 5, 12) [000526] -c---------- t526 = * IND long REG NA /--* t523 ref this in rdi +--* t524 long arg1 in r11 +--* t526 long control expr N101 ( 24, 21) [000024] --CXG------- t24 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint REG rax $20b N103 ( 1, 1) [000026] -c---------- t26 = CNS_INT bool 0 REG NA $40 /--* t24 bool +--* t26 bool N105 ( 27, 25) [000027] J--XG--N-U-- * NE void REG NA $28b N107 ( 29, 27) [000028] ---XG------- * JTRUE void REG NA ------------ BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} N001 ( 0, 0) [000454] ------------ t454 = PHI_ARG bool V07 loc1 u:7 $40 N002 ( 0, 0) [000453] ------------ t453 = PHI_ARG bool V07 loc1 u:6 $581 /--* t454 bool +--* t453 bool N003 ( 0, 0) [000440] ------------ t440 = * PHI bool /--* t440 bool N005 ( 0, 0) [000441] DA---------- * STORE_LCL_VAR bool V07 loc1 d:8 N111 (???,???) [000475] ------------ IL_OFFSET void IL offset: 0x6a REG NA N113 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t29 ref N115 (???,???) [000527] ------------ t527 = * PUTARG_REG ref REG rdi N117 ( 3, 10) [000326] ------------ t326 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce /--* t326 long N119 (???,???) [000528] ------------ t528 = * PUTARG_REG long REG r11 N121 ( 3, 10) [000529] ------------ t529 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t529 long N123 ( 5, 12) [000530] -c---------- t530 = * IND long REG NA /--* t527 ref this in rdi +--* t528 long arg1 in r11 +--* t530 long control expr N125 ( 24, 21) [000030] --CXG------- t30 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint REG rax $20e N127 ( 1, 1) [000032] -c---------- t32 = CNS_INT bool 0 REG NA $40 /--* t30 bool +--* t32 bool N129 ( 27, 25) [000033] J--XG--N-U-- * NE void REG NA $28f N131 ( 29, 27) [000034] ---XG------- * JTRUE void REG NA ------------ BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} N001 ( 0, 0) [000456] ------------ t456 = PHI_ARG bool V07 loc1 u:9 $40 N002 ( 0, 0) [000455] ------------ t455 = PHI_ARG bool V07 loc1 u:8 $582 /--* t456 bool +--* t455 bool N003 ( 0, 0) [000437] ------------ t437 = * PHI bool /--* t437 bool N005 ( 0, 0) [000438] DA---------- * STORE_LCL_VAR bool V07 loc1 d:10 N135 ( 1, 1) [000035] ------------ t35 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t35 ref N137 (???,???) [000531] ------------ t531 = * PUTARG_REG ref REG rdi N139 ( 1, 1) [000036] ------------ t36 = LCL_VAR byref V05 arg5 u:1 r15 REG r15 $c0 /--* t36 byref N141 (???,???) [000532] ------------ t532 = * PUTARG_REG byref REG rsi N143 ( 3, 10) [000533] ------------ t533 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t533 long N145 ( 5, 12) [000534] -c---------- t534 = * IND long REG NA /--* t531 ref this in rdi +--* t532 byref arg1 in rsi +--* t534 long control expr N147 ( 16, 10) [000037] --CXG------- t37 = * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics REG rax $167 /--* t37 ref N149 ( 20, 13) [000042] DA-XG------- * STORE_LCL_VAR ref (AX) V23 tmp12 NA REG NA N151 (???,???) [000476] ------------ IL_OFFSET void IL offset: 0x8b REG NA N153 ( 3, 10) [000046] ------------ t46 = CNS_INT(h) long 0xd1ffab1e class REG rsi $1d0 /--* t46 long N155 ( 5, 12) [000047] n----------- t47 = * IND long REG rsi /--* t47 long N157 (???,???) [000535] ------------ t535 = * PUTARG_REG long REG rsi N159 ( 3, 2) [000043] -------N---- t43 = LCL_VAR_ADDR byref V09 loc3 rdi * ref V09.array (offs=0x00) -> V23 tmp12 REG rdi /--* t43 byref N161 (???,???) [000536] ------------ t536 = * PUTARG_REG byref REG rdi N163 ( 3, 10) [000537] ------------ t537 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t537 long N165 ( 5, 12) [000538] -c---------- t538 = * IND long REG NA /--* t535 long arg1 in rsi +--* t536 byref this in rdi +--* t538 long control expr N167 ( 22, 23) [000045] --CXG------- t45 = * CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator REG rax,rdx $501 /--* t45 struct N169 ( 26, 26) [000050] DA-XG------- * STORE_LCL_VAR struct(AX) V12 tmp1 NA REG NA N171 ( 3, 2) [000341] -------N---- t341 = LCL_VAR_ADDR byref V12 tmp1 rsi REG rsi /--* t341 byref N173 ( 3, 3) [000343] DA---------- * STORE_LCL_VAR byref V25 tmp14 d:2 rsi REG rsi N175 ( 1, 1) [000345] ------------ t345 = LCL_VAR byref V25 tmp14 u:2 rsi Zero Fseq[_array] REG rsi $487 /--* t345 byref N177 ( 3, 2) [000346] ---X-------- t346 = * IND ref REG rdi /--* t346 ref N179 ( 7, 5) [000347] DA-XG------- * STORE_LCL_VAR ref (AX) V21 tmp10 NA REG NA N181 ( 1, 1) [000350] ------------ t350 = LCL_VAR byref V25 tmp14 u:2 rsi (last use) REG rsi $487 /--* t350 byref N183 ( 2, 2) [000352] -c---------- t352 = * LEA(b+8) byref REG NA /--* t352 byref N185 ( 4, 4) [000353] n----O------ t353 = * IND int REG rsi /--* t353 int N187 ( 8, 7) [000354] DA--GO------ * STORE_LCL_VAR int (AX) V22 tmp11 NA REG NA N189 (???,???) [000477] ------------ IL_OFFSET void IL offset: 0xe1 REG NA N191 ( 3, 10) [000415] ------------ t415 = CNS_INT(h) long 0xd1ffab1e class REG rsi $1d1 /--* t415 long N193 ( 5, 12) [000414] n----------- t414 = * IND long REG rsi /--* t414 long N195 (???,???) [000539] ------------ t539 = * PUTARG_REG long REG rsi N197 ( 3, 2) [000417] ----G--N---- t417 = LCL_VAR_ADDR byref V08 loc2 rdi * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 REG rdi /--* t417 byref N199 (???,???) [000540] ----G------- t540 = * PUTARG_REG byref REG rdi N201 ( 3, 10) [000541] ------------ t541 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t541 long N203 ( 5, 12) [000542] -c---------- t542 = * IND long REG NA /--* t539 long arg1 in rsi +--* t540 byref this in rdi +--* t542 long control expr N205 ( 22, 23) [000411] --CXG------- t411 = * CALL r2r_ind bool Enumerator[__Canon][System.__Canon].MoveNext REG rax $212 N207 ( 1, 1) [000418] -c---------- t418 = CNS_INT bool 0 REG NA $40 /--* t411 bool +--* t418 bool N209 ( 25, 27) [000409] J--XG--N-U-- * NE void REG NA $295 N211 ( 27, 29) [000419] ---XG------- * JTRUE void REG NA ------------ BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} N001 ( 0, 0) [000461] ------------ t461 = PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000457] ------------ t457 = PHI_ARG bool V07 loc1 u:10 $583 /--* t461 bool +--* t457 bool N003 ( 0, 0) [000431] ------------ t431 = * PHI bool /--* t431 bool N005 ( 0, 0) [000432] DA---------- * STORE_LCL_VAR bool V07 loc1 d:14 N215 (???,???) [000478] ------------ IL_OFFSET void IL offset: 0xea REG NA N217 ( 3, 2) [000125] -----------z t125 = LCL_VAR int V07 loc1 u:14 r13 (last use) REG r13 $584 /--* t125 int N219 ( 7, 5) [000127] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 rax REG rax ------------ BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} N001 ( 0, 0) [000463] ------------ t463 = PHI_ARG bool V06 loc0 u:4 rax $584 N002 ( 0, 0) [000448] ------------ t448 = PHI_ARG bool V06 loc0 u:2 rax $41 /--* t463 bool +--* t448 bool N003 ( 0, 0) [000425] ------------ t425 = * PHI bool /--* t425 bool N005 ( 0, 0) [000426] DA---------- * STORE_LCL_VAR bool V06 loc0 d:3 rax N223 (???,???) [000479] ------------ IL_OFFSET void IL offset: 0xec REG NA N225 ( 3, 2) [000128] ------------ t128 = LCL_VAR int V06 loc0 u:3 rax (last use) REG rax $585 /--* t128 int N227 ( 4, 3) [000129] ------------ * RETURN int REG NA $214 ------------ BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} N001 ( 0, 0) [000460] ------------ t460 = PHI_ARG bool V07 loc1 u:13 N002 ( 0, 0) [000458] ------------ t458 = PHI_ARG bool V07 loc1 u:10 $583 /--* t460 bool +--* t458 bool N003 ( 0, 0) [000434] ------------ t434 = * PHI bool /--* t434 bool N005 ( 0, 0) [000435] DA---------- * STORE_LCL_VAR bool V07 loc1 d:11 N231 (???,???) [000480] ------------ IL_OFFSET void IL offset: 0x95 REG NA N233 ( 3, 10) [000067] ------------ t67 = CNS_INT(h) long 0xd1ffab1e class REG rsi $1d1 /--* t67 long N235 ( 5, 12) [000068] n----------- t68 = * IND long REG rsi /--* t68 long N237 (???,???) [000543] ------------ t543 = * PUTARG_REG long REG rsi N239 ( 3, 2) [000064] -------N---- t64 = LCL_VAR_ADDR byref V08 loc2 rdi * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 REG rdi /--* t64 byref N241 (???,???) [000544] ------------ t544 = * PUTARG_REG byref REG rdi N243 ( 3, 10) [000545] ------------ t545 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t545 long N245 ( 5, 12) [000546] -c---------- t546 = * IND long REG NA /--* t543 long arg1 in rsi +--* t544 byref this in rdi +--* t546 long control expr N247 ( 22, 23) [000066] --CXG------- t66 = * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current REG rax $16c /--* t66 ref N249 ( 26, 26) [000360] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp15 d:2 rdi REG rdi N251 ( 3, 2) [000361] ------------ t361 = LCL_VAR ref V26 tmp15 u:2 rdi (last use) REG rdi $16c /--* t361 ref N253 (???,???) [000547] ------------ t547 = * PUTARG_REG ref REG rdi N255 ( 3, 2) [000069] ------------ t69 = LCL_VAR ref V01 arg1 u:1 r12 REG r12 $81 /--* t69 ref N257 (???,???) [000548] ------------ t548 = * PUTARG_REG ref REG rsi N259 ( 3, 10) [000356] ------------ t356 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 /--* t356 long N261 (???,???) [000549] ------------ t549 = * PUTARG_REG long REG r11 N263 ( 3, 10) [000550] ------------ t550 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t550 long N265 ( 5, 12) [000551] -c---------- t551 = * IND long REG NA /--* t547 ref this in rdi +--* t548 ref arg2 in rsi +--* t549 long arg1 in r11 +--* t551 long control expr N267 ( 55, 51) [000070] --CXG------- t70 = * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters REG rax,rdx $502 /--* t70 struct N269 ( 59, 54) [000073] DA-XG------- * STORE_LCL_VAR struct V13 tmp2 d:2 NA REG NA N271 ( 3, 4) [000076] ------------ t76 = LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] rax (last use) REG rax $370 /--* t76 ref N273 ( 7, 7) [000078] DA---------- * STORE_LCL_VAR ref V10 loc4 d:2 rax REG rax N275 (???,???) [000481] ------------ IL_OFFSET void IL offset: 0xa9 REG NA N277 ( 3, 2) [000080] -----------Z t80 = LCL_VAR ref V10 loc4 u:2 rax REG rax $370 /--* t80 ref N279 (???,???) [000552] ------------ t552 = * PUTARG_REG ref REG rdi N281 ( 3, 10) [000365] ------------ t365 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 /--* t365 long N283 (???,???) [000553] ------------ t553 = * PUTARG_REG long REG r11 N285 ( 3, 10) [000554] ------------ t554 = CNS_INT(h) long 0xd1ffab1e ftn REG rsi /--* t554 long N287 ( 5, 12) [000555] -c---------- t555 = * IND long REG NA /--* t552 ref this in rdi +--* t553 long arg1 in r11 +--* t555 long control expr N289 ( 26, 22) [000247] --CXG------- t247 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind REG rax $215 N291 ( 1, 1) [000248] -c---------- t248 = CNS_INT int 4 REG NA $44 /--* t247 int +--* t248 int N293 ( 28, 24) [000249] J--XG--N---- * NE void REG NA $296 N295 ( 30, 26) [000228] ---XG------- * JTRUE void REG NA ------------ BB10 [0A9..0AA) -> BB19 (always), preds={BB09} succs={BB19} N299 (???,???) [000482] ------------ IL_OFFSET void IL offset: 0xa9 REG NA N301 ( 3, 2) [000237] -----------z t237 = LCL_VAR ref V10 loc4 u:2 rdi REG rdi $370 /--* t237 ref N303 (???,???) [000556] ------------ t556 = * PUTARG_REG ref REG rdi N305 ( 1, 1) [000238] ------------ t238 = LCL_VAR byref V05 arg5 u:1 r15 REG r15 $c0 /--* t238 byref N307 (???,???) [000557] ------------ t557 = * PUTARG_REG byref REG rsi N309 ( 3, 10) [000558] ------------ t558 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t558 long N311 ( 5, 12) [000559] -c---------- t559 = * IND long REG NA /--* t556 ref arg0 in rdi +--* t557 byref arg1 in rsi +--* t559 long control expr N313 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics REG NA $VN.Void N315 (???,???) [000483] ------------ IL_OFFSET void IL offset: 0xa9 REG NA ------------ BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} N319 (???,???) [000484] ------------ IL_OFFSET void IL offset: 0x72 REG NA N321 ( 3, 2) [000130] -----------z t130 = LCL_VAR ref V00 arg0 u:1 rdi (last use) REG rdi $80 /--* t130 ref N323 (???,???) [000560] ------------ t560 = * PUTARG_REG ref REG rdi N325 ( 1, 1) [000131] ------------ t131 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t131 ref N327 (???,???) [000561] ------------ t561 = * PUTARG_REG ref REG rsi N329 ( 1, 1) [000132] ------------ t132 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t132 ref N331 (???,???) [000562] ------------ t562 = * PUTARG_REG ref REG rdx N333 ( 3, 2) [000133] ------------ t133 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 /--* t133 ref N335 (???,???) [000563] ------------ t563 = * PUTARG_REG ref REG rcx N337 ( 1, 1) [000134] ------------ t134 = LCL_VAR byref V05 arg5 u:1 r15 REG r15 $c0 /--* t134 byref N339 (???,???) [000564] ------------ t564 = * PUTARG_REG byref REG r8 N341 ( 3, 10) [000565] ------------ t565 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t565 long N343 ( 5, 12) [000566] -c---------- t566 = * IND long REG NA /--* t560 ref arg0 in rdi +--* t561 ref arg1 in rsi +--* t562 ref arg2 in rdx +--* t563 ref arg3 in rcx +--* t564 byref arg4 in r8 +--* t566 long control expr N345 ( 23, 17) [000135] --CXG------- t135 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint REG rax $20f N347 ( 1, 1) [000137] -c---------- t137 = CNS_INT bool 0 REG NA $40 /--* t135 bool +--* t137 bool N349 ( 26, 21) [000138] J--XG--N-U-- * EQ void REG NA $291 N351 ( 28, 23) [000139] ---XG------- * JTRUE void REG NA ------------ BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ------------ BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} N357 (???,???) [000485] ------------ IL_OFFSET void IL offset: 0xa9 REG NA N359 ( 1, 1) [000079] ------------ t79 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t79 ref N361 (???,???) [000567] ------------ t567 = * PUTARG_REG ref REG rdi N363 ( 3, 2) [000229] -----------z t229 = LCL_VAR ref V10 loc4 u:2 rsi REG rsi $370 /--* t229 ref N365 (???,???) [000568] ------------ t568 = * PUTARG_REG ref REG rsi N367 ( 1, 1) [000081] ------------ t81 = LCL_VAR byref V05 arg5 u:1 r15 REG r15 $c0 /--* t81 byref N369 (???,???) [000569] ------------ t569 = * PUTARG_REG byref REG rdx N371 ( 3, 10) [000570] ------------ t570 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t570 long N373 ( 5, 12) [000571] -c---------- t571 = * IND long REG NA /--* t567 ref arg0 in rdi +--* t568 ref arg1 in rsi +--* t569 byref arg2 in rdx +--* t571 long control expr N375 ( 19, 12) [000230] --CXG------- t230 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion REG rax $216 /--* t230 int N377 ( 20, 14) [000232] ---XG------- t232 = * CAST int <- bool <- int REG rsi $297 /--* t232 int N379 ( 24, 17) [000234] DA-XG------- * STORE_LCL_VAR int V19 tmp8 d:2 rsi REG rsi N381 ( 3, 2) [000235] ------------ t235 = LCL_VAR int V19 tmp8 u:2 rsi (last use) REG rsi $297 N383 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 REG NA $40 /--* t235 int +--* t85 int N385 ( 5, 4) [000086] J------N---- * EQ void REG NA $298 N387 ( 7, 6) [000087] ------------ * JTRUE void REG NA ------------ BB15 [0E1..0EA) -> BB09 (cond), preds={BB14,BB21} succs={BB16,BB09} N001 ( 0, 0) [000462] ------------ t462 = PHI_ARG bool V07 loc1 u:11 $586 N002 ( 0, 0) [000459] ------------ t459 = PHI_ARG bool V07 loc1 u:12 $40 /--* t462 bool +--* t459 bool N003 ( 0, 0) [000428] ------------ t428 = * PHI bool /--* t428 bool N005 ( 0, 0) [000429] DA---------- * STORE_LCL_VAR bool V07 loc1 d:13 N391 (???,???) [000486] ------------ IL_OFFSET void IL offset: 0xe1 REG NA N393 ( 3, 10) [000058] ------------ t58 = CNS_INT(h) long 0xd1ffab1e class REG rsi $1d1 /--* t58 long N395 ( 5, 12) [000059] n----------- t59 = * IND long REG rsi /--* t59 long N397 (???,???) [000572] ------------ t572 = * PUTARG_REG long REG rsi N399 ( 3, 2) [000055] -------N---- t55 = LCL_VAR_ADDR byref V08 loc2 rdi * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 REG rdi /--* t55 byref N401 (???,???) [000573] ------------ t573 = * PUTARG_REG byref REG rdi N403 ( 3, 10) [000574] ------------ t574 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t574 long N405 ( 5, 12) [000575] -c---------- t575 = * IND long REG NA /--* t572 long arg1 in rsi +--* t573 byref this in rdi +--* t575 long control expr N407 ( 22, 23) [000057] --CXG------- t57 = * CALL r2r_ind bool Enumerator[__Canon][System.__Canon].MoveNext REG rax $21b N409 ( 1, 1) [000061] -c---------- t61 = CNS_INT bool 0 REG NA $40 /--* t57 bool +--* t61 bool N411 ( 25, 27) [000062] J--XG--N-U-- * NE void REG NA $29b N413 ( 27, 29) [000063] ---XG------- * JTRUE void REG NA ------------ BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ------------ BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} N419 ( 1, 1) [000143] ------------ t143 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t143 ref N421 (???,???) [000576] ------------ t576 = * PUTARG_REG ref REG rdi N423 ( 1, 1) [000144] ------------ t144 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t144 ref N425 (???,???) [000577] ------------ t577 = * PUTARG_REG ref REG rsi N427 ( 3, 2) [000145] ------------ t145 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 /--* t145 ref N429 (???,???) [000578] ------------ t578 = * PUTARG_REG ref REG rdx N431 ( 3, 10) [000579] ------------ t579 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t579 long N433 ( 5, 12) [000580] -c---------- t580 = * IND long REG NA /--* t576 ref arg0 in rdi +--* t577 ref arg1 in rsi +--* t578 ref arg2 in rdx +--* t580 long control expr N435 ( 19, 12) [000146] --CXG------- t146 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint REG rax $20c N437 ( 1, 1) [000149] -c---------- t149 = CNS_INT bool 0 REG NA $40 /--* t146 bool +--* t149 bool N439 ( 22, 16) [000150] J--XG--N-U-- * NE void REG NA $28d N441 ( 24, 18) [000151] ---XG------- * JTRUE void REG NA ------------ BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} N445 (???,???) [000487] ------------ IL_OFFSET void IL offset: 0x68 REG NA N447 ( 1, 1) [000152] ------------ t152 = CNS_INT int 0 REG rdi $40 /--* t152 int N449 ( 5, 4) [000154] DA---------- * STORE_LCL_VAR int V07 loc1 d:7 rax REG rax N001 ( 4, 3) [000628] -----------Z t628 = LCL_VAR bool V07 loc1 rax REG rax ------------ BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB10} succs={BB20,BB21} N453 (???,???) [000488] ------------ IL_OFFSET void IL offset: 0xb5 REG NA N455 ( 3, 2) [000088] ------------ t88 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 N457 ( 1, 1) [000089] -c---------- t89 = CNS_INT ref null REG NA $VN.Null /--* t88 ref +--* t89 ref N459 ( 5, 4) [000090] J------N---- * EQ void REG NA $284 N461 ( 7, 6) [000091] ------------ * JTRUE void REG NA ------------ BB20 [0B9..0DF), preds={BB19} succs={BB21} N465 (???,???) [000489] ------------ IL_OFFSET void IL offset: 0xb9 REG NA N467 ( 1, 1) [000098] ------------ t98 = CNS_INT long 2 REG rdi $2c4 /--* t98 long N469 (???,???) [000581] ------------ t581 = * PUTARG_REG long REG rdi N471 ( 3, 10) [000582] ------------ t582 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t582 long N473 ( 5, 12) [000583] -c---------- t583 = * IND long REG NA /--* t581 long arg0 in rdi +--* t583 long control expr N475 ( 15, 7) [000099] --CXG------- t99 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 REG rax $376 /--* t99 ref N477 ( 19, 10) [000101] DA-XG------- * STORE_LCL_VAR ref V14 tmp3 d:2 rax REG rax N479 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 0 REG NA $40 N481 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V14 tmp3 u:2 rax REG rax $385 /--* t103 ref N483 (???,???) [000504] -c---------- t504 = * LEA(b+8) ref REG NA /--* t504 ref N485 ( 5, 4) [000377] ---X-------- t377 = * IND int REG rdx $299 /--* t377 int N487 ( 9, 7) [000465] DA-X-------- * STORE_LCL_VAR int V28 cse0 d:1 rdx REG rdx N489 ( 3, 2) [000466] -----------Z t466 = LCL_VAR int V28 cse0 u:1 rdx REG rdx $299 /--* t104 int +--* t466 int N491 ( 17, 17) [000378] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA $37c N493 ( 3, 2) [000375] -----------Z t375 = LCL_VAR ref V14 tmp3 u:2 rax REG rax $385 /--* t375 ref N495 ( 4, 3) [000383] ------------ t383 = * LEA(b+16) byref REG rdi N497 ( 1, 1) [000105] ------------ t105 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t383 byref +--* t105 ref N499 (???,???) [000490] -A-XG------- * STOREIND ref REG NA N501 ( 1, 1) [000109] -c---------- t109 = CNS_INT int 1 REG NA $41 N503 ( 3, 2) [000468] -c---------- t468 = LCL_VAR int V28 cse0 u:1 NA (last use) REG NA $3c1 /--* t109 int +--* t468 int N505 ( 8, 10) [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA $645 N507 ( 3, 2) [000385] -----------z t385 = LCL_VAR ref V14 tmp3 u:2 rax REG rax $385 /--* t385 ref N509 ( 4, 3) [000393] ------------ t393 = * LEA(b+24) byref REG rdi N511 ( 3, 2) [000110] -----------z t110 = LCL_VAR ref V10 loc4 u:2 rsi (last use) REG rsi $370 /--* t393 byref +--* t110 ref N513 (???,???) [000491] -A-XG------- * STOREIND ref REG NA N515 ( 3, 10) [000584] ------------ t584 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t584 long N517 ( 5, 12) [000585] -c---------- t585 = * IND long REG NA /--* t585 long control expr N519 ( 14, 5) [000259] --C--------- t259 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW REG rax $647 /--* t259 ref N521 ( 18, 8) [000261] DA---------- * STORE_LCL_VAR ref V20 tmp9 d:2 NA REG NA N523 ( 3, 10) [000586] ------------ t586 = CNS_INT(h) long 0xd1ffab1e ftn REG rdi /--* t586 long N525 ( 5, 12) [000587] -c---------- t587 = * IND long REG NA /--* t587 long control expr N527 ( 14, 5) [000252] H-CXG------- t252 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE REG rax $401 /--* t252 byref N529 ( 15, 9) [000254] -c---------- t254 = * LEA(b+1048) byref REG NA /--* t254 byref N531 ( 17, 11) [000255] ---XG------- t255 = * IND ref REG rsi /--* t255 ref N533 ( 21, 14) [000396] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp16 d:2 rsi REG rsi N535 ( 3, 2) [000397] ------------ t397 = LCL_VAR ref V27 tmp16 u:2 rsi (last use) REG rsi /--* t397 ref N537 (???,???) [000588] ------------ t588 = * PUTARG_REG ref REG rsi N539 ( 3, 2) [000262] -----------z t262 = LCL_VAR ref V20 tmp9 u:2 rdi REG rdi $647 /--* t262 ref N541 (???,???) [000589] ------------ t589 = * PUTARG_REG ref REG rdi N543 ( 3, 2) [000102] -----------z t102 = LCL_VAR ref V14 tmp3 u:2 rcx (last use) REG rcx $385 /--* t102 ref N545 (???,???) [000590] ------------ t590 = * PUTARG_REG ref REG rcx N547 ( 1, 4) [000256] ------------ t256 = CNS_INT int 0x7D2C REG rdx $64 /--* t256 int N549 (???,???) [000591] ------------ t591 = * PUTARG_REG int REG rdx N551 ( 3, 10) [000592] ------------ t592 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t592 long N553 ( 5, 12) [000593] -c---------- t593 = * IND long REG NA /--* t588 ref arg1 in rsi +--* t589 ref this in rdi +--* t590 ref arg3 in rcx +--* t591 int arg2 in rdx +--* t593 long control expr N555 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor REG NA $VN.Void N557 ( 1, 1) [000268] ------------ t268 = CNS_INT int 0 REG rdi $40 N559 (???,???) [000594] Dc-----N---- t594 = LCL_VAR_ADDR byref V15 tmp4 NA REG NA /--* t594 byref +--* t268 int N561 ( 5, 4) [000269] sA---------- * STORE_BLK struct (init) (Unroll) REG NA N563 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t96 ref N565 ( 5, 6) [000273] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:2->0[+0] Fseq[TypeParameter] NA REG NA N567 ( 3, 2) [000264] -----------z t264 = LCL_VAR ref V20 tmp9 u:2 rdi (last use) REG rdi $647 /--* t264 ref N569 ( 7, 7) [000277] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:3->0[+8] Fseq[DiagnosticInfo] NA REG NA N571 (???,???) [000492] ------------ IL_OFFSET void IL offset: 0xda REG NA N573 ( 3, 2) [000121] -c-----N---- t121 = LCL_VAR_ADDR byref V15 tmp4 u:4 NA (last use) REG NA /--* t121 byref N575 ( 9, 7) [000124] nc---------- t124 = * OBJ struct REG NA $507 /--* t124 struct N577 (???,???) [000595] ------------ * PUTARG_STK [+0x00] void (5 slots) (RepInstr) REG NA N579 ( 3, 2) [000095] ------------ t95 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 /--* t95 ref N581 (???,???) [000596] ------------ t596 = * PUTARG_REG ref REG rdi N583 ( 3, 10) [000401] ------------ t401 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t401 long N585 (???,???) [000597] ------------ t597 = * PUTARG_REG long REG r11 N587 ( 3, 10) [000598] ------------ t598 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t598 long N589 ( 5, 12) [000599] -c---------- t599 = * IND long REG NA /--* t596 ref this in rdi +--* t597 long arg1 in r11 +--* t599 long control expr N591 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add REG NA $VN.Void ------------ BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} N595 (???,???) [000493] ------------ IL_OFFSET void IL offset: 0xdf REG NA N597 ( 1, 1) [000092] ------------ t92 = CNS_INT int 0 REG rax $40 /--* t92 int N599 ( 5, 4) [000094] DA---------- * STORE_LCL_VAR int V07 loc1 d:12 NA REG NA ------------ BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} N603 (???,???) [000494] ------------ IL_OFFSET void IL offset: 0x48 REG NA N605 ( 1, 1) [000155] ------------ t155 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t155 ref N607 (???,???) [000600] ------------ t600 = * PUTARG_REG ref REG rdi N609 ( 1, 1) [000156] ------------ t156 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t156 ref N611 (???,???) [000601] ------------ t601 = * PUTARG_REG ref REG rsi N613 ( 3, 2) [000157] ------------ t157 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 /--* t157 ref N615 (???,???) [000602] ------------ t602 = * PUTARG_REG ref REG rdx N617 ( 3, 10) [000603] ------------ t603 = CNS_INT(h) long 0xd1ffab1e ftn REG rcx /--* t603 long N619 ( 5, 12) [000604] -c---------- t604 = * IND long REG NA /--* t600 ref arg0 in rdi +--* t601 ref arg1 in rsi +--* t602 ref arg2 in rdx +--* t604 long control expr N621 ( 19, 12) [000158] --CXG------- t158 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint REG rax $209 N623 ( 1, 1) [000160] -c---------- t160 = CNS_INT bool 0 REG NA $40 /--* t158 bool +--* t160 bool N625 ( 22, 16) [000161] J--XG--N-U-- * NE void REG NA $289 N627 ( 24, 18) [000162] ---XG------- * JTRUE void REG NA ------------ BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} N631 (???,???) [000495] ------------ IL_OFFSET void IL offset: 0x53 REG NA N633 ( 1, 1) [000163] ------------ t163 = CNS_INT int 0 REG rax $40 /--* t163 int N635 ( 5, 4) [000165] DA---------- * STORE_LCL_VAR int V07 loc1 d:5 rax REG rax N001 ( 4, 3) [000629] -----------Z t629 = LCL_VAR bool V07 loc1 rax REG rax ------------ BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} N639 (???,???) [000496] ------------ IL_OFFSET void IL offset: 0x8 REG NA N641 ( 1, 1) [000195] -c---------- t195 = CNS_INT int 1 REG NA $41 /--* t195 int N643 ( 5, 4) [000197] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 rax REG rax ------------ BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} N647 (???,???) [000497] ------------ IL_OFFSET void IL offset: 0x19 REG NA N649 ( 3, 2) [000166] ------------ t166 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 N651 ( 1, 1) [000167] -c---------- t167 = CNS_INT ref null REG NA $VN.Null /--* t166 ref +--* t167 ref N653 ( 5, 4) [000168] J------N---- * EQ void REG NA $284 N655 ( 7, 6) [000169] ------------ * JTRUE void REG NA ------------ BB26 [01D..03E), preds={BB25} succs={BB27} N659 (???,???) [000498] ------------ IL_OFFSET void IL offset: 0x1d REG NA N661 ( 1, 1) [000176] ------------ t176 = CNS_INT long 1 REG rdi $2c0 /--* t176 long N663 (???,???) [000605] ------------ t605 = * PUTARG_REG long REG rdi N665 ( 3, 10) [000606] ------------ t606 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t606 long N667 ( 5, 12) [000607] -c---------- t607 = * IND long REG NA /--* t605 long arg0 in rdi +--* t607 long control expr N669 ( 15, 7) [000177] --CXG------- t177 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 REG rax $342 /--* t177 ref N671 ( 19, 10) [000179] DA-XG------- * STORE_LCL_VAR ref V16 tmp5 d:2 rax REG rax N673 ( 1, 1) [000182] -c---------- t182 = CNS_INT int 0 REG NA $40 N675 ( 3, 2) [000181] ------------ t181 = LCL_VAR ref V16 tmp5 u:2 rax REG rax $380 /--* t181 ref N677 (???,???) [000507] -c---------- t507 = * LEA(b+8) ref REG NA /--* t507 ref N679 ( 5, 4) [000291] -c-X-------- t291 = * IND int REG NA $285 /--* t182 int +--* t291 int N681 ( 10, 12) [000292] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA $348 N683 ( 3, 2) [000289] -----------Z t289 = LCL_VAR ref V16 tmp5 u:2 rax REG rax $380 /--* t289 ref N685 ( 4, 3) [000297] ------------ t297 = * LEA(b+16) byref REG rdi N687 ( 1, 1) [000183] ------------ t183 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t297 byref +--* t183 ref N689 (???,???) [000499] -A-XG------- * STOREIND ref REG NA N691 ( 3, 10) [000608] ------------ t608 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t608 long N693 ( 5, 12) [000609] -c---------- t609 = * IND long REG NA /--* t609 long control expr N695 ( 14, 5) [000214] --C--------- t214 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW REG rax $34c /--* t214 ref N697 ( 18, 8) [000216] DA---------- * STORE_LCL_VAR ref V18 tmp7 d:2 NA REG NA N699 ( 3, 10) [000610] ------------ t610 = CNS_INT(h) long 0xd1ffab1e ftn REG rdi /--* t610 long N701 ( 5, 12) [000611] -c---------- t611 = * IND long REG NA /--* t611 long control expr N703 ( 14, 5) [000207] H-CXG------- t207 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE REG rax $401 /--* t207 byref N705 ( 15, 9) [000209] -c---------- t209 = * LEA(b+1048) byref REG NA /--* t209 byref N707 ( 17, 11) [000210] ---XG------- t210 = * IND ref REG rsi /--* t210 ref N709 ( 21, 14) [000300] DA-XG-----L- * STORE_LCL_VAR ref V24 tmp13 d:2 rsi REG rsi N711 ( 3, 2) [000301] ------------ t301 = LCL_VAR ref V24 tmp13 u:2 rsi (last use) REG rsi /--* t301 ref N713 (???,???) [000612] ------------ t612 = * PUTARG_REG ref REG rsi N715 ( 3, 2) [000217] -----------z t217 = LCL_VAR ref V18 tmp7 u:2 rdi REG rdi $34c /--* t217 ref N717 (???,???) [000613] ------------ t613 = * PUTARG_REG ref REG rdi N719 ( 3, 2) [000180] -----------z t180 = LCL_VAR ref V16 tmp5 u:2 rcx (last use) REG rcx $380 /--* t180 ref N721 (???,???) [000614] ------------ t614 = * PUTARG_REG ref REG rcx N723 ( 1, 4) [000211] ------------ t211 = CNS_INT int 0x7AA4 REG rdx $49 /--* t211 int N725 (???,???) [000615] ------------ t615 = * PUTARG_REG int REG rdx N727 ( 3, 10) [000616] ------------ t616 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t616 long N729 ( 5, 12) [000617] -c---------- t617 = * IND long REG NA /--* t612 ref arg1 in rsi +--* t613 ref this in rdi +--* t614 ref arg3 in rcx +--* t615 int arg2 in rdx +--* t617 long control expr N731 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor REG NA $VN.Void N733 ( 3, 3) [000189] ------------ t189 = LCL_VAR_ADDR byref V17 tmp6 rdi REG rdi $481 /--* t189 byref N735 (???,???) [000618] ------------ t618 = * PUTARG_REG byref REG rdi N737 ( 1, 1) [000174] ------------ t174 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t174 ref N739 (???,???) [000619] ------------ t619 = * PUTARG_REG ref REG rsi N741 ( 3, 2) [000219] -----------z t219 = LCL_VAR ref V18 tmp7 u:2 rdx (last use) REG rdx $34c /--* t219 ref N743 (???,???) [000620] ------------ t620 = * PUTARG_REG ref REG rdx N745 ( 3, 10) [000621] ------------ t621 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t621 long N747 ( 5, 12) [000622] -c---------- t622 = * IND long REG NA /--* t618 byref this in rdi +--* t619 ref arg1 in rsi +--* t620 ref arg2 in rdx +--* t622 long control expr N749 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor REG NA $VN.Void N751 (???,???) [000500] ------------ IL_OFFSET void IL offset: 0x39 REG NA N753 ( 3, 2) [000191] -c-----N---- t191 = LCL_VAR_ADDR byref V17 tmp6 NA REG NA /--* t191 byref N755 ( 9, 7) [000194] nc--G------- t194 = * OBJ struct REG NA /--* t194 struct N757 (???,???) [000623] ----G------- * PUTARG_STK [+0x00] void (5 slots) (RepInstr) REG NA N759 ( 3, 2) [000173] ------------ t173 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 /--* t173 ref N761 (???,???) [000624] ------------ t624 = * PUTARG_REG ref REG rdi N763 ( 3, 10) [000308] ------------ t308 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 /--* t308 long N765 (???,???) [000625] ------------ t625 = * PUTARG_REG long REG r11 N767 ( 3, 10) [000626] ------------ t626 = CNS_INT(h) long 0xd1ffab1e ftn REG rax /--* t626 long N769 ( 5, 12) [000627] -c---------- t627 = * IND long REG NA /--* t624 ref this in rdi +--* t625 long arg1 in r11 +--* t627 long control expr N771 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add REG NA $VN.Void ------------ BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} N775 (???,???) [000501] ------------ IL_OFFSET void IL offset: 0x3e REG NA N777 ( 1, 1) [000170] ------------ t170 = CNS_INT int 0 REG rax $40 /--* t170 int N779 ( 5, 4) [000172] DA---------- * STORE_LCL_VAR int V07 loc1 d:3 rax REG rax N001 ( 4, 3) [000630] -----------Z t630 = LCL_VAR bool V07 loc1 rax REG rax ------------ BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} N783 (???,???) [000502] ------------ IL_OFFSET void IL offset: 0x80 REG NA N785 ( 1, 1) [000140] ------------ t140 = CNS_INT int 0 REG rax $40 /--* t140 int N787 ( 5, 4) [000142] DA---------- * STORE_LCL_VAR int V07 loc1 d:9 rax REG rax N001 ( 4, 3) [000631] -----------Z t631 = LCL_VAR bool V07 loc1 rax REG rax ------------ BB29 [???..???) (throw), preds={} succs={} N791 ( 14, 5) [000505] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL REG NA ------------------------------------------------------------------------------------------------------------------- Final allocation ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 V2 Parm Alloc rbx | | | |V2 a| | | | | | | | | | 0.#1 V3 Parm Alloc r14 | | | |V2 a| | | | | | | |V3 a| | 0.#2 V5 Parm Alloc r15 | | | |V2 a| | | | | | | |V3 a|V5 a| 0.#3 V1 Parm Alloc r12 | | | |V2 a| | | | | |V1 a| |V3 a|V5 a| 0.#4 V4 Parm Alloc r13 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 0.#5 V0 Parm NoReg | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 1.#6 BB1 PredBB0 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 5.#7 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 5.#8 V3 Use Copy rdi | | | |V2 a| |V3 a| | | |V1 a|V4 a|V3 a|V5 a| 6.#9 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 6.#10 I19 Def Alloc rdi | | | |V2 a| |I19 a| | | |V1 a|V4 a|V3 a|V5 a| 8.#11 r11 Fixd Keep r11 | | | |V2 a| |I19 a| | | |V1 a|V4 a|V3 a|V5 a| 8.#12 C20 Def Alloc r11 | | | |V2 a| |I19 a| | |C20 a|V1 a|V4 a|V3 a|V5 a| 9.#13 r11 Fixd Keep r11 | | | |V2 a| |I19 a| | |C20 a|V1 a|V4 a|V3 a|V5 a| 9.#14 C20 Use * Keep r11 | | | |V2 a| |I19 a| | |C20 i|V1 a|V4 a|V3 a|V5 a| 10.#15 r11 Fixd Keep r11 | | | |V2 a| |I19 a| | | |V1 a|V4 a|V3 a|V5 a| 10.#16 I21 Def Alloc r11 | | | |V2 a| |I19 a| | |I21 a|V1 a|V4 a|V3 a|V5 a| 12.#17 C22 Def Alloc rsi | | | |V2 a|C22 a|I19 a| | |I21 a|V1 a|V4 a|V3 a|V5 a| 15.#18 rdi Fixd Keep rdi | | | |V2 a|C22 a|I19 a| | |I21 a|V1 a|V4 a|V3 a|V5 a| 15.#19 I19 Use * Keep rdi | | | |V2 a|C22 a|I19 i| | |I21 a|V1 a|V4 a|V3 a|V5 a| 15.#20 r11 Fixd Keep r11 | | | |V2 a|C22 a| | | |I21 a|V1 a|V4 a|V3 a|V5 a| 15.#21 I21 Use * Keep r11 | | | |V2 a|C22 a| | | |I21 i|V1 a|V4 a|V3 a|V5 a| 15.#22 C22 Use * Keep rsi | | | |V2 a|C22 i| | | | |V1 a|V4 a|V3 a|V5 a| 16.#23 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#24 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#25 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#26 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#27 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#28 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#29 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#30 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#31 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#32 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 16.#33 I23 Def Alloc rax |I23 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 19.#34 I23 Use * Keep rax |I23 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 23.#35 BB2 PredBB1 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 30.#36 V7 Def Alloc rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Spill rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 33.#37 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 33.#38 V3 Use Copy rdi | | | |V2 a| |V3 a| | | |V1 a|V4 a|V3 a|V5 a| 34.#39 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 34.#40 I24 Def Alloc rdi | | | |V2 a| |I24 a| | | |V1 a|V4 a|V3 a|V5 a| 36.#41 r11 Fixd Keep r11 | | | |V2 a| |I24 a| | | |V1 a|V4 a|V3 a|V5 a| 36.#42 C25 Def Alloc r11 | | | |V2 a| |I24 a| | |C25 a|V1 a|V4 a|V3 a|V5 a| 37.#43 r11 Fixd Keep r11 | | | |V2 a| |I24 a| | |C25 a|V1 a|V4 a|V3 a|V5 a| 37.#44 C25 Use * Keep r11 | | | |V2 a| |I24 a| | |C25 i|V1 a|V4 a|V3 a|V5 a| 38.#45 r11 Fixd Keep r11 | | | |V2 a| |I24 a| | | |V1 a|V4 a|V3 a|V5 a| 38.#46 I26 Def Alloc r11 | | | |V2 a| |I24 a| | |I26 a|V1 a|V4 a|V3 a|V5 a| 40.#47 C27 Def Alloc rsi | | | |V2 a|C27 a|I24 a| | |I26 a|V1 a|V4 a|V3 a|V5 a| 43.#48 rdi Fixd Keep rdi | | | |V2 a|C27 a|I24 a| | |I26 a|V1 a|V4 a|V3 a|V5 a| 43.#49 I24 Use * Keep rdi | | | |V2 a|C27 a|I24 i| | |I26 a|V1 a|V4 a|V3 a|V5 a| 43.#50 r11 Fixd Keep r11 | | | |V2 a|C27 a| | | |I26 a|V1 a|V4 a|V3 a|V5 a| 43.#51 I26 Use * Keep r11 | | | |V2 a|C27 a| | | |I26 i|V1 a|V4 a|V3 a|V5 a| 43.#52 C27 Use * Keep rsi | | | |V2 a|C27 i| | | | |V1 a|V4 a|V3 a|V5 a| 44.#53 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#54 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#55 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#56 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#57 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#58 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#59 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#60 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#61 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#62 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 44.#63 I28 Def Alloc rax |I28 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 45.#64 I28 Use * Keep rax |I28 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 46.#65 I29 Def Alloc rdi | | | |V2 a| |I29 a| | | |V1 a|V4 a|V3 a|V5 a| 47.#66 rdi Fixd Keep rdi | | | |V2 a| |I29 a| | | |V1 a|V4 a|V3 a|V5 a| 47.#67 I29 Use * Keep rdi | | | |V2 a| |I29 i| | | |V1 a|V4 a|V3 a|V5 a| 48.#68 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 48.#69 I30 Def Alloc rdi | | | |V2 a| |I30 a| | | |V1 a|V4 a|V3 a|V5 a| 50.#70 C31 Def Alloc rax |C31 a| | |V2 a| |I30 a| | | |V1 a|V4 a|V3 a|V5 a| 53.#71 rdi Fixd Keep rdi |C31 a| | |V2 a| |I30 a| | | |V1 a|V4 a|V3 a|V5 a| 53.#72 I30 Use * Keep rdi |C31 a| | |V2 a| |I30 i| | | |V1 a|V4 a|V3 a|V5 a| 53.#73 C31 Use * Keep rax |C31 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#74 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#75 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#76 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#77 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#78 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#79 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#80 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#81 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#82 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#83 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 54.#84 I32 Def Alloc rax |I32 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 57.#85 I32 Use * Keep rax |I32 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 61.#86 BB3 PredBB2 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 67.#87 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 67.#88 V2 Use Copy rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 68.#89 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 68.#90 I33 Def Alloc rdi | | | |V2 a| |I33 a| | | |V1 a|V4 a|V3 a|V5 a| 70.#91 r11 Fixd Keep r11 | | | |V2 a| |I33 a| | | |V1 a|V4 a|V3 a|V5 a| 70.#92 C34 Def Alloc r11 | | | |V2 a| |I33 a| | |C34 a|V1 a|V4 a|V3 a|V5 a| 71.#93 r11 Fixd Keep r11 | | | |V2 a| |I33 a| | |C34 a|V1 a|V4 a|V3 a|V5 a| 71.#94 C34 Use * Keep r11 | | | |V2 a| |I33 a| | |C34 i|V1 a|V4 a|V3 a|V5 a| 72.#95 r11 Fixd Keep r11 | | | |V2 a| |I33 a| | | |V1 a|V4 a|V3 a|V5 a| 72.#96 I35 Def Alloc r11 | | | |V2 a| |I33 a| | |I35 a|V1 a|V4 a|V3 a|V5 a| 74.#97 C36 Def Alloc rax |C36 a| | |V2 a| |I33 a| | |I35 a|V1 a|V4 a|V3 a|V5 a| 77.#98 rdi Fixd Keep rdi |C36 a| | |V2 a| |I33 a| | |I35 a|V1 a|V4 a|V3 a|V5 a| 77.#99 I33 Use * Keep rdi |C36 a| | |V2 a| |I33 i| | |I35 a|V1 a|V4 a|V3 a|V5 a| 77.#100 r11 Fixd Keep r11 |C36 a| | |V2 a| | | | |I35 a|V1 a|V4 a|V3 a|V5 a| 77.#101 I35 Use * Keep r11 |C36 a| | |V2 a| | | | |I35 i|V1 a|V4 a|V3 a|V5 a| 77.#102 C36 Use * Keep rax |C36 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#103 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#104 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#105 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#106 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#107 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#108 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#109 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#110 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#111 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#112 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 78.#113 I37 Def Alloc rax |I37 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 81.#114 I37 Use * Keep rax |I37 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 85.#115 BB4 PredBB3 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 91.#116 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 91.#117 V2 Use Copy rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 92.#118 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 92.#119 I38 Def Alloc rdi | | | |V2 a| |I38 a| | | |V1 a|V4 a|V3 a|V5 a| 94.#120 r11 Fixd Keep r11 | | | |V2 a| |I38 a| | | |V1 a|V4 a|V3 a|V5 a| 94.#121 C39 Def Alloc r11 | | | |V2 a| |I38 a| | |C39 a|V1 a|V4 a|V3 a|V5 a| 95.#122 r11 Fixd Keep r11 | | | |V2 a| |I38 a| | |C39 a|V1 a|V4 a|V3 a|V5 a| 95.#123 C39 Use * Keep r11 | | | |V2 a| |I38 a| | |C39 i|V1 a|V4 a|V3 a|V5 a| 96.#124 r11 Fixd Keep r11 | | | |V2 a| |I38 a| | | |V1 a|V4 a|V3 a|V5 a| 96.#125 I40 Def Alloc r11 | | | |V2 a| |I38 a| | |I40 a|V1 a|V4 a|V3 a|V5 a| 98.#126 C41 Def Alloc rax |C41 a| | |V2 a| |I38 a| | |I40 a|V1 a|V4 a|V3 a|V5 a| 101.#127 rdi Fixd Keep rdi |C41 a| | |V2 a| |I38 a| | |I40 a|V1 a|V4 a|V3 a|V5 a| 101.#128 I38 Use * Keep rdi |C41 a| | |V2 a| |I38 i| | |I40 a|V1 a|V4 a|V3 a|V5 a| 101.#129 r11 Fixd Keep r11 |C41 a| | |V2 a| | | | |I40 a|V1 a|V4 a|V3 a|V5 a| 101.#130 I40 Use * Keep r11 |C41 a| | |V2 a| | | | |I40 i|V1 a|V4 a|V3 a|V5 a| 101.#131 C41 Use * Keep rax |C41 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#132 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#133 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#134 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#135 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#136 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#137 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#138 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#139 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#140 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#141 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 102.#142 I42 Def Alloc rax |I42 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 105.#143 I42 Use * Keep rax |I42 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 109.#144 BB5 PredBB4 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 115.#145 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 115.#146 V2 Use Copy rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 116.#147 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 116.#148 I43 Def Alloc rdi | | | |V2 a| |I43 a| | | |V1 a|V4 a|V3 a|V5 a| 118.#149 r11 Fixd Keep r11 | | | |V2 a| |I43 a| | | |V1 a|V4 a|V3 a|V5 a| 118.#150 C44 Def Alloc r11 | | | |V2 a| |I43 a| | |C44 a|V1 a|V4 a|V3 a|V5 a| 119.#151 r11 Fixd Keep r11 | | | |V2 a| |I43 a| | |C44 a|V1 a|V4 a|V3 a|V5 a| 119.#152 C44 Use * Keep r11 | | | |V2 a| |I43 a| | |C44 i|V1 a|V4 a|V3 a|V5 a| 120.#153 r11 Fixd Keep r11 | | | |V2 a| |I43 a| | | |V1 a|V4 a|V3 a|V5 a| 120.#154 I45 Def Alloc r11 | | | |V2 a| |I43 a| | |I45 a|V1 a|V4 a|V3 a|V5 a| 122.#155 C46 Def Alloc rax |C46 a| | |V2 a| |I43 a| | |I45 a|V1 a|V4 a|V3 a|V5 a| 125.#156 rdi Fixd Keep rdi |C46 a| | |V2 a| |I43 a| | |I45 a|V1 a|V4 a|V3 a|V5 a| 125.#157 I43 Use * Keep rdi |C46 a| | |V2 a| |I43 i| | |I45 a|V1 a|V4 a|V3 a|V5 a| 125.#158 r11 Fixd Keep r11 |C46 a| | |V2 a| | | | |I45 a|V1 a|V4 a|V3 a|V5 a| 125.#159 I45 Use * Keep r11 |C46 a| | |V2 a| | | | |I45 i|V1 a|V4 a|V3 a|V5 a| 125.#160 C46 Use * Keep rax |C46 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#161 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#162 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#163 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#164 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#165 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#166 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#167 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#168 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#169 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#170 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 126.#171 I47 Def Alloc rax |I47 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 129.#172 I47 Use * Keep rax |I47 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 133.#173 BB6 PredBB5 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 137.#174 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 137.#175 V2 Use Copy rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 138.#176 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 138.#177 I48 Def Alloc rdi | | | |V2 a| |I48 a| | | |V1 a|V4 a|V3 a|V5 a| 141.#178 rsi Fixd Keep rsi | | | |V2 a| |I48 a| | | |V1 a|V4 a|V3 a|V5 a| 141.#179 V5 Use Copy rsi | | | |V2 a|V5 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 142.#180 rsi Fixd Keep rsi | | | |V2 a| |I48 a| | | |V1 a|V4 a|V3 a|V5 a| 142.#181 I49 Def Alloc rsi | | | |V2 a|I49 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 144.#182 C50 Def Alloc rax |C50 a| | |V2 a|I49 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 147.#183 rdi Fixd Keep rdi |C50 a| | |V2 a|I49 a|I48 a| | | |V1 a|V4 a|V3 a|V5 a| 147.#184 I48 Use * Keep rdi |C50 a| | |V2 a|I49 a|I48 i| | | |V1 a|V4 a|V3 a|V5 a| 147.#185 rsi Fixd Keep rsi |C50 a| | |V2 a|I49 a| | | | |V1 a|V4 a|V3 a|V5 a| 147.#186 I49 Use * Keep rsi |C50 a| | |V2 a|I49 i| | | | |V1 a|V4 a|V3 a|V5 a| 147.#187 C50 Use * Keep rax |C50 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#188 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#189 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#190 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#191 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#192 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#193 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#194 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#195 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#196 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#197 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 148.#198 I51 Def Alloc rax |I51 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 149.#199 I51 Use * Keep rax |I51 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 154.#200 C52 Def Alloc rsi | | | |V2 a|C52 a| | | | |V1 a|V4 a|V3 a|V5 a| 155.#201 C52 Use * Keep rsi | | | |V2 a|C52 i| | | | |V1 a|V4 a|V3 a|V5 a| 156.#202 I53 Def Alloc rsi | | | |V2 a|I53 a| | | | |V1 a|V4 a|V3 a|V5 a| 157.#203 rsi Fixd Keep rsi | | | |V2 a|I53 a| | | | |V1 a|V4 a|V3 a|V5 a| 157.#204 I53 Use * Keep rsi | | | |V2 a|I53 i| | | | |V1 a|V4 a|V3 a|V5 a| 158.#205 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 158.#206 I54 Def Alloc rsi | | | |V2 a|I54 a| | | | |V1 a|V4 a|V3 a|V5 a| 160.#207 I55 Def Alloc rdi | | | |V2 a|I54 a|I55 a| | | |V1 a|V4 a|V3 a|V5 a| 161.#208 rdi Fixd Keep rdi | | | |V2 a|I54 a|I55 a| | | |V1 a|V4 a|V3 a|V5 a| 161.#209 I55 Use * Keep rdi | | | |V2 a|I54 a|I55 i| | | |V1 a|V4 a|V3 a|V5 a| 162.#210 rdi Fixd Keep rdi | | | |V2 a|I54 a| | | | |V1 a|V4 a|V3 a|V5 a| 162.#211 I56 Def Alloc rdi | | | |V2 a|I54 a|I56 a| | | |V1 a|V4 a|V3 a|V5 a| 164.#212 C57 Def Alloc rax |C57 a| | |V2 a|I54 a|I56 a| | | |V1 a|V4 a|V3 a|V5 a| 167.#213 rsi Fixd Keep rsi |C57 a| | |V2 a|I54 a|I56 a| | | |V1 a|V4 a|V3 a|V5 a| 167.#214 I54 Use * Keep rsi |C57 a| | |V2 a|I54 i|I56 a| | | |V1 a|V4 a|V3 a|V5 a| 167.#215 rdi Fixd Keep rdi |C57 a| | |V2 a| |I56 a| | | |V1 a|V4 a|V3 a|V5 a| 167.#216 I56 Use * Keep rdi |C57 a| | |V2 a| |I56 i| | | |V1 a|V4 a|V3 a|V5 a| 167.#217 C57 Use * Keep rax |C57 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#218 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#219 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#220 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#221 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#222 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#223 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#224 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#225 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#226 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#227 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#228 I58 Def Alloc rax |I58 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#229 rdx Fixd Keep rdx |I58 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 168.#230 I59 Def Alloc rdx |I58 a| |I59 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 169.#231 I58 Use * Keep rax |I58 i| |I59 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 169.#232 I59 Use * Keep rdx | | |I59 i|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 172.#233 I60 Def Alloc rsi | | | |V2 a|I60 a| | | | |V1 a|V4 a|V3 a|V5 a| 173.#234 I60 Use * Keep rsi | | | |V2 a|I60 i| | | | |V1 a|V4 a|V3 a|V5 a| 174.#235 V25 Def Alloc rsi | | | |V2 a|V25 a| | | | |V1 a|V4 a|V3 a|V5 a| 177.#236 V25 Use Keep rsi | | | |V2 a|V25 a| | | | |V1 a|V4 a|V3 a|V5 a| 178.#237 I61 Def Alloc rdi | | | |V2 a|V25 a|I61 a| | | |V1 a|V4 a|V3 a|V5 a| 179.#238 I61 Use * Keep rdi | | | |V2 a|V25 a|I61 i| | | |V1 a|V4 a|V3 a|V5 a| 185.#239 V25 Use * Keep rsi | | | |V2 a|V25 i| | | | |V1 a|V4 a|V3 a|V5 a| 186.#240 I62 Def Alloc rsi | | | |V2 a|I62 a| | | | |V1 a|V4 a|V3 a|V5 a| 187.#241 I62 Use * Keep rsi | | | |V2 a|I62 i| | | | |V1 a|V4 a|V3 a|V5 a| 192.#242 C63 Def Alloc rsi | | | |V2 a|C63 a| | | | |V1 a|V4 a|V3 a|V5 a| 193.#243 C63 Use * Keep rsi | | | |V2 a|C63 i| | | | |V1 a|V4 a|V3 a|V5 a| 194.#244 I64 Def Alloc rsi | | | |V2 a|I64 a| | | | |V1 a|V4 a|V3 a|V5 a| 195.#245 rsi Fixd Keep rsi | | | |V2 a|I64 a| | | | |V1 a|V4 a|V3 a|V5 a| 195.#246 I64 Use * Keep rsi | | | |V2 a|I64 i| | | | |V1 a|V4 a|V3 a|V5 a| 196.#247 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 196.#248 I65 Def Alloc rsi | | | |V2 a|I65 a| | | | |V1 a|V4 a|V3 a|V5 a| 198.#249 I66 Def Alloc rdi | | | |V2 a|I65 a|I66 a| | | |V1 a|V4 a|V3 a|V5 a| 199.#250 rdi Fixd Keep rdi | | | |V2 a|I65 a|I66 a| | | |V1 a|V4 a|V3 a|V5 a| 199.#251 I66 Use * Keep rdi | | | |V2 a|I65 a|I66 i| | | |V1 a|V4 a|V3 a|V5 a| 200.#252 rdi Fixd Keep rdi | | | |V2 a|I65 a| | | | |V1 a|V4 a|V3 a|V5 a| 200.#253 I67 Def Alloc rdi | | | |V2 a|I65 a|I67 a| | | |V1 a|V4 a|V3 a|V5 a| 202.#254 C68 Def Alloc rax |C68 a| | |V2 a|I65 a|I67 a| | | |V1 a|V4 a|V3 a|V5 a| 205.#255 rsi Fixd Keep rsi |C68 a| | |V2 a|I65 a|I67 a| | | |V1 a|V4 a|V3 a|V5 a| 205.#256 I65 Use * Keep rsi |C68 a| | |V2 a|I65 i|I67 a| | | |V1 a|V4 a|V3 a|V5 a| 205.#257 rdi Fixd Keep rdi |C68 a| | |V2 a| |I67 a| | | |V1 a|V4 a|V3 a|V5 a| 205.#258 I67 Use * Keep rdi |C68 a| | |V2 a| |I67 i| | | |V1 a|V4 a|V3 a|V5 a| 205.#259 C68 Use * Keep rax |C68 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#260 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#261 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#262 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#263 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#264 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#265 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#266 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#267 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#268 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#269 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 206.#270 I69 Def Alloc rax |I69 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 209.#271 I69 Use * Keep rax |I69 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 213.#272 BB7 PredBB6 | | | | | | | | | | | | | | 219.#273 V7 Use * ReLod r13 | | | | | | | | | | |V7 a| | | Keep r13 | | | | | | | | | | |V7 i| | | 220.#274 V6 Def Alloc rax |V6 a| | | | | | | | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 221.#275 BB8 PredBB7 |V6 a| | | | | | | | | | | | | 227.#276 rax Fixd Keep rax |V6 a| | | | | | | | | | | | | 227.#277 V6 Use * Keep rax |V6 i| | | | | | | | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 229.#278 BB9 PredBB6 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 234.#279 C70 Def Alloc rsi | | | |V2 a|C70 a| | | | |V1 a|V4 a|V3 a|V5 a| 235.#280 C70 Use * Keep rsi | | | |V2 a|C70 i| | | | |V1 a|V4 a|V3 a|V5 a| 236.#281 I71 Def Alloc rsi | | | |V2 a|I71 a| | | | |V1 a|V4 a|V3 a|V5 a| 237.#282 rsi Fixd Keep rsi | | | |V2 a|I71 a| | | | |V1 a|V4 a|V3 a|V5 a| 237.#283 I71 Use * Keep rsi | | | |V2 a|I71 i| | | | |V1 a|V4 a|V3 a|V5 a| 238.#284 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 238.#285 I72 Def Alloc rsi | | | |V2 a|I72 a| | | | |V1 a|V4 a|V3 a|V5 a| 240.#286 I73 Def Alloc rdi | | | |V2 a|I72 a|I73 a| | | |V1 a|V4 a|V3 a|V5 a| 241.#287 rdi Fixd Keep rdi | | | |V2 a|I72 a|I73 a| | | |V1 a|V4 a|V3 a|V5 a| 241.#288 I73 Use * Keep rdi | | | |V2 a|I72 a|I73 i| | | |V1 a|V4 a|V3 a|V5 a| 242.#289 rdi Fixd Keep rdi | | | |V2 a|I72 a| | | | |V1 a|V4 a|V3 a|V5 a| 242.#290 I74 Def Alloc rdi | | | |V2 a|I72 a|I74 a| | | |V1 a|V4 a|V3 a|V5 a| 244.#291 C75 Def Alloc rax |C75 a| | |V2 a|I72 a|I74 a| | | |V1 a|V4 a|V3 a|V5 a| 247.#292 rsi Fixd Keep rsi |C75 a| | |V2 a|I72 a|I74 a| | | |V1 a|V4 a|V3 a|V5 a| 247.#293 I72 Use * Keep rsi |C75 a| | |V2 a|I72 i|I74 a| | | |V1 a|V4 a|V3 a|V5 a| 247.#294 rdi Fixd Keep rdi |C75 a| | |V2 a| |I74 a| | | |V1 a|V4 a|V3 a|V5 a| 247.#295 I74 Use * Keep rdi |C75 a| | |V2 a| |I74 i| | | |V1 a|V4 a|V3 a|V5 a| 247.#296 C75 Use * Keep rax |C75 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#297 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#298 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#299 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#300 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#301 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#302 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#303 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#304 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#305 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#306 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 248.#307 I76 Def Alloc rax |I76 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 249.#308 I76 Use * Keep rax |I76 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 250.#309 V26 Def Alloc rdi | | | |V2 a| |V26 a| | | |V1 a|V4 a|V3 a|V5 a| 253.#310 rdi Fixd Keep rdi | | | |V2 a| |V26 a| | | |V1 a|V4 a|V3 a|V5 a| 253.#311 V26 Use * Keep rdi | | | |V2 a| |V26 i| | | |V1 a|V4 a|V3 a|V5 a| 254.#312 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 254.#313 I77 Def Alloc rdi | | | |V2 a| |I77 a| | | |V1 a|V4 a|V3 a|V5 a| 257.#314 rsi Fixd Keep rsi | | | |V2 a| |I77 a| | | |V1 a|V4 a|V3 a|V5 a| 257.#315 V1 Use Copy rsi | | | |V2 a|V1 a|I77 a| | | |V1 a|V4 a|V3 a|V5 a| 258.#316 rsi Fixd Keep rsi | | | |V2 a| |I77 a| | | |V1 a|V4 a|V3 a|V5 a| 258.#317 I78 Def Alloc rsi | | | |V2 a|I78 a|I77 a| | | |V1 a|V4 a|V3 a|V5 a| 260.#318 r11 Fixd Keep r11 | | | |V2 a|I78 a|I77 a| | | |V1 a|V4 a|V3 a|V5 a| 260.#319 C79 Def Alloc r11 | | | |V2 a|I78 a|I77 a| | |C79 a|V1 a|V4 a|V3 a|V5 a| 261.#320 r11 Fixd Keep r11 | | | |V2 a|I78 a|I77 a| | |C79 a|V1 a|V4 a|V3 a|V5 a| 261.#321 C79 Use * Keep r11 | | | |V2 a|I78 a|I77 a| | |C79 i|V1 a|V4 a|V3 a|V5 a| 262.#322 r11 Fixd Keep r11 | | | |V2 a|I78 a|I77 a| | | |V1 a|V4 a|V3 a|V5 a| 262.#323 I80 Def Alloc r11 | | | |V2 a|I78 a|I77 a| | |I80 a|V1 a|V4 a|V3 a|V5 a| 264.#324 C81 Def Alloc rax |C81 a| | |V2 a|I78 a|I77 a| | |I80 a|V1 a|V4 a|V3 a|V5 a| 267.#325 rdi Fixd Keep rdi |C81 a| | |V2 a|I78 a|I77 a| | |I80 a|V1 a|V4 a|V3 a|V5 a| 267.#326 I77 Use * Keep rdi |C81 a| | |V2 a|I78 a|I77 i| | |I80 a|V1 a|V4 a|V3 a|V5 a| 267.#327 rsi Fixd Keep rsi |C81 a| | |V2 a|I78 a| | | |I80 a|V1 a|V4 a|V3 a|V5 a| 267.#328 I78 Use * Keep rsi |C81 a| | |V2 a|I78 i| | | |I80 a|V1 a|V4 a|V3 a|V5 a| 267.#329 r11 Fixd Keep r11 |C81 a| | |V2 a| | | | |I80 a|V1 a|V4 a|V3 a|V5 a| 267.#330 I80 Use * Keep r11 |C81 a| | |V2 a| | | | |I80 i|V1 a|V4 a|V3 a|V5 a| 267.#331 C81 Use * Keep rax |C81 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#332 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#333 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#334 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#335 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#336 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#337 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#338 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#339 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#340 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#341 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#342 I82 Def Alloc rax |I82 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#343 rdx Fixd Keep rdx |I82 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 268.#344 I83 Def Alloc rdx |I82 a| |I83 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 269.#345 I82 Use * Keep rax |I82 i| |I83 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 269.#346 I83 Use * Keep rdx | | |I83 i|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 272.#347 I84 Def Alloc rax |I84 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 273.#348 I84 Use * Keep rax |I84 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 274.#349 V10 Def Alloc rax |V10 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 279.#350 rdi Fixd Keep rdi |V10 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 279.#351 V10 Use Copy rdi |V10 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Spill rax |V10 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 280.#352 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 280.#353 I85 Def Alloc rdi | | | |V2 a| |I85 a| | | |V1 a|V4 a|V3 a|V5 a| 282.#354 r11 Fixd Keep r11 | | | |V2 a| |I85 a| | | |V1 a|V4 a|V3 a|V5 a| 282.#355 C86 Def Alloc r11 | | | |V2 a| |I85 a| | |C86 a|V1 a|V4 a|V3 a|V5 a| 283.#356 r11 Fixd Keep r11 | | | |V2 a| |I85 a| | |C86 a|V1 a|V4 a|V3 a|V5 a| 283.#357 C86 Use * Keep r11 | | | |V2 a| |I85 a| | |C86 i|V1 a|V4 a|V3 a|V5 a| 284.#358 r11 Fixd Keep r11 | | | |V2 a| |I85 a| | | |V1 a|V4 a|V3 a|V5 a| 284.#359 I87 Def Alloc r11 | | | |V2 a| |I85 a| | |I87 a|V1 a|V4 a|V3 a|V5 a| 286.#360 C88 Def Alloc rsi | | | |V2 a|C88 a|I85 a| | |I87 a|V1 a|V4 a|V3 a|V5 a| 289.#361 rdi Fixd Keep rdi | | | |V2 a|C88 a|I85 a| | |I87 a|V1 a|V4 a|V3 a|V5 a| 289.#362 I85 Use * Keep rdi | | | |V2 a|C88 a|I85 i| | |I87 a|V1 a|V4 a|V3 a|V5 a| 289.#363 r11 Fixd Keep r11 | | | |V2 a|C88 a| | | |I87 a|V1 a|V4 a|V3 a|V5 a| 289.#364 I87 Use * Keep r11 | | | |V2 a|C88 a| | | |I87 i|V1 a|V4 a|V3 a|V5 a| 289.#365 C88 Use * Keep rsi | | | |V2 a|C88 i| | | | |V1 a|V4 a|V3 a|V5 a| 290.#366 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#367 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#368 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#369 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#370 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#371 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#372 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#373 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#374 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#375 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 290.#376 I89 Def Alloc rax |I89 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 293.#377 I89 Use * Keep rax |I89 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 297.#378 BB10 PredBB9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 303.#379 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 303.#380 V10 Use ReLod rdi | | | |V2 a| |V10 a| | | |V1 a|V4 a|V3 a|V5 a| Keep rdi | | | |V2 a| |V10 i| | | |V1 a|V4 a|V3 a|V5 a| Spill rdi | | | |V2 a| |V10 i| | | |V1 a|V4 a|V3 a|V5 a| 304.#381 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 304.#382 I90 Def PtArg rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 307.#383 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 307.#384 V5 Use Copy rsi | | | |V2 a|V5 a| | | | |V1 a|V4 a|V3 a|V5 a| 308.#385 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 308.#386 I91 Def Alloc rsi | | | |V2 a|I91 a| | | | |V1 a|V4 a|V3 a|V5 a| 310.#387 C92 Def Alloc rax |C92 a| | |V2 a|I91 a| | | | |V1 a|V4 a|V3 a|V5 a| 313.#388 rdi Fixd Keep rdi |C92 a| | |V2 a|I91 a| | | | |V1 a|V4 a|V3 a|V5 a| 313.#389 I90 Use * PtArg rdi |C92 a| | |V2 a|I91 a| | | | |V1 a|V4 a|V3 a|V5 a| 313.#390 rsi Fixd Keep rsi |C92 a| | |V2 a|I91 a| | | | |V1 a|V4 a|V3 a|V5 a| 313.#391 I91 Use * Keep rsi |C92 a| | |V2 a|I91 i| | | | |V1 a|V4 a|V3 a|V5 a| 313.#392 C92 Use * Keep rax |C92 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#393 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#394 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#395 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#396 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#397 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#398 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#399 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#400 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 314.#401 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 317.#402 BB12 PredBB5 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 323.#403 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 323.#404 V0 Use * ReLod rdi | | | |V2 a| |V0 a| | | |V1 a|V4 a|V3 a|V5 a| Keep rdi | | | |V2 a| |V0 i| | | |V1 a|V4 a|V3 a|V5 a| 324.#405 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 324.#406 I93 Def Alloc rdi | | | |V2 a| |I93 a| | | |V1 a|V4 a|V3 a|V5 a| 327.#407 rsi Fixd Keep rsi | | | |V2 a| |I93 a| | | |V1 a|V4 a|V3 a|V5 a| 327.#408 V2 Use Copy rsi | | | |V2 a|V2 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 328.#409 rsi Fixd Keep rsi | | | |V2 a| |I93 a| | | |V1 a|V4 a|V3 a|V5 a| 328.#410 I94 Def Alloc rsi | | | |V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 331.#411 rdx Fixd Keep rdx | | | |V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 331.#412 V3 Use Copy rdx | | |V3 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 332.#413 rdx Fixd Keep rdx | | | |V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 332.#414 I95 Def Alloc rdx | | |I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 335.#415 rcx Fixd Keep rcx | | |I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 335.#416 V4 Use Copy rcx | |V4 a|I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 336.#417 rcx Fixd Keep rcx | | |I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 336.#418 I96 Def Alloc rcx | |I96 a|I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 339.#419 r8 Fixd Keep r8 | |I96 a|I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 339.#420 V5 Use Copy r8 | |I96 a|I95 a|V2 a|I94 a|I93 a|V5 a| | |V1 a|V4 a|V3 a|V5 a| 340.#421 r8 Fixd Keep r8 | |I96 a|I95 a|V2 a|I94 a|I93 a| | | |V1 a|V4 a|V3 a|V5 a| 340.#422 I97 Def Alloc r8 | |I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 342.#423 C98 Def Alloc rax |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#424 rdi Fixd Keep rdi |C98 a|I96 a|I95 a|V2 a|I94 a|I93 a|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#425 I93 Use * Keep rdi |C98 a|I96 a|I95 a|V2 a|I94 a|I93 i|I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#426 rsi Fixd Keep rsi |C98 a|I96 a|I95 a|V2 a|I94 a| |I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#427 I94 Use * Keep rsi |C98 a|I96 a|I95 a|V2 a|I94 i| |I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#428 rdx Fixd Keep rdx |C98 a|I96 a|I95 a|V2 a| | |I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#429 I95 Use * Keep rdx |C98 a|I96 a|I95 i|V2 a| | |I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#430 rcx Fixd Keep rcx |C98 a|I96 a| |V2 a| | |I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#431 I96 Use * Keep rcx |C98 a|I96 i| |V2 a| | |I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#432 r8 Fixd Keep r8 |C98 a| | |V2 a| | |I97 a| | |V1 a|V4 a|V3 a|V5 a| 345.#433 I97 Use * Keep r8 |C98 a| | |V2 a| | |I97 i| | |V1 a|V4 a|V3 a|V5 a| 345.#434 C98 Use * Keep rax |C98 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#435 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#436 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#437 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#438 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#439 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#440 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#441 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#442 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#443 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#444 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 346.#445 I99 Def Alloc rax |I99 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 349.#446 I99 Use * Keep rax |I99 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 353.#447 BB13 PredBB12 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 355.#448 BB14 PredBB9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 361.#449 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 361.#450 V3 Use Copy rdi | | | |V2 a| |V3 a| | | |V1 a|V4 a|V3 a|V5 a| 362.#451 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 362.#452 I100 Def Alloc rdi | | | |V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| 365.#453 rsi Fixd Keep rsi | | | |V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| 365.#454 V10 Use ReLod rsi | | | |V2 a|V10 a|I100a| | | |V1 a|V4 a|V3 a|V5 a| Keep rsi | | | |V2 a|V10 i|I100a| | | |V1 a|V4 a|V3 a|V5 a| Spill rsi | | | |V2 a|V10 i|I100a| | | |V1 a|V4 a|V3 a|V5 a| 366.#455 rsi Fixd Keep rsi | | | |V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| 366.#456 I101 Def PtArg rsi | | | |V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| 369.#457 rdx Fixd Keep rdx | | | |V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| 369.#458 V5 Use Copy rdx | | |V5 a|V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| 370.#459 rdx Fixd Keep rdx | | | |V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| 370.#460 I102 Def Alloc rdx | | |I102a|V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| 372.#461 C103 Def Alloc rax |C103a| |I102a|V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| 375.#462 rdi Fixd Keep rdi |C103a| |I102a|V2 a| |I100a| | | |V1 a|V4 a|V3 a|V5 a| 375.#463 I100 Use * Keep rdi |C103a| |I102a|V2 a| |I100i| | | |V1 a|V4 a|V3 a|V5 a| 375.#464 rsi Fixd Keep rsi |C103a| |I102a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 375.#465 I101 Use * PtArg rsi |C103a| |I102a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 375.#466 rdx Fixd Keep rdx |C103a| |I102a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 375.#467 I102 Use * Keep rdx |C103a| |I102i|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 375.#468 C103 Use * Keep rax |C103i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#469 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#470 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#471 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#472 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#473 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#474 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#475 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#476 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#477 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#478 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 376.#479 I104 Def Alloc rax |I104a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 377.#480 I104 Use * Keep rax |I104i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 378.#481 I105 Def Alloc rsi | | | |V2 a|I105a| | | | |V1 a|V4 a|V3 a|V5 a| 379.#482 I105 Use * Keep rsi | | | |V2 a|I105i| | | | |V1 a|V4 a|V3 a|V5 a| 380.#483 V19 Def Alloc rsi | | | |V2 a|V19 a| | | | |V1 a|V4 a|V3 a|V5 a| 385.#484 V19 Use * Keep rsi | | | |V2 a|V19 i| | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 389.#485 BB15 PredBB14 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 394.#486 C106 Def Alloc rsi | | | |V2 a|C106a| | | | |V1 a|V4 a|V3 a|V5 a| 395.#487 C106 Use * Keep rsi | | | |V2 a|C106i| | | | |V1 a|V4 a|V3 a|V5 a| 396.#488 I107 Def Alloc rsi | | | |V2 a|I107a| | | | |V1 a|V4 a|V3 a|V5 a| 397.#489 rsi Fixd Keep rsi | | | |V2 a|I107a| | | | |V1 a|V4 a|V3 a|V5 a| 397.#490 I107 Use * Keep rsi | | | |V2 a|I107i| | | | |V1 a|V4 a|V3 a|V5 a| 398.#491 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 398.#492 I108 Def Alloc rsi | | | |V2 a|I108a| | | | |V1 a|V4 a|V3 a|V5 a| 400.#493 I109 Def Alloc rdi | | | |V2 a|I108a|I109a| | | |V1 a|V4 a|V3 a|V5 a| 401.#494 rdi Fixd Keep rdi | | | |V2 a|I108a|I109a| | | |V1 a|V4 a|V3 a|V5 a| 401.#495 I109 Use * Keep rdi | | | |V2 a|I108a|I109i| | | |V1 a|V4 a|V3 a|V5 a| 402.#496 rdi Fixd Keep rdi | | | |V2 a|I108a| | | | |V1 a|V4 a|V3 a|V5 a| 402.#497 I110 Def Alloc rdi | | | |V2 a|I108a|I110a| | | |V1 a|V4 a|V3 a|V5 a| 404.#498 C111 Def Alloc rax |C111a| | |V2 a|I108a|I110a| | | |V1 a|V4 a|V3 a|V5 a| 407.#499 rsi Fixd Keep rsi |C111a| | |V2 a|I108a|I110a| | | |V1 a|V4 a|V3 a|V5 a| 407.#500 I108 Use * Keep rsi |C111a| | |V2 a|I108i|I110a| | | |V1 a|V4 a|V3 a|V5 a| 407.#501 rdi Fixd Keep rdi |C111a| | |V2 a| |I110a| | | |V1 a|V4 a|V3 a|V5 a| 407.#502 I110 Use * Keep rdi |C111a| | |V2 a| |I110i| | | |V1 a|V4 a|V3 a|V5 a| 407.#503 C111 Use * Keep rax |C111i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#504 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#505 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#506 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#507 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#508 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#509 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#510 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#511 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#512 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#513 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 408.#514 I112 Def Alloc rax |I112a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 411.#515 I112 Use * Keep rax |I112i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 415.#516 V2 ExpU | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 415.#517 V3 ExpU | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 415.#518 V5 ExpU | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 415.#519 V1 ExpU | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 415.#520 V4 ExpU | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 415.#521 BB16 PredBB6 | | | | | | | | | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 417.#522 BB17 PredBB4 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 421.#523 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 421.#524 V2 Use Copy rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 422.#525 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 422.#526 I113 Def Alloc rdi | | | |V2 a| |I113a| | | |V1 a|V4 a|V3 a|V5 a| 425.#527 rsi Fixd Keep rsi | | | |V2 a| |I113a| | | |V1 a|V4 a|V3 a|V5 a| 425.#528 V3 Use Copy rsi | | | |V2 a|V3 a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 426.#529 rsi Fixd Keep rsi | | | |V2 a| |I113a| | | |V1 a|V4 a|V3 a|V5 a| 426.#530 I114 Def Alloc rsi | | | |V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 429.#531 rdx Fixd Keep rdx | | | |V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 429.#532 V4 Use Copy rdx | | |V4 a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 430.#533 rdx Fixd Keep rdx | | | |V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 430.#534 I115 Def Alloc rdx | | |I115a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 432.#535 C116 Def Alloc rax |C116a| |I115a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 435.#536 rdi Fixd Keep rdi |C116a| |I115a|V2 a|I114a|I113a| | | |V1 a|V4 a|V3 a|V5 a| 435.#537 I113 Use * Keep rdi |C116a| |I115a|V2 a|I114a|I113i| | | |V1 a|V4 a|V3 a|V5 a| 435.#538 rsi Fixd Keep rsi |C116a| |I115a|V2 a|I114a| | | | |V1 a|V4 a|V3 a|V5 a| 435.#539 I114 Use * Keep rsi |C116a| |I115a|V2 a|I114i| | | | |V1 a|V4 a|V3 a|V5 a| 435.#540 rdx Fixd Keep rdx |C116a| |I115a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 435.#541 I115 Use * Keep rdx |C116a| |I115i|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 435.#542 C116 Use * Keep rax |C116i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#543 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#544 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#545 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#546 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#547 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#548 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#549 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#550 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#551 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#552 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 436.#553 I117 Def Alloc rax |I117a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 439.#554 I117 Use * Keep rax |I117i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 443.#555 V7 ExpU | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 443.#556 BB18 PredBB4 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 448.#557 C118 Def Alloc rdi | | | |V2 a| |C118a| | | |V1 a|V4 a|V3 a|V5 a| 449.#558 C118 Use * Keep rdi | | | |V2 a| |C118i| | | |V1 a|V4 a|V3 a|V5 a| 450.#559 V7 Def Alloc rax |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 451.#560 V0 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 451.#561 V7 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 451.#0 V7 Move STK | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 451.#562 BB19 PredBB10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 459.#563 V4 Use Keep r13 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 463.#564 BB20 PredBB19 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 468.#565 C119 Def Alloc rdi | | | |V2 a| |C119a| | | |V1 a|V4 a|V3 a|V5 a| 469.#566 rdi Fixd Keep rdi | | | |V2 a| |C119a| | | |V1 a|V4 a|V3 a|V5 a| 469.#567 C119 Use * Keep rdi | | | |V2 a| |C119i| | | |V1 a|V4 a|V3 a|V5 a| 470.#568 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 470.#569 I120 Def Alloc rdi | | | |V2 a| |I120a| | | |V1 a|V4 a|V3 a|V5 a| 472.#570 C121 Def Alloc rax |C121a| | |V2 a| |I120a| | | |V1 a|V4 a|V3 a|V5 a| 475.#571 rdi Fixd Keep rdi |C121a| | |V2 a| |I120a| | | |V1 a|V4 a|V3 a|V5 a| 475.#572 I120 Use * Keep rdi |C121a| | |V2 a| |I120i| | | |V1 a|V4 a|V3 a|V5 a| 475.#573 C121 Use * Keep rax |C121i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#574 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#575 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#576 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#577 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#578 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#579 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#580 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#581 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#582 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#583 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 476.#584 I122 Def Alloc rax |I122a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 477.#585 I122 Use * Keep rax |I122i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 478.#586 V14 Def Alloc rax |V14 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 485.#587 V14 Use Keep rax |V14 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 486.#588 I123 Def Alloc rdx |V14 a| |I123a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 487.#589 I123 Use * Keep rdx |V14 a| |I123i|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 488.#590 V28 Def Alloc rdx |V14 a| |V28 a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 491.#591 V28 Use Keep rdx |V14 a| |V28 i|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Spill rdx |V14 a| |V28 i|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 495.#592 V14 Use Keep rax |V14 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Spill rax |V14 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 496.#593 I124 Def Alloc rdi | | | |V2 a| |I124a| | | |V1 a|V4 a|V3 a|V5 a| 499.#594 rdi Fixd Keep rdi | | | |V2 a| |I124a| | | |V1 a|V4 a|V3 a|V5 a| 499.#595 I124 Use * Keep rdi | | | |V2 a| |I124i| | | |V1 a|V4 a|V3 a|V5 a| 499.#596 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 499.#597 V3 Use Copy rsi | | | |V2 a|V3 a| | | | |V1 a|V4 a|V3 a|V5 a| 500.#598 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#599 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#600 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#601 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#602 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#603 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#604 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#605 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#606 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#607 mm0 Kill Keep mm0 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#608 mm1 Kill Keep mm1 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#609 mm2 Kill Keep mm2 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#610 mm3 Kill Keep mm3 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#611 mm4 Kill Keep mm4 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#612 mm5 Kill Keep mm5 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#613 mm6 Kill Keep mm6 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#614 mm7 Kill Keep mm7 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#615 mm8 Kill Keep mm8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#616 mm9 Kill Keep mm9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#617 mm10 Kill Keep mm10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#618 mm11 Kill Keep mm11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#619 mm12 Kill Keep mm12 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#620 mm13 Kill Keep mm13 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#621 mm14 Kill Keep mm14 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 500.#622 mm15 Kill Keep mm15 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 505.#623 V28 Use * NoReg | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 509.#624 V14 Use ReLod rax |V14 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Keep rax |V14 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Spill rax |V14 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 510.#625 I125 Def Alloc rdi | | | |V2 a| |I125a| | | |V1 a|V4 a|V3 a|V5 a| 513.#626 rdi Fixd Keep rdi | | | |V2 a| |I125a| | | |V1 a|V4 a|V3 a|V5 a| 513.#627 I125 Use * Keep rdi | | | |V2 a| |I125i| | | |V1 a|V4 a|V3 a|V5 a| 513.#628 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 513.#629 V10 Use * ReLod rsi | | | |V2 a|V10 a| | | | |V1 a|V4 a|V3 a|V5 a| Keep rsi | | | |V2 a|V10 i| | | | |V1 a|V4 a|V3 a|V5 a| 514.#630 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#631 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#632 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#633 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#634 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#635 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#636 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#637 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#638 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#639 mm0 Kill Keep mm0 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#640 mm1 Kill Keep mm1 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#641 mm2 Kill Keep mm2 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#642 mm3 Kill Keep mm3 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#643 mm4 Kill Keep mm4 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#644 mm5 Kill Keep mm5 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#645 mm6 Kill Keep mm6 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#646 mm7 Kill Keep mm7 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#647 mm8 Kill Keep mm8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#648 mm9 Kill Keep mm9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#649 mm10 Kill Keep mm10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#650 mm11 Kill Keep mm11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#651 mm12 Kill Keep mm12 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#652 mm13 Kill Keep mm13 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#653 mm14 Kill Keep mm14 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 514.#654 mm15 Kill Keep mm15 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 516.#655 C126 Def Alloc rax |C126a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 519.#656 C126 Use * Keep rax |C126i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#657 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#658 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#659 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#660 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#661 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#662 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#663 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#664 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#665 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#666 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 520.#667 I127 Def Alloc rax |I127a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 521.#668 I127 Use * Keep rax |I127i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 522.#669 V20 Def Alloc rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Spill rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 524.#670 C128 Def Alloc rdi | | | |V2 a| |C128a| | | |V1 a|V4 a|V3 a|V5 a| 527.#671 C128 Use * Keep rdi | | | |V2 a| |C128i| | | |V1 a|V4 a|V3 a|V5 a| 528.#672 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#673 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#674 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#675 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#676 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#677 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#678 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#679 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#680 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#681 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 528.#682 I129 Def Alloc rax |I129a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 531.#683 I129 Use * Keep rax |I129i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 532.#684 I130 Def Alloc rsi | | | |V2 a|I130a| | | | |V1 a|V4 a|V3 a|V5 a| 533.#685 I130 Use * Keep rsi | | | |V2 a|I130i| | | | |V1 a|V4 a|V3 a|V5 a| 534.#686 V27 Def Alloc rsi | | | |V2 a|V27 a| | | | |V1 a|V4 a|V3 a|V5 a| 537.#687 rsi Fixd Keep rsi | | | |V2 a|V27 a| | | | |V1 a|V4 a|V3 a|V5 a| 537.#688 V27 Use * Keep rsi | | | |V2 a|V27 i| | | | |V1 a|V4 a|V3 a|V5 a| 538.#689 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 538.#690 I131 Def Alloc rsi | | | |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 541.#691 rdi Fixd Keep rdi | | | |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 541.#692 V20 Use ReLod rdi | | | |V2 a|I131a|V20 a| | | |V1 a|V4 a|V3 a|V5 a| Keep rdi | | | |V2 a|I131a|V20 i| | | |V1 a|V4 a|V3 a|V5 a| Spill rdi | | | |V2 a|I131a|V20 i| | | |V1 a|V4 a|V3 a|V5 a| 542.#693 rdi Fixd Keep rdi | | | |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 542.#694 I132 Def PtArg rdi | | | |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 545.#695 rcx Fixd Keep rcx | | | |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 545.#696 V14 Use * ReLod rcx | |V14 a| |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| Keep rcx | |V14 i| |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 546.#697 rcx Fixd Keep rcx | | | |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 546.#698 I133 Def Alloc rcx | |I133a| |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 548.#699 C134 Def Alloc rdx | |I133a|C134a|V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 549.#700 rdx Fixd Keep rdx | |I133a|C134a|V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 549.#701 C134 Use * Keep rdx | |I133a|C134i|V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 550.#702 rdx Fixd Keep rdx | |I133a| |V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 550.#703 I135 Def Alloc rdx | |I133a|I135a|V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 552.#704 C136 Def Alloc rax |C136a|I133a|I135a|V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 555.#705 rsi Fixd Keep rsi |C136a|I133a|I135a|V2 a|I131a| | | | |V1 a|V4 a|V3 a|V5 a| 555.#706 I131 Use * Keep rsi |C136a|I133a|I135a|V2 a|I131i| | | | |V1 a|V4 a|V3 a|V5 a| 555.#707 rdi Fixd Keep rdi |C136a|I133a|I135a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 555.#708 I132 Use * PtArg rdi |C136a|I133a|I135a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 555.#709 rcx Fixd Keep rcx |C136a|I133a|I135a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 555.#710 I133 Use * Keep rcx |C136a|I133i|I135a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 555.#711 rdx Fixd Keep rdx |C136a| |I135a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 555.#712 I135 Use * Keep rdx |C136a| |I135i|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 555.#713 C136 Use * Keep rax |C136i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#714 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#715 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#716 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#717 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#718 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#719 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#720 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#721 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 556.#722 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 558.#723 C137 Def Alloc rdi | | | |V2 a| |C137a| | | |V1 a|V4 a|V3 a|V5 a| 561.#724 I138 Def Alloc mm0 | | | |V2 a| |C137a| | | |V1 a|V4 a|V3 a|V5 a| 561.#725 C137 Use * Keep rdi | | | |V2 a| |C137i| | | |V1 a|V4 a|V3 a|V5 a| 561.#726 I138 Use * Keep mm0 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 565.#727 V2 Use Keep rbx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 569.#728 V20 Use * ReLod rdi | | | |V2 a| |V20 a| | | |V1 a|V4 a|V3 a|V5 a| Keep rdi | | | |V2 a| |V20 i| | | |V1 a|V4 a|V3 a|V5 a| 577.#729 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 577.#730 I139 Def Alloc rdi | | | |V2 a| |I139a| | | |V1 a|V4 a|V3 a|V5 a| 577.#731 rcx Fixd Keep rcx | | | |V2 a| |I139a| | | |V1 a|V4 a|V3 a|V5 a| 577.#732 I140 Def Alloc rcx | |I140a| |V2 a| |I139a| | | |V1 a|V4 a|V3 a|V5 a| 577.#733 rsi Fixd Keep rsi | |I140a| |V2 a| |I139a| | | |V1 a|V4 a|V3 a|V5 a| 577.#734 I141 Def Alloc rsi | |I140a| |V2 a|I141a|I139a| | | |V1 a|V4 a|V3 a|V5 a| 577.#735 I139 Use * Keep rdi | |I140a| |V2 a|I141a|I139i| | | |V1 a|V4 a|V3 a|V5 a| 577.#736 I140 Use * Keep rcx | |I140i| |V2 a|I141a| | | | |V1 a|V4 a|V3 a|V5 a| 577.#737 I141 Use * Keep rsi | | | |V2 a|I141i| | | | |V1 a|V4 a|V3 a|V5 a| 581.#738 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 581.#739 V4 Use Copy rdi | | | |V2 a| |V4 a| | | |V1 a|V4 a|V3 a|V5 a| 582.#740 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 582.#741 I142 Def Alloc rdi | | | |V2 a| |I142a| | | |V1 a|V4 a|V3 a|V5 a| 584.#742 r11 Fixd Keep r11 | | | |V2 a| |I142a| | | |V1 a|V4 a|V3 a|V5 a| 584.#743 C143 Def Alloc r11 | | | |V2 a| |I142a| | |C143a|V1 a|V4 a|V3 a|V5 a| 585.#744 r11 Fixd Keep r11 | | | |V2 a| |I142a| | |C143a|V1 a|V4 a|V3 a|V5 a| 585.#745 C143 Use * Keep r11 | | | |V2 a| |I142a| | |C143i|V1 a|V4 a|V3 a|V5 a| 586.#746 r11 Fixd Keep r11 | | | |V2 a| |I142a| | | |V1 a|V4 a|V3 a|V5 a| 586.#747 I144 Def Alloc r11 | | | |V2 a| |I142a| | |I144a|V1 a|V4 a|V3 a|V5 a| 588.#748 C145 Def Alloc rax |C145a| | |V2 a| |I142a| | |I144a|V1 a|V4 a|V3 a|V5 a| 591.#749 rdi Fixd Keep rdi |C145a| | |V2 a| |I142a| | |I144a|V1 a|V4 a|V3 a|V5 a| 591.#750 I142 Use * Keep rdi |C145a| | |V2 a| |I142i| | |I144a|V1 a|V4 a|V3 a|V5 a| 591.#751 r11 Fixd Keep r11 |C145a| | |V2 a| | | | |I144a|V1 a|V4 a|V3 a|V5 a| 591.#752 I144 Use * Keep r11 |C145a| | |V2 a| | | | |I144i|V1 a|V4 a|V3 a|V5 a| 591.#753 C145 Use * Keep rax |C145i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#754 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#755 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#756 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#757 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#758 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#759 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#760 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#761 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 592.#762 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 593.#763 BB21 PredBB19 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 598.#764 C146 Def Alloc rax |C146a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 599.#765 C146 Use * Keep rax |C146i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 600.#766 V7 Def Alloc rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Spill rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 601.#767 BB22 PredBB3 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 607.#768 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 607.#769 V2 Use Copy rdi | | | |V2 a| |V2 a| | | |V1 a|V4 a|V3 a|V5 a| 608.#770 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 608.#771 I147 Def Alloc rdi | | | |V2 a| |I147a| | | |V1 a|V4 a|V3 a|V5 a| 611.#772 rsi Fixd Keep rsi | | | |V2 a| |I147a| | | |V1 a|V4 a|V3 a|V5 a| 611.#773 V3 Use Copy rsi | | | |V2 a|V3 a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 612.#774 rsi Fixd Keep rsi | | | |V2 a| |I147a| | | |V1 a|V4 a|V3 a|V5 a| 612.#775 I148 Def Alloc rsi | | | |V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 615.#776 rdx Fixd Keep rdx | | | |V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 615.#777 V4 Use Copy rdx | | |V4 a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 616.#778 rdx Fixd Keep rdx | | | |V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 616.#779 I149 Def Alloc rdx | | |I149a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 618.#780 C150 Def Alloc rcx | |C150a|I149a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 621.#781 rdi Fixd Keep rdi | |C150a|I149a|V2 a|I148a|I147a| | | |V1 a|V4 a|V3 a|V5 a| 621.#782 I147 Use * Keep rdi | |C150a|I149a|V2 a|I148a|I147i| | | |V1 a|V4 a|V3 a|V5 a| 621.#783 rsi Fixd Keep rsi | |C150a|I149a|V2 a|I148a| | | | |V1 a|V4 a|V3 a|V5 a| 621.#784 I148 Use * Keep rsi | |C150a|I149a|V2 a|I148i| | | | |V1 a|V4 a|V3 a|V5 a| 621.#785 rdx Fixd Keep rdx | |C150a|I149a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 621.#786 I149 Use * Keep rdx | |C150a|I149i|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 621.#787 C150 Use * Keep rcx | |C150i| |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#788 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#789 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#790 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#791 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#792 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#793 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#794 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#795 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#796 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#797 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 622.#798 I151 Def Alloc rax |I151a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 625.#799 I151 Use * Keep rax |I151i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 629.#800 V7 ExpU | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 629.#801 BB23 PredBB3 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 634.#802 C152 Def Alloc rax |C152a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 635.#803 C152 Use * Keep rax |C152i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 636.#804 V7 Def Alloc rax |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#805 V2 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#806 V3 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#807 V5 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#808 V1 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#809 V4 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#810 V0 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#811 V7 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 637.#0 V7 Move STK | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 637.#812 BB24 PredBB1 | | | | | | | | | | | | | | 644.#813 V6 Def Alloc rax |V6 a| | | | | | | | | | | | | 645.#814 V6 ExpU |V6 a| | | | | | | | | | | | | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 645.#815 BB25 PredBB2 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 653.#816 V4 Use Keep r13 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 657.#817 BB26 PredBB25 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 662.#818 C153 Def Alloc rdi | | | |V2 a| |C153a| | | |V1 a|V4 a|V3 a|V5 a| 663.#819 rdi Fixd Keep rdi | | | |V2 a| |C153a| | | |V1 a|V4 a|V3 a|V5 a| 663.#820 C153 Use * Keep rdi | | | |V2 a| |C153i| | | |V1 a|V4 a|V3 a|V5 a| 664.#821 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 664.#822 I154 Def Alloc rdi | | | |V2 a| |I154a| | | |V1 a|V4 a|V3 a|V5 a| 666.#823 C155 Def Alloc rax |C155a| | |V2 a| |I154a| | | |V1 a|V4 a|V3 a|V5 a| 669.#824 rdi Fixd Keep rdi |C155a| | |V2 a| |I154a| | | |V1 a|V4 a|V3 a|V5 a| 669.#825 I154 Use * Keep rdi |C155a| | |V2 a| |I154i| | | |V1 a|V4 a|V3 a|V5 a| 669.#826 C155 Use * Keep rax |C155i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#827 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#828 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#829 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#830 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#831 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#832 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#833 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#834 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#835 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#836 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 670.#837 I156 Def Alloc rax |I156a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 671.#838 I156 Use * Keep rax |I156i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 672.#839 V16 Def Alloc rax |V16 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 681.#840 V16 Use Keep rax |V16 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 685.#841 V16 Use Keep rax |V16 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Spill rax |V16 i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 686.#842 I157 Def Alloc rdi | | | |V2 a| |I157a| | | |V1 a|V4 a|V3 a|V5 a| 689.#843 rdi Fixd Keep rdi | | | |V2 a| |I157a| | | |V1 a|V4 a|V3 a|V5 a| 689.#844 I157 Use * Keep rdi | | | |V2 a| |I157i| | | |V1 a|V4 a|V3 a|V5 a| 689.#845 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 689.#846 V3 Use Copy rsi | | | |V2 a|V3 a| | | | |V1 a|V4 a|V3 a|V5 a| 690.#847 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#848 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#849 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#850 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#851 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#852 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#853 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#854 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#855 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#856 mm0 Kill Keep mm0 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#857 mm1 Kill Keep mm1 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#858 mm2 Kill Keep mm2 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#859 mm3 Kill Keep mm3 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#860 mm4 Kill Keep mm4 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#861 mm5 Kill Keep mm5 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#862 mm6 Kill Keep mm6 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#863 mm7 Kill Keep mm7 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#864 mm8 Kill Keep mm8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#865 mm9 Kill Keep mm9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#866 mm10 Kill Keep mm10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#867 mm11 Kill Keep mm11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#868 mm12 Kill Keep mm12 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#869 mm13 Kill Keep mm13 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#870 mm14 Kill Keep mm14 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 690.#871 mm15 Kill Keep mm15 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 692.#872 C158 Def Alloc rax |C158a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 695.#873 C158 Use * Keep rax |C158i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#874 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#875 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#876 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#877 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#878 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#879 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#880 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#881 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#882 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#883 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 696.#884 I159 Def Alloc rax |I159a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 697.#885 I159 Use * Keep rax |I159i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 698.#886 V18 Def Alloc rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| Spill rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 700.#887 C160 Def Alloc rdi | | | |V2 a| |C160a| | | |V1 a|V4 a|V3 a|V5 a| 703.#888 C160 Use * Keep rdi | | | |V2 a| |C160i| | | |V1 a|V4 a|V3 a|V5 a| 704.#889 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#890 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#891 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#892 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#893 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#894 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#895 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#896 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#897 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#898 rax Fixd Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 704.#899 I161 Def Alloc rax |I161a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 707.#900 I161 Use * Keep rax |I161i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 708.#901 I162 Def Alloc rsi | | | |V2 a|I162a| | | | |V1 a|V4 a|V3 a|V5 a| 709.#902 I162 Use * Keep rsi | | | |V2 a|I162i| | | | |V1 a|V4 a|V3 a|V5 a| 710.#903 V24 Def Alloc rsi | | | |V2 a|V24 a| | | | |V1 a|V4 a|V3 a|V5 a| 713.#904 rsi Fixd Keep rsi | | | |V2 a|V24 a| | | | |V1 a|V4 a|V3 a|V5 a| 713.#905 V24 Use * Keep rsi | | | |V2 a|V24 i| | | | |V1 a|V4 a|V3 a|V5 a| 714.#906 rsi Fixd Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 714.#907 I163 Def Alloc rsi | | | |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 717.#908 rdi Fixd Keep rdi | | | |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 717.#909 V18 Use ReLod rdi | | | |V2 a|I163a|V18 a| | | |V1 a|V4 a|V3 a|V5 a| Keep rdi | | | |V2 a|I163a|V18 i| | | |V1 a|V4 a|V3 a|V5 a| Spill rdi | | | |V2 a|I163a|V18 i| | | |V1 a|V4 a|V3 a|V5 a| 718.#910 rdi Fixd Keep rdi | | | |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 718.#911 I164 Def PtArg rdi | | | |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 721.#912 rcx Fixd Keep rcx | | | |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 721.#913 V16 Use * ReLod rcx | |V16 a| |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| Keep rcx | |V16 i| |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 722.#914 rcx Fixd Keep rcx | | | |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 722.#915 I165 Def Alloc rcx | |I165a| |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 724.#916 C166 Def Alloc rdx | |I165a|C166a|V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 725.#917 rdx Fixd Keep rdx | |I165a|C166a|V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 725.#918 C166 Use * Keep rdx | |I165a|C166i|V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 726.#919 rdx Fixd Keep rdx | |I165a| |V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 726.#920 I167 Def Alloc rdx | |I165a|I167a|V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 728.#921 C168 Def Alloc rax |C168a|I165a|I167a|V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 731.#922 rsi Fixd Keep rsi |C168a|I165a|I167a|V2 a|I163a| | | | |V1 a|V4 a|V3 a|V5 a| 731.#923 I163 Use * Keep rsi |C168a|I165a|I167a|V2 a|I163i| | | | |V1 a|V4 a|V3 a|V5 a| 731.#924 rdi Fixd Keep rdi |C168a|I165a|I167a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 731.#925 I164 Use * PtArg rdi |C168a|I165a|I167a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 731.#926 rcx Fixd Keep rcx |C168a|I165a|I167a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 731.#927 I165 Use * Keep rcx |C168a|I165i|I167a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 731.#928 rdx Fixd Keep rdx |C168a| |I167a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 731.#929 I167 Use * Keep rdx |C168a| |I167i|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 731.#930 C168 Use * Keep rax |C168i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#931 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#932 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#933 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#934 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#935 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#936 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#937 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#938 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 732.#939 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 734.#940 I169 Def Alloc rdi | | | |V2 a| |I169a| | | |V1 a|V4 a|V3 a|V5 a| 735.#941 rdi Fixd Keep rdi | | | |V2 a| |I169a| | | |V1 a|V4 a|V3 a|V5 a| 735.#942 I169 Use * Keep rdi | | | |V2 a| |I169i| | | |V1 a|V4 a|V3 a|V5 a| 736.#943 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 736.#944 I170 Def Alloc rdi | | | |V2 a| |I170a| | | |V1 a|V4 a|V3 a|V5 a| 739.#945 rsi Fixd Keep rsi | | | |V2 a| |I170a| | | |V1 a|V4 a|V3 a|V5 a| 739.#946 V2 Use Copy rsi | | | |V2 a|V2 a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 740.#947 rsi Fixd Keep rsi | | | |V2 a| |I170a| | | |V1 a|V4 a|V3 a|V5 a| 740.#948 I171 Def Alloc rsi | | | |V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 743.#949 rdx Fixd Keep rdx | | | |V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 743.#950 V18 Use * ReLod rdx | | |V18 a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| Keep rdx | | |V18 i|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 744.#951 rdx Fixd Keep rdx | | | |V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 744.#952 I172 Def Alloc rdx | | |I172a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 746.#953 C173 Def Alloc rax |C173a| |I172a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 749.#954 rdi Fixd Keep rdi |C173a| |I172a|V2 a|I171a|I170a| | | |V1 a|V4 a|V3 a|V5 a| 749.#955 I170 Use * Keep rdi |C173a| |I172a|V2 a|I171a|I170i| | | |V1 a|V4 a|V3 a|V5 a| 749.#956 rsi Fixd Keep rsi |C173a| |I172a|V2 a|I171a| | | | |V1 a|V4 a|V3 a|V5 a| 749.#957 I171 Use * Keep rsi |C173a| |I172a|V2 a|I171i| | | | |V1 a|V4 a|V3 a|V5 a| 749.#958 rdx Fixd Keep rdx |C173a| |I172a|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 749.#959 I172 Use * Keep rdx |C173a| |I172i|V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 749.#960 C173 Use * Keep rax |C173i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#961 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#962 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#963 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#964 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#965 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#966 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#967 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#968 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 750.#969 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 757.#970 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 757.#971 I174 Def Alloc rdi | | | |V2 a| |I174a| | | |V1 a|V4 a|V3 a|V5 a| 757.#972 rcx Fixd Keep rcx | | | |V2 a| |I174a| | | |V1 a|V4 a|V3 a|V5 a| 757.#973 I175 Def Alloc rcx | |I175a| |V2 a| |I174a| | | |V1 a|V4 a|V3 a|V5 a| 757.#974 rsi Fixd Keep rsi | |I175a| |V2 a| |I174a| | | |V1 a|V4 a|V3 a|V5 a| 757.#975 I176 Def Alloc rsi | |I175a| |V2 a|I176a|I174a| | | |V1 a|V4 a|V3 a|V5 a| 757.#976 I174 Use * Keep rdi | |I175a| |V2 a|I176a|I174i| | | |V1 a|V4 a|V3 a|V5 a| 757.#977 I175 Use * Keep rcx | |I175i| |V2 a|I176a| | | | |V1 a|V4 a|V3 a|V5 a| 757.#978 I176 Use * Keep rsi | | | |V2 a|I176i| | | | |V1 a|V4 a|V3 a|V5 a| 761.#979 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 761.#980 V4 Use Copy rdi | | | |V2 a| |V4 a| | | |V1 a|V4 a|V3 a|V5 a| 762.#981 rdi Fixd Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 762.#982 I177 Def Alloc rdi | | | |V2 a| |I177a| | | |V1 a|V4 a|V3 a|V5 a| 764.#983 r11 Fixd Keep r11 | | | |V2 a| |I177a| | | |V1 a|V4 a|V3 a|V5 a| 764.#984 C178 Def Alloc r11 | | | |V2 a| |I177a| | |C178a|V1 a|V4 a|V3 a|V5 a| 765.#985 r11 Fixd Keep r11 | | | |V2 a| |I177a| | |C178a|V1 a|V4 a|V3 a|V5 a| 765.#986 C178 Use * Keep r11 | | | |V2 a| |I177a| | |C178i|V1 a|V4 a|V3 a|V5 a| 766.#987 r11 Fixd Keep r11 | | | |V2 a| |I177a| | | |V1 a|V4 a|V3 a|V5 a| 766.#988 I179 Def Alloc r11 | | | |V2 a| |I177a| | |I179a|V1 a|V4 a|V3 a|V5 a| 768.#989 C180 Def Alloc rax |C180a| | |V2 a| |I177a| | |I179a|V1 a|V4 a|V3 a|V5 a| 771.#990 rdi Fixd Keep rdi |C180a| | |V2 a| |I177a| | |I179a|V1 a|V4 a|V3 a|V5 a| 771.#991 I177 Use * Keep rdi |C180a| | |V2 a| |I177i| | |I179a|V1 a|V4 a|V3 a|V5 a| 771.#992 r11 Fixd Keep r11 |C180a| | |V2 a| | | | |I179a|V1 a|V4 a|V3 a|V5 a| 771.#993 I179 Use * Keep r11 |C180a| | |V2 a| | | | |I179i|V1 a|V4 a|V3 a|V5 a| 771.#994 C180 Use * Keep rax |C180i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#995 rax Kill Keep rax | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#996 rcx Kill Keep rcx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#997 rdx Kill Keep rdx | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#998 rsi Kill Keep rsi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#999 rdi Kill Keep rdi | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#1000 r8 Kill Keep r8 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#1001 r9 Kill Keep r9 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#1002 r10 Kill Keep r10 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 772.#1003 r11 Kill Keep r11 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 773.#1004 BB27 PredBB25 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 778.#1005 C181 Def Alloc rax |C181a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 779.#1006 C181 Use * Keep rax |C181i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 780.#1007 V7 Def Alloc rax |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 781.#1008 V0 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 781.#1009 V7 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 781.#0 V7 Move STK | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 781.#1010 BB28 PredBB12 | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 786.#1011 C182 Def Alloc rax |C182a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 787.#1012 C182 Use * Keep rax |C182i| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 788.#1013 V7 Def Alloc rax |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#1014 V2 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#1015 V3 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#1016 V5 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#1017 V1 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#1018 V4 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#1019 V7 ExpU |V7 a| | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| 789.#0 V7 Move STK | | | |V2 a| | | | | |V1 a|V4 a|V3 a|V5 a| ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | ----------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 789.#1020 BB29 PredBB28 | | | | | | | | | | | | | | 792.#1021 rax Kill Keep rax | | | | | | | | | | | | | | 792.#1022 rcx Kill Keep rcx | | | | | | | | | | | | | | 792.#1023 rdx Kill Keep rdx | | | | | | | | | | | | | | 792.#1024 rsi Kill Keep rsi | | | | | | | | | | | | | | 792.#1025 rdi Kill Keep rdi | | | | | | | | | | | | | | 792.#1026 r8 Kill Keep r8 | | | | | | | | | | | | | | 792.#1027 r9 Kill Keep r9 | | | | | | | | | | | | | | 792.#1028 r10 Kill Keep r10 | | | | | | | | | | | | | | 792.#1029 r11 Kill Keep r11 | | | | | | | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- BB02 [ 20988]: SpillCount = 1, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0 BB09 [ 6120]: SpillCount = 1, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0 BB10 [ 12240]: SpillCount = 1, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0 BB14 [ 6120]: SpillCount = 1, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0 BB18 [ 22]: SpillCount = 0, ResolutionMovs = 1, SplitEdges = 0, CopyReg = 0 BB20 [ 479]: SpillCount = 5, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0 BB21 [ 479]: SpillCount = 1, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0 BB23 [ 0]: SpillCount = 0, ResolutionMovs = 1, SplitEdges = 0, CopyReg = 0 BB26 [ 0]: SpillCount = 3, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 0 BB27 [ 0]: SpillCount = 0, ResolutionMovs = 1, SplitEdges = 0, CopyReg = 0 BB28 [ 0]: SpillCount = 0, ResolutionMovs = 1, SplitEdges = 0, CopyReg = 0 Total Tracked Vars: 21 Total Reg Cand Vars: 19 Total number of Intervals: 182 Total number of RefPositions: 1029 Total Spill Count: 13 Weighted: 48342 Total CopyReg Count: 0 Weighted: 0 Total ResolutionMov Count: 4 Weighted: 22 Total number of split edges: 0 Total Number of spill temps created: 0 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V02(rdx=>rbx) V03(rcx=>r14) V05(r9=>r15) V01(rsi=>r12) V04(r8=>r13) V00(rdi=>STK) BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} ===== N003. V03(r14) N005. rdi = PUTARG_REG; r14 N007. r11 = CNS_INT(h) 0xd1ffab1e ftn N009. r11 = PUTARG_REG; r11 N011. rsi = CNS_INT(h) 0xd1ffab1e ftn N013. STK = IND ; rsi N015. rax = CALLV stub; rdi,r11,STK N017. CNS_INT 4 N019. EQ ; rax N021. JTRUE Var=Reg end of BB01: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB02: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N025. IL_OFFSET IL offset: 0xf N027. CNS_INT 1 N029. V07(STK) N031. V03(r14) N033. rdi = PUTARG_REG; r14 N035. r11 = CNS_INT(h) 0xd1ffab1e ftn N037. r11 = PUTARG_REG; r11 N039. rsi = CNS_INT(h) 0xd1ffab1e ftn N041. STK = IND ; rsi N043. rax = CALLV stub; rdi,r11,STK N045. rdi = CAST ; rax N047. rdi = PUTARG_REG; rdi N049. rax = CNS_INT(h) 0xd1ffab1e ftn N051. STK = IND ; rax N053. rax = CALL r2r_ind; rdi,STK N055. CNS_INT 0 N057. NE ; rax N059. JTRUE Var=Reg end of BB02: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} ===== Predecessor for variable locations: BB02 Var=Reg beg of BB03: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N063. IL_OFFSET IL offset: 0x40 N065. V02(rbx) N067. rdi = PUTARG_REG; rbx N069. r11 = CNS_INT(h) 0xd1ffab1e ftn N071. r11 = PUTARG_REG; r11 N073. rax = CNS_INT(h) 0xd1ffab1e ftn N075. STK = IND ; rax N077. rax = CALLV stub; rdi,r11,STK N079. CNS_INT 0 N081. NE ; rax N083. JTRUE Var=Reg end of BB03: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} ===== Predecessor for variable locations: BB03 Var=Reg beg of BB04: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N087. IL_OFFSET IL offset: 0x55 N089. V02(rbx) N091. rdi = PUTARG_REG; rbx N093. r11 = CNS_INT(h) 0xd1ffab1e ftn N095. r11 = PUTARG_REG; r11 N097. rax = CNS_INT(h) 0xd1ffab1e ftn N099. STK = IND ; rax N101. rax = CALLV stub; rdi,r11,STK N103. CNS_INT 0 N105. NE ; rax N107. JTRUE Var=Reg end of BB04: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB05: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N111. IL_OFFSET IL offset: 0x6a N113. V02(rbx) N115. rdi = PUTARG_REG; rbx N117. r11 = CNS_INT(h) 0xd1ffab1e ftn N119. r11 = PUTARG_REG; r11 N121. rax = CNS_INT(h) 0xd1ffab1e ftn N123. STK = IND ; rax N125. rax = CALLV stub; rdi,r11,STK N127. CNS_INT 0 N129. NE ; rax N131. JTRUE Var=Reg end of BB05: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} ===== Predecessor for variable locations: BB05 Var=Reg beg of BB06: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N135. V02(rbx) N137. rdi = PUTARG_REG; rbx N139. V05(r15) N141. rsi = PUTARG_REG; r15 N143. rax = CNS_INT(h) 0xd1ffab1e ftn N145. STK = IND ; rax N147. rax = CALL r2r_ind; rdi,rsi,STK N149. V23 MEM; rax N151. IL_OFFSET IL offset: 0x8b N153. rsi = CNS_INT(h) 0xd1ffab1e class N155. rsi = IND ; rsi N157. rsi = PUTARG_REG; rsi N159. rdi = LCL_VAR_ADDR V09 loc3 rdi ref V09.array (offs=0x00) -> V23 tmp12 N161. rdi = PUTARG_REG; rdi N163. rax = CNS_INT(h) 0xd1ffab1e ftn N165. STK = IND ; rax N167. rax,rdx = CALL r2r_ind; rsi,rdi,STK N169. V12 MEM; rax,rdx N171. rsi = LCL_VAR_ADDR V12 tmp1 rsi * N173. V25(rsi); rsi N175. V25(rsi) N177. rdi = IND ; rsi N179. V21 MEM; rdi N181. V25(rsi*) N183. STK = LEA(b+8) ; rsi* N185. rsi = IND ; STK N187. V22 MEM; rsi N189. IL_OFFSET IL offset: 0xe1 N191. rsi = CNS_INT(h) 0xd1ffab1e class N193. rsi = IND ; rsi N195. rsi = PUTARG_REG; rsi N197. rdi = LCL_VAR_ADDR V08 loc2 rdi ref V08._array (offs=0x00) -> V21 tmp10 int V08._index (offs=0x08) -> V22 tmp11 N199. rdi = PUTARG_REG; rdi N201. rax = CNS_INT(h) 0xd1ffab1e ftn N203. STK = IND ; rax N205. rax = CALL r2r_ind; rsi,rdi,STK N207. CNS_INT 0 N209. NE ; rax N211. JTRUE Var=Reg end of BB06: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} ===== Predecessor for variable locations: BB06 Var=Reg beg of BB07: none N215. IL_OFFSET IL offset: 0xea N217. V07(r13*)R * N219. V06(rax); r13* Var=Reg end of BB07: V06=rax BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB08: V06=rax N223. IL_OFFSET IL offset: 0xec N225. V06(rax*) N227. RETURN ; rax* Var=Reg end of BB08: none BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} ===== Predecessor for variable locations: BB06 Var=Reg beg of BB09: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N231. IL_OFFSET IL offset: 0x95 N233. rsi = CNS_INT(h) 0xd1ffab1e class N235. rsi = IND ; rsi N237. rsi = PUTARG_REG; rsi N239. rdi = LCL_VAR_ADDR V08 loc2 rdi ref V08._array (offs=0x00) -> V21 tmp10 int V08._index (offs=0x08) -> V22 tmp11 N241. rdi = PUTARG_REG; rdi N243. rax = CNS_INT(h) 0xd1ffab1e ftn N245. STK = IND ; rax N247. rax = CALL r2r_ind; rsi,rdi,STK * N249. V26(rdi); rax N251. V26(rdi*) N253. rdi = PUTARG_REG; rdi* N255. V01(r12) N257. rsi = PUTARG_REG; r12 N259. r11 = CNS_INT(h) 0xd1ffab1e ftn N261. r11 = PUTARG_REG; r11 N263. rax = CNS_INT(h) 0xd1ffab1e ftn N265. STK = IND ; rax N267. rax,rdx = CALLV stub; rdi,rsi,r11,STK N269. V13 MEM; rax,rdx N271. rax = V13 MEM * N273. V10(rax); rax N275. IL_OFFSET IL offset: 0xa9 S N277. V10(rax) N279. rdi = PUTARG_REG; rax N281. r11 = CNS_INT(h) 0xd1ffab1e ftn N283. r11 = PUTARG_REG; r11 N285. rsi = CNS_INT(h) 0xd1ffab1e ftn N287. STK = IND ; rsi N289. rax = CALLV stub; rdi,r11,STK N291. CNS_INT 4 N293. NE ; rax N295. JTRUE Var=Reg end of BB09: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB10 [0A9..0AA) -> BB19 (always), preds={BB09} succs={BB19} ===== Predecessor for variable locations: BB09 Var=Reg beg of BB10: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N299. IL_OFFSET IL offset: 0xa9 S N301. V10(rdi)R N303. rdi = PUTARG_REG; rdi N305. V05(r15) N307. rsi = PUTARG_REG; r15 N309. rax = CNS_INT(h) 0xd1ffab1e ftn N311. STK = IND ; rax N313. CALL r2r_ind; rdi,rsi,STK N315. IL_OFFSET IL offset: 0xa9 Var=Reg end of BB10: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} ===== Predecessor for variable locations: BB05 Var=Reg beg of BB12: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N319. IL_OFFSET IL offset: 0x72 N321. V00(rdi*)R N323. rdi = PUTARG_REG; rdi* N325. V02(rbx) N327. rsi = PUTARG_REG; rbx N329. V03(r14) N331. rdx = PUTARG_REG; r14 N333. V04(r13) N335. rcx = PUTARG_REG; r13 N337. V05(r15) N339. r8 = PUTARG_REG; r15 N341. rax = CNS_INT(h) 0xd1ffab1e ftn N343. STK = IND ; rax N345. rax = CALL r2r_ind; rdi,rsi,rdx,rcx,r8,STK N347. CNS_INT 0 N349. EQ ; rax N351. JTRUE Var=Reg end of BB12: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} ===== Predecessor for variable locations: BB12 Var=Reg beg of BB13: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 Var=Reg end of BB13: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} ===== Predecessor for variable locations: BB09 Var=Reg beg of BB14: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N357. IL_OFFSET IL offset: 0xa9 N359. V03(r14) N361. rdi = PUTARG_REG; r14 S N363. V10(rsi)R N365. rsi = PUTARG_REG; rsi N367. V05(r15) N369. rdx = PUTARG_REG; r15 N371. rax = CNS_INT(h) 0xd1ffab1e ftn N373. STK = IND ; rax N375. rax = CALL r2r_ind; rdi,rsi,rdx,STK N377. rsi = CAST ; rax * N379. V19(rsi); rsi N381. V19(rsi*) N383. CNS_INT 0 N385. EQ ; rsi* N387. JTRUE Var=Reg end of BB14: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB15 [0E1..0EA) -> BB09 (cond), preds={BB14,BB21} succs={BB16,BB09} ===== Predecessor for variable locations: BB14 Var=Reg beg of BB15: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N391. IL_OFFSET IL offset: 0xe1 N393. rsi = CNS_INT(h) 0xd1ffab1e class N395. rsi = IND ; rsi N397. rsi = PUTARG_REG; rsi N399. rdi = LCL_VAR_ADDR V08 loc2 rdi ref V08._array (offs=0x00) -> V21 tmp10 int V08._index (offs=0x08) -> V22 tmp11 N401. rdi = PUTARG_REG; rdi N403. rax = CNS_INT(h) 0xd1ffab1e ftn N405. STK = IND ; rax N407. rax = CALL r2r_ind; rsi,rdi,STK N409. CNS_INT 0 N411. NE ; rax N413. JTRUE Var=Reg end of BB15: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} ===== Predecessor for variable locations: BB06 Var=Reg beg of BB16: none Var=Reg end of BB16: none BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB17: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N419. V02(rbx) N421. rdi = PUTARG_REG; rbx N423. V03(r14) N425. rsi = PUTARG_REG; r14 N427. V04(r13) N429. rdx = PUTARG_REG; r13 N431. rax = CNS_INT(h) 0xd1ffab1e ftn N433. STK = IND ; rax N435. rax = CALL r2r_ind; rdi,rsi,rdx,STK N437. CNS_INT 0 N439. NE ; rax N441. JTRUE Var=Reg end of BB17: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB18: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N445. IL_OFFSET IL offset: 0x68 N447. rdi = CNS_INT 0 * N449. V07(rax); rdi $ N001. V07(rax) Var=Reg end of BB18: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB10} succs={BB20,BB21} ===== Predecessor for variable locations: BB10 Var=Reg beg of BB19: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N453. IL_OFFSET IL offset: 0xb5 N455. V04(r13) N457. CNS_INT null N459. EQ ; r13 N461. JTRUE Var=Reg end of BB19: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB20 [0B9..0DF), preds={BB19} succs={BB21} ===== Predecessor for variable locations: BB19 Var=Reg beg of BB20: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N465. IL_OFFSET IL offset: 0xb9 N467. rdi = CNS_INT 2 N469. rdi = PUTARG_REG; rdi N471. rax = CNS_INT(h) 0xd1ffab1e ftn N473. STK = IND ; rax N475. rax = CALL help r2r_ind; rdi,STK * N477. V14(rax); rax N479. CNS_INT 0 N481. V14(rax) N483. STK = LEA(b+8) ; rax N485. rdx = IND ; STK * N487. V28(rdx); rdx S N489. V28(rdx) N491. ARR_BOUNDS_CHECK_Rng; rdx S N493. V14(rax) N495. rdi = LEA(b+16); rax N497. V03(r14) N499. STOREIND ; rdi,r14 N501. CNS_INT 1 N503. V28(STK*) N505. ARR_BOUNDS_CHECK_Rng S N507. V14(rax)R N509. rdi = LEA(b+24); rax N511. V10(rsi*)R N513. STOREIND ; rdi,rsi* N515. rax = CNS_INT(h) 0xd1ffab1e ftn N517. STK = IND ; rax N519. rax = CALL help r2r_ind; STK N521. V20(STK); rax N523. rdi = CNS_INT(h) 0xd1ffab1e ftn N525. STK = IND ; rdi N527. rax = CALL help r2r_ind; STK N529. STK = LEA(b+1048); rax N531. rsi = IND ; STK * N533. V27(rsi); rsi N535. V27(rsi*) N537. rsi = PUTARG_REG; rsi* S N539. V20(rdi)R N541. rdi = PUTARG_REG; rdi N543. V14(rcx*)R N545. rcx = PUTARG_REG; rcx* N547. rdx = CNS_INT 0x7D2C N549. rdx = PUTARG_REG; rdx N551. rax = CNS_INT(h) 0xd1ffab1e ftn N553. STK = IND ; rax N555. CALL r2r_ind; rsi,rdi,rcx,rdx,STK N557. rdi = CNS_INT 0 N559. LCL_VAR_ADDR V15 tmp4 NA N561. STORE_BLK; rdi N563. V02(rbx) N565. V15 MEM; rbx N567. V20(rdi*)R N569. V15 MEM; rdi* N571. IL_OFFSET IL offset: 0xda N573. LCL_VAR_ADDR V15 tmp4 u:4 NA (last use) N575. OBJ N577. PUTARG_STK [+0x00] N579. V04(r13) N581. rdi = PUTARG_REG; r13 N583. r11 = CNS_INT(h) 0xd1ffab1e ftn N585. r11 = PUTARG_REG; r11 N587. rax = CNS_INT(h) 0xd1ffab1e ftn N589. STK = IND ; rax N591. CALLV stub; rdi,r11,STK Var=Reg end of BB20: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} ===== Predecessor for variable locations: BB19 Var=Reg beg of BB21: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N595. IL_OFFSET IL offset: 0xdf N597. rax = CNS_INT 0 N599. V07(STK); rax Var=Reg end of BB21: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} ===== Predecessor for variable locations: BB03 Var=Reg beg of BB22: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N603. IL_OFFSET IL offset: 0x48 N605. V02(rbx) N607. rdi = PUTARG_REG; rbx N609. V03(r14) N611. rsi = PUTARG_REG; r14 N613. V04(r13) N615. rdx = PUTARG_REG; r13 N617. rcx = CNS_INT(h) 0xd1ffab1e ftn N619. STK = IND ; rcx N621. rax = CALL r2r_ind; rdi,rsi,rdx,STK N623. CNS_INT 0 N625. NE ; rax N627. JTRUE Var=Reg end of BB22: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} ===== Predecessor for variable locations: BB03 Var=Reg beg of BB23: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N631. IL_OFFSET IL offset: 0x53 N633. rax = CNS_INT 0 * N635. V07(rax); rax $ N001. V07(rax) Var=Reg end of BB23: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB24: none N639. IL_OFFSET IL offset: 0x8 N641. CNS_INT 1 * N643. V06(rax) Var=Reg end of BB24: V06=rax BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} ===== Predecessor for variable locations: BB02 Var=Reg beg of BB25: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N647. IL_OFFSET IL offset: 0x19 N649. V04(r13) N651. CNS_INT null N653. EQ ; r13 N655. JTRUE Var=Reg end of BB25: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB26 [01D..03E), preds={BB25} succs={BB27} ===== Predecessor for variable locations: BB25 Var=Reg beg of BB26: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N659. IL_OFFSET IL offset: 0x1d N661. rdi = CNS_INT 1 N663. rdi = PUTARG_REG; rdi N665. rax = CNS_INT(h) 0xd1ffab1e ftn N667. STK = IND ; rax N669. rax = CALL help r2r_ind; rdi,STK * N671. V16(rax); rax N673. CNS_INT 0 N675. V16(rax) N677. STK = LEA(b+8) ; rax N679. STK = IND ; STK N681. ARR_BOUNDS_CHECK_Rng; STK S N683. V16(rax) N685. rdi = LEA(b+16); rax N687. V03(r14) N689. STOREIND ; rdi,r14 N691. rax = CNS_INT(h) 0xd1ffab1e ftn N693. STK = IND ; rax N695. rax = CALL help r2r_ind; STK N697. V18(STK); rax N699. rdi = CNS_INT(h) 0xd1ffab1e ftn N701. STK = IND ; rdi N703. rax = CALL help r2r_ind; STK N705. STK = LEA(b+1048); rax N707. rsi = IND ; STK * N709. V24(rsi); rsi N711. V24(rsi*) N713. rsi = PUTARG_REG; rsi* S N715. V18(rdi)R N717. rdi = PUTARG_REG; rdi N719. V16(rcx*)R N721. rcx = PUTARG_REG; rcx* N723. rdx = CNS_INT 0x7AA4 N725. rdx = PUTARG_REG; rdx N727. rax = CNS_INT(h) 0xd1ffab1e ftn N729. STK = IND ; rax N731. CALL r2r_ind; rsi,rdi,rcx,rdx,STK N733. rdi = LCL_VAR_ADDR V17 tmp6 rdi N735. rdi = PUTARG_REG; rdi N737. V02(rbx) N739. rsi = PUTARG_REG; rbx N741. V18(rdx*)R N743. rdx = PUTARG_REG; rdx* N745. rax = CNS_INT(h) 0xd1ffab1e ftn N747. STK = IND ; rax N749. CALL r2r_ind; rdi,rsi,rdx,STK N751. IL_OFFSET IL offset: 0x39 N753. LCL_VAR_ADDR V17 tmp6 NA N755. OBJ N757. PUTARG_STK [+0x00] N759. V04(r13) N761. rdi = PUTARG_REG; r13 N763. r11 = CNS_INT(h) 0xd1ffab1e ftn N765. r11 = PUTARG_REG; r11 N767. rax = CNS_INT(h) 0xd1ffab1e ftn N769. STK = IND ; rax N771. CALLV stub; rdi,r11,STK Var=Reg end of BB26: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} ===== Predecessor for variable locations: BB25 Var=Reg beg of BB27: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N775. IL_OFFSET IL offset: 0x3e N777. rax = CNS_INT 0 * N779. V07(rax); rax $ N001. V07(rax) Var=Reg end of BB27: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} ===== Predecessor for variable locations: BB12 Var=Reg beg of BB28: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 N783. IL_OFFSET IL offset: 0x80 N785. rax = CNS_INT 0 * N787. V07(rax); rax $ N001. V07(rax) Var=Reg end of BB28: V02=rbx V03=r14 V05=r15 V01=r12 V04=r13 BB29 [???..???) (throw), preds={} succs={} ===== Predecessor for variable locations: BB28 Var=Reg beg of BB29: none N791. CALL help Var=Reg end of BB29: none *************** Finishing PHASE Linear scan register alloc *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight IBC lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 20988 [000..008)-> BB24 ( cond ) i label target gcsafe IBC LIR BB02 [0002] 1 BB01 1 20988 [00F..019)-> BB25 ( cond ) i label target gcsafe IBC LIR BB03 [0006] 2 BB02,BB27 1 20988 [040..048)-> BB22 ( cond ) i label target gcsafe IBC LIR BB04 [0009] 3 BB03,BB22,BB23 1 20988 [055..05D)-> BB17 ( cond ) i label target gcsafe IBC LIR BB05 [0012] 3 BB04,BB17,BB18 1 20988 [06A..072)-> BB12 ( cond ) i label target gcsafe IBC LIR BB06 [0015] 3 BB05,BB13,BB28 1 20988 [082..095)-> BB09 ( cond ) i label target gcsafe IBC LIR BB07 [0021] 2 BB06,BB16 1 20988 [0EA..0EC) i label target gcsafe IBC LIR BB08 [0022] 2 BB24,BB07 1 20988 [0EC..0EE) (return) i label target gcsafe IBC LIR BB09 [0016] 2 BB06,BB15 0.29 6120 [095..0B5)-> BB14 ( cond ) i Loop label target gcsafe bwd bwd-target IBC LIR BB10 [0027] 1 BB09 0.58 [0A9..0AA)-> BB19 (always) i gcsafe bwd LIR BB12 [0013] 1 BB05 0.01 87 [072..080)-> BB28 ( cond ) i label target gcsafe IBC LIR BB13 [0036] 1 BB12 0.01 87 [???..???)-> BB06 (always) internal gcsafe IBC LIR BB14 [0028] 1 BB09 0.29 6120 [0A9..0AA)-> BB19 ( cond ) i label target gcsafe bwd IBC LIR BB15 [0020] 2 BB14,BB21 0.29 6120 [0E1..0EA)-> BB09 ( cond ) i Loop label target gcsafe bwd IBC LIR BB16 [0035] 1 BB15 0.15 [???..???)-> BB07 (always) internal gcsafe LIR BB17 [0010] 1 BB04 0.03 614 [05D..068)-> BB05 ( cond ) i label target gcsafe IBC LIR BB18 [0011] 1 BB17 0.01 22 [068..06A)-> BB05 (always) i gcsafe IBC LIR BB19 [0017] 2 BB14,BB10 0.02 479 [0B5..0B9)-> BB21 ( cond ) i label target gcsafe bwd IBC LIR BB20 [0018] 1 BB19 0.02 479 [0B9..0DF) i gcsafe idxlen new[] newobj bwd IBC LIR BB21 [0019] 2 BB19,BB20 0.02 479 [0DF..0E1)-> BB15 (always) i label target gcsafe bwd IBC LIR BB22 [0007] 1 BB03 0.01 131 [048..053)-> BB04 ( cond ) i label target gcsafe IBC LIR BB23 [0008] 1 BB22 0 0 [053..055)-> BB04 (always) i rare gcsafe IBC LIR BB24 [0001] 1 BB01 0 0 [008..00F)-> BB08 (always) i rare label target gcsafe IBC LIR BB25 [0003] 1 BB02 0 0 [019..01D)-> BB27 ( cond ) i rare label target gcsafe IBC LIR BB26 [0004] 1 BB25 0 0 [01D..03E) i rare gcsafe idxlen new[] newobj IBC LIR BB27 [0005] 2 BB25,BB26 0 0 [03E..040)-> BB03 (always) i rare label target gcsafe IBC LIR BB28 [0014] 1 BB12 0 0 [080..082)-> BB06 (always) i rare label target gcsafe IBC LIR BB29 [0038] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Modified regs: [rax rcx rdx rbx rsi rdi r8-r15 mm0-mm15] Callee-saved registers pushed: 5 [rbx r12-r15] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V07 loc1, size=4, stkOffs=-0x3c Pad V08 loc2, size=16, stkOffs=-0x40, pad=4 Assign V08 loc2, size=16, stkOffs=-0x50 Assign V09 loc3, size=8, stkOffs=-0x58 Assign V12 tmp1, size=16, stkOffs=-0x68 Assign V13 tmp2, size=16, stkOffs=-0x78 Assign V15 tmp4, size=40, stkOffs=-0xa0 Assign V17 tmp6, size=40, stkOffs=-0xc8 Assign V28 cse0, size=4, stkOffs=-0xcc Pad V00 arg0, size=8, stkOffs=-0xd0, pad=4 Assign V00 arg0, size=8, stkOffs=-0xd8 Assign V10 loc4, size=8, stkOffs=-0xe0 Assign V14 tmp3, size=8, stkOffs=-0xe8 Assign V16 tmp5, size=8, stkOffs=-0xf0 Assign V18 tmp7, size=8, stkOffs=-0xf8 Assign V20 tmp9, size=8, stkOffs=-0x100 Assign V11 OutArgs, size=40, stkOffs=-0x128 --- delta bump 8 for RA --- delta bump 8 for FP --- delta bump 0 for RBP frame --- virtual stack offset to actual stack offset delta is 16 -- V00 was -216, now -200 -- V01 was 0, now 16 -- V02 was 0, now 16 -- V03 was 0, now 16 -- V04 was 0, now 16 -- V05 was 0, now 16 -- V07 was -60, now -44 -- V08 was -80, now -64 -- V09 was -88, now -72 -- V10 was -224, now -208 -- V11 was -296, now -280 -- V12 was -104, now -88 -- V13 was -120, now -104 -- V14 was -232, now -216 -- V15 was -160, now -144 -- V16 was -240, now -224 -- V17 was -200, now -184 -- V18 was -248, now -232 -- V20 was -256, now -240 -- V28 was -204, now -188 ; Final local variable assignments ; ; V00 arg0 [V00,T06] ( 3, 2.01) ref -> [rbp-0xC8] class-hnd ; V01 arg1 [V01,T04] ( 3, 2.29) ref -> r12 class-hnd ; V02 arg2 [V02,T00] ( 11, 6.07) ref -> rbx class-hnd ; V03 arg3 [V03,T01] ( 10, 4.36) ref -> r14 class-hnd ; V04 arg4 [V04,T05] ( 9, 2.09) ref -> r13 class-hnd ; V05 arg5 [V05,T03] ( 6, 3.88) byref -> r15 ; V06 loc0 [V06,T08] ( 3, 2 ) bool -> rax ; V07 loc1 [V07,T07] ( 7, 2.03) bool -> [rbp-0x2C] ; V08 loc2 [V08 ] ( 5, 3.58) struct (16) [rbp-0x40] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V09 loc3 [V09 ] ( 2, 2 ) struct ( 8) [rbp-0x48] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V10 loc4 [V10,T09] ( 5, 1.47) ref -> [rbp-0xD0] class-hnd ; V11 OutArgs [V11 ] ( 1, 1 ) lclBlk (40) [rsp+0x00] "OutgoingArgSpace" ; V12 tmp1 [V12 ] ( 2, 4 ) struct (16) [rbp-0x58] do-not-enreg[XSBR] multireg-ret must-init addr-exposed "Return value temp for multireg return" ; V13 tmp2 [V13,T12] ( 2, 1.16) struct (16) [rbp-0x68] do-not-enreg[SFR] multireg-ret must-init "Return value temp for multireg return" ; V14 tmp3 [V14,T13] ( 5, 0.20) ref -> [rbp-0xD8] class-hnd exact "dup spill" ; V15 tmp4 [V15,T14] ( 4, 0.16) struct (40) [rbp-0x90] do-not-enreg[SFB] must-init "NewObj constructor temp" ; V16 tmp5 [V16,T18] ( 4, 0 ) ref -> [rbp-0xE0] class-hnd exact "dup spill" ; V17 tmp6 [V17 ] ( 2, 0 ) struct (40) [rbp-0xB8] do-not-enreg[XS] must-init addr-exposed "NewObj constructor temp" ; V18 tmp7 [V18,T19] ( 3, 0 ) ref -> [rbp-0xE8] class-hnd exact "NewObj constructor temp" ; V19 tmp8 [V19,T10] ( 2, 0.58) bool -> rsi "Inline stloc first use temp" ; V20 tmp9 [V20,T15] ( 3, 0.12) ref -> [rbp-0xF0] class-hnd exact "NewObj constructor temp" ; V21 tmp10 [V21 ] ( 4, 2.58) ref -> [rbp-0x40] do-not-enreg[X] addr-exposed V08._array(offs=0x00) P-DEP "field V08._array (fldOffset=0x0)" ; V22 tmp11 [V22 ] ( 4, 2.58) int -> [rbp-0x38] do-not-enreg[X] addr-exposed V08._index(offs=0x08) P-DEP "field V08._index (fldOffset=0x8)" ; V23 tmp12 [V23 ] ( 2, 2 ) ref -> [rbp-0x48] do-not-enreg[X] addr-exposed V09.array(offs=0x00) P-DEP "field V09.array (fldOffset=0x0)" ; V24 tmp13 [V24,T20] ( 2, 0 ) ref -> rsi "argument with side effect" ; V25 tmp14 [V25,T02] ( 3, 6 ) byref -> rsi "BlockOp address local" ; V26 tmp15 [V26,T11] ( 2, 1.16) ref -> rdi "argument with side effect" ; V27 tmp16 [V27,T16] ( 2, 0.08) ref -> rsi "argument with side effect" ; V28 cse0 [V28,T17] ( 3, 0.06) int -> [rbp-0xBC] "CSE - conservative" ; ; Lcl frame size = 248 Setting stack level from -572662307 to 0 =============== Generating BB01 [000..008) -> BB24 (cond), preds={} succs={BB02,BB24} flags=0x00000004.600b0020: i label target gcsafe IBC LIR BB01 IN (6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap Recording Var Locations at start of BB01 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Change life 0000000000000000 {} -> 000000000000007B {V00 V01 V02 V03 V04 V05} V02 in reg rbx is becoming live [------] Live regs: 00000000 {} => 00000008 {rbx} V03 in reg r14 is becoming live [------] Live regs: 00000008 {rbx} => 00004008 {rbx r14} V05 in reg r15 is becoming live [------] Live regs: 00004008 {rbx r14} => 0000C008 {rbx r14 r15} V01 in reg r12 is becoming live [------] Live regs: 0000C008 {rbx r14 r15} => 0000D008 {rbx r12 r14 r15} V04 in reg r13 is becoming live [------] Live regs: 0000D008 {rbx r12 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} V00 becoming live Live regs: (unchanged) 0000F008 {rbx r12 r13 r14 r15} GC regs: (unchanged) 00007008 {rbx r12 r13 r14} Byref regs: (unchanged) 00008000 {r15} L_M22628_BB01: Label: IG02, GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB01, IL range [000..008) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) Generating: N003 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t0 ref Generating: N005 (???,???) [000508] ------------ t508 = * PUTARG_REG ref REG rdi IN0001: mov rdi, r14 GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N007 ( 3, 10) [000279] ------------ t279 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 IN0002: mov r11, (reloc 0xd1ffab1e) /--* t279 long Generating: N009 (???,???) [000509] ------------ t509 = * PUTARG_REG long REG r11 Generating: N011 ( 3, 10) [000510] ------------ t510 = CNS_INT(h) long 0xd1ffab1e ftn REG rsi IN0003: mov rsi, (reloc 0xd1ffab1e) /--* t510 long Generating: N013 ( 5, 12) [000511] -c---------- t511 = * IND long REG NA /--* t508 ref this in rdi +--* t509 long arg1 in r11 +--* t511 long control expr Generating: N015 ( 24, 21) [000198] --CXG------- t198 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind REG rax $200 GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN0004: cmp dword ptr [rdi], edi Call: GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0005: call qword ptr [rsi]Microsoft.CodeAnalysis.VisualBasic.Symbol:get_Kind():int:this Generating: N017 ( 1, 1) [000199] -c---------- t199 = CNS_INT int 4 REG NA $44 /--* t198 int +--* t199 int Generating: N019 ( 26, 23) [000200] J--XG--N---- * EQ void REG NA $280 IN0006: cmp eax, 4 Generating: N021 ( 28, 25) [000006] ---XG------- * JTRUE void REG NA IN0007: je L_M22628_BB24 Scope info: end block BB01, IL range [000..008) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) =============== Generating BB02 [00F..019) -> BB25 (cond), preds={BB01} succs={BB03,BB25} flags=0x00000004.600b0020: i label target gcsafe IBC LIR BB02 IN (6)={V02 V03 V05 V01 V04 V00 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB02 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Liveness not changing: 000000000000007B {V00 V01 V02 V03 V04 V05} Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB02: G_M22628_IG02: ; offs=000000H, funclet=00, bbWeight=1 Label: IG03, GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB02, IL range [00F..019) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) Added IP mapping: 0x000F STACK_EMPTY (G_M22628_IG03,ins#0,ofs#0) label Generating: N025 (???,???) [000472] ------------ IL_OFFSET void IL offset: 0xf REG NA Generating: N027 ( 1, 1) [000007] -c---------- t7 = CNS_INT int 1 REG NA $41 /--* t7 int Generating: N029 ( 5, 4) [000009] DA---------- * STORE_LCL_VAR int V07 loc1 d:2 NA REG NA IN0008: mov dword ptr [V07 rbp-2CH], 1 Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V07} Generating: N031 ( 1, 1) [000010] ------------ t10 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t10 ref Generating: N033 (???,???) [000512] ------------ t512 = * PUTARG_REG ref REG rdi IN0009: mov rdi, r14 GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N035 ( 3, 10) [000284] ------------ t284 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c1 IN000a: mov r11, (reloc 0xd1ffab1e) /--* t284 long Generating: N037 (???,???) [000513] ------------ t513 = * PUTARG_REG long REG r11 Generating: N039 ( 3, 10) [000514] ------------ t514 = CNS_INT(h) long 0xd1ffab1e ftn REG rsi IN000b: mov rsi, (reloc 0xd1ffab1e) /--* t514 long Generating: N041 ( 5, 12) [000515] -c---------- t515 = * IND long REG NA /--* t512 ref this in rdi +--* t513 long arg1 in r11 +--* t515 long control expr Generating: N043 ( 24, 21) [000202] --CXG------- t202 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.get_SpecialType REG rax $204 GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} Call: GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN000c: call qword ptr [rsi]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol:get_SpecialType():byte:this /--* t202 int Generating: N045 ( 25, 23) [000203] ---XG------- t203 = * CAST int <- byte <- int REG rdi $281 IN000d: movsx rdi, al /--* t203 int Generating: N047 (???,???) [000516] ---XG------- t516 = * PUTARG_REG int REG rdi Generating: N049 ( 3, 10) [000517] ------------ t517 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN000e: mov rax, (reloc 0xd1ffab1e) /--* t517 long Generating: N051 ( 5, 12) [000518] -c---------- t518 = * IND long REG NA /--* t516 int arg0 in rdi +--* t518 long control expr Generating: N053 ( 39, 29) [000204] --CXG------- t204 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions.IsRestrictedType REG rax $205 Call: GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN000f: call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions:IsRestrictedType(byte):bool Generating: N055 ( 1, 1) [000014] -c---------- t14 = CNS_INT bool 0 REG NA $40 /--* t204 bool +--* t14 bool Generating: N057 ( 42, 33) [000015] J--XG--N-U-- * NE void REG NA $283 IN0010: test al, al Generating: N059 ( 44, 35) [000016] ---XG------- * JTRUE void REG NA IN0011: jne L_M22628_BB25 Scope info: end block BB02, IL range [00F..019) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) =============== Generating BB03 [040..048) -> BB22 (cond), preds={BB02,BB27} succs={BB04,BB22} flags=0x00000004.600b0020: i label target gcsafe IBC LIR BB03 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB03 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Liveness not changing: 00000000000000FB {V00 V01 V02 V03 V04 V05 V07} Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB03: G_M22628_IG03: ; offs=000024H, funclet=00, bbWeight=1 Label: IG04, GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB03, IL range [040..048) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) 7 (V07 loc1) [000..0EE) Added IP mapping: 0x0040 STACK_EMPTY (G_M22628_IG04,ins#0,ofs#0) label Generating: N063 (???,???) [000473] ------------ IL_OFFSET void IL offset: 0x40 REG NA Generating: N065 ( 1, 1) [000017] ------------ t17 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t17 ref Generating: N067 (???,???) [000519] ------------ t519 = * PUTARG_REG ref REG rdi IN0012: mov rdi, rbx GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N069 ( 3, 10) [000312] ------------ t312 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ca IN0013: mov r11, (reloc 0xd1ffab1e) /--* t312 long Generating: N071 (???,???) [000520] ------------ t520 = * PUTARG_REG long REG r11 Generating: N073 ( 3, 10) [000521] ------------ t521 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN0014: mov rax, (reloc 0xd1ffab1e) /--* t521 long Generating: N075 ( 5, 12) [000522] -c---------- t522 = * IND long REG NA /--* t519 ref this in rdi +--* t520 long arg1 in r11 +--* t522 long control expr Generating: N077 ( 24, 21) [000018] --CXG------- t18 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasConstructorConstraint REG rax $208 GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN0015: cmp dword ptr [rdi], edi Call: GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0016: call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasConstructorConstraint():bool:this Generating: N079 ( 1, 1) [000020] -c---------- t20 = CNS_INT bool 0 REG NA $40 /--* t18 bool +--* t20 bool Generating: N081 ( 27, 25) [000021] J--XG--N-U-- * NE void REG NA $287 IN0017: test al, al Generating: N083 ( 29, 27) [000022] ---XG------- * JTRUE void REG NA IN0018: jne L_M22628_BB22 Scope info: end block BB03, IL range [040..048) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) 7 (V07 loc1) [000..0EE) =============== Generating BB04 [055..05D) -> BB17 (cond), preds={BB03,BB22,BB23} succs={BB05,BB17} flags=0x00000004.600b0020: i label target gcsafe IBC LIR BB04 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB04 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Liveness not changing: 00000000000000FB {V00 V01 V02 V03 V04 V05 V07} Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB04: G_M22628_IG04: ; offs=00005CH, funclet=00, bbWeight=1 Label: IG05, GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB04, IL range [055..05D) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) 7 (V07 loc1) [000..0EE) Added IP mapping: 0x0055 STACK_EMPTY (G_M22628_IG05,ins#0,ofs#0) label Generating: N087 (???,???) [000474] ------------ IL_OFFSET void IL offset: 0x55 REG NA Generating: N089 ( 1, 1) [000023] ------------ t23 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t23 ref Generating: N091 (???,???) [000523] ------------ t523 = * PUTARG_REG ref REG rdi IN0019: mov rdi, rbx GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N093 ( 3, 10) [000319] ------------ t319 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1cc IN001a: mov r11, (reloc 0xd1ffab1e) /--* t319 long Generating: N095 (???,???) [000524] ------------ t524 = * PUTARG_REG long REG r11 Generating: N097 ( 3, 10) [000525] ------------ t525 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN001b: mov rax, (reloc 0xd1ffab1e) /--* t525 long Generating: N099 ( 5, 12) [000526] -c---------- t526 = * IND long REG NA /--* t523 ref this in rdi +--* t524 long arg1 in r11 +--* t526 long control expr Generating: N101 ( 24, 21) [000024] --CXG------- t24 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasReferenceTypeConstraint REG rax $20b GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} Call: GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN001c: call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasReferenceTypeConstraint():bool:this Generating: N103 ( 1, 1) [000026] -c---------- t26 = CNS_INT bool 0 REG NA $40 /--* t24 bool +--* t26 bool Generating: N105 ( 27, 25) [000027] J--XG--N-U-- * NE void REG NA $28b IN001d: test al, al Generating: N107 ( 29, 27) [000028] ---XG------- * JTRUE void REG NA IN001e: jne L_M22628_BB17 Scope info: end block BB04, IL range [055..05D) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) 7 (V07 loc1) [000..0EE) =============== Generating BB05 [06A..072) -> BB12 (cond), preds={BB04,BB17,BB18} succs={BB06,BB12} flags=0x00000004.600b0020: i label target gcsafe IBC LIR BB05 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB05 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Liveness not changing: 00000000000000FB {V00 V01 V02 V03 V04 V05 V07} Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB05: G_M22628_IG05: ; offs=00007FH, funclet=00, bbWeight=1 Label: IG06, GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB05, IL range [06A..072) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) 7 (V07 loc1) [000..0EE) Added IP mapping: 0x006A STACK_EMPTY (G_M22628_IG06,ins#0,ofs#0) label Generating: N111 (???,???) [000475] ------------ IL_OFFSET void IL offset: 0x6a REG NA Generating: N113 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t29 ref Generating: N115 (???,???) [000527] ------------ t527 = * PUTARG_REG ref REG rdi IN001f: mov rdi, rbx GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N117 ( 3, 10) [000326] ------------ t326 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1ce IN0020: mov r11, (reloc 0xd1ffab1e) /--* t326 long Generating: N119 (???,???) [000528] ------------ t528 = * PUTARG_REG long REG r11 Generating: N121 ( 3, 10) [000529] ------------ t529 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN0021: mov rax, (reloc 0xd1ffab1e) /--* t529 long Generating: N123 ( 5, 12) [000530] -c---------- t530 = * IND long REG NA /--* t527 ref this in rdi +--* t528 long arg1 in r11 +--* t530 long control expr Generating: N125 ( 24, 21) [000030] --CXG------- t30 = * CALLV stub bool Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.get_HasValueTypeConstraint REG rax $20e GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} Call: GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0022: call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasValueTypeConstraint():bool:this Generating: N127 ( 1, 1) [000032] -c---------- t32 = CNS_INT bool 0 REG NA $40 /--* t30 bool +--* t32 bool Generating: N129 ( 27, 25) [000033] J--XG--N-U-- * NE void REG NA $28f IN0023: test al, al Generating: N131 ( 29, 27) [000034] ---XG------- * JTRUE void REG NA IN0024: jne L_M22628_BB12 Scope info: end block BB05, IL range [06A..072) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) 7 (V07 loc1) [000..0EE) =============== Generating BB06 [082..095) -> BB09 (cond), preds={BB05,BB13,BB28} succs={BB07,BB09} flags=0x00000004.600b0020: i label target gcsafe IBC LIR BB06 IN (6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB06 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Change life 00000000000000FB {V00 V01 V02 V03 V04 V05 V07} -> 00000000000000BB {V01 V02 V03 V04 V05 V07} V00 becoming dead Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB06: G_M22628_IG06: ; offs=0000A0H, funclet=00, bbWeight=1 Label: IG07, GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB06, IL range [082..095) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 7 (V07 loc1) [000..0EE) Generating: N135 ( 1, 1) [000035] ------------ t35 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t35 ref Generating: N137 (???,???) [000531] ------------ t531 = * PUTARG_REG ref REG rdi IN0025: mov rdi, rbx GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N139 ( 1, 1) [000036] ------------ t36 = LCL_VAR byref V05 arg5 u:1 r15 REG r15 $c0 /--* t36 byref Generating: N141 (???,???) [000532] ------------ t532 = * PUTARG_REG byref REG rsi IN0026: mov rsi, r15 Byref regs: 00008000 {r15} => 00008040 {rsi r15} Generating: N143 ( 3, 10) [000533] ------------ t533 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN0027: mov rax, (reloc 0xd1ffab1e) /--* t533 long Generating: N145 ( 5, 12) [000534] -c---------- t534 = * IND long REG NA /--* t531 ref this in rdi +--* t532 byref arg1 in rsi +--* t534 long control expr Generating: N147 ( 16, 10) [000037] --CXG------- t37 = * CALL r2r_ind ref Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol.ConstraintTypesWithDefinitionUseSiteDiagnostics REG rax $167 GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} Byref regs: 00008040 {rsi r15} => 00008000 {r15} Call: GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0028: call gword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:ConstraintTypesWithDefinitionUseSiteDiagnostics(byref):System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]:this GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} /--* t37 ref Generating: N149 ( 20, 13) [000042] DA-XG------- * STORE_LCL_VAR ref (AX) V23 tmp12 NA REG NA GC regs: 00007009 {rax rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN0029: mov gword ptr [V23 rbp-48H], rax Added IP mapping: 0x008B STACK_EMPTY (G_M22628_IG07,ins#5,ofs#22) label Generating: N151 (???,???) [000476] ------------ IL_OFFSET void IL offset: 0x8b REG NA Generating: N153 ( 3, 10) [000046] ------------ t46 = CNS_INT(h) long 0xd1ffab1e class REG rsi $1d0 IN002a: mov rsi, (reloc 0xd1ffab1e) /--* t46 long Generating: N155 ( 5, 12) [000047] n----------- t47 = * IND long REG rsi IN002b: mov rsi, qword ptr [rsi] /--* t47 long Generating: N157 (???,???) [000535] ------------ t535 = * PUTARG_REG long REG rsi Generating: N159 ( 3, 2) [000043] -------N---- t43 = LCL_VAR_ADDR byref V09 loc3 rdi * ref V09.array (offs=0x00) -> V23 tmp12 REG rdi IN002c: lea rdi, bword ptr [V09 rbp-48H] Byref regs: 00008000 {r15} => 00008080 {rdi r15} /--* t43 byref Generating: N161 (???,???) [000536] ------------ t536 = * PUTARG_REG byref REG rdi Byref regs: 00008080 {rdi r15} => 00008000 {r15} Byref regs: 00008000 {r15} => 00008080 {rdi r15} Generating: N163 ( 3, 10) [000537] ------------ t537 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN002d: mov rax, (reloc 0xd1ffab1e) /--* t537 long Generating: N165 ( 5, 12) [000538] -c---------- t538 = * IND long REG NA /--* t535 long arg1 in rsi +--* t536 byref this in rdi +--* t538 long control expr Generating: N167 ( 22, 23) [000045] --CXG------- t45 = * CALL r2r_ind struct System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon].GetEnumerator REG rax,rdx $501 Byref regs: 00008080 {rdi r15} => 00008000 {r15} Call: GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN002e: call gword ptr [rax]System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:GetEnumerator():Enumerator[__Canon]:this GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} /--* t45 struct Generating: N169 ( 26, 26) [000050] DA-XG------- * STORE_LCL_VAR struct(AX) V12 tmp1 NA REG NA GC regs: 00007009 {rax rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN002f: mov gword ptr [V12 rbp-58H], rax IN0030: mov qword ptr [V12+0x8 rbp-50H], rdx Generating: N171 ( 3, 2) [000341] -------N---- t341 = LCL_VAR_ADDR byref V12 tmp1 rsi REG rsi IN0031: lea rsi, bword ptr [V12 rbp-58H] Byref regs: 00008000 {r15} => 00008040 {rsi r15} /--* t341 byref Generating: N173 ( 3, 3) [000343] DA---------- * STORE_LCL_VAR byref V25 tmp14 d:2 rsi REG rsi Byref regs: 00008040 {rsi r15} => 00008000 {r15} V25 in reg rsi is becoming live [000343] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F048 {rbx rsi r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V07} => {V01 V02 V03 V04 V05 V07 V25} Byref regs: 00008000 {r15} => 00008040 {rsi r15} Generating: N175 ( 1, 1) [000345] ------------ t345 = LCL_VAR byref V25 tmp14 u:2 rsi Zero Fseq[_array] REG rsi $487 /--* t345 byref Generating: N177 ( 3, 2) [000346] ---X-------- t346 = * IND ref REG rdi IN0032: mov rdi, gword ptr [rsi] GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} /--* t346 ref Generating: N179 ( 7, 5) [000347] DA-XG------- * STORE_LCL_VAR ref (AX) V21 tmp10 NA REG NA GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN0033: mov gword ptr [V21 rbp-40H], rdi Generating: N181 ( 1, 1) [000350] ------------ t350 = LCL_VAR byref V25 tmp14 u:2 rsi (last use) REG rsi $487 /--* t350 byref Generating: N183 ( 2, 2) [000352] -c---------- t352 = * LEA(b+8) byref REG NA /--* t352 byref Generating: N185 ( 4, 4) [000353] n----O------ t353 = * IND int REG rsi V25 in reg rsi is becoming dead [000350] Live regs: 0000F048 {rbx rsi r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V07 V25} => {V01 V02 V03 V04 V05 V07} Byref regs: 00008040 {rsi r15} => 00008000 {r15} IN0034: mov esi, dword ptr [rsi+8] /--* t353 int Generating: N187 ( 8, 7) [000354] DA--GO------ * STORE_LCL_VAR int (AX) V22 tmp11 NA REG NA IN0035: mov dword ptr [V22 rbp-38H], esi Added IP mapping: 0x00E1 STACK_EMPTY (G_M22628_IG07,ins#17,ofs#76) Generating: N189 (???,???) [000477] ------------ IL_OFFSET void IL offset: 0xe1 REG NA Generating: N191 ( 3, 10) [000415] ------------ t415 = CNS_INT(h) long 0xd1ffab1e class REG rsi $1d1 IN0036: mov rsi, (reloc 0xd1ffab1e) /--* t415 long Generating: N193 ( 5, 12) [000414] n----------- t414 = * IND long REG rsi IN0037: mov rsi, qword ptr [rsi] /--* t414 long Generating: N195 (???,???) [000539] ------------ t539 = * PUTARG_REG long REG rsi Generating: N197 ( 3, 2) [000417] ----G--N---- t417 = LCL_VAR_ADDR byref V08 loc2 rdi * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 REG rdi IN0038: lea rdi, bword ptr [V08 rbp-40H] Byref regs: 00008000 {r15} => 00008080 {rdi r15} /--* t417 byref Generating: N199 (???,???) [000540] ----G------- t540 = * PUTARG_REG byref REG rdi Byref regs: 00008080 {rdi r15} => 00008000 {r15} Byref regs: 00008000 {r15} => 00008080 {rdi r15} Generating: N201 ( 3, 10) [000541] ------------ t541 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN0039: mov rax, (reloc 0xd1ffab1e) /--* t541 long Generating: N203 ( 5, 12) [000542] -c---------- t542 = * IND long REG NA /--* t539 long arg1 in rsi +--* t540 byref this in rdi +--* t542 long control expr Generating: N205 ( 22, 23) [000411] --CXG------- t411 = * CALL r2r_ind bool Enumerator[__Canon][System.__Canon].MoveNext REG rax $212 Byref regs: 00008080 {rdi r15} => 00008000 {r15} Call: GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN003a: call qword ptr [rax]Enumerator[__Canon][System.__Canon]:MoveNext():bool:this Generating: N207 ( 1, 1) [000418] -c---------- t418 = CNS_INT bool 0 REG NA $40 /--* t411 bool +--* t418 bool Generating: N209 ( 25, 27) [000409] J--XG--N-U-- * NE void REG NA $295 IN003b: test al, al Generating: N211 ( 27, 29) [000419] ---XG------- * JTRUE void REG NA IN003c: jne L_M22628_BB09 Scope info: end block BB06, IL range [082..095) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 7 (V07 loc1) [000..0EE) =============== Generating BB07 [0EA..0EC), preds={BB06,BB16} succs={BB08} flags=0x00000000.600b0020: i label target gcsafe IBC LIR BB07 IN (1)={V07 } OUT(1)={ V06} Recording Var Locations at start of BB07 Change life 00000000000000BB {V01 V02 V03 V04 V05 V07} -> 0000000000000080 {V07} V02 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V03 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V05 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V01 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V04 in reg r13 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M22628_BB07: G_M22628_IG07: ; offs=0000C1H, funclet=00, bbWeight=1 Label: IG08, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB07, IL range [0EA..0EC) Scope info: open scopes = 7 (V07 loc1) [000..0EE) Added IP mapping: 0x00EA STACK_EMPTY (G_M22628_IG08,ins#0,ofs#0) label Generating: N215 (???,???) [000478] ------------ IL_OFFSET void IL offset: 0xea REG NA Generating: N217 ( 3, 2) [000125] -----------z t125 = LCL_VAR int V07 loc1 u:14 r13 (last use) REG r13 $584 /--* t125 int Generating: N219 ( 7, 5) [000127] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 rax REG rax IN003d: mov r13d, dword ptr [V07 rbp-2CH] V07 in reg r13 is becoming live [000125] Live regs: 00000000 {} => 00002000 {r13} V07 in reg r13 is becoming dead [000125] Live regs: 00002000 {r13} => 00000000 {} Live vars: {V07} => {} IN003e: mov eax, r13d V06 in reg rax is becoming live [000127] Live regs: 00000000 {} => 00000001 {rax} Live vars: {} => {V06} Scope info: end block BB07, IL range [0EA..0EC) Scope info: open scopes = =============== Generating BB08 [0EC..0EE) (return), preds={BB24,BB07} succs={} flags=0x00000000.600b0020: i label target gcsafe IBC LIR BB08 IN (1)={V06} OUT(0)={ } Recording Var Locations at start of BB08 V06(rax) Liveness not changing: 0000000000000100 {V06} Live regs: 00000000 {} => 00000001 {rax} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M22628_BB08: G_M22628_IG08: ; offs=000132H, funclet=00, bbWeight=1 Label: IG09, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB08, IL range [0EC..0EE) Scope info: open scopes = 6 (V06 loc0) [000..0EE) Added IP mapping: 0x00EC STACK_EMPTY (G_M22628_IG09,ins#0,ofs#0) label Generating: N223 (???,???) [000479] ------------ IL_OFFSET void IL offset: 0xec REG NA Generating: N225 ( 3, 2) [000128] ------------ t128 = LCL_VAR int V06 loc0 u:3 rax (last use) REG rax $585 /--* t128 int Generating: N227 ( 4, 3) [000129] ------------ * RETURN int REG NA $214 V06 in reg rax is becoming dead [000128] Live regs: 00000001 {rax} => 00000000 {} Live vars: {V06} => {} Scope info: end block BB08, IL range [0EC..0EE) Scope info: ending scope, LVnum=0 [000..0EE) Scope info: ending scope, LVnum=1 [000..0EE) Scope info: ending scope, LVnum=2 [000..0EE) Scope info: ending scope, LVnum=3 [000..0EE) Scope info: ending scope, LVnum=4 [000..0EE) Scope info: ending scope, LVnum=5 [000..0EE) Scope info: ending scope, LVnum=6 [000..0EE) Scope info: ending scope, LVnum=7 [000..0EE) Scope info: ending scope, LVnum=8 [000..0EE) siEndScope: Failed to end scope for V08 Scope info: ending scope, LVnum=9 [000..0EE) siEndScope: Failed to end scope for V09 Scope info: ending scope, LVnum=10 [000..0EE) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M22628_IG09,ins#0,ofs#0) label Reserving epilog IG for block BB08 *************** After placeholder IG creation G_M22628_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M22628_IG02: ; offs=000000H, size=0024H, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG03: ; offs=000024H, size=0038H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG04: ; offs=00005CH, size=0023H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG05: ; offs=00007FH, size=0021H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG06: ; offs=0000A0H, size=0021H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG07: ; offs=0000C1H, size=0071H, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG08: ; offs=000132H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M22628_IG09: ; epilog placeholder, next placeholder=, BB08 [0022], epilog <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} G_M22628_IG10: ; offs=000239H, size=0000H, gcrefRegs=00000000 {} <-- Current IG =============== Generating BB09 [095..0B5) -> BB14 (cond), preds={BB06,BB15} succs={BB10,BB14} flags=0x00000014.620b2020: i Loop label target gcsafe bwd bwd-target IBC LIR BB09 IN (6)={V02 V03 V05 V01 V04 V07 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V07 V10} + ByrefExposed + GcHeap Recording Var Locations at start of BB09 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) V07(r13->STK) Change life 0000000000000000 {} -> 00000000000000BB {V01 V02 V03 V04 V05 V07} V02 in reg rbx is becoming live [------] Live regs: 00000000 {} => 00000008 {rbx} V03 in reg r14 is becoming live [------] Live regs: 00000008 {rbx} => 00004008 {rbx r14} V05 in reg r15 is becoming live [------] Live regs: 00004008 {rbx r14} => 0000C008 {rbx r14 r15} V01 in reg r12 is becoming live [------] Live regs: 0000C008 {rbx r14 r15} => 0000D008 {rbx r12 r14 r15} V04 in reg r13 is becoming live [------] Live regs: 0000D008 {rbx r12 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live regs: (unchanged) 0000F008 {rbx r12 r13 r14 r15} GC regs: (unchanged) 00007008 {rbx r12 r13 r14} Byref regs: (unchanged) 00008000 {r15} L_M22628_BB09: Label: IG10, GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB09, IL range [095..0B5) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 7 (V07 loc1) [000..0EE) Added IP mapping: 0x0095 STACK_EMPTY (G_M22628_IG10,ins#0,ofs#0) label Generating: N231 (???,???) [000480] ------------ IL_OFFSET void IL offset: 0x95 REG NA Generating: N233 ( 3, 10) [000067] ------------ t67 = CNS_INT(h) long 0xd1ffab1e class REG rsi $1d1 IN003f: mov rsi, (reloc 0xd1ffab1e) /--* t67 long Generating: N235 ( 5, 12) [000068] n----------- t68 = * IND long REG rsi IN0040: mov rsi, qword ptr [rsi] /--* t68 long Generating: N237 (???,???) [000543] ------------ t543 = * PUTARG_REG long REG rsi Generating: N239 ( 3, 2) [000064] -------N---- t64 = LCL_VAR_ADDR byref V08 loc2 rdi * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 REG rdi IN0041: lea rdi, bword ptr [V08 rbp-40H] Byref regs: 00008000 {r15} => 00008080 {rdi r15} /--* t64 byref Generating: N241 (???,???) [000544] ------------ t544 = * PUTARG_REG byref REG rdi Byref regs: 00008080 {rdi r15} => 00008000 {r15} Byref regs: 00008000 {r15} => 00008080 {rdi r15} Generating: N243 ( 3, 10) [000545] ------------ t545 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN0042: mov rax, (reloc 0xd1ffab1e) /--* t545 long Generating: N245 ( 5, 12) [000546] -c---------- t546 = * IND long REG NA /--* t543 long arg1 in rsi +--* t544 byref this in rdi +--* t546 long control expr Generating: N247 ( 22, 23) [000066] --CXG------- t66 = * CALL r2r_ind ref Enumerator[__Canon][System.__Canon].get_Current REG rax $16c Byref regs: 00008080 {rdi r15} => 00008000 {r15} Call: GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0043: call gword ptr [rax]Enumerator[__Canon][System.__Canon]:get_Current():System.__Canon:this GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} /--* t66 ref Generating: N249 ( 26, 26) [000360] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp15 d:2 rdi REG rdi GC regs: 00007009 {rax rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN0044: mov rdi, rax V26 in reg rdi is becoming live [000360] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F088 {rbx rdi r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V07} => {V01 V02 V03 V04 V05 V07 V26} GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N251 ( 3, 2) [000361] ------------ t361 = LCL_VAR ref V26 tmp15 u:2 rdi (last use) REG rdi $16c /--* t361 ref Generating: N253 (???,???) [000547] ------------ t547 = * PUTARG_REG ref REG rdi V26 in reg rdi is becoming dead [000361] Live regs: 0000F088 {rbx rdi r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V07 V26} => {V01 V02 V03 V04 V05 V07} GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N255 ( 3, 2) [000069] ------------ t69 = LCL_VAR ref V01 arg1 u:1 r12 REG r12 $81 /--* t69 ref Generating: N257 (???,???) [000548] ------------ t548 = * PUTARG_REG ref REG rsi IN0045: mov rsi, r12 GC regs: 00007088 {rbx rdi r12 r13 r14} => 000070C8 {rbx rsi rdi r12 r13 r14} Generating: N259 ( 3, 10) [000356] ------------ t356 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1d3 IN0046: mov r11, (reloc 0xd1ffab1e) /--* t356 long Generating: N261 (???,???) [000549] ------------ t549 = * PUTARG_REG long REG r11 Generating: N263 ( 3, 10) [000550] ------------ t550 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN0047: mov rax, (reloc 0xd1ffab1e) /--* t550 long Generating: N265 ( 5, 12) [000551] -c---------- t551 = * IND long REG NA /--* t547 ref this in rdi +--* t548 ref arg2 in rsi +--* t549 long arg1 in r11 +--* t551 long control expr Generating: N267 ( 55, 51) [000070] --CXG------- t70 = * CALLV stub struct Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol.InternalSubstituteTypeParameters REG rax,rdx $502 GC regs: 000070C8 {rbx rsi rdi r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} GC regs: 00007048 {rbx rsi r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN0048: cmp dword ptr [rdi], edi Call: GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0049: call gword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol:InternalSubstituteTypeParameters(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution):Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeWithModifiers:this GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} GC regs: 00007009 {rax rbx r12 r13 r14} => 0000700D {rax rdx rbx r12 r13 r14} /--* t70 struct Generating: N269 ( 59, 54) [000073] DA-XG------- * STORE_LCL_VAR struct V13 tmp2 d:2 NA REG NA GC regs: 0000700D {rax rdx rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN004a: mov gword ptr [V13 rbp-68H], rax IN004b: mov gword ptr [V13+0x8 rbp-60H], rdx Live vars: {V01 V02 V03 V04 V05 V07} => {V01 V02 V03 V04 V05 V07 V13} Generating: N271 ( 3, 4) [000076] ------------ t76 = LCL_FLD ref V13 tmp2 u:2[+0] Fseq[Type] rax (last use) REG rax $370 IN004c: mov rax, gword ptr [V13 rbp-68H] Live vars: {V01 V02 V03 V04 V05 V07 V13} => {V01 V02 V03 V04 V05 V07} GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} /--* t76 ref Generating: N273 ( 7, 7) [000078] DA---------- * STORE_LCL_VAR ref V10 loc4 d:2 rax REG rax GC regs: 00007009 {rax rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} V10 in reg rax is becoming live [000078] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F009 {rax rbx r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V07} => {V01 V02 V03 V04 V05 V07 V10} GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} Added IP mapping: 0x00A9 STACK_EMPTY (G_M22628_IG10,ins#14,ofs#71) Generating: N275 (???,???) [000481] ------------ IL_OFFSET void IL offset: 0xa9 REG NA Generating: N277 ( 3, 2) [000080] -----------Z t80 = LCL_VAR ref V10 loc4 u:2 rax REG rax $370 /--* t80 ref Generating: N279 (???,???) [000552] ------------ t552 = * PUTARG_REG ref REG rdi IN004d: mov gword ptr [V10 rbp-D0H], rax V10 in reg rax is becoming dead [000080] Live regs: 0000F009 {rax rbx r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00007009 {rax rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} Var V10 becoming live IN004e: mov rdi, rax GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N281 ( 3, 10) [000365] ------------ t365 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c0 IN004f: mov r11, (reloc 0xd1ffab1e) /--* t365 long Generating: N283 (???,???) [000553] ------------ t553 = * PUTARG_REG long REG r11 Generating: N285 ( 3, 10) [000554] ------------ t554 = CNS_INT(h) long 0xd1ffab1e ftn REG rsi IN0050: mov rsi, (reloc 0xd1ffab1e) /--* t554 long Generating: N287 ( 5, 12) [000555] -c---------- t555 = * IND long REG NA /--* t552 ref this in rdi +--* t553 long arg1 in r11 +--* t555 long control expr Generating: N289 ( 26, 22) [000247] --CXG------- t247 = * CALLV stub int Microsoft.CodeAnalysis.VisualBasic.Symbol.get_Kind REG rax $215 GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN0051: cmp dword ptr [rdi], edi Call: GCvars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0052: call qword ptr [rsi]Microsoft.CodeAnalysis.VisualBasic.Symbol:get_Kind():int:this Generating: N291 ( 1, 1) [000248] -c---------- t248 = CNS_INT int 4 REG NA $44 /--* t247 int +--* t248 int Generating: N293 ( 28, 24) [000249] J--XG--N---- * NE void REG NA $296 IN0053: cmp eax, 4 Generating: N295 ( 30, 26) [000228] ---XG------- * JTRUE void REG NA IN0054: jne L_M22628_BB14 Scope info: end block BB09, IL range [095..0B5) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 7 (V07 loc1) [000..0EE) =============== Generating BB10 [0A9..0AA) -> BB19 (always), preds={BB09} succs={BB19} flags=0x00000004.42080020: i gcsafe bwd LIR BB10 IN (6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap Recording Var Locations at start of BB10 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Change life 00000000000002BB {V01 V02 V03 V04 V05 V07 V10} -> 000000000000023B {V01 V02 V03 V04 V05 V10} Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB10: G_M22628_IG10: ; offs=000239H, funclet=00, bbWeight=0.29 Label: IG11, GCvars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB10, IL range [0A9..0AA) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 10 (V10 loc4) [000..0EE) genIPmappingAdd: ignoring duplicate IL offset 0xa9 Generating: N299 (???,???) [000482] ------------ IL_OFFSET void IL offset: 0xa9 REG NA Generating: N301 ( 3, 2) [000237] -----------z t237 = LCL_VAR ref V10 loc4 u:2 rdi REG rdi $370 /--* t237 ref Generating: N303 (???,???) [000556] ------------ t556 = * PUTARG_REG ref REG rdi IN0055: mov rdi, gword ptr [V10 rbp-D0H] GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N305 ( 1, 1) [000238] ------------ t238 = LCL_VAR byref V05 arg5 u:1 r15 REG r15 $c0 /--* t238 byref Generating: N307 (???,???) [000557] ------------ t557 = * PUTARG_REG byref REG rsi IN0056: mov rsi, r15 Byref regs: 00008000 {r15} => 00008040 {rsi r15} Generating: N309 ( 3, 10) [000558] ------------ t558 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN0057: mov rax, (reloc 0xd1ffab1e) /--* t558 long Generating: N311 ( 5, 12) [000559] -c---------- t559 = * IND long REG NA /--* t556 ref arg0 in rdi +--* t557 byref arg1 in rsi +--* t559 long control expr Generating: N313 ( 18, 10) [000239] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions.AddUseSiteDiagnostics REG NA $VN.Void GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} Byref regs: 00008040 {rsi r15} => 00008000 {r15} Call: GCvars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0058: call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:AddUseSiteDiagnostics(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref) genIPmappingAdd: ignoring duplicate IL offset 0xa9 Generating: N315 (???,???) [000483] ------------ IL_OFFSET void IL offset: 0xa9 REG NA Scope info: end block BB10, IL range [0A9..0AA) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 10 (V10 loc4) [000..0EE) IN0059: jmp L_M22628_BB19 =============== Generating BB12 [072..080) -> BB28 (cond), preds={BB05} succs={BB13,BB28} flags=0x00000004.600b0020: i label target gcsafe IBC LIR BB12 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB12 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Change life 000000000000023B {V01 V02 V03 V04 V05 V10} -> 00000000000000FB {V00 V01 V02 V03 V04 V05 V07} V10 becoming dead V00 becoming live Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB12: G_M22628_IG11: ; offs=0002ABH, funclet=00, bbWeight=0.58 Label: IG12, GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB12, IL range [072..080) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) 7 (V07 loc1) [000..0EE) Added IP mapping: 0x0072 STACK_EMPTY (G_M22628_IG12,ins#0,ofs#0) label Generating: N319 (???,???) [000484] ------------ IL_OFFSET void IL offset: 0x72 REG NA Generating: N321 ( 3, 2) [000130] -----------z t130 = LCL_VAR ref V00 arg0 u:1 rdi (last use) REG rdi $80 /--* t130 ref Generating: N323 (???,???) [000560] ------------ t560 = * PUTARG_REG ref REG rdi IN005a: mov rdi, gword ptr [V00 rbp-C8H] Removing V00 from gcVarPtrSetCur V00 in reg rdi is becoming live [000130] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F088 {rbx rdi r12 r13 r14 r15} GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} V00 in reg rdi is becoming dead [000130] Live regs: 0000F088 {rbx rdi r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V07} => {V01 V02 V03 V04 V05 V07} GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N325 ( 1, 1) [000131] ------------ t131 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t131 ref Generating: N327 (???,???) [000561] ------------ t561 = * PUTARG_REG ref REG rsi IN005b: mov rsi, rbx GC regs: 00007088 {rbx rdi r12 r13 r14} => 000070C8 {rbx rsi rdi r12 r13 r14} Generating: N329 ( 1, 1) [000132] ------------ t132 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t132 ref Generating: N331 (???,???) [000562] ------------ t562 = * PUTARG_REG ref REG rdx IN005c: mov rdx, r14 GC regs: 000070C8 {rbx rsi rdi r12 r13 r14} => 000070CC {rdx rbx rsi rdi r12 r13 r14} Generating: N333 ( 3, 2) [000133] ------------ t133 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 /--* t133 ref Generating: N335 (???,???) [000563] ------------ t563 = * PUTARG_REG ref REG rcx IN005d: mov rcx, r13 GC regs: 000070CC {rdx rbx rsi rdi r12 r13 r14} => 000070CE {rcx rdx rbx rsi rdi r12 r13 r14} Generating: N337 ( 1, 1) [000134] ------------ t134 = LCL_VAR byref V05 arg5 u:1 r15 REG r15 $c0 /--* t134 byref Generating: N339 (???,???) [000564] ------------ t564 = * PUTARG_REG byref REG r8 IN005e: mov r8, r15 Byref regs: 00008000 {r15} => 00008100 {r8 r15} Generating: N341 ( 3, 10) [000565] ------------ t565 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN005f: mov rax, (reloc 0xd1ffab1e) /--* t565 long Generating: N343 ( 5, 12) [000566] -c---------- t566 = * IND long REG NA /--* t560 ref arg0 in rdi +--* t561 ref arg1 in rsi +--* t562 ref arg2 in rdx +--* t563 ref arg3 in rcx +--* t564 byref arg4 in r8 +--* t566 long control expr Generating: N345 ( 23, 17) [000135] --CXG------- t135 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesValueTypeConstraint REG rax $20f GC regs: 000070CE {rcx rdx rbx rsi rdi r12 r13 r14} => 0000704E {rcx rdx rbx rsi r12 r13 r14} GC regs: 0000704E {rcx rdx rbx rsi r12 r13 r14} => 0000700E {rcx rdx rbx r12 r13 r14} GC regs: 0000700E {rcx rdx rbx r12 r13 r14} => 0000700A {rcx rbx r12 r13 r14} GC regs: 0000700A {rcx rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} Byref regs: 00008100 {r8 r15} => 00008000 {r15} Call: GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0060: call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesValueTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool Generating: N347 ( 1, 1) [000137] -c---------- t137 = CNS_INT bool 0 REG NA $40 /--* t135 bool +--* t137 bool Generating: N349 ( 26, 21) [000138] J--XG--N-U-- * EQ void REG NA $291 IN0061: test al, al Generating: N351 ( 28, 23) [000139] ---XG------- * JTRUE void REG NA IN0062: je L_M22628_BB28 Scope info: end block BB12, IL range [072..080) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 7 (V07 loc1) [000..0EE) =============== Generating BB13 [???..???) -> BB06 (always), preds={BB12} succs={BB06} flags=0x00000000.60080040: internal gcsafe IBC LIR BB13 IN (6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB13 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Liveness not changing: 00000000000000BB {V01 V02 V03 V04 V05 V07} Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB13: Scope info: begin block BB13, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M22628_IG12,ins#9,ofs#39) label Scope info: end block BB13, IL range [???..???) Scope info: ignoring block end IN0063: jmp L_M22628_BB06 =============== Generating BB14 [0A9..0AA) -> BB19 (cond), preds={BB09} succs={BB15,BB19} flags=0x00000004.620b0020: i label target gcsafe bwd IBC LIR BB14 IN (7)={V02 V03 V05 V01 V04 V07 V10} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V07 V10} + ByrefExposed + GcHeap Recording Var Locations at start of BB14 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Change life 00000000000000BB {V01 V02 V03 V04 V05 V07} -> 00000000000002BB {V01 V02 V03 V04 V05 V07 V10} V10 becoming live Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB14: G_M22628_IG12: ; offs=0002C6H, funclet=00, bbWeight=0.01 Label: IG13, GCvars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB14, IL range [0A9..0AA) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 7 (V07 loc1) [000..0EE) 10 (V10 loc4) [000..0EE) Added IP mapping: 0x00A9 STACK_EMPTY (G_M22628_IG13,ins#0,ofs#0) label Generating: N357 (???,???) [000485] ------------ IL_OFFSET void IL offset: 0xa9 REG NA Generating: N359 ( 1, 1) [000079] ------------ t79 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t79 ref Generating: N361 (???,???) [000567] ------------ t567 = * PUTARG_REG ref REG rdi IN0064: mov rdi, r14 GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N363 ( 3, 2) [000229] -----------z t229 = LCL_VAR ref V10 loc4 u:2 rsi REG rsi $370 /--* t229 ref Generating: N365 (???,???) [000568] ------------ t568 = * PUTARG_REG ref REG rsi IN0065: mov rsi, gword ptr [V10 rbp-D0H] GC regs: 00007088 {rbx rdi r12 r13 r14} => 000070C8 {rbx rsi rdi r12 r13 r14} GC regs: 000070C8 {rbx rsi rdi r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} GC regs: 00007088 {rbx rdi r12 r13 r14} => 000070C8 {rbx rsi rdi r12 r13 r14} Generating: N367 ( 1, 1) [000081] ------------ t81 = LCL_VAR byref V05 arg5 u:1 r15 REG r15 $c0 /--* t81 byref Generating: N369 (???,???) [000569] ------------ t569 = * PUTARG_REG byref REG rdx IN0066: mov rdx, r15 Byref regs: 00008000 {r15} => 00008004 {rdx r15} Generating: N371 ( 3, 10) [000570] ------------ t570 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN0067: mov rax, (reloc 0xd1ffab1e) /--* t570 long Generating: N373 ( 5, 12) [000571] -c---------- t571 = * IND long REG NA /--* t567 ref arg0 in rdi +--* t568 ref arg1 in rsi +--* t569 byref arg2 in rdx +--* t571 long control expr Generating: N375 ( 19, 12) [000230] --CXG------- t230 = * CALL r2r_ind int Microsoft.CodeAnalysis.VisualBasic.Conversions.HasWideningDirectCastConversionButNotEnumTypeConversion REG rax $216 GC regs: 000070C8 {rbx rsi rdi r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} GC regs: 00007048 {rbx rsi r12 r13 r14} => 00007008 {rbx r12 r13 r14} Byref regs: 00008004 {rdx r15} => 00008000 {r15} Call: GCvars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0068: call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Conversions:HasWideningDirectCastConversionButNotEnumTypeConversion(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool /--* t230 int Generating: N377 ( 20, 14) [000232] ---XG------- t232 = * CAST int <- bool <- int REG rsi $297 IN0069: movzx rsi, al /--* t232 int Generating: N379 ( 24, 17) [000234] DA-XG------- * STORE_LCL_VAR int V19 tmp8 d:2 rsi REG rsi V19 in reg rsi is becoming live [000234] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F048 {rbx rsi r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V07 V10} => {V01 V02 V03 V04 V05 V07 V10 V19} Generating: N381 ( 3, 2) [000235] ------------ t235 = LCL_VAR int V19 tmp8 u:2 rsi (last use) REG rsi $297 Generating: N383 ( 1, 1) [000085] -c---------- t85 = CNS_INT int 0 REG NA $40 /--* t235 int +--* t85 int Generating: N385 ( 5, 4) [000086] J------N---- * EQ void REG NA $298 V19 in reg rsi is becoming dead [000235] Live regs: 0000F048 {rbx rsi r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V07 V10 V19} => {V01 V02 V03 V04 V05 V07 V10} IN006a: test esi, esi Generating: N387 ( 7, 6) [000087] ------------ * JTRUE void REG NA IN006b: je L_M22628_BB19 Scope info: end block BB14, IL range [0A9..0AA) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 7 (V07 loc1) [000..0EE) 10 (V10 loc4) [000..0EE) =============== Generating BB15 [0E1..0EA) -> BB09 (cond), preds={BB14,BB21} succs={BB16,BB09} flags=0x00000004.620b2020: i Loop label target gcsafe bwd IBC LIR BB15 IN (6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB15 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Change life 00000000000002BB {V01 V02 V03 V04 V05 V07 V10} -> 00000000000000BB {V01 V02 V03 V04 V05 V07} V10 becoming dead Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB15: G_M22628_IG13: ; offs=0002F2H, funclet=00, bbWeight=0.29 Label: IG14, GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB15, IL range [0E1..0EA) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 7 (V07 loc1) [000..0EE) Added IP mapping: 0x00E1 STACK_EMPTY (G_M22628_IG14,ins#0,ofs#0) label Generating: N391 (???,???) [000486] ------------ IL_OFFSET void IL offset: 0xe1 REG NA Generating: N393 ( 3, 10) [000058] ------------ t58 = CNS_INT(h) long 0xd1ffab1e class REG rsi $1d1 IN006c: mov rsi, (reloc 0xd1ffab1e) /--* t58 long Generating: N395 ( 5, 12) [000059] n----------- t59 = * IND long REG rsi IN006d: mov rsi, qword ptr [rsi] /--* t59 long Generating: N397 (???,???) [000572] ------------ t572 = * PUTARG_REG long REG rsi Generating: N399 ( 3, 2) [000055] -------N---- t55 = LCL_VAR_ADDR byref V08 loc2 rdi * ref V08._array (offs=0x00) -> V21 tmp10 * int V08._index (offs=0x08) -> V22 tmp11 REG rdi IN006e: lea rdi, bword ptr [V08 rbp-40H] Byref regs: 00008000 {r15} => 00008080 {rdi r15} /--* t55 byref Generating: N401 (???,???) [000573] ------------ t573 = * PUTARG_REG byref REG rdi Byref regs: 00008080 {rdi r15} => 00008000 {r15} Byref regs: 00008000 {r15} => 00008080 {rdi r15} Generating: N403 ( 3, 10) [000574] ------------ t574 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN006f: mov rax, (reloc 0xd1ffab1e) /--* t574 long Generating: N405 ( 5, 12) [000575] -c---------- t575 = * IND long REG NA /--* t572 long arg1 in rsi +--* t573 byref this in rdi +--* t575 long control expr Generating: N407 ( 22, 23) [000057] --CXG------- t57 = * CALL r2r_ind bool Enumerator[__Canon][System.__Canon].MoveNext REG rax $21b Byref regs: 00008080 {rdi r15} => 00008000 {r15} Call: GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0070: call qword ptr [rax]Enumerator[__Canon][System.__Canon]:MoveNext():bool:this Generating: N409 ( 1, 1) [000061] -c---------- t61 = CNS_INT bool 0 REG NA $40 /--* t57 bool +--* t61 bool Generating: N411 ( 25, 27) [000062] J--XG--N-U-- * NE void REG NA $29b IN0071: test al, al Generating: N413 ( 27, 29) [000063] ---XG------- * JTRUE void REG NA IN0072: jne L_M22628_BB09 Scope info: end block BB15, IL range [0E1..0EA) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 7 (V07 loc1) [000..0EE) =============== Generating BB16 [???..???) -> BB07 (always), preds={BB15} succs={BB07} flags=0x00000000.40080040: internal gcsafe LIR BB16 IN (1)={V07} OUT(1)={V07} Recording Var Locations at start of BB16 Change life 00000000000000BB {V01 V02 V03 V04 V05 V07} -> 0000000000000080 {V07} V02 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V03 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V05 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V01 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V04 in reg r13 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M22628_BB16: G_M22628_IG14: ; offs=000317H, funclet=00, bbWeight=0.29 Label: IG15, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB16, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M22628_IG15,ins#0,ofs#0) label Scope info: end block BB16, IL range [???..???) Scope info: ignoring block end IN0073: jmp L_M22628_BB07 =============== Generating BB17 [05D..068) -> BB05 (cond), preds={BB04} succs={BB18,BB05} flags=0x00000004.600b0020: i label target gcsafe IBC LIR BB17 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB17 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) V00(rdi->STK) Change life 0000000000000080 {V07} -> 00000000000000FB {V00 V01 V02 V03 V04 V05 V07} V02 in reg rbx is becoming live [------] Live regs: 00000000 {} => 00000008 {rbx} V03 in reg r14 is becoming live [------] Live regs: 00000008 {rbx} => 00004008 {rbx r14} V05 in reg r15 is becoming live [------] Live regs: 00004008 {rbx r14} => 0000C008 {rbx r14 r15} V01 in reg r12 is becoming live [------] Live regs: 0000C008 {rbx r14 r15} => 0000D008 {rbx r12 r14 r15} V04 in reg r13 is becoming live [------] Live regs: 0000D008 {rbx r12 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} V00 becoming live Live regs: (unchanged) 0000F008 {rbx r12 r13 r14 r15} GC regs: (unchanged) 00007008 {rbx r12 r13 r14} Byref regs: (unchanged) 00008000 {r15} L_M22628_BB17: G_M22628_IG15: ; offs=00033CH, funclet=00, bbWeight=0.15 Label: IG16, GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB17, IL range [05D..068) Scope info: open scopes = 7 (V07 loc1) [000..0EE) 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) Generating: N419 ( 1, 1) [000143] ------------ t143 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t143 ref Generating: N421 (???,???) [000576] ------------ t576 = * PUTARG_REG ref REG rdi IN0074: mov rdi, rbx GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N423 ( 1, 1) [000144] ------------ t144 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t144 ref Generating: N425 (???,???) [000577] ------------ t577 = * PUTARG_REG ref REG rsi IN0075: mov rsi, r14 GC regs: 00007088 {rbx rdi r12 r13 r14} => 000070C8 {rbx rsi rdi r12 r13 r14} Generating: N427 ( 3, 2) [000145] ------------ t145 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 /--* t145 ref Generating: N429 (???,???) [000578] ------------ t578 = * PUTARG_REG ref REG rdx IN0076: mov rdx, r13 GC regs: 000070C8 {rbx rsi rdi r12 r13 r14} => 000070CC {rdx rbx rsi rdi r12 r13 r14} Generating: N431 ( 3, 10) [000579] ------------ t579 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN0077: mov rax, (reloc 0xd1ffab1e) /--* t579 long Generating: N433 ( 5, 12) [000580] -c---------- t580 = * IND long REG NA /--* t576 ref arg0 in rdi +--* t577 ref arg1 in rsi +--* t578 ref arg2 in rdx +--* t580 long control expr Generating: N435 ( 19, 12) [000146] --CXG------- t146 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesReferenceTypeConstraint REG rax $20c GC regs: 000070CC {rdx rbx rsi rdi r12 r13 r14} => 0000704C {rdx rbx rsi r12 r13 r14} GC regs: 0000704C {rdx rbx rsi r12 r13 r14} => 0000700C {rdx rbx r12 r13 r14} GC regs: 0000700C {rdx rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} Call: GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0078: call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesReferenceTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool Generating: N437 ( 1, 1) [000149] -c---------- t149 = CNS_INT bool 0 REG NA $40 /--* t146 bool +--* t149 bool Generating: N439 ( 22, 16) [000150] J--XG--N-U-- * NE void REG NA $28d IN0079: test al, al Generating: N441 ( 24, 18) [000151] ---XG------- * JTRUE void REG NA IN007a: jne L_M22628_BB05 Scope info: end block BB17, IL range [05D..068) Scope info: open scopes = 7 (V07 loc1) [000..0EE) 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) =============== Generating BB18 [068..06A) -> BB05 (always), preds={BB17} succs={BB05} flags=0x00000000.60080020: i gcsafe IBC LIR BB18 IN (6)={V02 V03 V05 V01 V04 V00 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB18 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Change life 00000000000000FB {V00 V01 V02 V03 V04 V05 V07} -> 000000000000007B {V00 V01 V02 V03 V04 V05} Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB18: G_M22628_IG16: ; offs=000341H, funclet=00, bbWeight=0.03 Label: IG17, GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB18, IL range [068..06A) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) Added IP mapping: 0x0068 STACK_EMPTY (G_M22628_IG17,ins#0,ofs#0) label Generating: N445 (???,???) [000487] ------------ IL_OFFSET void IL offset: 0x68 REG NA Generating: N447 ( 1, 1) [000152] ------------ t152 = CNS_INT int 0 REG rdi $40 IN007b: xor edi, edi /--* t152 int Generating: N449 ( 5, 4) [000154] DA---------- * STORE_LCL_VAR int V07 loc1 d:7 rax REG rax IN007c: xor eax, eax V07 in reg rax is becoming live [000154] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F009 {rax rbx r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V07} Generating: N001 ( 4, 3) [000628] -----------Z t628 = LCL_VAR bool V07 loc1 rax REG rax IN007d: mov dword ptr [V07 rbp-2CH], eax V07 in reg rax is becoming dead [000628] Live regs: 0000F009 {rax rbx r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Scope info: end block BB18, IL range [068..06A) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) IN007e: jmp L_M22628_BB05 =============== Generating BB19 [0B5..0B9) -> BB21 (cond), preds={BB14,BB10} succs={BB20,BB21} flags=0x00000000.620b0020: i label target gcsafe bwd IBC LIR BB19 IN (6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap Recording Var Locations at start of BB19 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Change life 00000000000000FB {V00 V01 V02 V03 V04 V05 V07} -> 000000000000023B {V01 V02 V03 V04 V05 V10} V00 becoming dead V10 becoming live Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB19: G_M22628_IG17: ; offs=00035EH, funclet=00, bbWeight=0.01 Label: IG18, GCvars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB19, IL range [0B5..0B9) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 10 (V10 loc4) [000..0EE) Added IP mapping: 0x00B5 STACK_EMPTY (G_M22628_IG18,ins#0,ofs#0) label Generating: N453 (???,???) [000488] ------------ IL_OFFSET void IL offset: 0xb5 REG NA Generating: N455 ( 3, 2) [000088] ------------ t88 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 Generating: N457 ( 1, 1) [000089] -c---------- t89 = CNS_INT ref null REG NA $VN.Null /--* t88 ref +--* t89 ref Generating: N459 ( 5, 4) [000090] J------N---- * EQ void REG NA $284 IN007f: test r13, r13 Generating: N461 ( 7, 6) [000091] ------------ * JTRUE void REG NA IN0080: je L_M22628_BB21 Scope info: end block BB19, IL range [0B5..0B9) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 10 (V10 loc4) [000..0EE) =============== Generating BB20 [0B9..0DF), preds={BB19} succs={BB21} flags=0x00000004.62e80020: i gcsafe idxlen new[] newobj bwd IBC LIR BB20 IN (6)={V02 V03 V05 V01 V04 V10} + ByrefExposed + GcHeap OUT(5)={V02 V03 V05 V01 V04 } + ByrefExposed + GcHeap Recording Var Locations at start of BB20 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Liveness not changing: 000000000000023B {V01 V02 V03 V04 V05 V10} Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB20: Scope info: begin block BB20, IL range [0B9..0DF) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 10 (V10 loc4) [000..0EE) Added IP mapping: 0x00B9 STACK_EMPTY (G_M22628_IG18,ins#2,ofs#9) label Generating: N465 (???,???) [000489] ------------ IL_OFFSET void IL offset: 0xb9 REG NA Generating: N467 ( 1, 1) [000098] ------------ t98 = CNS_INT long 2 REG rdi $2c4 IN0081: mov edi, 2 /--* t98 long Generating: N469 (???,???) [000581] ------------ t581 = * PUTARG_REG long REG rdi Generating: N471 ( 3, 10) [000582] ------------ t582 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN0082: mov rax, (reloc 0xd1ffab1e) /--* t582 long Generating: N473 ( 5, 12) [000583] -c---------- t583 = * IND long REG NA /--* t581 long arg0 in rdi +--* t583 long control expr Generating: N475 ( 15, 7) [000099] --CXG------- t99 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 REG rax $376 Call: GCvars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0083: call gword ptr [rax]CORINFO_HELP_READYTORUN_NEWARR_1 GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} /--* t99 ref Generating: N477 ( 19, 10) [000101] DA-XG------- * STORE_LCL_VAR ref V14 tmp3 d:2 rax REG rax GC regs: 00007009 {rax rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} V14 in reg rax is becoming live [000101] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F009 {rax rbx r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V10} => {V01 V02 V03 V04 V05 V10 V14} GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} Generating: N479 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 0 REG NA $40 Generating: N481 ( 3, 2) [000103] ------------ t103 = LCL_VAR ref V14 tmp3 u:2 rax REG rax $385 /--* t103 ref Generating: N483 (???,???) [000504] -c---------- t504 = * LEA(b+8) ref REG NA /--* t504 ref Generating: N485 ( 5, 4) [000377] ---X-------- t377 = * IND int REG rdx $299 IN0084: mov edx, dword ptr [rax+8] /--* t377 int Generating: N487 ( 9, 7) [000465] DA-X-------- * STORE_LCL_VAR int V28 cse0 d:1 rdx REG rdx V28 in reg rdx is becoming live [000465] Live regs: 0000F009 {rax rbx r12 r13 r14 r15} => 0000F00D {rax rdx rbx r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V10 V14} => {V01 V02 V03 V04 V05 V10 V14 V28} Generating: N489 ( 3, 2) [000466] -----------Z t466 = LCL_VAR int V28 cse0 u:1 rdx REG rdx $299 /--* t104 int +--* t466 int Generating: N491 ( 17, 17) [000378] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA $37c IN0085: mov dword ptr [V28 rbp-BCH], edx V28 in reg rdx is becoming dead [000466] Live regs: 0000F00D {rax rdx rbx r12 r13 r14 r15} => 0000F009 {rax rbx r12 r13 r14 r15} IN0086: cmp edx, 0 IN0087: jbe L_M22628_BB29 Generating: N493 ( 3, 2) [000375] -----------Z t375 = LCL_VAR ref V14 tmp3 u:2 rax REG rax $385 /--* t375 ref Generating: N495 ( 4, 3) [000383] ------------ t383 = * LEA(b+16) byref REG rdi IN0088: mov gword ptr [V14 rbp-D8H], rax V14 in reg rax is becoming dead [000375] Live regs: 0000F009 {rax rbx r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00007009 {rax rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} Var V14 becoming live IN0089: lea rdi, bword ptr [rax+16] Byref regs: 00008000 {r15} => 00008080 {rdi r15} Generating: N497 ( 1, 1) [000105] ------------ t105 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t383 byref +--* t105 ref Generating: N499 (???,???) [000490] -A-XG------- * STOREIND ref REG NA Byref regs: 00008080 {rdi r15} => 00008000 {r15} IN008a: mov rsi, r14 NoGC Call: savedSet=0000F008 {rbx r12 r13 r14 r15} Call: GCvars=0000000000002200 {V10 V14}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN008b: call CORINFO_HELP_ASSIGN_REF Generating: N501 ( 1, 1) [000109] -c---------- t109 = CNS_INT int 1 REG NA $41 Generating: N503 ( 3, 2) [000468] -c---------- t468 = LCL_VAR int V28 cse0 u:1 NA (last use) REG NA $3c1 /--* t109 int +--* t468 int Generating: N505 ( 8, 10) [000388] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA $645 Live vars: {V01 V02 V03 V04 V05 V10 V14 V28} => {V01 V02 V03 V04 V05 V10 V14} IN008c: cmp dword ptr [V28 rbp-BCH], 1 IN008d: jbe L_M22628_BB29 Generating: N507 ( 3, 2) [000385] -----------z t385 = LCL_VAR ref V14 tmp3 u:2 rax REG rax $385 /--* t385 ref Generating: N509 ( 4, 3) [000393] ------------ t393 = * LEA(b+24) byref REG rdi IN008e: mov rax, gword ptr [V14 rbp-D8H] GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} GC regs: 00007009 {rax rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN008f: lea rdi, bword ptr [rax+24] Byref regs: 00008000 {r15} => 00008080 {rdi r15} Generating: N511 ( 3, 2) [000110] -----------z t110 = LCL_VAR ref V10 loc4 u:2 rsi (last use) REG rsi $370 /--* t393 byref +--* t110 ref Generating: N513 (???,???) [000491] -A-XG------- * STOREIND ref REG NA Byref regs: 00008080 {rdi r15} => 00008000 {r15} IN0090: mov rsi, gword ptr [V10 rbp-D0H] Removing V10 from gcVarPtrSetCur V10 in reg rsi is becoming live [000110] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F048 {rbx rsi r12 r13 r14 r15} GC regs: 00007008 {rbx r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} V10 in reg rsi is becoming dead [000110] Live regs: 0000F048 {rbx rsi r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V10 V14} => {V01 V02 V03 V04 V05 V14} GC regs: 00007048 {rbx rsi r12 r13 r14} => 00007008 {rbx r12 r13 r14} NoGC Call: savedSet=0000F008 {rbx r12 r13 r14 r15} Call: GCvars=0000000000002000 {V14}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0091: call CORINFO_HELP_ASSIGN_REF Generating: N515 ( 3, 10) [000584] ------------ t584 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN0092: mov rax, (reloc 0xd1ffab1e) /--* t584 long Generating: N517 ( 5, 12) [000585] -c---------- t585 = * IND long REG NA /--* t585 long control expr Generating: N519 ( 14, 5) [000259] --C--------- t259 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW REG rax $647 Call: GCvars=0000000000002000 {V14}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0093: call gword ptr [rax]CORINFO_HELP_READYTORUN_NEW GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} /--* t259 ref Generating: N521 ( 18, 8) [000261] DA---------- * STORE_LCL_VAR ref V20 tmp9 d:2 NA REG NA GC regs: 00007009 {rax rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN0094: mov gword ptr [V20 rbp-F0H], rax Live vars: {V01 V02 V03 V04 V05 V14} => {V01 V02 V03 V04 V05 V14 V20} GCvars: {V14} => {V14 V20} Generating: N523 ( 3, 10) [000586] ------------ t586 = CNS_INT(h) long 0xd1ffab1e ftn REG rdi IN0095: mov rdi, (reloc 0xd1ffab1e) /--* t586 long Generating: N525 ( 5, 12) [000587] -c---------- t587 = * IND long REG NA /--* t587 long control expr Generating: N527 ( 14, 5) [000252] H-CXG------- t252 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE REG rax $401 Call: GCvars=000000000000A000 {V14 V20}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0096: call bword ptr [rdi]CORINFO_HELP_READYTORUN_STATIC_BASE Byref regs: 00008000 {r15} => 00008001 {rax r15} /--* t252 byref Generating: N529 ( 15, 9) [000254] -c---------- t254 = * LEA(b+1048) byref REG NA /--* t254 byref Generating: N531 ( 17, 11) [000255] ---XG------- t255 = * IND ref REG rsi Byref regs: 00008001 {rax r15} => 00008000 {r15} IN0097: mov rsi, gword ptr [rax+0418H] GC regs: 00007008 {rbx r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} /--* t255 ref Generating: N533 ( 21, 14) [000396] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp16 d:2 rsi REG rsi GC regs: 00007048 {rbx rsi r12 r13 r14} => 00007008 {rbx r12 r13 r14} V27 in reg rsi is becoming live [000396] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F048 {rbx rsi r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V14 V20} => {V01 V02 V03 V04 V05 V14 V20 V27} GC regs: 00007008 {rbx r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} Generating: N535 ( 3, 2) [000397] ------------ t397 = LCL_VAR ref V27 tmp16 u:2 rsi (last use) REG rsi /--* t397 ref Generating: N537 (???,???) [000588] ------------ t588 = * PUTARG_REG ref REG rsi V27 in reg rsi is becoming dead [000397] Live regs: 0000F048 {rbx rsi r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V14 V20 V27} => {V01 V02 V03 V04 V05 V14 V20} GC regs: 00007048 {rbx rsi r12 r13 r14} => 00007008 {rbx r12 r13 r14} GC regs: 00007008 {rbx r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} Generating: N539 ( 3, 2) [000262] -----------z t262 = LCL_VAR ref V20 tmp9 u:2 rdi REG rdi $647 /--* t262 ref Generating: N541 (???,???) [000589] ------------ t589 = * PUTARG_REG ref REG rdi IN0098: mov rdi, gword ptr [V20 rbp-F0H] GC regs: 00007048 {rbx rsi r12 r13 r14} => 000070C8 {rbx rsi rdi r12 r13 r14} GC regs: 000070C8 {rbx rsi rdi r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} GC regs: 00007048 {rbx rsi r12 r13 r14} => 000070C8 {rbx rsi rdi r12 r13 r14} Generating: N543 ( 3, 2) [000102] -----------z t102 = LCL_VAR ref V14 tmp3 u:2 rcx (last use) REG rcx $385 /--* t102 ref Generating: N545 (???,???) [000590] ------------ t590 = * PUTARG_REG ref REG rcx IN0099: mov rcx, gword ptr [V14 rbp-D8H] Removing V14 from gcVarPtrSetCur V14 in reg rcx is becoming live [000102] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F00A {rcx rbx r12 r13 r14 r15} GC regs: 000070C8 {rbx rsi rdi r12 r13 r14} => 000070CA {rcx rbx rsi rdi r12 r13 r14} V14 in reg rcx is becoming dead [000102] Live regs: 0000F00A {rcx rbx r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V14 V20} => {V01 V02 V03 V04 V05 V20} GC regs: 000070CA {rcx rbx rsi rdi r12 r13 r14} => 000070C8 {rbx rsi rdi r12 r13 r14} GC regs: 000070C8 {rbx rsi rdi r12 r13 r14} => 000070CA {rcx rbx rsi rdi r12 r13 r14} Generating: N547 ( 1, 4) [000256] ------------ t256 = CNS_INT int 0x7D2C REG rdx $64 IN009a: mov edx, 0x7D2C /--* t256 int Generating: N549 (???,???) [000591] ------------ t591 = * PUTARG_REG int REG rdx Generating: N551 ( 3, 10) [000592] ------------ t592 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN009b: mov rax, (reloc 0xd1ffab1e) /--* t592 long Generating: N553 ( 5, 12) [000593] -c---------- t593 = * IND long REG NA /--* t588 ref arg1 in rsi +--* t589 ref this in rdi +--* t590 ref arg3 in rcx +--* t591 int arg2 in rdx +--* t593 long control expr Generating: N555 ( 48, 34) [000263] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor REG NA $VN.Void GC regs: 000070CA {rcx rbx rsi rdi r12 r13 r14} => 0000708A {rcx rbx rdi r12 r13 r14} GC regs: 0000708A {rcx rbx rdi r12 r13 r14} => 0000700A {rcx rbx r12 r13 r14} GC regs: 0000700A {rcx rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} Call: GCvars=0000000000008000 {V20}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN009c: call qword ptr [rax]Microsoft.CodeAnalysis.DiagnosticInfo:.ctor(Microsoft.CodeAnalysis.CommonMessageProvider,int,System.Object[]):this Generating: N557 ( 1, 1) [000268] ------------ t268 = CNS_INT int 0 REG rdi $40 IN009d: xor edi, edi Generating: N559 (???,???) [000594] Dc-----N---- t594 = LCL_VAR_ADDR byref V15 tmp4 NA REG NA /--* t594 byref +--* t268 int Generating: N561 ( 5, 4) [000269] sA---------- * STORE_BLK struct (init) (Unroll) REG NA IN009e: xorps xmm0, xmm0 IN009f: movups xmmword ptr [V15 rbp-90H], xmm0 IN00a0: movups xmmword ptr [V15+0x10 rbp-80H], xmm0 IN00a1: mov qword ptr [V15+0x20 rbp-70H], rdi Generating: N563 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t96 ref Generating: N565 ( 5, 6) [000273] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:2->0[+0] Fseq[TypeParameter] NA REG NA IN00a2: mov gword ptr [V15 rbp-90H], rbx Generating: N567 ( 3, 2) [000264] -----------z t264 = LCL_VAR ref V20 tmp9 u:2 rdi (last use) REG rdi $647 /--* t264 ref Generating: N569 ( 7, 7) [000277] UA---------- * STORE_LCL_FLD ref V15 tmp4 ud:3->0[+8] Fseq[DiagnosticInfo] NA REG NA IN00a3: mov rdi, gword ptr [V20 rbp-F0H] Removing V20 from gcVarPtrSetCur V20 in reg rdi is becoming live [000264] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F088 {rbx rdi r12 r13 r14 r15} GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} V20 in reg rdi is becoming dead [000264] Live regs: 0000F088 {rbx rdi r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05 V20} => {V01 V02 V03 V04 V05} GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN00a4: mov gword ptr [V15+0x8 rbp-88H], rdi Added IP mapping: 0x00DA (G_M22628_IG18,ins#38,ofs#209) Generating: N571 (???,???) [000492] ------------ IL_OFFSET void IL offset: 0xda REG NA Generating: N573 ( 3, 2) [000121] -c-----N---- t121 = LCL_VAR_ADDR byref V15 tmp4 u:4 NA (last use) REG NA /--* t121 byref Generating: N575 ( 9, 7) [000124] nc---------- t124 = * OBJ struct REG NA $507 /--* t124 struct Generating: N577 (???,???) [000595] ------------ * PUTARG_STK [+0x00] void (5 slots) (RepInstr) REG NA IN00a5: lea rdi, [V11 rsp] IN00a6: lea rsi, [V15 rbp-90H] IN00a7: mov rcx, gword ptr [rsi] IN00a8: mov gword ptr [V11 rsp], rcx IN00a9: add rsi, 8 IN00aa: add rdi, 8 IN00ab: mov rcx, gword ptr [rsi] IN00ac: mov gword ptr [V11+0x8 rsp+08H], rcx IN00ad: add rsi, 8 IN00ae: add rdi, 8 IN00af: mov rcx, gword ptr [rsi] G_M22628_IG18: ; offs=00036AH, funclet=00, bbWeight=0.02 IN00b0: mov gword ptr [V11+0x10 rsp+10H], rcx IN00b1: add rsi, 8 IN00b2: add rdi, 8 IN00b3: mov rcx, gword ptr [rsi] IN00b4: mov gword ptr [V11+0x18 rsp+18H], rcx IN00b5: add rsi, 8 IN00b6: add rdi, 8 IN00b7: movsq Generating: N579 ( 3, 2) [000095] ------------ t95 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 /--* t95 ref Generating: N581 (???,???) [000596] ------------ t596 = * PUTARG_REG ref REG rdi IN00b8: mov rdi, r13 GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N583 ( 3, 10) [000401] ------------ t401 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 IN00b9: mov r11, (reloc 0xd1ffab1e) /--* t401 long Generating: N585 (???,???) [000597] ------------ t597 = * PUTARG_REG long REG r11 Generating: N587 ( 3, 10) [000598] ------------ t598 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN00ba: mov rax, (reloc 0xd1ffab1e) /--* t598 long Generating: N589 ( 5, 12) [000599] -c---------- t599 = * IND long REG NA /--* t596 ref this in rdi +--* t597 long arg1 in r11 +--* t599 long control expr Generating: N591 ( 38, 29) [000122] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add REG NA $VN.Void GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} Call: GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00bb: call qword ptr [rax]Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo]:Add(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo):this Scope info: end block BB20, IL range [0B9..0DF) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) =============== Generating BB21 [0DF..0E1) -> BB15 (always), preds={BB19,BB20} succs={BB15} flags=0x00000000.620b0020: i label target gcsafe bwd IBC LIR BB21 IN (5)={V02 V03 V05 V01 V04 } + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB21 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Liveness not changing: 000000000000003B {V01 V02 V03 V04 V05} Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB21: G_M22628_IG19: ; offs=000468H, funclet=00, bbWeight=0.02 Label: IG20, GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB21, IL range [0DF..0E1) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) Added IP mapping: 0x00DF STACK_EMPTY (G_M22628_IG20,ins#0,ofs#0) label Generating: N595 (???,???) [000493] ------------ IL_OFFSET void IL offset: 0xdf REG NA Generating: N597 ( 1, 1) [000092] ------------ t92 = CNS_INT int 0 REG rax $40 IN00bc: xor eax, eax /--* t92 int Generating: N599 ( 5, 4) [000094] DA---------- * STORE_LCL_VAR int V07 loc1 d:12 NA REG NA IN00bd: mov dword ptr [V07 rbp-2CH], eax Live vars: {V01 V02 V03 V04 V05} => {V01 V02 V03 V04 V05 V07} Scope info: end block BB21, IL range [0DF..0E1) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) IN00be: jmp L_M22628_BB15 =============== Generating BB22 [048..053) -> BB04 (cond), preds={BB03} succs={BB23,BB04} flags=0x00000004.600b0020: i label target gcsafe IBC LIR BB22 IN (7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB22 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Change life 00000000000000BB {V01 V02 V03 V04 V05 V07} -> 00000000000000FB {V00 V01 V02 V03 V04 V05 V07} V00 becoming live Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB22: G_M22628_IG20: ; offs=0004A0H, funclet=00, bbWeight=0.02 Label: IG21, GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB22, IL range [048..053) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) 7 (V07 loc1) [000..0EE) Added IP mapping: 0x0048 STACK_EMPTY (G_M22628_IG21,ins#0,ofs#0) label Generating: N603 (???,???) [000494] ------------ IL_OFFSET void IL offset: 0x48 REG NA Generating: N605 ( 1, 1) [000155] ------------ t155 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t155 ref Generating: N607 (???,???) [000600] ------------ t600 = * PUTARG_REG ref REG rdi IN00bf: mov rdi, rbx GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N609 ( 1, 1) [000156] ------------ t156 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t156 ref Generating: N611 (???,???) [000601] ------------ t601 = * PUTARG_REG ref REG rsi IN00c0: mov rsi, r14 GC regs: 00007088 {rbx rdi r12 r13 r14} => 000070C8 {rbx rsi rdi r12 r13 r14} Generating: N613 ( 3, 2) [000157] ------------ t157 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 /--* t157 ref Generating: N615 (???,???) [000602] ------------ t602 = * PUTARG_REG ref REG rdx IN00c1: mov rdx, r13 GC regs: 000070C8 {rbx rsi rdi r12 r13 r14} => 000070CC {rdx rbx rsi rdi r12 r13 r14} Generating: N617 ( 3, 10) [000603] ------------ t603 = CNS_INT(h) long 0xd1ffab1e ftn REG rcx IN00c2: mov rcx, (reloc 0xd1ffab1e) /--* t603 long Generating: N619 ( 5, 12) [000604] -c---------- t604 = * IND long REG NA /--* t600 ref arg0 in rdi +--* t601 ref arg1 in rsi +--* t602 ref arg2 in rdx +--* t604 long control expr Generating: N621 ( 19, 12) [000158] --CXG------- t158 = * CALL r2r_ind bool Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper.SatisfiesConstructorConstraint REG rax $209 GC regs: 000070CC {rdx rbx rsi rdi r12 r13 r14} => 0000704C {rdx rbx rsi r12 r13 r14} GC regs: 0000704C {rdx rbx rsi r12 r13 r14} => 0000700C {rdx rbx r12 r13 r14} GC regs: 0000700C {rdx rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} Call: GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00c3: call qword ptr [rcx]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesConstructorConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool Generating: N623 ( 1, 1) [000160] -c---------- t160 = CNS_INT bool 0 REG NA $40 /--* t158 bool +--* t160 bool Generating: N625 ( 22, 16) [000161] J--XG--N-U-- * NE void REG NA $289 IN00c4: test al, al Generating: N627 ( 24, 18) [000162] ---XG------- * JTRUE void REG NA IN00c5: jne L_M22628_BB04 Scope info: end block BB22, IL range [048..053) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) 7 (V07 loc1) [000..0EE) =============== Generating BB23 [053..055) -> BB04 (always), preds={BB22} succs={BB04} flags=0x00000000.60081020: i rare gcsafe IBC LIR BB23 IN (6)={V02 V03 V05 V01 V04 V00 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB23 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Change life 00000000000000FB {V00 V01 V02 V03 V04 V05 V07} -> 000000000000007B {V00 V01 V02 V03 V04 V05} Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB23: G_M22628_IG21: ; offs=0004AAH, funclet=00, bbWeight=0.01 Label: IG22, GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB23, IL range [053..055) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) Added IP mapping: 0x0053 STACK_EMPTY (G_M22628_IG22,ins#0,ofs#0) label Generating: N631 (???,???) [000495] ------------ IL_OFFSET void IL offset: 0x53 REG NA Generating: N633 ( 1, 1) [000163] ------------ t163 = CNS_INT int 0 REG rax $40 IN00c6: xor eax, eax /--* t163 int Generating: N635 ( 5, 4) [000165] DA---------- * STORE_LCL_VAR int V07 loc1 d:5 rax REG rax V07 in reg rax is becoming live [000165] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F009 {rax rbx r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V07} Generating: N001 ( 4, 3) [000629] -----------Z t629 = LCL_VAR bool V07 loc1 rax REG rax IN00c7: mov dword ptr [V07 rbp-2CH], eax V07 in reg rax is becoming dead [000629] Live regs: 0000F009 {rax rbx r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Scope info: end block BB23, IL range [053..055) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) IN00c8: jmp L_M22628_BB04 =============== Generating BB24 [008..00F) -> BB08 (always), preds={BB01} succs={BB08} flags=0x00000000.600b1020: i rare label target gcsafe IBC LIR BB24 IN (0)={ } OUT(1)={V06} Recording Var Locations at start of BB24 Change life 00000000000000FB {V00 V01 V02 V03 V04 V05 V07} -> 0000000000000000 {} V02 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V03 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V05 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V01 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V04 in reg r13 is becoming dead [------] Live regs: (unchanged) 00000000 {} V00 becoming dead Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M22628_BB24: G_M22628_IG22: ; offs=0004C7H, funclet=00, bbWeight=0 Label: IG23, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB24, IL range [008..00F) Scope info: open scopes = Added IP mapping: 0x0008 STACK_EMPTY (G_M22628_IG23,ins#0,ofs#0) label Generating: N639 (???,???) [000496] ------------ IL_OFFSET void IL offset: 0x8 REG NA Generating: N641 ( 1, 1) [000195] -c---------- t195 = CNS_INT int 1 REG NA $41 /--* t195 int Generating: N643 ( 5, 4) [000197] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 rax REG rax IN00c9: mov eax, 1 V06 in reg rax is becoming live [000197] Live regs: 00000000 {} => 00000001 {rax} Live vars: {} => {V06} Scope info: end block BB24, IL range [008..00F) Scope info: open scopes = IN00ca: jmp L_M22628_BB08 =============== Generating BB25 [019..01D) -> BB27 (cond), preds={BB02} succs={BB26,BB27} flags=0x00000000.600b1020: i rare label target gcsafe IBC LIR BB25 IN (6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap Recording Var Locations at start of BB25 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Change life 0000000000000100 {V06} -> 000000000000007B {V00 V01 V02 V03 V04 V05} V06 in reg rax is becoming dead [------] Live regs: (unchanged) 00000000 {} V02 in reg rbx is becoming live [------] Live regs: 00000000 {} => 00000008 {rbx} V03 in reg r14 is becoming live [------] Live regs: 00000008 {rbx} => 00004008 {rbx r14} V05 in reg r15 is becoming live [------] Live regs: 00004008 {rbx r14} => 0000C008 {rbx r14 r15} V01 in reg r12 is becoming live [------] Live regs: 0000C008 {rbx r14 r15} => 0000D008 {rbx r12 r14 r15} V04 in reg r13 is becoming live [------] Live regs: 0000D008 {rbx r12 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} V00 becoming live Live regs: (unchanged) 0000F008 {rbx r12 r13 r14 r15} GC regs: (unchanged) 00007008 {rbx r12 r13 r14} Byref regs: (unchanged) 00008000 {r15} L_M22628_BB25: G_M22628_IG23: ; offs=0004D1H, funclet=00, bbWeight=0 Label: IG24, GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB25, IL range [019..01D) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) Added IP mapping: 0x0019 STACK_EMPTY (G_M22628_IG24,ins#0,ofs#0) label Generating: N647 (???,???) [000497] ------------ IL_OFFSET void IL offset: 0x19 REG NA Generating: N649 ( 3, 2) [000166] ------------ t166 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 Generating: N651 ( 1, 1) [000167] -c---------- t167 = CNS_INT ref null REG NA $VN.Null /--* t166 ref +--* t167 ref Generating: N653 ( 5, 4) [000168] J------N---- * EQ void REG NA $284 IN00cb: test r13, r13 Generating: N655 ( 7, 6) [000169] ------------ * JTRUE void REG NA IN00cc: je L_M22628_BB27 Scope info: end block BB25, IL range [019..01D) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) =============== Generating BB26 [01D..03E), preds={BB25} succs={BB27} flags=0x00000004.60e81020: i rare gcsafe idxlen new[] newobj IBC LIR BB26 IN (6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V00} + ByrefExposed + GcHeap Recording Var Locations at start of BB26 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Liveness not changing: 000000000000007B {V00 V01 V02 V03 V04 V05} Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB26: Scope info: begin block BB26, IL range [01D..03E) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) Added IP mapping: 0x001D STACK_EMPTY (G_M22628_IG24,ins#2,ofs#9) label Generating: N659 (???,???) [000498] ------------ IL_OFFSET void IL offset: 0x1d REG NA Generating: N661 ( 1, 1) [000176] ------------ t176 = CNS_INT long 1 REG rdi $2c0 IN00cd: mov edi, 1 /--* t176 long Generating: N663 (???,???) [000605] ------------ t605 = * PUTARG_REG long REG rdi Generating: N665 ( 3, 10) [000606] ------------ t606 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN00ce: mov rax, (reloc 0xd1ffab1e) /--* t606 long Generating: N667 ( 5, 12) [000607] -c---------- t607 = * IND long REG NA /--* t605 long arg0 in rdi +--* t607 long control expr Generating: N669 ( 15, 7) [000177] --CXG------- t177 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEWARR_1 REG rax $342 Call: GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00cf: call gword ptr [rax]CORINFO_HELP_READYTORUN_NEWARR_1 GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} /--* t177 ref Generating: N671 ( 19, 10) [000179] DA-XG------- * STORE_LCL_VAR ref V16 tmp5 d:2 rax REG rax GC regs: 00007009 {rax rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} V16 in reg rax is becoming live [000179] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F009 {rax rbx r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V16} GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} Generating: N673 ( 1, 1) [000182] -c---------- t182 = CNS_INT int 0 REG NA $40 Generating: N675 ( 3, 2) [000181] ------------ t181 = LCL_VAR ref V16 tmp5 u:2 rax REG rax $380 /--* t181 ref Generating: N677 (???,???) [000507] -c---------- t507 = * LEA(b+8) ref REG NA /--* t507 ref Generating: N679 ( 5, 4) [000291] -c-X-------- t291 = * IND int REG NA $285 /--* t182 int +--* t291 int Generating: N681 ( 10, 12) [000292] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA $348 IN00d0: cmp dword ptr [rax+8], 0 IN00d1: jbe L_M22628_BB29 Generating: N683 ( 3, 2) [000289] -----------Z t289 = LCL_VAR ref V16 tmp5 u:2 rax REG rax $380 /--* t289 ref Generating: N685 ( 4, 3) [000297] ------------ t297 = * LEA(b+16) byref REG rdi IN00d2: mov gword ptr [V16 rbp-E0H], rax V16 in reg rax is becoming dead [000289] Live regs: 0000F009 {rax rbx r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00007009 {rax rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} Var V16 becoming live IN00d3: lea rdi, bword ptr [rax+16] Byref regs: 00008000 {r15} => 00008080 {rdi r15} Generating: N687 ( 1, 1) [000183] ------------ t183 = LCL_VAR ref V03 arg3 u:1 r14 REG r14 $83 /--* t297 byref +--* t183 ref Generating: N689 (???,???) [000499] -A-XG------- * STOREIND ref REG NA Byref regs: 00008080 {rdi r15} => 00008000 {r15} IN00d4: mov rsi, r14 NoGC Call: savedSet=0000F008 {rbx r12 r13 r14 r15} Call: GCvars=0000000000040040 {V00 V16}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00d5: call CORINFO_HELP_ASSIGN_REF Generating: N691 ( 3, 10) [000608] ------------ t608 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN00d6: mov rax, (reloc 0xd1ffab1e) /--* t608 long Generating: N693 ( 5, 12) [000609] -c---------- t609 = * IND long REG NA /--* t609 long control expr Generating: N695 ( 14, 5) [000214] --C--------- t214 = * CALL help r2r_ind ref HELPER.CORINFO_HELP_READYTORUN_NEW REG rax $34c Call: GCvars=0000000000040040 {V00 V16}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00d7: call gword ptr [rax]CORINFO_HELP_READYTORUN_NEW GC regs: 00007008 {rbx r12 r13 r14} => 00007009 {rax rbx r12 r13 r14} /--* t214 ref Generating: N697 ( 18, 8) [000216] DA---------- * STORE_LCL_VAR ref V18 tmp7 d:2 NA REG NA GC regs: 00007009 {rax rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} IN00d8: mov gword ptr [V18 rbp-E8H], rax Live vars: {V00 V01 V02 V03 V04 V05 V16} => {V00 V01 V02 V03 V04 V05 V16 V18} GCvars: {V00 V16} => {V00 V16 V18} Generating: N699 ( 3, 10) [000610] ------------ t610 = CNS_INT(h) long 0xd1ffab1e ftn REG rdi IN00d9: mov rdi, (reloc 0xd1ffab1e) /--* t610 long Generating: N701 ( 5, 12) [000611] -c---------- t611 = * IND long REG NA /--* t611 long control expr Generating: N703 ( 14, 5) [000207] H-CXG------- t207 = * CALL help r2r_ind byref HELPER.CORINFO_HELP_READYTORUN_STATIC_BASE REG rax $401 Call: GCvars=00000000000C0040 {V00 V16 V18}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00da: call bword ptr [rdi]CORINFO_HELP_READYTORUN_STATIC_BASE Byref regs: 00008000 {r15} => 00008001 {rax r15} /--* t207 byref Generating: N705 ( 15, 9) [000209] -c---------- t209 = * LEA(b+1048) byref REG NA /--* t209 byref Generating: N707 ( 17, 11) [000210] ---XG------- t210 = * IND ref REG rsi Byref regs: 00008001 {rax r15} => 00008000 {r15} IN00db: mov rsi, gword ptr [rax+0418H] GC regs: 00007008 {rbx r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} /--* t210 ref Generating: N709 ( 21, 14) [000300] DA-XG-----L- * STORE_LCL_VAR ref V24 tmp13 d:2 rsi REG rsi GC regs: 00007048 {rbx rsi r12 r13 r14} => 00007008 {rbx r12 r13 r14} V24 in reg rsi is becoming live [000300] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F048 {rbx rsi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V16 V18} => {V00 V01 V02 V03 V04 V05 V16 V18 V24} GC regs: 00007008 {rbx r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} Generating: N711 ( 3, 2) [000301] ------------ t301 = LCL_VAR ref V24 tmp13 u:2 rsi (last use) REG rsi /--* t301 ref Generating: N713 (???,???) [000612] ------------ t612 = * PUTARG_REG ref REG rsi V24 in reg rsi is becoming dead [000301] Live regs: 0000F048 {rbx rsi r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V16 V18 V24} => {V00 V01 V02 V03 V04 V05 V16 V18} GC regs: 00007048 {rbx rsi r12 r13 r14} => 00007008 {rbx r12 r13 r14} GC regs: 00007008 {rbx r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} Generating: N715 ( 3, 2) [000217] -----------z t217 = LCL_VAR ref V18 tmp7 u:2 rdi REG rdi $34c /--* t217 ref Generating: N717 (???,???) [000613] ------------ t613 = * PUTARG_REG ref REG rdi IN00dc: mov rdi, gword ptr [V18 rbp-E8H] GC regs: 00007048 {rbx rsi r12 r13 r14} => 000070C8 {rbx rsi rdi r12 r13 r14} GC regs: 000070C8 {rbx rsi rdi r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} GC regs: 00007048 {rbx rsi r12 r13 r14} => 000070C8 {rbx rsi rdi r12 r13 r14} Generating: N719 ( 3, 2) [000180] -----------z t180 = LCL_VAR ref V16 tmp5 u:2 rcx (last use) REG rcx $380 /--* t180 ref Generating: N721 (???,???) [000614] ------------ t614 = * PUTARG_REG ref REG rcx IN00dd: mov rcx, gword ptr [V16 rbp-E0H] Removing V16 from gcVarPtrSetCur V16 in reg rcx is becoming live [000180] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F00A {rcx rbx r12 r13 r14 r15} GC regs: 000070C8 {rbx rsi rdi r12 r13 r14} => 000070CA {rcx rbx rsi rdi r12 r13 r14} V16 in reg rcx is becoming dead [000180] Live regs: 0000F00A {rcx rbx r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V16 V18} => {V00 V01 V02 V03 V04 V05 V18} GC regs: 000070CA {rcx rbx rsi rdi r12 r13 r14} => 000070C8 {rbx rsi rdi r12 r13 r14} GC regs: 000070C8 {rbx rsi rdi r12 r13 r14} => 000070CA {rcx rbx rsi rdi r12 r13 r14} Generating: N723 ( 1, 4) [000211] ------------ t211 = CNS_INT int 0x7AA4 REG rdx $49 IN00de: mov edx, 0x7AA4 /--* t211 int Generating: N725 (???,???) [000615] ------------ t615 = * PUTARG_REG int REG rdx Generating: N727 ( 3, 10) [000616] ------------ t616 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN00df: mov rax, (reloc 0xd1ffab1e) /--* t616 long Generating: N729 ( 5, 12) [000617] -c---------- t617 = * IND long REG NA /--* t612 ref arg1 in rsi +--* t613 ref this in rdi +--* t614 ref arg3 in rcx +--* t615 int arg2 in rdx +--* t617 long control expr Generating: N731 ( 48, 34) [000218] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.DiagnosticInfo..ctor REG NA $VN.Void GC regs: 000070CA {rcx rbx rsi rdi r12 r13 r14} => 0000708A {rcx rbx rdi r12 r13 r14} GC regs: 0000708A {rcx rbx rdi r12 r13 r14} => 0000700A {rcx rbx r12 r13 r14} GC regs: 0000700A {rcx rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} Call: GCvars=0000000000080040 {V00 V18}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00e0: call qword ptr [rax]Microsoft.CodeAnalysis.DiagnosticInfo:.ctor(Microsoft.CodeAnalysis.CommonMessageProvider,int,System.Object[]):this Generating: N733 ( 3, 3) [000189] ------------ t189 = LCL_VAR_ADDR byref V17 tmp6 rdi REG rdi $481 IN00e1: lea rdi, bword ptr [V17 rbp-B8H] Byref regs: 00008000 {r15} => 00008080 {rdi r15} /--* t189 byref Generating: N735 (???,???) [000618] ------------ t618 = * PUTARG_REG byref REG rdi Byref regs: 00008080 {rdi r15} => 00008000 {r15} Byref regs: 00008000 {r15} => 00008080 {rdi r15} Generating: N737 ( 1, 1) [000174] ------------ t174 = LCL_VAR ref V02 arg2 u:1 rbx REG rbx $82 /--* t174 ref Generating: N739 (???,???) [000619] ------------ t619 = * PUTARG_REG ref REG rsi IN00e2: mov rsi, rbx GC regs: 00007008 {rbx r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} Generating: N741 ( 3, 2) [000219] -----------z t219 = LCL_VAR ref V18 tmp7 u:2 rdx (last use) REG rdx $34c /--* t219 ref Generating: N743 (???,???) [000620] ------------ t620 = * PUTARG_REG ref REG rdx IN00e3: mov rdx, gword ptr [V18 rbp-E8H] Removing V18 from gcVarPtrSetCur V18 in reg rdx is becoming live [000219] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F00C {rdx rbx r12 r13 r14 r15} GC regs: 00007048 {rbx rsi r12 r13 r14} => 0000704C {rdx rbx rsi r12 r13 r14} V18 in reg rdx is becoming dead [000219] Live regs: 0000F00C {rdx rbx r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V18} => {V00 V01 V02 V03 V04 V05} GC regs: 0000704C {rdx rbx rsi r12 r13 r14} => 00007048 {rbx rsi r12 r13 r14} GC regs: 00007048 {rbx rsi r12 r13 r14} => 0000704C {rdx rbx rsi r12 r13 r14} Generating: N745 ( 3, 10) [000621] ------------ t621 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN00e4: mov rax, (reloc 0xd1ffab1e) /--* t621 long Generating: N747 ( 5, 12) [000622] -c---------- t622 = * IND long REG NA /--* t618 byref this in rdi +--* t619 ref arg1 in rsi +--* t620 ref arg2 in rdx +--* t622 long control expr Generating: N749 ( 21, 15) [000190] --CXG------- * CALL r2r_ind void Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo..ctor REG NA $VN.Void Byref regs: 00008080 {rdi r15} => 00008000 {r15} GC regs: 0000704C {rdx rbx rsi r12 r13 r14} => 0000700C {rdx rbx r12 r13 r14} GC regs: 0000700C {rdx rbx r12 r13 r14} => 00007008 {rbx r12 r13 r14} Call: GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00e5: call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this Added IP mapping: 0x0039 (G_M22628_IG24,ins#27,ofs#153) Generating: N751 (???,???) [000500] ------------ IL_OFFSET void IL offset: 0x39 REG NA Generating: N753 ( 3, 2) [000191] -c-----N---- t191 = LCL_VAR_ADDR byref V17 tmp6 NA REG NA /--* t191 byref Generating: N755 ( 9, 7) [000194] nc--G------- t194 = * OBJ struct REG NA /--* t194 struct Generating: N757 (???,???) [000623] ----G------- * PUTARG_STK [+0x00] void (5 slots) (RepInstr) REG NA IN00e6: lea rdi, [V11 rsp] IN00e7: lea rsi, [V17 rbp-B8H] IN00e8: mov rcx, gword ptr [rsi] IN00e9: mov gword ptr [V11 rsp], rcx IN00ea: add rsi, 8 IN00eb: add rdi, 8 IN00ec: mov rcx, gword ptr [rsi] IN00ed: mov gword ptr [V11+0x8 rsp+08H], rcx IN00ee: add rsi, 8 IN00ef: add rdi, 8 IN00f0: mov rcx, gword ptr [rsi] IN00f1: mov gword ptr [V11+0x10 rsp+10H], rcx IN00f2: add rsi, 8 IN00f3: add rdi, 8 IN00f4: mov rcx, gword ptr [rsi] IN00f5: mov gword ptr [V11+0x18 rsp+18H], rcx IN00f6: add rsi, 8 IN00f7: add rdi, 8 IN00f8: movsq Generating: N759 ( 3, 2) [000173] ------------ t173 = LCL_VAR ref V04 arg4 u:1 r13 REG r13 $84 /--* t173 ref Generating: N761 (???,???) [000624] ------------ t624 = * PUTARG_REG ref REG rdi IN00f9: mov rdi, r13 GC regs: 00007008 {rbx r12 r13 r14} => 00007088 {rbx rdi r12 r13 r14} Generating: N763 ( 3, 10) [000308] ------------ t308 = CNS_INT(h) long 0xd1ffab1e ftn REG r11 $1c7 IN00fa: mov r11, (reloc 0xd1ffab1e) /--* t308 long Generating: N765 (???,???) [000625] ------------ t625 = * PUTARG_REG long REG r11 Generating: N767 ( 3, 10) [000626] ------------ t626 = CNS_INT(h) long 0xd1ffab1e ftn REG rax IN00fb: mov rax, (reloc 0xd1ffab1e) /--* t626 long Generating: N769 ( 5, 12) [000627] -c---------- t627 = * IND long REG NA /--* t624 ref this in rdi +--* t625 long arg1 in r11 +--* t627 long control expr Generating: N771 ( 38, 29) [000192] --CXG------- * CALLV stub void Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo].Add REG NA $VN.Void GC regs: 00007088 {rbx rdi r12 r13 r14} => 00007008 {rbx r12 r13 r14} Call: GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} G_M22628_IG24: ; offs=0004DBH, funclet=00, bbWeight=0 IN00fc: call qword ptr [rax]Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo]:Add(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo):this Scope info: end block BB26, IL range [01D..03E) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) =============== Generating BB27 [03E..040) -> BB03 (always), preds={BB25,BB26} succs={BB03} flags=0x00000000.600b1020: i rare label target gcsafe IBC LIR BB27 IN (6)={V02 V03 V05 V01 V04 V00 } + ByrefExposed + GcHeap OUT(7)={V02 V03 V05 V01 V04 V00 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB27 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Liveness not changing: 000000000000007B {V00 V01 V02 V03 V04 V05} Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB27: G_M22628_IG25: ; offs=0005D7H, funclet=00, bbWeight=0 Label: IG26, GCvars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB27, IL range [03E..040) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) Added IP mapping: 0x003E STACK_EMPTY (G_M22628_IG26,ins#0,ofs#0) label Generating: N775 (???,???) [000501] ------------ IL_OFFSET void IL offset: 0x3e REG NA Generating: N777 ( 1, 1) [000170] ------------ t170 = CNS_INT int 0 REG rax $40 IN00fd: xor eax, eax /--* t170 int Generating: N779 ( 5, 4) [000172] DA---------- * STORE_LCL_VAR int V07 loc1 d:3 rax REG rax V07 in reg rax is becoming live [000172] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F009 {rax rbx r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V07} Generating: N001 ( 4, 3) [000630] -----------Z t630 = LCL_VAR bool V07 loc1 rax REG rax IN00fe: mov dword ptr [V07 rbp-2CH], eax V07 in reg rax is becoming dead [000630] Live regs: 0000F009 {rax rbx r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Scope info: end block BB27, IL range [03E..040) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) 0 (V00 arg0) [000..0EE) IN00ff: jmp L_M22628_BB03 =============== Generating BB28 [080..082) -> BB06 (always), preds={BB12} succs={BB06} flags=0x00000000.600b1020: i rare label target gcsafe IBC LIR BB28 IN (5)={V02 V03 V05 V01 V04 } + ByrefExposed + GcHeap OUT(6)={V02 V03 V05 V01 V04 V07} + ByrefExposed + GcHeap Recording Var Locations at start of BB28 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) Change life 00000000000000FB {V00 V01 V02 V03 V04 V05 V07} -> 000000000000003B {V01 V02 V03 V04 V05} V00 becoming dead Live regs: 00000000 {} => 0000F008 {rbx r12 r13 r14 r15} GC regs: 00000000 {} => 00007008 {rbx r12 r13 r14} Byref regs: 00000000 {} => 00008000 {r15} L_M22628_BB28: G_M22628_IG26: ; offs=0005D9H, funclet=00, bbWeight=0 Label: IG27, GCvars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} Scope info: begin block BB28, IL range [080..082) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) Added IP mapping: 0x0080 STACK_EMPTY (G_M22628_IG27,ins#0,ofs#0) label Generating: N783 (???,???) [000502] ------------ IL_OFFSET void IL offset: 0x80 REG NA Generating: N785 ( 1, 1) [000140] ------------ t140 = CNS_INT int 0 REG rax $40 IN0100: xor eax, eax /--* t140 int Generating: N787 ( 5, 4) [000142] DA---------- * STORE_LCL_VAR int V07 loc1 d:9 rax REG rax V07 in reg rax is becoming live [000142] Live regs: 0000F008 {rbx r12 r13 r14 r15} => 0000F009 {rax rbx r12 r13 r14 r15} Live vars: {V01 V02 V03 V04 V05} => {V01 V02 V03 V04 V05 V07} Generating: N001 ( 4, 3) [000631] -----------Z t631 = LCL_VAR bool V07 loc1 rax REG rax IN0101: mov dword ptr [V07 rbp-2CH], eax V07 in reg rax is becoming dead [000631] Live regs: 0000F009 {rax rbx r12 r13 r14 r15} => 0000F008 {rbx r12 r13 r14 r15} Scope info: end block BB28, IL range [080..082) Scope info: open scopes = 2 (V02 arg2) [000..0EE) 3 (V03 arg3) [000..0EE) 5 (V05 arg5) [000..0EE) 1 (V01 arg1) [000..0EE) 4 (V04 arg4) [000..0EE) IN0102: jmp L_M22628_BB06 =============== Generating BB29 [???..???) (throw), preds={} succs={} flags=0x00000000.40031070: keep i internal rare label target LIR BB29 IN (0)={} OUT(0)={} Recording Var Locations at start of BB29 Change life 00000000000000BB {V01 V02 V03 V04 V05 V07} -> 0000000000000000 {} V02 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V03 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V05 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V01 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V04 in reg r13 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M22628_BB29: G_M22628_IG27: ; offs=0005E3H, funclet=00, bbWeight=0 Label: IG28, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB29, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M22628_IG28,ins#0,ofs#0) label Generating: N791 ( 14, 5) [000505] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL REG NA Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0103: call CORINFO_HELP_RNGCHKFAIL Scope info: end block BB29, IL range [???..???) Scope info: ignoring block end IN0104: int3 Liveness not changing: 0000000000000000 {} # compCycleEstimate = 908, compSizeEstimate = 739 Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool ; Final local variable assignments ; ; V00 arg0 [V00,T06] ( 3, 2.01) ref -> [rbp-0xC8] class-hnd ; V01 arg1 [V01,T04] ( 3, 2.29) ref -> r12 class-hnd ; V02 arg2 [V02,T00] ( 11, 6.07) ref -> rbx class-hnd ; V03 arg3 [V03,T01] ( 10, 4.36) ref -> r14 class-hnd ; V04 arg4 [V04,T05] ( 9, 2.09) ref -> r13 class-hnd ; V05 arg5 [V05,T03] ( 6, 3.88) byref -> r15 ; V06 loc0 [V06,T08] ( 3, 2 ) bool -> rax ; V07 loc1 [V07,T07] ( 7, 2.03) bool -> [rbp-0x2C] ; V08 loc2 [V08 ] ( 5, 3.58) struct (16) [rbp-0x40] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V09 loc3 [V09 ] ( 2, 2 ) struct ( 8) [rbp-0x48] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V10 loc4 [V10,T09] ( 5, 1.47) ref -> [rbp-0xD0] class-hnd ; V11 OutArgs [V11 ] ( 1, 1 ) lclBlk (40) [rsp+0x00] "OutgoingArgSpace" ; V12 tmp1 [V12 ] ( 2, 4 ) struct (16) [rbp-0x58] do-not-enreg[XSBR] multireg-ret must-init addr-exposed "Return value temp for multireg return" ; V13 tmp2 [V13,T12] ( 2, 1.16) struct (16) [rbp-0x68] do-not-enreg[SFR] multireg-ret must-init "Return value temp for multireg return" ; V14 tmp3 [V14,T13] ( 5, 0.20) ref -> [rbp-0xD8] class-hnd exact "dup spill" ; V15 tmp4 [V15,T14] ( 4, 0.16) struct (40) [rbp-0x90] do-not-enreg[SFB] must-init "NewObj constructor temp" ; V16 tmp5 [V16,T18] ( 4, 0 ) ref -> [rbp-0xE0] class-hnd exact "dup spill" ; V17 tmp6 [V17 ] ( 2, 0 ) struct (40) [rbp-0xB8] do-not-enreg[XS] must-init addr-exposed "NewObj constructor temp" ; V18 tmp7 [V18,T19] ( 3, 0 ) ref -> [rbp-0xE8] class-hnd exact "NewObj constructor temp" ; V19 tmp8 [V19,T10] ( 2, 0.58) bool -> rsi "Inline stloc first use temp" ; V20 tmp9 [V20,T15] ( 3, 0.12) ref -> [rbp-0xF0] class-hnd exact "NewObj constructor temp" ; V21 tmp10 [V21 ] ( 4, 2.58) ref -> [rbp-0x40] do-not-enreg[X] addr-exposed V08._array(offs=0x00) P-DEP "field V08._array (fldOffset=0x0)" ; V22 tmp11 [V22 ] ( 4, 2.58) int -> [rbp-0x38] do-not-enreg[X] addr-exposed V08._index(offs=0x08) P-DEP "field V08._index (fldOffset=0x8)" ; V23 tmp12 [V23 ] ( 2, 2 ) ref -> [rbp-0x48] do-not-enreg[X] addr-exposed V09.array(offs=0x00) P-DEP "field V09.array (fldOffset=0x0)" ; V24 tmp13 [V24,T20] ( 2, 0 ) ref -> rsi "argument with side effect" ; V25 tmp14 [V25,T02] ( 3, 6 ) byref -> rsi "BlockOp address local" ; V26 tmp15 [V26,T11] ( 2, 1.16) ref -> rdi "argument with side effect" ; V27 tmp16 [V27,T16] ( 2, 0.08) ref -> rsi "argument with side effect" ; V28 cse0 [V28,T17] ( 3, 0.06) int -> [rbp-0xBC] "CSE - conservative" ; ; Lcl frame size = 248 *************** Before prolog / epilog generation G_M22628_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M22628_IG02: ; offs=000000H, size=0024H, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG03: ; offs=000024H, size=0038H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG04: ; offs=00005CH, size=0023H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG05: ; offs=00007FH, size=0021H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG06: ; offs=0000A0H, size=0021H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG07: ; offs=0000C1H, size=0071H, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG08: ; offs=000132H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M22628_IG09: ; epilog placeholder, next placeholder=, BB08 [0022], epilog <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} G_M22628_IG10: ; offs=000239H, size=0072H, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG11: ; offs=0002ABH, size=001BH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG12: ; offs=0002C6H, size=002CH, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG13: ; offs=0002F2H, size=0025H, gcVars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG14: ; offs=000317H, size=0025H, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG15: ; offs=00033CH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M22628_IG16: ; offs=000341H, size=001DH, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG17: ; offs=00035EH, size=000CH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG18: ; offs=00036AH, size=00FEH, gcVars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG19: ; offs=000468H, size=0038H, extend G_M22628_IG20: ; offs=0004A0H, size=000AH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG21: ; offs=0004AAH, size=001DH, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG22: ; offs=0004C7H, size=000AH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG23: ; offs=0004D1H, size=000AH, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref G_M22628_IG24: ; offs=0004DBH, size=00FCH, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG25: ; offs=0005D7H, size=0002H, extend G_M22628_IG26: ; offs=0005D9H, size=000AH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG27: ; offs=0005E3H, size=000AH, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG28: ; offs=0005EDH, size=0000H, gcrefRegs=00000000 {} <-- Current IG Recording Var Locations at start of BB01 V02(rbx) V03(r14) V05(r15) V01(r12) V04(r13) G_M22628_IG28: ; offs=0005EDH, funclet=00, bbWeight=0 *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M22628_IG01,ins#0,ofs#0) label __prolog: Found 34 lvMustInit int-sized stack slots, frame offsets 184 through 48 IN0105: push rbp IN0106: push r15 IN0107: push r14 IN0108: push r13 IN0109: push r12 IN010a: push rbx IN010b: sub rsp, 248 IN010c: lea rbp, [rsp+120H] IN010d: xor rax, rax IN010e: mov qword ptr [rbp-B8H], rax IN010f: xorps xmm8, xmm8 IN0110: movaps xmmword ptr [rbp-B0H], xmm8 IN0111: movaps xmmword ptr [rbp-A0H], xmm8 IN0112: mov rax, -96 IN0113: movaps xmmword ptr [rbp+rax-30H], xmm8 IN0114: movaps xmmword ptr [rbp+rax-20H], xmm8 IN0115: movaps xmmword ptr [rbp+rax-10H], xmm8 IN0116: add rax, 48 IN0117: jne SHORT -5 instr *************** In genClearStackVec3ArgUpperBits() *************** In genFnPrologCalleeRegArgs() for int regs IN0118: mov gword ptr [V00 rbp-C8H], rdi IN0119: mov r12, rsi IN011a: mov rbx, rdx IN011b: mov r14, rcx IN011c: mov r13, r8 IN011d: mov r15, r9 *************** In genEnregisterIncomingStackArgs() 6 tracked GC refs are at stack offsets -00F0 ... FFFFFF40 G_M22628_IG01: ; offs=000000H, funclet=00, bbWeight=1 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {} IN011e: lea rsp, [rbp-28H] IN011f: pop rbx IN0120: pop r12 IN0121: pop r13 IN0122: pop r14 IN0123: pop r15 IN0124: pop rbp IN0125: ret G_M22628_IG09: ; offs=000139H, funclet=00, bbWeight=1 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M22628_IG01: ; func=00, offs=000000H, size=006EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M22628_IG02: ; offs=00006EH, size=0024H, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG03: ; offs=000092H, size=0038H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG04: ; offs=0000CAH, size=0023H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG05: ; offs=0000EDH, size=0021H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG06: ; offs=00010EH, size=0021H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG07: ; offs=00012FH, size=0071H, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG08: ; offs=0001A0H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M22628_IG09: ; offs=0001A7H, size=000FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc G_M22628_IG10: ; offs=0001B6H, size=0072H, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG11: ; offs=000228H, size=001BH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG12: ; offs=000243H, size=002CH, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG13: ; offs=00026FH, size=0025H, gcVars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG14: ; offs=000294H, size=0025H, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG15: ; offs=0002B9H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M22628_IG16: ; offs=0002BEH, size=001DH, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG17: ; offs=0002DBH, size=000CH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG18: ; offs=0002E7H, size=00FEH, gcVars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG19: ; offs=0003E5H, size=0038H, extend G_M22628_IG20: ; offs=00041DH, size=000AH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG21: ; offs=000427H, size=001DH, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG22: ; offs=000444H, size=000AH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG23: ; offs=00044EH, size=000AH, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref G_M22628_IG24: ; offs=000458H, size=00FCH, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG25: ; offs=000554H, size=0002H, extend G_M22628_IG26: ; offs=000556H, size=000AH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref G_M22628_IG27: ; offs=000560H, size=000AH, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref G_M22628_IG28: ; offs=00056AH, size=0006H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref *************** In emitJumpDistBind() Adjusted offset of BB02 from 006E to 006E Binding: IN0007: 000000 je L_M22628_BB24 Binding L_M22628_BB24to G_M22628_IG23 Estimate of fwd jump [D1FFAB1E/007]: 008C -> 044E = 03C0 Adjusted offset of BB03 from 0092 to 0092 Binding: IN0011: 000000 jne L_M22628_BB25 Binding L_M22628_BB25to G_M22628_IG24 Estimate of fwd jump [D1FFAB1E/017]: 00C4 -> 0458 = 0392 Adjusted offset of BB04 from 00CA to 00CA Binding: IN0018: 000000 jne L_M22628_BB22 Binding L_M22628_BB22to G_M22628_IG21 Estimate of fwd jump [D1FFAB1E/024]: 00E7 -> 0427 = 033E Adjusted offset of BB05 from 00ED to 00ED Binding: IN001e: 000000 jne L_M22628_BB17 Binding L_M22628_BB17to G_M22628_IG16 Estimate of fwd jump [D1FFAB1E/030]: 0108 -> 02BE = 01B4 Adjusted offset of BB06 from 010E to 010E Binding: IN0024: 000000 jne L_M22628_BB12 Binding L_M22628_BB12to G_M22628_IG12 Estimate of fwd jump [D1FFAB1E/036]: 0129 -> 0243 = 0118 Adjusted offset of BB07 from 012F to 012F Binding: IN003c: 000000 jne L_M22628_BB09 Binding L_M22628_BB09to G_M22628_IG10 Estimate of fwd jump [D1FFAB1E/060]: 019A -> 01B6 = 001A Shrinking jump [D1FFAB1E/060] Adjusted offset of BB08 from 01A0 to 019C Adjusted offset of BB09 from 01A7 to 01A3 Adjusted offset of BB10 from 01B6 to 01B2 Binding: IN0054: 000000 jne L_M22628_BB14 Binding L_M22628_BB14to G_M22628_IG13 Estimate of fwd jump [D1FFAB1E/084]: 021E -> 026B = 004B Shrinking jump [D1FFAB1E/084] Adjusted offset of BB11 from 0228 to 0220 Binding: IN0059: 000000 jmp L_M22628_BB19 Binding L_M22628_BB19to G_M22628_IG18 Estimate of fwd jump [D1FFAB1E/089]: 0236 -> 02DF = 00A7 Adjusted offset of BB12 from 0243 to 023B Binding: IN0062: 000000 je L_M22628_BB28 Binding L_M22628_BB28to G_M22628_IG27 Estimate of fwd jump [D1FFAB1E/098]: 025C -> 0558 = 02FA Binding: IN0063: 000000 jmp L_M22628_BB06 Binding L_M22628_BB06to G_M22628_IG07 Estimate of bwd jump [D1FFAB1E/099]: 0262 -> 012F = 0135 Adjusted offset of BB13 from 026F to 0267 Binding: IN006b: 000000 je L_M22628_BB19 Binding L_M22628_BB19to G_M22628_IG18 Estimate of fwd jump [D1FFAB1E/107]: 0286 -> 02DF = 0057 Shrinking jump [D1FFAB1E/107] Adjusted offset of BB14 from 0294 to 0288 Binding: IN0072: 000000 jne L_M22628_BB09 Binding L_M22628_BB09to G_M22628_IG10 Estimate of bwd jump [D1FFAB1E/114]: 02A7 -> 01B2 = 00F7 Adjusted offset of BB15 from 02B9 to 02AD Binding: IN0073: 000000 jmp L_M22628_BB07 Binding L_M22628_BB07to G_M22628_IG08 Estimate of bwd jump [D1FFAB1E/115]: 02AD -> 019C = 0113 Adjusted offset of BB16 from 02BE to 02B2 Binding: IN007a: 000000 jne L_M22628_BB05 Binding L_M22628_BB05to G_M22628_IG06 Estimate of bwd jump [D1FFAB1E/122]: 02C9 -> 010E = 01BD Adjusted offset of BB17 from 02DB to 02CF Binding: IN007e: 000000 jmp L_M22628_BB05 Binding L_M22628_BB05to G_M22628_IG06 Estimate of bwd jump [D1FFAB1E/126]: 02D6 -> 010E = 01CA Adjusted offset of BB18 from 02E7 to 02DB Binding: IN0080: 000000 je L_M22628_BB21 Binding L_M22628_BB21to G_M22628_IG20 Estimate of fwd jump [D1FFAB1E/128]: 02DE -> 0411 = 0131 Binding: IN0087: 000000 jbe L_M22628_BB29 Binding L_M22628_BB29to G_M22628_IG28 Estimate of fwd jump [D1FFAB1E/135]: 0301 -> 055E = 025B Binding: IN008d: 000000 jbe L_M22628_BB29 Binding L_M22628_BB29to G_M22628_IG28 Estimate of fwd jump [D1FFAB1E/141]: 0321 -> 055E = 023B Adjusted offset of BB19 from 03E5 to 03D9 Adjusted offset of BB20 from 041D to 0411 Binding: IN00be: 000000 jmp L_M22628_BB15 Binding L_M22628_BB15to G_M22628_IG14 Estimate of bwd jump [D1FFAB1E/190]: 0416 -> 0288 = 0190 Adjusted offset of BB21 from 0427 to 041B Binding: IN00c5: 000000 jne L_M22628_BB04 Binding L_M22628_BB04to G_M22628_IG05 Estimate of bwd jump [D1FFAB1E/197]: 0432 -> 00ED = 0347 Adjusted offset of BB22 from 0444 to 0438 Binding: IN00c8: 000000 jmp L_M22628_BB04 Binding L_M22628_BB04to G_M22628_IG05 Estimate of bwd jump [D1FFAB1E/200]: 043D -> 00ED = 0352 Adjusted offset of BB23 from 044E to 0442 Binding: IN00ca: 000000 jmp L_M22628_BB08 Binding L_M22628_BB08to G_M22628_IG09 Estimate of bwd jump [D1FFAB1E/202]: 0447 -> 01A3 = 02A6 Adjusted offset of BB24 from 0458 to 044C Binding: IN00cc: 000000 je L_M22628_BB27 Binding L_M22628_BB27to G_M22628_IG26 Estimate of fwd jump [D1FFAB1E/204]: 044F -> 054A = 00F9 Binding: IN00d1: 000000 jbe L_M22628_BB29 Binding L_M22628_BB29to G_M22628_IG28 Estimate of fwd jump [D1FFAB1E/209]: 046A -> 055E = 00F2 Adjusted offset of BB25 from 0554 to 0548 Adjusted offset of BB26 from 0556 to 054A Binding: IN00ff: 000000 jmp L_M22628_BB03 Binding L_M22628_BB03to G_M22628_IG04 Estimate of bwd jump [D1FFAB1E/255]: 054F -> 00CA = 0487 Adjusted offset of BB27 from 0560 to 0554 Binding: IN0102: 000000 jmp L_M22628_BB06 Binding L_M22628_BB06to G_M22628_IG07 Estimate of bwd jump [D1FFAB1E/258]: 0559 -> 012F = 042C Adjusted offset of BB28 from 056A to 055E Total shrinkage = 12, min extra jump size = 40 *************** Finishing PHASE Generate code *************** Starting PHASE Emit code Hot code size = 0x564 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x14) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M22628_IG01: ; func=00, offs=000000H, size=006EH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN0105: 000000 push rbp IN0106: 000001 push r15 IN0107: 000003 push r14 IN0108: 000005 push r13 IN0109: 000007 push r12 IN010a: 000009 push rbx IN010b: 00000A sub rsp, 248 IN010c: 000011 lea rbp, [rsp+120H] IN010d: 000019 xor rax, rax IN010e: 00001B mov qword ptr [rbp-B8H], rax IN010f: 000022 xorps xmm8, xmm8 IN0110: 000026 movaps xmmword ptr [rbp-B0H], xmm8 IN0111: 00002E movaps xmmword ptr [rbp-A0H], xmm8 IN0112: 000036 mov rax, -96 IN0113: 000040 movaps xmmword ptr [rbp+rax-30H], xmm8 IN0114: 000046 movaps xmmword ptr [rbp+rax-20H], xmm8 IN0115: 00004C movaps xmmword ptr [rbp+rax-10H], xmm8 IN0116: 000052 add rax, 48 IN0117: 000056 jne SHORT -5 instr [D1FFAB1E] gcr var born at [rbp-C8H] IN0118: 000058 mov gword ptr [rbp-C8H], rdi gcrReg +[r12] IN0119: 00005F mov r12, rsi gcrReg +[rbx] IN011a: 000062 mov rbx, rdx gcrReg +[r14] IN011b: 000065 mov r14, rcx gcrReg +[r13] IN011c: 000068 mov r13, r8 byrReg +[r15] IN011d: 00006B mov r15, r9 ;; bbWeight=1 PerfScore 27.08 G_M22628_IG02: ; func=00, offs=00006EH, size=0024H, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref New GC ref live vars=0000000000000040 {V00} gcrReg +[rdi] IN0001: 00006E mov rdi, r14 IN0002: 000071 mov r11, (reloc 0xd1ffab1e) IN0003: 00007B mov rsi, (reloc 0xd1ffab1e) IN0004: 000085 cmp dword ptr [rdi], edi New gcrReg live regs=00007008 {rbx r12 r13 r14} ; Call at 0087 [stk=0], GCvars=[rbp-C8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0005: 000087 call qword ptr [rsi]Microsoft.CodeAnalysis.VisualBasic.Symbol:get_Kind():int:this IN0006: 000089 cmp eax, 4 IN0007: 00008C je G_M22628_IG23 ;; bbWeight=1 PerfScore 7.00 G_M22628_IG03: ; func=00, offs=000092H, size=0038H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN0008: 000092 mov dword ptr [rbp-2CH], 1 gcrReg +[rdi] IN0009: 000099 mov rdi, r14 IN000a: 00009C mov r11, (reloc 0xd1ffab1e) IN000b: 0000A6 mov rsi, (reloc 0xd1ffab1e) New gcrReg live regs=00007008 {rbx r12 r13 r14} ; Call at 00B0 [stk=0], GCvars=[rbp-C8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN000c: 0000B0 call qword ptr [rsi]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol:get_SpecialType():byte:this IN000d: 0000B2 movsx rdi, al IN000e: 0000B6 mov rax, (reloc 0xd1ffab1e) ; Call at 00C0 [stk=0], GCvars=[rbp-C8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN000f: 0000C0 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions:IsRestrictedType(byte):bool IN0010: 0000C2 test al, al IN0011: 0000C4 jne G_M22628_IG24 ;; bbWeight=1 PerfScore 9.50 G_M22628_IG04: ; func=00, offs=0000CAH, size=0023H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref gcrReg +[rdi] IN0012: 0000CA mov rdi, rbx IN0013: 0000CD mov r11, (reloc 0xd1ffab1e) IN0014: 0000D7 mov rax, (reloc 0xd1ffab1e) IN0015: 0000E1 cmp dword ptr [rdi], edi New gcrReg live regs=00007008 {rbx r12 r13 r14} ; Call at 00E3 [stk=0], GCvars=[rbp-C8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0016: 0000E3 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasConstructorConstraint():bool:this IN0017: 0000E5 test al, al IN0018: 0000E7 jne G_M22628_IG21 ;; bbWeight=1 PerfScore 7.00 G_M22628_IG05: ; func=00, offs=0000EDH, size=0021H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref gcrReg +[rdi] IN0019: 0000ED mov rdi, rbx IN001a: 0000F0 mov r11, (reloc 0xd1ffab1e) IN001b: 0000FA mov rax, (reloc 0xd1ffab1e) New gcrReg live regs=00007008 {rbx r12 r13 r14} ; Call at 0104 [stk=0], GCvars=[rbp-C8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN001c: 000104 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasReferenceTypeConstraint():bool:this IN001d: 000106 test al, al IN001e: 000108 jne G_M22628_IG16 ;; bbWeight=1 PerfScore 5.00 G_M22628_IG06: ; func=00, offs=00010EH, size=0021H, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref gcrReg +[rdi] IN001f: 00010E mov rdi, rbx IN0020: 000111 mov r11, (reloc 0xd1ffab1e) IN0021: 00011B mov rax, (reloc 0xd1ffab1e) New gcrReg live regs=00007008 {rbx r12 r13 r14} ; Call at 0125 [stk=0], GCvars=[rbp-C8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0022: 000125 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasValueTypeConstraint():bool:this IN0023: 000127 test al, al IN0024: 000129 jne G_M22628_IG12 ;; bbWeight=1 PerfScore 5.00 G_M22628_IG07: ; func=00, offs=00012FH, size=006DH, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref, isz New GC ref live vars=0000000000000000 {} [D1FFAB1E] gcr var died at [rbp-C8H] gcrReg +[rdi] IN0025: 00012F mov rdi, rbx byrReg +[rsi] IN0026: 000132 mov rsi, r15 IN0027: 000135 mov rax, (reloc 0xd1ffab1e) New gcrReg live regs=00007009 {rax rbx r12 r13 r14} New byrReg live regs=00008000 {r15} ; Call at 013F [stk=0], GCvars=none, gcrefRegs=00007009 {rax rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0028: 00013F call gword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:ConstraintTypesWithDefinitionUseSiteDiagnostics(byref):System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]:this IN0029: 000141 mov gword ptr [rbp-48H], rax IN002a: 000145 mov rsi, (reloc 0xd1ffab1e) IN002b: 00014F mov rsi, qword ptr [rsi] byrReg +[rdi] IN002c: 000152 lea rdi, bword ptr [rbp-48H] gcrReg -[rax] IN002d: 000156 mov rax, (reloc 0xd1ffab1e) New gcrReg live regs=00007009 {rax rbx r12 r13 r14} New byrReg live regs=00008000 {r15} ; Call at 0160 [stk=0], GCvars=none, gcrefRegs=00007009 {rax rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN002e: 000160 call gword ptr [rax]System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:GetEnumerator():Enumerator[__Canon]:this IN002f: 000162 mov gword ptr [rbp-58H], rax IN0030: 000166 mov qword ptr [rbp-50H], rdx byrReg +[rsi] IN0031: 00016A lea rsi, bword ptr [rbp-58H] gcrReg +[rdi] IN0032: 00016E mov rdi, gword ptr [rsi] IN0033: 000171 mov gword ptr [rbp-40H], rdi byrReg -[rsi] IN0034: 000175 mov esi, dword ptr [rsi+8] IN0035: 000178 mov dword ptr [rbp-38H], esi IN0036: 00017B mov rsi, (reloc 0xd1ffab1e) IN0037: 000185 mov rsi, qword ptr [rsi] gcrReg -[rdi] byrReg +[rdi] IN0038: 000188 lea rdi, bword ptr [rbp-40H] gcrReg -[rax] IN0039: 00018C mov rax, (reloc 0xd1ffab1e) New byrReg live regs=00008000 {r15} ; Call at 0196 [stk=0], GCvars=none, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN003a: 000196 call qword ptr [rax]Enumerator[__Canon][System.__Canon]:MoveNext():bool:this IN003b: 000198 test al, al IN003c: 00019A jne SHORT G_M22628_IG10 ;; bbWeight=1 PerfScore 26.50 G_M22628_IG08: ; func=00, offs=00019CH, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref New gcrReg live regs=00000000 {} New byrReg live regs=00000000 {} IN003d: 00019C mov r13d, dword ptr [rbp-2CH] IN003e: 0001A0 mov eax, r13d ;; bbWeight=1 PerfScore 1.25 G_M22628_IG09: ; func=00, offs=0001A3H, size=000FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc IN011e: 0001A3 lea rsp, [rbp-28H] IN011f: 0001A7 pop rbx IN0120: 0001A8 pop r12 IN0121: 0001AA pop r13 IN0122: 0001AC pop r14 IN0123: 0001AE pop r15 IN0124: 0001B0 pop rbp IN0125: 0001B1 ret ;; bbWeight=1 PerfScore 4.50 G_M22628_IG10: ; func=00, offs=0001B2H, size=006EH, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref, isz New gcrReg live regs=00007008 {rbx r12 r13 r14} New byrReg live regs=00008000 {r15} IN003f: 0001B2 mov rsi, (reloc 0xd1ffab1e) IN0040: 0001BC mov rsi, qword ptr [rsi] byrReg +[rdi] IN0041: 0001BF lea rdi, bword ptr [rbp-40H] IN0042: 0001C3 mov rax, (reloc 0xd1ffab1e) New gcrReg live regs=00007009 {rax rbx r12 r13 r14} New byrReg live regs=00008000 {r15} ; Call at 01CD [stk=0], GCvars=none, gcrefRegs=00007009 {rax rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0043: 0001CD call gword ptr [rax]Enumerator[__Canon][System.__Canon]:get_Current():System.__Canon:this gcrReg +[rdi] IN0044: 0001CF mov rdi, rax gcrReg +[rsi] IN0045: 0001D2 mov rsi, r12 IN0046: 0001D5 mov r11, (reloc 0xd1ffab1e) gcrReg -[rax] IN0047: 0001DF mov rax, (reloc 0xd1ffab1e) IN0048: 0001E9 cmp dword ptr [rdi], edi New gcrReg live regs=0000700D {rax rdx rbx r12 r13 r14} ; Call at 01EB [stk=0], GCvars=none, gcrefRegs=0000700D {rax rdx rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0049: 0001EB call gword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol:InternalSubstituteTypeParameters(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution):Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeWithModifiers:this IN004a: 0001ED mov gword ptr [rbp-68H], rax IN004b: 0001F1 mov gword ptr [rbp-60H], rdx IN004c: 0001F5 mov rax, gword ptr [rbp-68H] [D1FFAB1E] gcr var born at [rbp-D0H] IN004d: 0001F9 mov gword ptr [rbp-D0H], rax gcrReg +[rdi] IN004e: 000200 mov rdi, rax IN004f: 000203 mov r11, (reloc 0xd1ffab1e) IN0050: 00020D mov rsi, (reloc 0xd1ffab1e) IN0051: 000217 cmp dword ptr [rdi], edi New GC ref live vars=0000000000000200 {V10} New gcrReg live regs=00007008 {rbx r12 r13 r14} ; Call at 0219 [stk=0], GCvars=[rbp-D0H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0052: 000219 call qword ptr [rsi]Microsoft.CodeAnalysis.VisualBasic.Symbol:get_Kind():int:this IN0053: 00021B cmp eax, 4 IN0054: 00021E jne SHORT G_M22628_IG13 ;; bbWeight=0.29 PerfScore 6.67 G_M22628_IG11: ; func=00, offs=000220H, size=001BH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref gcrReg +[rdi] IN0055: 000220 mov rdi, gword ptr [rbp-D0H] byrReg +[rsi] IN0056: 000227 mov rsi, r15 IN0057: 00022A mov rax, (reloc 0xd1ffab1e) New gcrReg live regs=00007008 {rbx r12 r13 r14} New byrReg live regs=00008000 {r15} ; Call at 0234 [stk=0], GCvars=[rbp-D0H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0058: 000234 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:AddUseSiteDiagnostics(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref) IN0059: 000236 jmp G_M22628_IG18 ;; bbWeight=0.58 PerfScore 3.77 G_M22628_IG12: ; func=00, offs=00023BH, size=002CH, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref New GC ref live vars=0000000000000040 {V00} [D1FFAB1E] gcr var born at [rbp-C8H] [D1FFAB1E] gcr var died at [rbp-D0H] gcrReg +[rdi] IN005a: 00023B mov rdi, gword ptr [rbp-C8H] gcrReg +[rsi] IN005b: 000242 mov rsi, rbx gcrReg +[rdx] IN005c: 000245 mov rdx, r14 gcrReg +[rcx] IN005d: 000248 mov rcx, r13 byrReg +[r8] IN005e: 00024B mov r8, r15 IN005f: 00024E mov rax, (reloc 0xd1ffab1e) New GC ref live vars=0000000000000000 {} [D1FFAB1E] gcr var died at [rbp-C8H] New gcrReg live regs=00007008 {rbx r12 r13 r14} New byrReg live regs=00008000 {r15} ; Call at 0258 [stk=0], GCvars=none, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0060: 000258 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesValueTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool IN0061: 00025A test al, al IN0062: 00025C je G_M22628_IG27 IN0063: 000262 jmp G_M22628_IG07 ;; bbWeight=0.01 PerfScore 0.09 G_M22628_IG13: ; func=00, offs=000267H, size=0021H, gcVars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref, isz New GC ref live vars=0000000000000200 {V10} [D1FFAB1E] gcr var born at [rbp-D0H] gcrReg +[rdi] IN0064: 000267 mov rdi, r14 gcrReg +[rsi] IN0065: 00026A mov rsi, gword ptr [rbp-D0H] byrReg +[rdx] IN0066: 000271 mov rdx, r15 IN0067: 000274 mov rax, (reloc 0xd1ffab1e) New gcrReg live regs=00007008 {rbx r12 r13 r14} New byrReg live regs=00008000 {r15} ; Call at 027E [stk=0], GCvars=[rbp-D0H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0068: 00027E call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Conversions:HasWideningDirectCastConversionButNotEnumTypeConversion(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool IN0069: 000280 movzx rsi, al IN006a: 000284 test esi, esi IN006b: 000286 je SHORT G_M22628_IG18 ;; bbWeight=0.29 PerfScore 1.81 G_M22628_IG14: ; func=00, offs=000288H, size=0025H, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref New GC ref live vars=0000000000000000 {} [D1FFAB1E] gcr var died at [rbp-D0H] IN006c: 000288 mov rsi, (reloc 0xd1ffab1e) IN006d: 000292 mov rsi, qword ptr [rsi] byrReg +[rdi] IN006e: 000295 lea rdi, bword ptr [rbp-40H] IN006f: 000299 mov rax, (reloc 0xd1ffab1e) New byrReg live regs=00008000 {r15} ; Call at 02A3 [stk=0], GCvars=none, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0070: 0002A3 call qword ptr [rax]Enumerator[__Canon][System.__Canon]:MoveNext():bool:this IN0071: 0002A5 test al, al IN0072: 0002A7 jne G_M22628_IG10 ;; bbWeight=0.29 PerfScore 2.10 G_M22628_IG15: ; func=00, offs=0002ADH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref New gcrReg live regs=00000000 {} New byrReg live regs=00000000 {} IN0073: 0002AD jmp G_M22628_IG08 ;; bbWeight=0.15 PerfScore 0.30 G_M22628_IG16: ; func=00, offs=0002B2H, size=001DH, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref New GC ref live vars=0000000000000040 {V00} [D1FFAB1E] gcr var born at [rbp-C8H] New gcrReg live regs=00007008 {rbx r12 r13 r14} New byrReg live regs=00008000 {r15} gcrReg +[rdi] IN0074: 0002B2 mov rdi, rbx gcrReg +[rsi] IN0075: 0002B5 mov rsi, r14 gcrReg +[rdx] IN0076: 0002B8 mov rdx, r13 IN0077: 0002BB mov rax, (reloc 0xd1ffab1e) New gcrReg live regs=00007008 {rbx r12 r13 r14} ; Call at 02C5 [stk=0], GCvars=[rbp-C8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0078: 0002C5 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesReferenceTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool IN0079: 0002C7 test al, al IN007a: 0002C9 jne G_M22628_IG06 ;; bbWeight=0.03 PerfScore 0.16 G_M22628_IG17: ; func=00, offs=0002CFH, size=000CH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN007b: 0002CF xor edi, edi IN007c: 0002D1 xor eax, eax IN007d: 0002D3 mov dword ptr [rbp-2CH], eax IN007e: 0002D6 jmp G_M22628_IG06 ;; bbWeight=0.01 PerfScore 0.04 G_M22628_IG18: ; func=00, offs=0002DBH, size=00FEH, gcVars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref New GC ref live vars=0000000000000200 {V10} [D1FFAB1E] gcr var died at [rbp-C8H] [D1FFAB1E] gcr var born at [rbp-D0H] IN007f: 0002DB test r13, r13 IN0080: 0002DE je G_M22628_IG20 IN0081: 0002E4 mov edi, 2 IN0082: 0002E9 mov rax, (reloc 0xd1ffab1e) New gcrReg live regs=00007009 {rax rbx r12 r13 r14} ; Call at 02F3 [stk=0], GCvars=[rbp-D0H], gcrefRegs=00007009 {rax rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0083: 0002F3 call gword ptr [rax]CORINFO_HELP_READYTORUN_NEWARR_1 IN0084: 0002F5 mov edx, dword ptr [rax+8] IN0085: 0002F8 mov dword ptr [rbp-BCH], edx IN0086: 0002FE cmp edx, 0 IN0087: 000301 jbe G_M22628_IG28 [D1FFAB1E] gcr var born at [rbp-D8H] IN0088: 000307 mov gword ptr [rbp-D8H], rax byrReg +[rdi] IN0089: 00030E lea rdi, bword ptr [rax+16] gcrReg +[rsi] IN008a: 000312 mov rsi, r14 New GC ref live vars=0000000000002200 {V10 V14} New gcrReg live regs=00007008 {rbx r12 r13 r14} New byrReg live regs=00008000 {r15} IN008b: 000315 call CORINFO_HELP_ASSIGN_REF IN008c: 00031A cmp dword ptr [rbp-BCH], 1 IN008d: 000321 jbe G_M22628_IG28 gcrReg +[rax] IN008e: 000327 mov rax, gword ptr [rbp-D8H] byrReg +[rdi] IN008f: 00032E lea rdi, bword ptr [rax+24] gcrReg +[rsi] IN0090: 000332 mov rsi, gword ptr [rbp-D0H] New GC ref live vars=0000000000002000 {V14} [D1FFAB1E] gcr var died at [rbp-D0H] New gcrReg live regs=00007008 {rbx r12 r13 r14} New byrReg live regs=00008000 {r15} IN0091: 000339 call CORINFO_HELP_ASSIGN_REF IN0092: 00033E mov rax, (reloc 0xd1ffab1e) New gcrReg live regs=00007009 {rax rbx r12 r13 r14} ; Call at 0348 [stk=0], GCvars=[rbp-D8H], gcrefRegs=00007009 {rax rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN0093: 000348 call gword ptr [rax]CORINFO_HELP_READYTORUN_NEW [D1FFAB1E] gcr var born at [rbp-F0H] IN0094: 00034A mov gword ptr [rbp-F0H], rax IN0095: 000351 mov rdi, (reloc 0xd1ffab1e) New GC ref live vars=000000000000A000 {V14 V20} New gcrReg live regs=00007008 {rbx r12 r13 r14} New byrReg live regs=00008001 {rax r15} ; Call at 035B [stk=0], GCvars=[rbp-F0H] [rbp-D8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008001 {rax r15} IN0096: 00035B call bword ptr [rdi]CORINFO_HELP_READYTORUN_STATIC_BASE gcrReg +[rsi] IN0097: 00035D mov rsi, gword ptr [rax+0418H] gcrReg +[rdi] IN0098: 000364 mov rdi, gword ptr [rbp-F0H] gcrReg +[rcx] IN0099: 00036B mov rcx, gword ptr [rbp-D8H] IN009a: 000372 mov edx, 0x7D2C byrReg -[rax] IN009b: 000377 mov rax, (reloc 0xd1ffab1e) New GC ref live vars=0000000000008000 {V20} [D1FFAB1E] gcr var died at [rbp-D8H] New gcrReg live regs=00007008 {rbx r12 r13 r14} ; Call at 0381 [stk=0], GCvars=[rbp-F0H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN009c: 000381 call qword ptr [rax]Microsoft.CodeAnalysis.DiagnosticInfo:.ctor(Microsoft.CodeAnalysis.CommonMessageProvider,int,System.Object[]):this IN009d: 000383 xor edi, edi IN009e: 000385 xorps xmm0, xmm0 IN009f: 000388 movups xmmword ptr [rbp-90H], xmm0 IN00a0: 00038F movups xmmword ptr [rbp-80H], xmm0 IN00a1: 000393 mov qword ptr [rbp-70H], rdi IN00a2: 000397 mov gword ptr [rbp-90H], rbx gcrReg +[rdi] IN00a3: 00039E mov rdi, gword ptr [rbp-F0H] IN00a4: 0003A5 mov gword ptr [rbp-88H], rdi gcrReg -[rdi] IN00a5: 0003AC lea rdi, [rsp] IN00a6: 0003B0 lea rsi, [rbp-90H] gcrReg +[rcx] IN00a7: 0003B7 mov rcx, gword ptr [rsi] IN00a8: 0003BA mov gword ptr [rsp], rcx IN00a9: 0003BE add rsi, 8 IN00aa: 0003C2 add rdi, 8 IN00ab: 0003C6 mov rcx, gword ptr [rsi] IN00ac: 0003C9 mov gword ptr [rsp+08H], rcx IN00ad: 0003CE add rsi, 8 IN00ae: 0003D2 add rdi, 8 IN00af: 0003D6 mov rcx, gword ptr [rsi] ;; bbWeight=0.02 PerfScore 1.02 G_M22628_IG19: ; func=00, offs=0003D9H, size=0038H, extend IN00b0: 0003D9 mov gword ptr [rsp+10H], rcx IN00b1: 0003DE add rsi, 8 IN00b2: 0003E2 add rdi, 8 IN00b3: 0003E6 mov rcx, gword ptr [rsi] IN00b4: 0003E9 mov gword ptr [rsp+18H], rcx IN00b5: 0003EE add rsi, 8 IN00b6: 0003F2 add rdi, 8 IN00b7: 0003F6 movsq gcrReg +[rdi] IN00b8: 0003F8 mov rdi, r13 IN00b9: 0003FB mov r11, (reloc 0xd1ffab1e) IN00ba: 000405 mov rax, (reloc 0xd1ffab1e) New GC ref live vars=0000000000000000 {} [D1FFAB1E] gcr var died at [rbp-F0H] New gcrReg live regs=00007008 {rbx r12 r13 r14} ; Call at 040F [stk=0], GCvars=none, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00bb: 00040F call qword ptr [rax]Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo]:Add(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo):this ;; bbWeight=0.02 PerfScore 0.20 G_M22628_IG20: ; func=00, offs=000411H, size=000AH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN00bc: 000411 xor eax, eax IN00bd: 000413 mov dword ptr [rbp-2CH], eax IN00be: 000416 jmp G_M22628_IG14 ;; bbWeight=0.02 PerfScore 0.07 G_M22628_IG21: ; func=00, offs=00041BH, size=001DH, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref New GC ref live vars=0000000000000040 {V00} [D1FFAB1E] gcr var born at [rbp-C8H] gcrReg +[rdi] IN00bf: 00041B mov rdi, rbx gcrReg +[rsi] IN00c0: 00041E mov rsi, r14 gcrReg +[rdx] IN00c1: 000421 mov rdx, r13 IN00c2: 000424 mov rcx, (reloc 0xd1ffab1e) New gcrReg live regs=00007008 {rbx r12 r13 r14} ; Call at 042E [stk=0], GCvars=[rbp-C8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00c3: 00042E call qword ptr [rcx]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesConstructorConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool IN00c4: 000430 test al, al IN00c5: 000432 jne G_M22628_IG05 ;; bbWeight=0.01 PerfScore 0.05 G_M22628_IG22: ; func=00, offs=000438H, size=000AH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN00c6: 000438 xor eax, eax IN00c7: 00043A mov dword ptr [rbp-2CH], eax IN00c8: 00043D jmp G_M22628_IG05 ;; bbWeight=0 PerfScore 0.00 G_M22628_IG23: ; func=00, offs=000442H, size=000AH, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref New GC ref live vars=0000000000000000 {} [D1FFAB1E] gcr var died at [rbp-C8H] New gcrReg live regs=00000000 {} New byrReg live regs=00000000 {} IN00c9: 000442 mov eax, 1 IN00ca: 000447 jmp G_M22628_IG09 ;; bbWeight=0 PerfScore 0.00 G_M22628_IG24: ; func=00, offs=00044CH, size=00FCH, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref New GC ref live vars=0000000000000040 {V00} [D1FFAB1E] gcr var born at [rbp-C8H] New gcrReg live regs=00007008 {rbx r12 r13 r14} New byrReg live regs=00008000 {r15} IN00cb: 00044C test r13, r13 IN00cc: 00044F je G_M22628_IG26 IN00cd: 000455 mov edi, 1 IN00ce: 00045A mov rax, (reloc 0xd1ffab1e) New gcrReg live regs=00007009 {rax rbx r12 r13 r14} ; Call at 0464 [stk=0], GCvars=[rbp-C8H], gcrefRegs=00007009 {rax rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00cf: 000464 call gword ptr [rax]CORINFO_HELP_READYTORUN_NEWARR_1 IN00d0: 000466 cmp dword ptr [rax+8], 0 IN00d1: 00046A jbe G_M22628_IG28 [D1FFAB1E] gcr var born at [rbp-E0H] IN00d2: 000470 mov gword ptr [rbp-E0H], rax byrReg +[rdi] IN00d3: 000477 lea rdi, bword ptr [rax+16] gcrReg +[rsi] IN00d4: 00047B mov rsi, r14 New GC ref live vars=0000000000040040 {V00 V16} New gcrReg live regs=00007008 {rbx r12 r13 r14} New byrReg live regs=00008000 {r15} IN00d5: 00047E call CORINFO_HELP_ASSIGN_REF IN00d6: 000483 mov rax, (reloc 0xd1ffab1e) New gcrReg live regs=00007009 {rax rbx r12 r13 r14} ; Call at 048D [stk=0], GCvars=[rbp-E0H] [rbp-C8H], gcrefRegs=00007009 {rax rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00d7: 00048D call gword ptr [rax]CORINFO_HELP_READYTORUN_NEW [D1FFAB1E] gcr var born at [rbp-E8H] IN00d8: 00048F mov gword ptr [rbp-E8H], rax IN00d9: 000496 mov rdi, (reloc 0xd1ffab1e) New GC ref live vars=00000000000C0040 {V00 V16 V18} New gcrReg live regs=00007008 {rbx r12 r13 r14} New byrReg live regs=00008001 {rax r15} ; Call at 04A0 [stk=0], GCvars=[rbp-E8H] [rbp-E0H] [rbp-C8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008001 {rax r15} IN00da: 0004A0 call bword ptr [rdi]CORINFO_HELP_READYTORUN_STATIC_BASE gcrReg +[rsi] IN00db: 0004A2 mov rsi, gword ptr [rax+0418H] gcrReg +[rdi] IN00dc: 0004A9 mov rdi, gword ptr [rbp-E8H] gcrReg +[rcx] IN00dd: 0004B0 mov rcx, gword ptr [rbp-E0H] IN00de: 0004B7 mov edx, 0x7AA4 byrReg -[rax] IN00df: 0004BC mov rax, (reloc 0xd1ffab1e) New GC ref live vars=0000000000080040 {V00 V18} [D1FFAB1E] gcr var died at [rbp-E0H] New gcrReg live regs=00007008 {rbx r12 r13 r14} ; Call at 04C6 [stk=0], GCvars=[rbp-E8H] [rbp-C8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00e0: 0004C6 call qword ptr [rax]Microsoft.CodeAnalysis.DiagnosticInfo:.ctor(Microsoft.CodeAnalysis.CommonMessageProvider,int,System.Object[]):this byrReg +[rdi] IN00e1: 0004C8 lea rdi, bword ptr [rbp-B8H] gcrReg +[rsi] IN00e2: 0004CF mov rsi, rbx gcrReg +[rdx] IN00e3: 0004D2 mov rdx, gword ptr [rbp-E8H] IN00e4: 0004D9 mov rax, (reloc 0xd1ffab1e) New GC ref live vars=0000000000000040 {V00} [D1FFAB1E] gcr var died at [rbp-E8H] New gcrReg live regs=00007008 {rbx r12 r13 r14} New byrReg live regs=00008000 {r15} ; Call at 04E3 [stk=0], GCvars=[rbp-C8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00e5: 0004E3 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this IN00e6: 0004E5 lea rdi, [rsp] IN00e7: 0004E9 lea rsi, [rbp-B8H] gcrReg +[rcx] IN00e8: 0004F0 mov rcx, gword ptr [rsi] IN00e9: 0004F3 mov gword ptr [rsp], rcx IN00ea: 0004F7 add rsi, 8 IN00eb: 0004FB add rdi, 8 IN00ec: 0004FF mov rcx, gword ptr [rsi] IN00ed: 000502 mov gword ptr [rsp+08H], rcx IN00ee: 000507 add rsi, 8 IN00ef: 00050B add rdi, 8 IN00f0: 00050F mov rcx, gword ptr [rsi] IN00f1: 000512 mov gword ptr [rsp+10H], rcx IN00f2: 000517 add rsi, 8 IN00f3: 00051B add rdi, 8 IN00f4: 00051F mov rcx, gword ptr [rsi] IN00f5: 000522 mov gword ptr [rsp+18H], rcx IN00f6: 000527 add rsi, 8 IN00f7: 00052B add rdi, 8 IN00f8: 00052F movsq gcrReg +[rdi] IN00f9: 000531 mov rdi, r13 IN00fa: 000534 mov r11, (reloc 0xd1ffab1e) IN00fb: 00053E mov rax, (reloc 0xd1ffab1e) ;; bbWeight=0 PerfScore 0.00 G_M22628_IG25: ; func=00, offs=000548H, size=0002H, extend New gcrReg live regs=00007008 {rbx r12 r13 r14} ; Call at 0548 [stk=0], GCvars=[rbp-C8H], gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15} IN00fc: 000548 call qword ptr [rax]Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo]:Add(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo):this ;; bbWeight=0 PerfScore 0.00 G_M22628_IG26: ; func=00, offs=00054AH, size=000AH, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN00fd: 00054A xor eax, eax IN00fe: 00054C mov dword ptr [rbp-2CH], eax IN00ff: 00054F jmp G_M22628_IG04 ;; bbWeight=0 PerfScore 0.00 G_M22628_IG27: ; func=00, offs=000554H, size=000AH, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref New GC ref live vars=0000000000000000 {} [D1FFAB1E] gcr var died at [rbp-C8H] IN0100: 000554 xor eax, eax IN0101: 000556 mov dword ptr [rbp-2CH], eax IN0102: 000559 jmp G_M22628_IG07 ;; bbWeight=0 PerfScore 0.00 G_M22628_IG28: ; func=00, offs=00055EH, size=0006H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref New gcrReg live regs=00000000 {} New byrReg live regs=00000000 {} ; Call at 055E [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0103: 00055E call CORINFO_HELP_RNGCHKFAIL IN0104: 000563 int3 ;; bbWeight=0 PerfScore 0.00Allocated method code size = 1380 , actual size = 1380 ; Total bytes of code 1380, prolog size 88, PerfScore 247.10, (MethodHash=a679a79b) for method Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool ; ============================================================ *************** After end code gen, before unwindEmit() G_M22628_IG01: ; func=00, offs=000000H, size=006EH, bbWeight=1 PerfScore 27.08, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN0105: 000000 push rbp IN0106: 000001 push r15 IN0107: 000003 push r14 IN0108: 000005 push r13 IN0109: 000007 push r12 IN010a: 000009 push rbx IN010b: 00000A sub rsp, 248 IN010c: 000011 lea rbp, [rsp+120H] IN010d: 000019 xor rax, rax IN010e: 00001B mov qword ptr [rbp-B8H], rax IN010f: 000022 xorps xmm8, xmm8 IN0110: 000026 movaps xmmword ptr [rbp-B0H], xmm8 IN0111: 00002E movaps xmmword ptr [rbp-A0H], xmm8 IN0112: 000036 mov rax, -96 IN0113: 000040 movaps xmmword ptr [rbp+rax-30H], xmm8 IN0114: 000046 movaps xmmword ptr [rbp+rax-20H], xmm8 IN0115: 00004C movaps xmmword ptr [rbp+rax-10H], xmm8 IN0116: 000052 add rax, 48 IN0117: 000056 jne SHORT -5 instr IN0118: 000058 mov gword ptr [V00 rbp-C8H], rdi IN0119: 00005F mov r12, rsi IN011a: 000062 mov rbx, rdx IN011b: 000065 mov r14, rcx IN011c: 000068 mov r13, r8 IN011d: 00006B mov r15, r9 G_M22628_IG02: ; offs=00006EH, size=0024H, bbWeight=1 PerfScore 7.00, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref IN0001: 00006E mov rdi, r14 IN0002: 000071 mov r11, (reloc 0xd1ffab1e) IN0003: 00007B mov rsi, (reloc 0xd1ffab1e) IN0004: 000085 cmp dword ptr [rdi], edi IN0005: 000087 call qword ptr [rsi]Microsoft.CodeAnalysis.VisualBasic.Symbol:get_Kind():int:this IN0006: 000089 cmp eax, 4 IN0007: 00008C je G_M22628_IG23 G_M22628_IG03: ; offs=000092H, size=0038H, bbWeight=1 PerfScore 9.50, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN0008: 000092 mov dword ptr [V07 rbp-2CH], 1 IN0009: 000099 mov rdi, r14 IN000a: 00009C mov r11, (reloc 0xd1ffab1e) IN000b: 0000A6 mov rsi, (reloc 0xd1ffab1e) IN000c: 0000B0 call qword ptr [rsi]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol:get_SpecialType():byte:this IN000d: 0000B2 movsx rdi, al IN000e: 0000B6 mov rax, (reloc 0xd1ffab1e) IN000f: 0000C0 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.SpecialTypeExtensions:IsRestrictedType(byte):bool IN0010: 0000C2 test al, al IN0011: 0000C4 jne G_M22628_IG24 G_M22628_IG04: ; offs=0000CAH, size=0023H, bbWeight=1 PerfScore 7.00, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN0012: 0000CA mov rdi, rbx IN0013: 0000CD mov r11, (reloc 0xd1ffab1e) IN0014: 0000D7 mov rax, (reloc 0xd1ffab1e) IN0015: 0000E1 cmp dword ptr [rdi], edi IN0016: 0000E3 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasConstructorConstraint():bool:this IN0017: 0000E5 test al, al IN0018: 0000E7 jne G_M22628_IG21 G_M22628_IG05: ; offs=0000EDH, size=0021H, bbWeight=1 PerfScore 5.00, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN0019: 0000ED mov rdi, rbx IN001a: 0000F0 mov r11, (reloc 0xd1ffab1e) IN001b: 0000FA mov rax, (reloc 0xd1ffab1e) IN001c: 000104 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasReferenceTypeConstraint():bool:this IN001d: 000106 test al, al IN001e: 000108 jne G_M22628_IG16 G_M22628_IG06: ; offs=00010EH, size=0021H, bbWeight=1 PerfScore 5.00, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN001f: 00010E mov rdi, rbx IN0020: 000111 mov r11, (reloc 0xd1ffab1e) IN0021: 00011B mov rax, (reloc 0xd1ffab1e) IN0022: 000125 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:get_HasValueTypeConstraint():bool:this IN0023: 000127 test al, al IN0024: 000129 jne G_M22628_IG12 G_M22628_IG07: ; offs=00012FH, size=006DH, bbWeight=1 PerfScore 26.50, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref, isz IN0025: 00012F mov rdi, rbx IN0026: 000132 mov rsi, r15 IN0027: 000135 mov rax, (reloc 0xd1ffab1e) IN0028: 00013F call gword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol:ConstraintTypesWithDefinitionUseSiteDiagnostics(byref):System.Collections.Immutable.ImmutableArray`1[[Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol, Microsoft.CodeAnalysis.VisualBasic, Version=1.1.0.0, Culture=neutral, PublicKeyToken=31bf3856ad364e35]]:this IN0029: 000141 mov gword ptr [V23 rbp-48H], rax IN002a: 000145 mov rsi, (reloc 0xd1ffab1e) IN002b: 00014F mov rsi, qword ptr [rsi] IN002c: 000152 lea rdi, bword ptr [V09 rbp-48H] IN002d: 000156 mov rax, (reloc 0xd1ffab1e) IN002e: 000160 call gword ptr [rax]System.Collections.Immutable.ImmutableArray`1[__Canon][System.__Canon]:GetEnumerator():Enumerator[__Canon]:this IN002f: 000162 mov gword ptr [V12 rbp-58H], rax IN0030: 000166 mov qword ptr [V12+0x8 rbp-50H], rdx IN0031: 00016A lea rsi, bword ptr [V12 rbp-58H] IN0032: 00016E mov rdi, gword ptr [rsi] IN0033: 000171 mov gword ptr [V21 rbp-40H], rdi IN0034: 000175 mov esi, dword ptr [rsi+8] IN0035: 000178 mov dword ptr [V22 rbp-38H], esi IN0036: 00017B mov rsi, (reloc 0xd1ffab1e) IN0037: 000185 mov rsi, qword ptr [rsi] IN0038: 000188 lea rdi, bword ptr [V08 rbp-40H] IN0039: 00018C mov rax, (reloc 0xd1ffab1e) IN003a: 000196 call qword ptr [rax]Enumerator[__Canon][System.__Canon]:MoveNext():bool:this IN003b: 000198 test al, al IN003c: 00019A jne SHORT G_M22628_IG10 G_M22628_IG08: ; offs=00019CH, size=0007H, bbWeight=1 PerfScore 1.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN003d: 00019C mov r13d, dword ptr [V07 rbp-2CH] IN003e: 0001A0 mov eax, r13d G_M22628_IG09: ; offs=0001A3H, size=000FH, bbWeight=1 PerfScore 4.50, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc IN011e: 0001A3 lea rsp, [rbp-28H] IN011f: 0001A7 pop rbx IN0120: 0001A8 pop r12 IN0121: 0001AA pop r13 IN0122: 0001AC pop r14 IN0123: 0001AE pop r15 IN0124: 0001B0 pop rbp IN0125: 0001B1 ret G_M22628_IG10: ; offs=0001B2H, size=006EH, bbWeight=0.29 PerfScore 6.67, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref, isz IN003f: 0001B2 mov rsi, (reloc 0xd1ffab1e) IN0040: 0001BC mov rsi, qword ptr [rsi] IN0041: 0001BF lea rdi, bword ptr [V08 rbp-40H] IN0042: 0001C3 mov rax, (reloc 0xd1ffab1e) IN0043: 0001CD call gword ptr [rax]Enumerator[__Canon][System.__Canon]:get_Current():System.__Canon:this IN0044: 0001CF mov rdi, rax IN0045: 0001D2 mov rsi, r12 IN0046: 0001D5 mov r11, (reloc 0xd1ffab1e) IN0047: 0001DF mov rax, (reloc 0xd1ffab1e) IN0048: 0001E9 cmp dword ptr [rdi], edi IN0049: 0001EB call gword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol:InternalSubstituteTypeParameters(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution):Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeWithModifiers:this IN004a: 0001ED mov gword ptr [V13 rbp-68H], rax IN004b: 0001F1 mov gword ptr [V13+0x8 rbp-60H], rdx IN004c: 0001F5 mov rax, gword ptr [V13 rbp-68H] IN004d: 0001F9 mov gword ptr [V10 rbp-D0H], rax IN004e: 000200 mov rdi, rax IN004f: 000203 mov r11, (reloc 0xd1ffab1e) IN0050: 00020D mov rsi, (reloc 0xd1ffab1e) IN0051: 000217 cmp dword ptr [rdi], edi IN0052: 000219 call qword ptr [rsi]Microsoft.CodeAnalysis.VisualBasic.Symbol:get_Kind():int:this IN0053: 00021B cmp eax, 4 IN0054: 00021E jne SHORT G_M22628_IG13 G_M22628_IG11: ; offs=000220H, size=001BH, bbWeight=0.58 PerfScore 3.77, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN0055: 000220 mov rdi, gword ptr [V10 rbp-D0H] IN0056: 000227 mov rsi, r15 IN0057: 00022A mov rax, (reloc 0xd1ffab1e) IN0058: 000234 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbolExtensions:AddUseSiteDiagnostics(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref) IN0059: 000236 jmp G_M22628_IG18 G_M22628_IG12: ; offs=00023BH, size=002CH, bbWeight=0.01 PerfScore 0.09, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref IN005a: 00023B mov rdi, gword ptr [V00 rbp-C8H] IN005b: 000242 mov rsi, rbx IN005c: 000245 mov rdx, r14 IN005d: 000248 mov rcx, r13 IN005e: 00024B mov r8, r15 IN005f: 00024E mov rax, (reloc 0xd1ffab1e) IN0060: 000258 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesValueTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool IN0061: 00025A test al, al IN0062: 00025C je G_M22628_IG27 IN0063: 000262 jmp G_M22628_IG07 G_M22628_IG13: ; offs=000267H, size=0021H, bbWeight=0.29 PerfScore 1.81, gcVars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref, isz IN0064: 000267 mov rdi, r14 IN0065: 00026A mov rsi, gword ptr [V10 rbp-D0H] IN0066: 000271 mov rdx, r15 IN0067: 000274 mov rax, (reloc 0xd1ffab1e) IN0068: 00027E call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Conversions:HasWideningDirectCastConversionButNotEnumTypeConversion(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,byref):bool IN0069: 000280 movzx rsi, al IN006a: 000284 test esi, esi IN006b: 000286 je SHORT G_M22628_IG18 G_M22628_IG14: ; offs=000288H, size=0025H, bbWeight=0.29 PerfScore 2.10, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref IN006c: 000288 mov rsi, (reloc 0xd1ffab1e) IN006d: 000292 mov rsi, qword ptr [rsi] IN006e: 000295 lea rdi, bword ptr [V08 rbp-40H] IN006f: 000299 mov rax, (reloc 0xd1ffab1e) IN0070: 0002A3 call qword ptr [rax]Enumerator[__Canon][System.__Canon]:MoveNext():bool:this IN0071: 0002A5 test al, al IN0072: 0002A7 jne G_M22628_IG10 G_M22628_IG15: ; offs=0002ADH, size=0005H, bbWeight=0.15 PerfScore 0.30, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN0073: 0002AD jmp G_M22628_IG08 G_M22628_IG16: ; offs=0002B2H, size=001DH, bbWeight=0.03 PerfScore 0.16, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref IN0074: 0002B2 mov rdi, rbx IN0075: 0002B5 mov rsi, r14 IN0076: 0002B8 mov rdx, r13 IN0077: 0002BB mov rax, (reloc 0xd1ffab1e) IN0078: 0002C5 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesReferenceTypeConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool IN0079: 0002C7 test al, al IN007a: 0002C9 jne G_M22628_IG06 G_M22628_IG17: ; offs=0002CFH, size=000CH, bbWeight=0.01 PerfScore 0.04, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN007b: 0002CF xor edi, edi IN007c: 0002D1 xor eax, eax IN007d: 0002D3 mov dword ptr [V07 rbp-2CH], eax IN007e: 0002D6 jmp G_M22628_IG06 G_M22628_IG18: ; offs=0002DBH, size=00FEH, bbWeight=0.02 PerfScore 1.02, gcVars=0000000000000200 {V10}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref IN007f: 0002DB test r13, r13 IN0080: 0002DE je G_M22628_IG20 IN0081: 0002E4 mov edi, 2 IN0082: 0002E9 mov rax, (reloc 0xd1ffab1e) IN0083: 0002F3 call gword ptr [rax]CORINFO_HELP_READYTORUN_NEWARR_1 IN0084: 0002F5 mov edx, dword ptr [rax+8] IN0085: 0002F8 mov dword ptr [V28 rbp-BCH], edx IN0086: 0002FE cmp edx, 0 IN0087: 000301 jbe G_M22628_IG28 IN0088: 000307 mov gword ptr [V14 rbp-D8H], rax IN0089: 00030E lea rdi, bword ptr [rax+16] IN008a: 000312 mov rsi, r14 IN008b: 000315 call CORINFO_HELP_ASSIGN_REF IN008c: 00031A cmp dword ptr [V28 rbp-BCH], 1 IN008d: 000321 jbe G_M22628_IG28 IN008e: 000327 mov rax, gword ptr [V14 rbp-D8H] IN008f: 00032E lea rdi, bword ptr [rax+24] IN0090: 000332 mov rsi, gword ptr [V10 rbp-D0H] IN0091: 000339 call CORINFO_HELP_ASSIGN_REF IN0092: 00033E mov rax, (reloc 0xd1ffab1e) IN0093: 000348 call gword ptr [rax]CORINFO_HELP_READYTORUN_NEW IN0094: 00034A mov gword ptr [V20 rbp-F0H], rax IN0095: 000351 mov rdi, (reloc 0xd1ffab1e) IN0096: 00035B call bword ptr [rdi]CORINFO_HELP_READYTORUN_STATIC_BASE IN0097: 00035D mov rsi, gword ptr [rax+0418H] IN0098: 000364 mov rdi, gword ptr [V20 rbp-F0H] IN0099: 00036B mov rcx, gword ptr [V14 rbp-D8H] IN009a: 000372 mov edx, 0x7D2C IN009b: 000377 mov rax, (reloc 0xd1ffab1e) IN009c: 000381 call qword ptr [rax]Microsoft.CodeAnalysis.DiagnosticInfo:.ctor(Microsoft.CodeAnalysis.CommonMessageProvider,int,System.Object[]):this IN009d: 000383 xor edi, edi IN009e: 000385 xorps xmm0, xmm0 IN009f: 000388 movups xmmword ptr [V15 rbp-90H], xmm0 IN00a0: 00038F movups xmmword ptr [V15+0x10 rbp-80H], xmm0 IN00a1: 000393 mov qword ptr [V15+0x20 rbp-70H], rdi IN00a2: 000397 mov gword ptr [V15 rbp-90H], rbx IN00a3: 00039E mov rdi, gword ptr [V20 rbp-F0H] IN00a4: 0003A5 mov gword ptr [V15+0x8 rbp-88H], rdi IN00a5: 0003AC lea rdi, [V11 rsp] IN00a6: 0003B0 lea rsi, [V15 rbp-90H] IN00a7: 0003B7 mov rcx, gword ptr [rsi] IN00a8: 0003BA mov gword ptr [V11 rsp], rcx IN00a9: 0003BE add rsi, 8 IN00aa: 0003C2 add rdi, 8 IN00ab: 0003C6 mov rcx, gword ptr [rsi] IN00ac: 0003C9 mov gword ptr [V11+0x8 rsp+08H], rcx IN00ad: 0003CE add rsi, 8 IN00ae: 0003D2 add rdi, 8 IN00af: 0003D6 mov rcx, gword ptr [rsi] G_M22628_IG19: ; offs=0003D9H, size=0038H, bbWeight=0.02 PerfScore 0.20, extend IN00b0: 0003D9 mov gword ptr [V11+0x10 rsp+10H], rcx IN00b1: 0003DE add rsi, 8 IN00b2: 0003E2 add rdi, 8 IN00b3: 0003E6 mov rcx, gword ptr [rsi] IN00b4: 0003E9 mov gword ptr [V11+0x18 rsp+18H], rcx IN00b5: 0003EE add rsi, 8 IN00b6: 0003F2 add rdi, 8 IN00b7: 0003F6 movsq IN00b8: 0003F8 mov rdi, r13 IN00b9: 0003FB mov r11, (reloc 0xd1ffab1e) IN00ba: 000405 mov rax, (reloc 0xd1ffab1e) IN00bb: 00040F call qword ptr [rax]Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo]:Add(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo):this G_M22628_IG20: ; offs=000411H, size=000AH, bbWeight=0.02 PerfScore 0.07, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN00bc: 000411 xor eax, eax IN00bd: 000413 mov dword ptr [V07 rbp-2CH], eax IN00be: 000416 jmp G_M22628_IG14 G_M22628_IG21: ; offs=00041BH, size=001DH, bbWeight=0.01 PerfScore 0.05, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref IN00bf: 00041B mov rdi, rbx IN00c0: 00041E mov rsi, r14 IN00c1: 000421 mov rdx, r13 IN00c2: 000424 mov rcx, (reloc 0xd1ffab1e) IN00c3: 00042E call qword ptr [rcx]Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:SatisfiesConstructorConstraint(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo]):bool IN00c4: 000430 test al, al IN00c5: 000432 jne G_M22628_IG05 G_M22628_IG22: ; offs=000438H, size=000AH, bbWeight=0 PerfScore 0.00, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN00c6: 000438 xor eax, eax IN00c7: 00043A mov dword ptr [V07 rbp-2CH], eax IN00c8: 00043D jmp G_M22628_IG05 G_M22628_IG23: ; offs=000442H, size=000AH, bbWeight=0 PerfScore 0.00, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref IN00c9: 000442 mov eax, 1 IN00ca: 000447 jmp G_M22628_IG09 G_M22628_IG24: ; offs=00044CH, size=00FCH, bbWeight=0 PerfScore 0.00, gcVars=0000000000000040 {V00}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref IN00cb: 00044C test r13, r13 IN00cc: 00044F je G_M22628_IG26 IN00cd: 000455 mov edi, 1 IN00ce: 00045A mov rax, (reloc 0xd1ffab1e) IN00cf: 000464 call gword ptr [rax]CORINFO_HELP_READYTORUN_NEWARR_1 IN00d0: 000466 cmp dword ptr [rax+8], 0 IN00d1: 00046A jbe G_M22628_IG28 IN00d2: 000470 mov gword ptr [V16 rbp-E0H], rax IN00d3: 000477 lea rdi, bword ptr [rax+16] IN00d4: 00047B mov rsi, r14 IN00d5: 00047E call CORINFO_HELP_ASSIGN_REF IN00d6: 000483 mov rax, (reloc 0xd1ffab1e) IN00d7: 00048D call gword ptr [rax]CORINFO_HELP_READYTORUN_NEW IN00d8: 00048F mov gword ptr [V18 rbp-E8H], rax IN00d9: 000496 mov rdi, (reloc 0xd1ffab1e) IN00da: 0004A0 call bword ptr [rdi]CORINFO_HELP_READYTORUN_STATIC_BASE IN00db: 0004A2 mov rsi, gword ptr [rax+0418H] IN00dc: 0004A9 mov rdi, gword ptr [V18 rbp-E8H] IN00dd: 0004B0 mov rcx, gword ptr [V16 rbp-E0H] IN00de: 0004B7 mov edx, 0x7AA4 IN00df: 0004BC mov rax, (reloc 0xd1ffab1e) IN00e0: 0004C6 call qword ptr [rax]Microsoft.CodeAnalysis.DiagnosticInfo:.ctor(Microsoft.CodeAnalysis.CommonMessageProvider,int,System.Object[]):this IN00e1: 0004C8 lea rdi, bword ptr [V17 rbp-B8H] IN00e2: 0004CF mov rsi, rbx IN00e3: 0004D2 mov rdx, gword ptr [V18 rbp-E8H] IN00e4: 0004D9 mov rax, (reloc 0xd1ffab1e) IN00e5: 0004E3 call qword ptr [rax]Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo:.ctor(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.DiagnosticInfo):this IN00e6: 0004E5 lea rdi, [V11 rsp] IN00e7: 0004E9 lea rsi, [V17 rbp-B8H] IN00e8: 0004F0 mov rcx, gword ptr [rsi] IN00e9: 0004F3 mov gword ptr [V11 rsp], rcx IN00ea: 0004F7 add rsi, 8 IN00eb: 0004FB add rdi, 8 IN00ec: 0004FF mov rcx, gword ptr [rsi] IN00ed: 000502 mov gword ptr [V11+0x8 rsp+08H], rcx IN00ee: 000507 add rsi, 8 IN00ef: 00050B add rdi, 8 IN00f0: 00050F mov rcx, gword ptr [rsi] IN00f1: 000512 mov gword ptr [V11+0x10 rsp+10H], rcx IN00f2: 000517 add rsi, 8 IN00f3: 00051B add rdi, 8 IN00f4: 00051F mov rcx, gword ptr [rsi] IN00f5: 000522 mov gword ptr [V11+0x18 rsp+18H], rcx IN00f6: 000527 add rsi, 8 IN00f7: 00052B add rdi, 8 IN00f8: 00052F movsq IN00f9: 000531 mov rdi, r13 IN00fa: 000534 mov r11, (reloc 0xd1ffab1e) IN00fb: 00053E mov rax, (reloc 0xd1ffab1e) G_M22628_IG25: ; offs=000548H, size=0002H, bbWeight=0 PerfScore 0.00, extend IN00fc: 000548 call qword ptr [rax]Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo][Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo]:Add(Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterDiagnosticInfo):this G_M22628_IG26: ; offs=00054AH, size=000AH, bbWeight=0 PerfScore 0.00, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, byref IN00fd: 00054A xor eax, eax IN00fe: 00054C mov dword ptr [V07 rbp-2CH], eax IN00ff: 00054F jmp G_M22628_IG04 G_M22628_IG27: ; offs=000554H, size=000AH, bbWeight=0 PerfScore 0.00, gcVars=0000000000000000 {}, gcrefRegs=00007008 {rbx r12 r13 r14}, byrefRegs=00008000 {r15}, gcvars, byref IN0100: 000554 xor eax, eax IN0101: 000556 mov dword ptr [V07 rbp-2CH], eax IN0102: 000559 jmp G_M22628_IG07 G_M22628_IG28: ; offs=00055EH, size=0006H, bbWeight=0 PerfScore 0.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN0103: 00055E call CORINFO_HELP_RNGCHKFAIL IN0104: 000563 int3 *************** Finishing PHASE Emit code *************** Starting PHASE Emit GC+EH tables Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0xd1ffab1e (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x11 CountOfUnwindCodes: 8 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x11 UnwindOp: UWOP_ALLOC_LARGE (1) OpInfo: 0 - Scaled small Size: 31 * 8 = 248 = 0x000F8 CodeOffset: 0x0A UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3) CodeOffset: 0x09 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r12 (12) CodeOffset: 0x07 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r13 (13) CodeOffset: 0x05 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14) CodeOffset: 0x03 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r15 (15) CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) allocUnwindInfo(pHotCode=0x00000000D1FFAB1E, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x564, unwindSize=0x14, pUnwindBlock=0x00000000D1FFAB1E, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 31 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x000F : 0x00000092 ( STACK_EMPTY ) IL offs 0x0040 : 0x000000CA ( STACK_EMPTY ) IL offs 0x0055 : 0x000000ED ( STACK_EMPTY ) IL offs 0x006A : 0x0000010E ( STACK_EMPTY ) IL offs 0x008B : 0x00000145 ( STACK_EMPTY ) IL offs 0x00E1 : 0x0000017B ( STACK_EMPTY ) IL offs 0x00EA : 0x0000019C ( STACK_EMPTY ) IL offs 0x00EC : 0x000001A3 ( STACK_EMPTY ) IL offs EPILOG : 0x000001A3 ( STACK_EMPTY ) IL offs 0x0095 : 0x000001B2 ( STACK_EMPTY ) IL offs 0x00A9 : 0x000001F9 ( STACK_EMPTY ) IL offs 0x0072 : 0x0000023B ( STACK_EMPTY ) IL offs NO_MAP : 0x00000262 ( STACK_EMPTY ) IL offs 0x00A9 : 0x00000267 ( STACK_EMPTY ) IL offs 0x00E1 : 0x00000288 ( STACK_EMPTY ) IL offs NO_MAP : 0x000002AD ( STACK_EMPTY ) IL offs 0x0068 : 0x000002CF ( STACK_EMPTY ) IL offs 0x00B5 : 0x000002DB ( STACK_EMPTY ) IL offs 0x00B9 : 0x000002E4 ( STACK_EMPTY ) IL offs 0x00DA : 0x000003AC IL offs 0x00DF : 0x00000411 ( STACK_EMPTY ) IL offs 0x0048 : 0x0000041B ( STACK_EMPTY ) IL offs 0x0053 : 0x00000438 ( STACK_EMPTY ) IL offs 0x0008 : 0x00000442 ( STACK_EMPTY ) IL offs 0x0019 : 0x0000044C ( STACK_EMPTY ) IL offs 0x001D : 0x00000455 ( STACK_EMPTY ) IL offs 0x0039 : 0x000004E5 IL offs 0x003E : 0x0000054A ( STACK_EMPTY ) IL offs 0x0080 : 0x00000554 ( STACK_EMPTY ) IL offs NO_MAP : 0x0000055E ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 38 *************** Variable debug info 38 live ranges 0( UNKNOWN) : From 00000000h to 0000006Eh, in rdi 1( UNKNOWN) : From 00000000h to 0000006Eh, in rsi 2( UNKNOWN) : From 00000000h to 0000006Eh, in rdx 3( UNKNOWN) : From 00000000h to 0000006Eh, in rcx 4( UNKNOWN) : From 00000000h to 0000006Eh, in r8 5( UNKNOWN) : From 00000000h to 0000006Eh, in r9 0( UNKNOWN) : From 0000006Eh to 0000012Fh, in rbp[-200] (1 slot) 2( UNKNOWN) : From 0000006Eh to 0000019Ch, in rbx 3( UNKNOWN) : From 0000006Eh to 0000019Ch, in r14 5( UNKNOWN) : From 0000006Eh to 0000019Ch, in r15 1( UNKNOWN) : From 0000006Eh to 0000019Ch, in r12 4( UNKNOWN) : From 0000006Eh to 0000019Ch, in r13 7( UNKNOWN) : From 000000CAh to 000001A0h, in rbp[-44] (1 slot) 7( UNKNOWN) : From 000001B2h to 00000220h, in rbp[-44] (1 slot) 10( UNKNOWN) : From 00000220h to 0000023Bh, in rsi 0( UNKNOWN) : From 0000023Bh to 00000242h, in rbp[-200] (1 slot) 10( UNKNOWN) : From 00000267h to 00000288h, in rsi 2( UNKNOWN) : From 000001B2h to 000002ADh, in rbx 3( UNKNOWN) : From 000001B2h to 000002ADh, in r14 5( UNKNOWN) : From 000001B2h to 000002ADh, in r15 1( UNKNOWN) : From 000001B2h to 000002ADh, in r12 4( UNKNOWN) : From 000001B2h to 000002ADh, in r13 7( UNKNOWN) : From 0000023Bh to 000002CFh, in rbp[-44] (1 slot) 0( UNKNOWN) : From 000002B2h to 000002DBh, in rbp[-200] (1 slot) 10( UNKNOWN) : From 000002DBh to 00000339h, in rsi 7( UNKNOWN) : From 0000041Bh to 00000438h, in rbp[-44] (1 slot) 2( UNKNOWN) : From 000002B2h to 00000442h, in rbx 3( UNKNOWN) : From 000002B2h to 00000442h, in r14 5( UNKNOWN) : From 000002B2h to 00000442h, in r15 1( UNKNOWN) : From 000002B2h to 00000442h, in r12 4( UNKNOWN) : From 000002B2h to 00000442h, in r13 0( UNKNOWN) : From 0000041Bh to 00000442h, in rbp[-200] (1 slot) 0( UNKNOWN) : From 0000044Ch to 00000554h, in rbp[-200] (1 slot) 2( UNKNOWN) : From 0000044Ch to 0000055Eh, in rbx 3( UNKNOWN) : From 0000044Ch to 0000055Eh, in r14 5( UNKNOWN) : From 0000044Ch to 0000055Eh, in r15 1( UNKNOWN) : From 0000044Ch to 0000055Eh, in r12 4( UNKNOWN) : From 0000044Ch to 0000055Eh, in r13 *************** In gcInfoBlockHdrSave() Set code length to 1380. Set ReturnKind to Scalar. Set stack base register to rbp. Set Outgoing stack arg area size to 40. Stack slot id for offset -64 (0xffffffc0) (frame) (untracked) = 0. Stack slot id for offset -72 (0xffffffb8) (frame) (untracked) = 1. Stack slot id for offset -88 (0xffffffa8) (frame) (untracked) = 2. Stack slot id for offset -104 (0xffffff98) (frame) (untracked) = 3. Stack slot id for offset -96 (0xffffffa0) (frame) (untracked) = 4. Stack slot id for offset -144 (0xffffff70) (frame) (untracked) = 5. Stack slot id for offset -136 (0xffffff78) (frame) (untracked) = 6. Stack slot id for offset -128 (0xffffff80) (frame) (untracked) = 7. Stack slot id for offset -120 (0xffffff88) (frame) (untracked) = 8. Stack slot id for offset -184 (0xffffff48) (frame) (untracked) = 9. Stack slot id for offset -176 (0xffffff50) (frame) (untracked) = 10. Stack slot id for offset -168 (0xffffff58) (frame) (untracked) = 11. Stack slot id for offset -160 (0xffffff60) (frame) (untracked) = 12. Stack slot id for offset -200 (0xffffff38) (frame) = 13. Stack slot id for offset -208 (0xffffff30) (frame) = 14. Stack slot id for offset -216 (0xffffff28) (frame) = 15. Stack slot id for offset -240 (0xffffff10) (frame) = 16. Stack slot id for offset -224 (0xffffff20) (frame) = 17. Stack slot id for offset -232 (0xffffff18) (frame) = 18. Register slot id for reg rbx = 19. Register slot id for reg r12 = 20. Register slot id for reg r13 = 21. Register slot id for reg r14 = 22. Register slot id for reg r15 (byref) = 23. Set state of slot 13 at instr offset 0x5f to Live. Set state of slot 13 at instr offset 0x12f to Dead. Set state of slot 14 at instr offset 0x200 to Live. Set state of slot 14 at instr offset 0x23b to Dead. Set state of slot 13 at instr offset 0x23b to Live. Set state of slot 13 at instr offset 0x258 to Dead. Set state of slot 14 at instr offset 0x267 to Live. Set state of slot 14 at instr offset 0x288 to Dead. Set state of slot 13 at instr offset 0x2b2 to Live. Set state of slot 13 at instr offset 0x2db to Dead. Set state of slot 14 at instr offset 0x2db to Live. Set state of slot 14 at instr offset 0x339 to Dead. Set state of slot 15 at instr offset 0x30e to Live. Set state of slot 15 at instr offset 0x381 to Dead. Set state of slot 16 at instr offset 0x351 to Live. Set state of slot 16 at instr offset 0x40f to Dead. Set state of slot 13 at instr offset 0x41b to Live. Set state of slot 13 at instr offset 0x442 to Dead. Set state of slot 13 at instr offset 0x44c to Live. Set state of slot 13 at instr offset 0x554 to Dead. Set state of slot 17 at instr offset 0x477 to Live. Set state of slot 17 at instr offset 0x4c6 to Dead. Set state of slot 18 at instr offset 0x496 to Live. Set state of slot 18 at instr offset 0x4e3 to Dead. Set state of slot 19 at instr offset 0x87 to Live. Set state of slot 20 at instr offset 0x87 to Live. Set state of slot 21 at instr offset 0x87 to Live. Set state of slot 22 at instr offset 0x87 to Live. Set state of slot 23 at instr offset 0x87 to Live. Set state of slot 19 at instr offset 0x89 to Dead. Set state of slot 20 at instr offset 0x89 to Dead. Set state of slot 21 at instr offset 0x89 to Dead. Set state of slot 22 at instr offset 0x89 to Dead. Set state of slot 23 at instr offset 0x89 to Dead. Set state of slot 19 at instr offset 0xb0 to Live. Set state of slot 20 at instr offset 0xb0 to Live. Set state of slot 21 at instr offset 0xb0 to Live. Set state of slot 22 at instr offset 0xb0 to Live. Set state of slot 23 at instr offset 0xb0 to Live. Set state of slot 19 at instr offset 0xb2 to Dead. Set state of slot 20 at instr offset 0xb2 to Dead. Set state of slot 21 at instr offset 0xb2 to Dead. Set state of slot 22 at instr offset 0xb2 to Dead. Set state of slot 23 at instr offset 0xb2 to Dead. Set state of slot 19 at instr offset 0xc0 to Live. Set state of slot 20 at instr offset 0xc0 to Live. Set state of slot 21 at instr offset 0xc0 to Live. Set state of slot 22 at instr offset 0xc0 to Live. Set state of slot 23 at instr offset 0xc0 to Live. Set state of slot 19 at instr offset 0xc2 to Dead. Set state of slot 20 at instr offset 0xc2 to Dead. Set state of slot 21 at instr offset 0xc2 to Dead. Set state of slot 22 at instr offset 0xc2 to Dead. Set state of slot 23 at instr offset 0xc2 to Dead. Set state of slot 19 at instr offset 0xe3 to Live. Set state of slot 20 at instr offset 0xe3 to Live. Set state of slot 21 at instr offset 0xe3 to Live. Set state of slot 22 at instr offset 0xe3 to Live. Set state of slot 23 at instr offset 0xe3 to Live. Set state of slot 19 at instr offset 0xe5 to Dead. Set state of slot 20 at instr offset 0xe5 to Dead. Set state of slot 21 at instr offset 0xe5 to Dead. Set state of slot 22 at instr offset 0xe5 to Dead. Set state of slot 23 at instr offset 0xe5 to Dead. Set state of slot 19 at instr offset 0x104 to Live. Set state of slot 20 at instr offset 0x104 to Live. Set state of slot 21 at instr offset 0x104 to Live. Set state of slot 22 at instr offset 0x104 to Live. Set state of slot 23 at instr offset 0x104 to Live. Set state of slot 19 at instr offset 0x106 to Dead. Set state of slot 20 at instr offset 0x106 to Dead. Set state of slot 21 at instr offset 0x106 to Dead. Set state of slot 22 at instr offset 0x106 to Dead. Set state of slot 23 at instr offset 0x106 to Dead. Set state of slot 19 at instr offset 0x125 to Live. Set state of slot 20 at instr offset 0x125 to Live. Set state of slot 21 at instr offset 0x125 to Live. Set state of slot 22 at instr offset 0x125 to Live. Set state of slot 23 at instr offset 0x125 to Live. Set state of slot 19 at instr offset 0x127 to Dead. Set state of slot 20 at instr offset 0x127 to Dead. Set state of slot 21 at instr offset 0x127 to Dead. Set state of slot 22 at instr offset 0x127 to Dead. Set state of slot 23 at instr offset 0x127 to Dead. Set state of slot 19 at instr offset 0x13f to Live. Set state of slot 20 at instr offset 0x13f to Live. Set state of slot 21 at instr offset 0x13f to Live. Set state of slot 22 at instr offset 0x13f to Live. Set state of slot 23 at instr offset 0x13f to Live. Set state of slot 19 at instr offset 0x141 to Dead. Set state of slot 20 at instr offset 0x141 to Dead. Set state of slot 21 at instr offset 0x141 to Dead. Set state of slot 22 at instr offset 0x141 to Dead. Set state of slot 23 at instr offset 0x141 to Dead. Set state of slot 19 at instr offset 0x160 to Live. Set state of slot 20 at instr offset 0x160 to Live. Set state of slot 21 at instr offset 0x160 to Live. Set state of slot 22 at instr offset 0x160 to Live. Set state of slot 23 at instr offset 0x160 to Live. Set state of slot 19 at instr offset 0x162 to Dead. Set state of slot 20 at instr offset 0x162 to Dead. Set state of slot 21 at instr offset 0x162 to Dead. Set state of slot 22 at instr offset 0x162 to Dead. Set state of slot 23 at instr offset 0x162 to Dead. Set state of slot 19 at instr offset 0x196 to Live. Set state of slot 20 at instr offset 0x196 to Live. Set state of slot 21 at instr offset 0x196 to Live. Set state of slot 22 at instr offset 0x196 to Live. Set state of slot 23 at instr offset 0x196 to Live. Set state of slot 19 at instr offset 0x198 to Dead. Set state of slot 20 at instr offset 0x198 to Dead. Set state of slot 21 at instr offset 0x198 to Dead. Set state of slot 22 at instr offset 0x198 to Dead. Set state of slot 23 at instr offset 0x198 to Dead. Set state of slot 19 at instr offset 0x1cd to Live. Set state of slot 20 at instr offset 0x1cd to Live. Set state of slot 21 at instr offset 0x1cd to Live. Set state of slot 22 at instr offset 0x1cd to Live. Set state of slot 23 at instr offset 0x1cd to Live. Set state of slot 19 at instr offset 0x1cf to Dead. Set state of slot 20 at instr offset 0x1cf to Dead. Set state of slot 21 at instr offset 0x1cf to Dead. Set state of slot 22 at instr offset 0x1cf to Dead. Set state of slot 23 at instr offset 0x1cf to Dead. Set state of slot 19 at instr offset 0x1eb to Live. Set state of slot 20 at instr offset 0x1eb to Live. Set state of slot 21 at instr offset 0x1eb to Live. Set state of slot 22 at instr offset 0x1eb to Live. Set state of slot 23 at instr offset 0x1eb to Live. Set state of slot 19 at instr offset 0x1ed to Dead. Set state of slot 20 at instr offset 0x1ed to Dead. Set state of slot 21 at instr offset 0x1ed to Dead. Set state of slot 22 at instr offset 0x1ed to Dead. Set state of slot 23 at instr offset 0x1ed to Dead. Set state of slot 19 at instr offset 0x219 to Live. Set state of slot 20 at instr offset 0x219 to Live. Set state of slot 21 at instr offset 0x219 to Live. Set state of slot 22 at instr offset 0x219 to Live. Set state of slot 23 at instr offset 0x219 to Live. Set state of slot 19 at instr offset 0x21b to Dead. Set state of slot 20 at instr offset 0x21b to Dead. Set state of slot 21 at instr offset 0x21b to Dead. Set state of slot 22 at instr offset 0x21b to Dead. Set state of slot 23 at instr offset 0x21b to Dead. Set state of slot 19 at instr offset 0x234 to Live. Set state of slot 20 at instr offset 0x234 to Live. Set state of slot 21 at instr offset 0x234 to Live. Set state of slot 22 at instr offset 0x234 to Live. Set state of slot 23 at instr offset 0x234 to Live. Set state of slot 19 at instr offset 0x236 to Dead. Set state of slot 20 at instr offset 0x236 to Dead. Set state of slot 21 at instr offset 0x236 to Dead. Set state of slot 22 at instr offset 0x236 to Dead. Set state of slot 23 at instr offset 0x236 to Dead. Set state of slot 19 at instr offset 0x258 to Live. Set state of slot 20 at instr offset 0x258 to Live. Set state of slot 21 at instr offset 0x258 to Live. Set state of slot 22 at instr offset 0x258 to Live. Set state of slot 23 at instr offset 0x258 to Live. Set state of slot 19 at instr offset 0x25a to Dead. Set state of slot 20 at instr offset 0x25a to Dead. Set state of slot 21 at instr offset 0x25a to Dead. Set state of slot 22 at instr offset 0x25a to Dead. Set state of slot 23 at instr offset 0x25a to Dead. Set state of slot 19 at instr offset 0x27e to Live. Set state of slot 20 at instr offset 0x27e to Live. Set state of slot 21 at instr offset 0x27e to Live. Set state of slot 22 at instr offset 0x27e to Live. Set state of slot 23 at instr offset 0x27e to Live. Set state of slot 19 at instr offset 0x280 to Dead. Set state of slot 20 at instr offset 0x280 to Dead. Set state of slot 21 at instr offset 0x280 to Dead. Set state of slot 22 at instr offset 0x280 to Dead. Set state of slot 23 at instr offset 0x280 to Dead. Set state of slot 19 at instr offset 0x2a3 to Live. Set state of slot 20 at instr offset 0x2a3 to Live. Set state of slot 21 at instr offset 0x2a3 to Live. Set state of slot 22 at instr offset 0x2a3 to Live. Set state of slot 23 at instr offset 0x2a3 to Live. Set state of slot 19 at instr offset 0x2a5 to Dead. Set state of slot 20 at instr offset 0x2a5 to Dead. Set state of slot 21 at instr offset 0x2a5 to Dead. Set state of slot 22 at instr offset 0x2a5 to Dead. Set state of slot 23 at instr offset 0x2a5 to Dead. Set state of slot 19 at instr offset 0x2c5 to Live. Set state of slot 20 at instr offset 0x2c5 to Live. Set state of slot 21 at instr offset 0x2c5 to Live. Set state of slot 22 at instr offset 0x2c5 to Live. Set state of slot 23 at instr offset 0x2c5 to Live. Set state of slot 19 at instr offset 0x2c7 to Dead. Set state of slot 20 at instr offset 0x2c7 to Dead. Set state of slot 21 at instr offset 0x2c7 to Dead. Set state of slot 22 at instr offset 0x2c7 to Dead. Set state of slot 23 at instr offset 0x2c7 to Dead. Set state of slot 19 at instr offset 0x2f3 to Live. Set state of slot 20 at instr offset 0x2f3 to Live. Set state of slot 21 at instr offset 0x2f3 to Live. Set state of slot 22 at instr offset 0x2f3 to Live. Set state of slot 23 at instr offset 0x2f3 to Live. Set state of slot 19 at instr offset 0x2f5 to Dead. Set state of slot 20 at instr offset 0x2f5 to Dead. Set state of slot 21 at instr offset 0x2f5 to Dead. Set state of slot 22 at instr offset 0x2f5 to Dead. Set state of slot 23 at instr offset 0x2f5 to Dead. Set state of slot 19 at instr offset 0x348 to Live. Set state of slot 20 at instr offset 0x348 to Live. Set state of slot 21 at instr offset 0x348 to Live. Set state of slot 22 at instr offset 0x348 to Live. Set state of slot 23 at instr offset 0x348 to Live. Set state of slot 19 at instr offset 0x34a to Dead. Set state of slot 20 at instr offset 0x34a to Dead. Set state of slot 21 at instr offset 0x34a to Dead. Set state of slot 22 at instr offset 0x34a to Dead. Set state of slot 23 at instr offset 0x34a to Dead. Set state of slot 19 at instr offset 0x35b to Live. Set state of slot 20 at instr offset 0x35b to Live. Set state of slot 21 at instr offset 0x35b to Live. Set state of slot 22 at instr offset 0x35b to Live. Set state of slot 23 at instr offset 0x35b to Live. Set state of slot 19 at instr offset 0x35d to Dead. Set state of slot 20 at instr offset 0x35d to Dead. Set state of slot 21 at instr offset 0x35d to Dead. Set state of slot 22 at instr offset 0x35d to Dead. Set state of slot 23 at instr offset 0x35d to Dead. Set state of slot 19 at instr offset 0x381 to Live. Set state of slot 20 at instr offset 0x381 to Live. Set state of slot 21 at instr offset 0x381 to Live. Set state of slot 22 at instr offset 0x381 to Live. Set state of slot 23 at instr offset 0x381 to Live. Set state of slot 19 at instr offset 0x383 to Dead. Set state of slot 20 at instr offset 0x383 to Dead. Set state of slot 21 at instr offset 0x383 to Dead. Set state of slot 22 at instr offset 0x383 to Dead. Set state of slot 23 at instr offset 0x383 to Dead. Set state of slot 19 at instr offset 0x40f to Live. Set state of slot 20 at instr offset 0x40f to Live. Set state of slot 21 at instr offset 0x40f to Live. Set state of slot 22 at instr offset 0x40f to Live. Set state of slot 23 at instr offset 0x40f to Live. Set state of slot 19 at instr offset 0x411 to Dead. Set state of slot 20 at instr offset 0x411 to Dead. Set state of slot 21 at instr offset 0x411 to Dead. Set state of slot 22 at instr offset 0x411 to Dead. Set state of slot 23 at instr offset 0x411 to Dead. Set state of slot 19 at instr offset 0x42e to Live. Set state of slot 20 at instr offset 0x42e to Live. Set state of slot 21 at instr offset 0x42e to Live. Set state of slot 22 at instr offset 0x42e to Live. Set state of slot 23 at instr offset 0x42e to Live. Set state of slot 19 at instr offset 0x430 to Dead. Set state of slot 20 at instr offset 0x430 to Dead. Set state of slot 21 at instr offset 0x430 to Dead. Set state of slot 22 at instr offset 0x430 to Dead. Set state of slot 23 at instr offset 0x430 to Dead. Set state of slot 19 at instr offset 0x464 to Live. Set state of slot 20 at instr offset 0x464 to Live. Set state of slot 21 at instr offset 0x464 to Live. Set state of slot 22 at instr offset 0x464 to Live. Set state of slot 23 at instr offset 0x464 to Live. Set state of slot 19 at instr offset 0x466 to Dead. Set state of slot 20 at instr offset 0x466 to Dead. Set state of slot 21 at instr offset 0x466 to Dead. Set state of slot 22 at instr offset 0x466 to Dead. Set state of slot 23 at instr offset 0x466 to Dead. Set state of slot 19 at instr offset 0x48d to Live. Set state of slot 20 at instr offset 0x48d to Live. Set state of slot 21 at instr offset 0x48d to Live. Set state of slot 22 at instr offset 0x48d to Live. Set state of slot 23 at instr offset 0x48d to Live. Set state of slot 19 at instr offset 0x48f to Dead. Set state of slot 20 at instr offset 0x48f to Dead. Set state of slot 21 at instr offset 0x48f to Dead. Set state of slot 22 at instr offset 0x48f to Dead. Set state of slot 23 at instr offset 0x48f to Dead. Set state of slot 19 at instr offset 0x4a0 to Live. Set state of slot 20 at instr offset 0x4a0 to Live. Set state of slot 21 at instr offset 0x4a0 to Live. Set state of slot 22 at instr offset 0x4a0 to Live. Set state of slot 23 at instr offset 0x4a0 to Live. Set state of slot 19 at instr offset 0x4a2 to Dead. Set state of slot 20 at instr offset 0x4a2 to Dead. Set state of slot 21 at instr offset 0x4a2 to Dead. Set state of slot 22 at instr offset 0x4a2 to Dead. Set state of slot 23 at instr offset 0x4a2 to Dead. Set state of slot 19 at instr offset 0x4c6 to Live. Set state of slot 20 at instr offset 0x4c6 to Live. Set state of slot 21 at instr offset 0x4c6 to Live. Set state of slot 22 at instr offset 0x4c6 to Live. Set state of slot 23 at instr offset 0x4c6 to Live. Set state of slot 19 at instr offset 0x4c8 to Dead. Set state of slot 20 at instr offset 0x4c8 to Dead. Set state of slot 21 at instr offset 0x4c8 to Dead. Set state of slot 22 at instr offset 0x4c8 to Dead. Set state of slot 23 at instr offset 0x4c8 to Dead. Set state of slot 19 at instr offset 0x4e3 to Live. Set state of slot 20 at instr offset 0x4e3 to Live. Set state of slot 21 at instr offset 0x4e3 to Live. Set state of slot 22 at instr offset 0x4e3 to Live. Set state of slot 23 at instr offset 0x4e3 to Live. Set state of slot 19 at instr offset 0x4e5 to Dead. Set state of slot 20 at instr offset 0x4e5 to Dead. Set state of slot 21 at instr offset 0x4e5 to Dead. Set state of slot 22 at instr offset 0x4e5 to Dead. Set state of slot 23 at instr offset 0x4e5 to Dead. Set state of slot 19 at instr offset 0x548 to Live. Set state of slot 20 at instr offset 0x548 to Live. Set state of slot 21 at instr offset 0x548 to Live. Set state of slot 22 at instr offset 0x548 to Live. Set state of slot 23 at instr offset 0x548 to Live. Set state of slot 19 at instr offset 0x54a to Dead. Set state of slot 20 at instr offset 0x54a to Dead. Set state of slot 21 at instr offset 0x54a to Dead. Set state of slot 22 at instr offset 0x54a to Dead. Set state of slot 23 at instr offset 0x54a to Dead. Defining 30 call sites: Offset 0x87, size 2. Offset 0xb0, size 2. Offset 0xc0, size 2. Offset 0xe3, size 2. Offset 0x104, size 2. Offset 0x125, size 2. Offset 0x13f, size 2. Offset 0x160, size 2. Offset 0x196, size 2. Offset 0x1cd, size 2. Offset 0x1eb, size 2. Offset 0x219, size 2. Offset 0x234, size 2. Offset 0x258, size 2. Offset 0x27e, size 2. Offset 0x2a3, size 2. Offset 0x2c5, size 2. Offset 0x2f3, size 2. Offset 0x348, size 2. Offset 0x35b, size 2. Offset 0x381, size 2. Offset 0x40f, size 2. Offset 0x42e, size 2. Offset 0x464, size 2. Offset 0x48d, size 2. Offset 0x4a0, size 2. Offset 0x4c6, size 2. Offset 0x4e3, size 2. Offset 0x548, size 2. Offset 0x55e, size 5. *************** Finishing PHASE Emit GC+EH tables Method code size: 1380 Allocations for Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool (MethodHash=a679a79b) count: 8726, size: 581701, max = 4080 allocateMemory: 655360, nraUsed: 593512 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 6460 | 1.11% ASTNode | 88096 | 15.14% InstDesc | 26388 | 4.54% ImpStack | 384 | 0.07% BasicBlock | 11448 | 1.97% fgArgInfo | 4392 | 0.76% fgArgInfoPtrArr | 608 | 0.10% FlowList | 1632 | 0.28% TreeStatementList | 128 | 0.02% SiScope | 2712 | 0.47% DominatorMemory | 1392 | 0.24% LSRA | 6280 | 1.08% LSRA_Interval | 14640 | 2.52% LSRA_RefPosition | 65920 | 11.33% Reachability | 16 | 0.00% SSA | 7872 | 1.35% ValueNumber | 31709 | 5.45% LvaTable | 6948 | 1.19% UnwindInfo | 0 | 0.00% hashBv | 1040 | 0.18% bitset | 1096 | 0.19% FixedBitVect | 144 | 0.02% Generic | 10882 | 1.87% LocalAddressVisitor | 512 | 0.09% FieldSeqStore | 744 | 0.13% ZeroOffsetFieldMap | 416 | 0.07% ArrayInfoMap | 312 | 0.05% MemoryPhiArg | 608 | 0.10% CSE | 3264 | 0.56% GC | 13238 | 2.28% CorTailCallInfo | 0 | 0.00% Inlining | 12384 | 2.13% ArrayStack | 256 | 0.04% DebugInfo | 1432 | 0.25% DebugOnly | 249625 | 42.91% Codegen | 1184 | 0.20% LoopOpt | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 2923 | 0.50% RangeCheck | 1208 | 0.21% CopyProp | 2832 | 0.49% SideEffects | 0 | 0.00% ObjectAllocator | 0 | 0.00% VariableLiveRanges | 0 | 0.00% ClassLayout | 488 | 0.08% TailMergeThrows | 0 | 0.00% EarlyProp | 0 | 0.00% ZeroInit | 88 | 0.02% ****** DONE compiling Microsoft.CodeAnalysis.VisualBasic.Symbols.ConstraintsHelper:CheckConstraints(Microsoft.CodeAnalysis.VisualBasic.Symbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSubstitution,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeParameterSymbol,Microsoft.CodeAnalysis.VisualBasic.Symbols.TypeSymbol,Microsoft.CodeAnalysis.ArrayBuilder`1[TypeParameterDiagnosticInfo],byref):bool