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Copy file name to clipboardExpand all lines: ERRATA.md
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## Shell Errata
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Shell errata is [documented here](./hdk/docs/AWS_Shell_ERRATA.md)
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## Vitis
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* Support for Vitis software emulation has been deprecated by AMD, therefore, no longer supported.
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## HDK
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* Multiple SDE instances per CL is not supported in this release. Support is planned for a future release.
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* DRAM Data retention is not supported for CL designs with less than 4 DDRs enabled
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### flop_ccf.sv bug
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We have identified a bug in the `flop_ccf.sv` module that can potentially impact timing closure of designs.
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The module is instantiated in `sh_ddr.sv` and inadvertently introduces a timing path on the reset logic.
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Although there is no functional impact, it may increase Vivado tool’s effort in timing closure of design.
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There should be no functional impact from this bug if your design has already met timing.
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We have identified a bug in the `flop_ccf.sv` module that can potentially impact timing closure of designs.
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The module is instantiated in `sh_ddr.sv` and inadvertently introduces a timing path on the reset logic.
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Although there is no functional impact, it may increase Vivado tool’s effort in timing closure of design.
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There should be no functional impact from this bug if your design has already met timing.
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This bug is fixed in aws-fpga release v1.4.19
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Q: Which designs does this bug affect?
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A: This bug only affects designs that instantiate the sh_ddr module.
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Q: How do I fix my design if I am affected by this bug?
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A: Pull aws-fpga release v1.4.19 or later from the aws-fpga github and rebuild your cl design.
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The flop_ccf.sv files from the latest release that contain the fix are: [sh_ddr/synth/flop_ccf.sv](https://github.com/aws/aws-fpga/blob/master/hdk/common/shell_v04261818/design/sh_ddr/synth/flop_ccf.sv) &
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A: Pull aws-fpga release v1.4.19 or later from the aws-fpga github and rebuild your cl design.
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The flop_ccf.sv files from the latest release that contain the fix are: [sh_ddr/synth/flop_ccf.sv](https://github.com/aws/aws-fpga/blob/master/hdk/common/shell_v04261818/design/sh_ddr/synth/flop_ccf.sv) &
### Xilinx Design Advisory for UltraScale/UltraScale+ DDR4/DDR3 IP - Memory IP Timing Exceptions (AR# 73068)
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AWS EC2 F1 customers using the DDR4 IP in customer logic (HDK or SDAccel/Vitis designs) may be impacted by a recent design advisory from Xilinx.
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AWS customers may experience hardware failures including: post calibration data errors and DQS gate tracking issues. The error condition is build dependent and errors would need to be detected on the first write/read access after a successful calibration to prevent further data corruption.
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To detect if your build is impacted by this bug, AWS recommends all EC2 F1 customers utilizing the DDR4 IP in their designs should run a TCL script on the design checkpoint point (DCP) to check to determine if the design is susceptible to this issue. If the check passes, your design is safe to use as the hardware will function properly.
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If the check fails, the design is susceptible to the issue and will need to be regenerated using the same tool version with the AR 73068 patch.
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For designs under development, we recommend applying the patch to your on-premises tools or update to developer kit v1.4.15.
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To detect if your build is impacted by this bug, AWS recommends all EC2 F1 customers utilizing the DDR4 IP in their designs should run a TCL script on the design checkpoint point (DCP) to check to determine if the design is susceptible to this issue. If the check passes, your design is safe to use as the hardware will function properly.
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If the check fails, the design is susceptible to the issue and will need to be regenerated using the same tool version with the AR 73068 patch.
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For designs under development, we recommend applying the patch to your on-premises tools or update to developer kit v1.4.15.
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For additional details, please refer to the [Xilinx Answer Record #73068](https://support.xilinx.com/s/article/73068?language=en_US)
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We recommend using [Developer Kit Release v1.4.15a](https://github.com/aws/aws-fpga/releases/tag/v1.4.15a) or newer to allow for patching and fixing the DDR4 IP timing exception by re-generating the IP.
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### 2019.1
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### 2019.1
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* Vivado `compile_simlib` command fails to generate the following verilog IP libraries for the following simulators.
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* Please refer to the Xilinx Answer record for details.
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| Library(verilog) | Simulator | Xilinx Answer Record |
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| Library(verilog) | Simulator | Xilinx Answer Record |
Copy file name to clipboardExpand all lines: Vitis/README.md
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# Table of Content
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1.[Overview](#overview)
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2.[Prerequisites](#prerequisites)
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*[AWS Account, F1/EC2 Instances, On-Premises, AWS IAM Permissions, AWS CLI and S3 Setup](#iss)
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*[Github and Environment Setup](#gitsetenv)
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3.[Build the host application, Xilinx FPGA binary and verify you are ready for FPGA acceleration](#createapp)
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*[Emulate the code](#emu)
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*[Software Emulation](#swemu)
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*[Hardware Emulation](#hwemu)
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*[Build the host application and Xilinx FPGA Binary](#hw)
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4.[Create an Amazon FPGA Image (AFI)](#createafi)
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5.[Run the FPGA accelerated application on F1](#runonf1)
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6.[Additional Vitis Information](#read)
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-[Quick Start Guide to Accelerating your C/C++ application on an AWS F1 FPGA Instance with Vitis](#quick-start-guide-to-accelerating-your-cc-application-on-an-aws-f1-fpga-instance-with-vitis)
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-[Table of Content](#table-of-content)
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-[Overview](#overview)
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-[Prerequisites](#prerequisites)
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-[AWS Account, F1/EC2 Instances, On-Premises, AWS IAM Permissions, AWS CLI and S3 Setup (One-time Setup)](#aws-account-f1ec2-instances-on-premises-aws-iam-permissions-aws-cli-and-s3-setup-one-time-setup)
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-[Github and Environment Setup](#github-and-environment-setup)
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-[1. Build the host application, Xilinx FPGA binary and verify you are ready for FPGA acceleration](#1-build-the-host-application-xilinx-fpga-binary-and-verify-you-are-ready-for-fpga-acceleration)
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* Sourcing the *vitis_setup.sh* script:
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* Downloads and sets the correct AWS Platform:
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* AWS Vitis Platform that contains the dynamic hardware that enables Vitis kernels to run on AWS F1 instances.
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* Valid platforms for shell_v04261818: `AWS_PLATFORM_201920_3` (Default) AWS F1 Vitis platform.
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* Valid platforms for shell_v04261818: `AWS_PLATFORM_201920_4` (Default) AWS F1 Vitis platform.
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* Sets up the Xilinx Vitis example submodules.
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* Installs the required libraries and package dependencies.
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* Run environment checks to verify supported tool/lib versions.
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# Emulate your Code
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The main goal of emulation is to ensure functional correctness and to determine how to partition the application between the host CPU and the FPGA.
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HW/SW Emulation does not require use of actual FPGA's and can be run on any compute instances. Using non-F1 EC2 compute instances for initial development will help reduce costs.
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<aname="swemu"></a>
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## Software (SW) Emulation
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For CPU-based (SW) emulation, both the host code and the FPGA binary code are compiled to run on an x86 processor.
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SW Emulation enables developers to iterate and refine the algorithms through fast compilation.
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The iteration time is similar to software compile and run cycles on a CPU.
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The instructions below describe how to run the Vitis SW Emulation flow using the Makefile provided with a simple "hello world" example
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```
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$ cd $VITIS_DIR/examples/xilinx/hello_world
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$ make clean
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$ make run TARGET=sw_emu DEVICE=$AWS_PLATFORM all
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```
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For more information on how to debug your application in a SW Emulation environment.
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HW Emulation does not require use of actual FPGA's and can be run on any compute instances. Using non-F1 EC2 compute instances for initial development will help reduce costs.
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<aname="hwemu"></a>
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## Hardware (HW) Emulation
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```
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$ cd $VITIS_DIR/examples/xilinx/hello_world
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$ make clean
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$ make run TARGET=hw_emu DEVICE=$AWS_PLATFORM all
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$ make run TARGET=hw_emu PLATFORM=$AWS_PLATFORM all
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```
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For more information on how to debug your application in a HW Emulation environment.
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```
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$ cd $VITIS_DIR/examples/xilinx/hello_world
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$ make clean
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$ make TARGET=hw DEVICE=$AWS_PLATFORM all
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$ make TARGET=hw PLATFORM=$AWS_PLATFORM all
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```
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NOTE: If you encounter an error with `No current synthesis run set`, you may have previously run the [HDK IPI examples](../hdk/docs/IPI_GUI_Vivado_Setup.md) and created a `Vivado_init.tcl` file in `~/.Xilinx/Vivado`. This will cause [problems](https://forums.aws.amazon.com/thread.jspa?threadID=268202&tstart=25) with the build process, thus it is recommended to remove it before starting a hardware system build.
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This assumes you have:
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*[Compiled your host application and Xilinx FPGA Binary](#hw)
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* Validated your code using [SW/HW Emulation](#emu) and you are ready to create an AFI and test on F1.
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* Validated your code using [HW Emulation](#emu) and you are ready to create an AFI and test on F1.
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*[Setup AWS CLI and S3 bucket](docs/Setup_AWS_CLI_and_S3_Bucket.md) for AFI creation
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The [create_vitis_afi.sh](./tools/create_vitis_afi.sh) script is provided to facilitate AFI creation from a Xilinx FPGA Binary, it:
## 5. Make Runtime AMI available on the AWS Marketplace
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* Please see [Section 5 of the AWS Marketplace Seller's Guide](https://awsmp-loadforms.s3.amazonaws.com/AWS_Marketplace_-_Seller_Guide.pdf#page=19) for more details.
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* Please see [Section 5 of the AWS Marketplace Seller's Guide](https://awsmp-loadforms.s3.amazonaws.com/AWS_Marketplace_-_Seller_Guide.pdf#page=19) for more details.
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```sudo systemctl restart mpd```
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**Note that MPD service starts asynchronously, so you might have to wait till all the slots are loaded with the Default AFI before your application can run.**
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## Custom Runtime AMI usecase
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On your custom Runtime AMI, MPD will be enabled by default once you install Xilinx XRT.
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On startup, MPD will check if the instance has FPGA's and will load the Default AFI's.
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## Default AFI details
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The Default AFI loaded is a regular `Hello World` AFI that provides the Device ID 0xF010.
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# Centos/RHEL build and install steps
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# Ubuntu build and install steps
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```bash
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XRT_RELEASE_TAG=2019.2.0.3# Substitute XRT_RELEASE_TAG=<TAG from above table>
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XRT_RELEASE_TAG=202410.2.17.319# Substitute XRT_RELEASE_TAG=<TAG from above table>
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git clone https://github.com/aws/aws-fpga.git
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sudo ./src/runtime_src/tools/scripts/xrtdeps.sh
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cd build
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scl enable devtoolset-6 bash
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./build.sh
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cd Release
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sudo apt reinstall ./xrt_*.rpm -y
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```
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# AL2 build and install steps
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```bash
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XRT_RELEASE_TAG=202010.2.6.AWS # Substitute XRT_RELEASE_TAG=<TAG from above table>
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