Updated cl_sde IPs to 2024.1

Author: czfpga

hdk/cl/examples/cl_sde/ip/ila_axi4.xci

@@ -1,3 +1,148 @@
+2024.1:
+ * Version 6.2 (Rev. 15)
+ * General: IP packaging adjustments to address warnings from IP Packager integrity check
+ * Revision change in one or more subcores
+
+2023.2.2:
+ * Version 6.2 (Rev. 14)
+ * No changes
+
+2023.2.1:
+ * Version 6.2 (Rev. 14)
+ * No changes
+
+2023.2:
+ * Version 6.2 (Rev. 14)
+ * General: Rebrand to AMD copyright information
+ * Revision change in one or more subcores
+
+2023.1.2:
+ * Version 6.2 (Rev. 13)
+ * No changes
+
+2023.1.1:
+ * Version 6.2 (Rev. 13)
+ * No changes
+
+2023.1:
+ * Version 6.2 (Rev. 13)
+ * Revision change in one or more subcores
+
+2022.2.2:
+ * Version 6.2 (Rev. 12)
+ * No changes
+
+2022.2.1:
+ * Version 6.2 (Rev. 12)
+ * No changes
+
+2022.2:
+ * Version 6.2 (Rev. 12)
+ * No changes
+
+2022.1.2:
+ * Version 6.2 (Rev. 12)
+ * No changes
+
+2022.1.1:
+ * Version 6.2 (Rev. 12)
+ * No changes
+
+2022.1:
+ * Version 6.2 (Rev. 12)
+ * No changes
+
+2021.2.2:
+ * Version 6.2 (Rev. 12)
+ * No changes
+
+2021.2.1:
+ * Version 6.2 (Rev. 12)
+ * No changes
+
+2021.2:
+ * Version 6.2 (Rev. 12)
+ * General: Updated the Example design XDC files for pin locs
+ * Revision change in one or more subcores
+
+2021.1.1:
+ * Version 6.2 (Rev. 11)
+ * No changes
+
+2021.1:
+ * Version 6.2 (Rev. 11)
+ * No changes
+
+2020.3:
+ * Version 6.2 (Rev. 11)
+ * No changes
+
+2020.2.2:
+ * Version 6.2 (Rev. 11)
+ * No changes
+
+2020.2.1:
+ * Version 6.2 (Rev. 11)
+ * No changes
+
+2020.2:
+ * Version 6.2 (Rev. 11)
+ * No changes
+
+2020.1.1:
+ * Version 6.2 (Rev. 11)
+ * No changes
+
+2020.1:
+ * Version 6.2 (Rev. 11)
+ * General: Added security attribute
+
+2019.2.2:
+ * Version 6.2 (Rev. 10)
+ * No changes
+
+2019.2.1:
+ * Version 6.2 (Rev. 10)
+ * No changes
+
+2019.2:
+ * Version 6.2 (Rev. 10)
+ * General: Updated the waivers for CDC
+ * Revision change in one or more subcores
+
+2019.1.3:
+ * Version 6.2 (Rev. 9)
+ * No changes
+
+2019.1.2:
+ * Version 6.2 (Rev. 9)
+ * No changes
+
+2019.1.1:
+ * Version 6.2 (Rev. 9)
+ * No changes
+
+2019.1:
+ * Version 6.2 (Rev. 9)
+ * General: Updated the waivers for CDC
+ * Revision change in one or more subcores
+
+2018.3.1:
+ * Version 6.2 (Rev. 8)
+ * No changes
+
+2018.3:
+ * Version 6.2 (Rev. 8)
+ * General: Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2018.2:
+ * Version 6.2 (Rev. 7)
+ * General: Added device support for virtexuplus58gf family
+
+2018.1:
+ * Version 6.2 (Rev. 6)
+ * General: Updated ILA to handle XDC warnings
+
 2017.4:
  * Version 6.2 (Rev. 5)
  * General: Updated ILA to handle XDC warnings
@@ -27,14 +172,15 @@
  * Revision change in one or more subcores
 
 2016.2:
- * Version 6.1
- * No changes
+ * Version 6.1 (Rev. 1)
+ * Revision change in one or more subcores
 
 2016.1:
  * Version 6.1
  * Updated the IP to support 2 Windows & 1 Sample count configuration
  * Number of comparator increased from 1 to 16 in basic mode and 4 to 16 in advanced mode
  * Updated probe data width register
+ * Revision change in one or more subcores
 
 2015.4.2:
  * Version 6.0 (Rev. 1)
@@ -47,11 +193,13 @@
 2015.4:
  * Version 6.0 (Rev. 1)
  * No change
+ * Revision change in one or more subcores
 
 2015.3:
  * Version 6.0
  * Fixed Timing10 DRC violations in ILA IP.
  * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Revision change in one or more subcores
 
 2015.2.1:
  * Version 5.1 (Rev. 1)
@@ -112,24 +260,23 @@
  * Version 2.0
  * Native Vivado Release
 
-(c) Copyright 2000 - 2018 Xilinx, Inc. All rights reserved.
+(c) Copyright 2000 - 2024 Advanced Micro Devices, Inc. All rights reserved.
 
 This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
+of AMD and is protected under U.S. and international copyright
+and other intellectual property laws.
 
 DISCLAIMER
 This disclaimer is not a license and does not grant any
 rights to the materials distributed herewith. Except as
 otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
+AMD, and to the maximum extent permitted by applicable
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-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
 AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-(2) Xilinx shall not be liable (whether in contract or tort,
+(2) AMD shall not be liable (whether in contract or tort,
 including negligence, or under any other theory of
 liability) for any loss or damage of any kind or nature
 related to, arising under or in connection with these
@@ -138,11 +285,11 @@ special, incidental, or consequential loss or damage
 (including loss of data, profits, goodwill, or any type of
 loss or damage suffered as a result of any action brought
 by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
+reasonably foreseeable or AMD had been advised of the
 possibility of the same.
 
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-Xilinx products are not designed or intended to be fail-
+AMD products are not designed or intended to be fail-
 safe, or for use in any application requiring fail-safe
 performance, such as life-support or safety devices or
 systems, Class III medical devices, nuclear facilities,
@@ -151,7 +298,7 @@ other applications that could lead to death, personal
 injury, or severe property or environmental damage
 (individually and collectively, "Critical
 Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
+liability of any use of AMD products in Critical
 Applications, subject only to applicable laws and
 regulations governing limitations on product liability.