HSD #15011820475: arm: dts: soc64: Revert "changing DDR aliasing addresses"

This commit "HSD #15010938416: arm: dts: soc64: changing DDR aliasing addresses" is causing the uboot to break. Revert this commit fixes the ethernet packet issue. Signed-off-by: Lokanathan, Raaj <raaj.lokanathan@intel.com>

Author: raajloka

arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi

@@ -28,29 +28,9 @@
 };
 
 memory {
-/*
- * Recommended Aliasing addresses
- *
- * 16GB
- * <0 0x00000000 0 0x80000000>,
- * <0x10 0x80000000 3 0x80000000>;
- *
- * 8GB
- * <0 0x00000000 0 0x80000000>,
- * <0x10 0x80000000 1 0x80000000>;
- *
- * 4GB
- * <0 0x00000000 0 0x80000000>,
- * <0x10 0x80000000 0 0x80000000>;
- *
- * 2GB
- * <0 0x00000000 0 0x80000000>;
- *
- * Note: Need to set CONFIG_NR_DRAM_BANKS=1 for 2GB in defconfig
- * Default CONFIG_NR_DRAM_BANKS=2 is used for other DDR size
- */
+/* 8GB */
 reg = <0 0x00000000 0 0x80000000>,
- <0x10 0x80000000 1 0x80000000>;
+ <2 0x80000000 1 0x80000000>;
 
 };
 };

arch/arm/dts/socfpga_stratix10_socdk.dts

@@ -36,29 +36,9 @@
 #address-cells = <2>;
 #size-cells = <2>;
 device_type = "memory";
-/*
- * Recommended Aliasing addresses
- *
- * 16GB
- * <0 0x00000000 0 0x80000000>,
- * <0x10 0x80000000 3 0x80000000>;
- *
- * 8GB
- * <0 0x00000000 0 0x80000000>,
- * <0x10 0x80000000 1 0x80000000>;
- *
- * 4GB
- * <0 0x00000000 0 0x80000000>,
- * <0x10 0x80000000 0 0x80000000>;
- *
- * 2GB
- * <0 0x00000000 0 0x80000000>;
- *
- * Note: Need to set CONFIG_NR_DRAM_BANKS=1 for 2GB in defconfig
- * Default CONFIG_NR_DRAM_BANKS=2 is used for other DDR size
- */
+/* 4GB */
 reg = <0 0x00000000 0 0x80000000>,
- <0x10 0x80000000 0 0x80000000>;
+ <1 0x80000000 0 0x80000000>;
 bootph-all;
 };
 };

arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi

@@ -12,29 +12,9 @@
 #address-cells = <2>;
 #size-cells = <2>;
 device_type = "memory";
-/*
- * Recommended Aliasing addresses
- *
- * 16GB
- * <0 0x00000000 0 0x80000000>,
- * <0x10 0x80000000 3 0x80000000>;
- *
- * 8GB
- * <0 0x00000000 0 0x80000000>,
- * <0x10 0x80000000 1 0x80000000>;
- *
- * 4GB
- * <0 0x00000000 0 0x80000000>,
- * <0x10 0x80000000 0 0x80000000>;
- *
- * 2GB
- * <0 0x00000000 0 0x80000000>;
- *
- * Note: Need to set CONFIG_NR_DRAM_BANKS=1 for 2GB in defconfig
- * Default CONFIG_NR_DRAM_BANKS=2 is used for other DDR size
- */
+/* 4GB */
 reg = <0 0x00000000 0 0x80000000>,
- <0x10 0x80000000 0 0x80000000>;
+ <1 0x80000000 0 0x80000000>;
 bootph-all;
 };