Added lock checking

Author: makermelissa

adafruit_bitbangio.py

@@ -71,6 +71,11 @@ def unlock(self):
  else:
  raise ValueError("Not locked")
 
+ def _check_lock(self):
+ if not self._locked:
+ raise RuntimeError("First call try_lock()")
+ return True
+
  def __enter__(self):
  return self
 
@@ -111,25 +116,28 @@ def __init__(self, scl, sda, *, frequency=400000, timeout=1):
  def scan(self):
  """Perform an I2C Device Scan"""
  found = []
- for address in range(0, 0x80):
- if self._probe(address):
- found.append(address)
+ if self._check_lock():
+ for address in range(0, 0x80):
+ if self._probe(address):
+ found.append(address)
  return found
 
  def writeto(self, address, buffer, *, start=0, end=None, stop=True):
  """Write data from the buffer to an address"""
  if end is None:
  end = len(buffer)
- self._write(address, buffer[start:end], stop)
+ if self._check_lock():
+ self._write(address, buffer[start:end], stop)
 
  def readfrom_into(self, address, buffer, *, start=0, end=None):
  """Read data from an address and into the buffer"""
  if end is None:
  end = len(buffer)
 
- readin = self._read(address, end - start)
- for i in range(end - start):
- buffer[i + start] = readin[i]
+ if self._check_lock():
+ readin = self._read(address, end - start)
+ for i in range(end - start):
+ buffer[i + start] = readin[i]
 
  def writeto_then_readfrom(
  self,
@@ -150,8 +158,9 @@ def writeto_then_readfrom(
  out_end = len(buffer_out)
  if in_end is None:
  in_end = len(buffer_in)
- self.writeto(address, buffer_out, start=out_start, end=out_end, stop=stop)
- self.readfrom_into(address, buffer_in, start=in_start, end=in_end)
+ if self._check_lock():
+ self.writeto(address, buffer_out, start=out_start, end=out_end, stop=stop)
+ self.readfrom_into(address, buffer_in, start=in_start, end=in_end)
 
  def _scl_low(self):
  self._scl.value = 0
@@ -308,7 +317,7 @@ def __init__(self, clock, MOSI=None, MISO=None):
 
  def configure(self, *, baudrate=100000, polarity=0, phase=0, bits=8):
  """Configures the SPI bus. Only valid when locked."""
- if self._locked:
+ if self._check_lock():
  if not isinstance(baudrate, int):
  raise ValueError("baudrate must be an integer")
  if not isinstance(bits, int):
@@ -325,9 +334,6 @@ def configure(self, *, baudrate=100000, polarity=0, phase=0, bits=8):
  self._bits = bits
  self._half_period = (1 / self._baudrate) / 2 # 50% Duty Cyle delay
 
- else:
- raise RuntimeError("First call try_lock()")
-
  def _wait(self, start=None):
  """Wait for up to one half cycle"""
  while (start + self._half_period) > monotonic():
@@ -344,26 +350,28 @@ def write(self, buffer, start=0, end=None):
  if end is None:
  end = len(buffer)
 
- start_time = monotonic()
- for byte in buffer[start:end]:
- for bit_position in range(self._bits):
- bit_value = byte & 0x80 >> bit_position
- # Set clock to base
- if not self._phase: # Mode 0, 2
- self._mosi.value = bit_value
- self._sclk.value = self._polarity
- start_time = self._wait(start_time)
-
- # Flip clock off base
- if self._phase: # Mode 1, 3
- self._mosi.value = bit_value
- self._sclk.value = not self._polarity
- start_time = self._wait(start_time)
-
- # Return pins to base positions
- self._mosi.value = 0
- self._sclk.value = self._polarity
+ if self._check_lock():
+ start_time = monotonic()
+ for byte in buffer[start:end]:
+ for bit_position in range(self._bits):
+ bit_value = byte & 0x80 >> bit_position
+ # Set clock to base
+ if not self._phase: # Mode 0, 2
+ self._mosi.value = bit_value
+ self._sclk.value = self._polarity
+ start_time = self._wait(start_time)
 
+ # Flip clock off base
+ if self._phase: # Mode 1, 3
+ self._mosi.value = bit_value
+ self._sclk.value = not self._polarity
+ start_time = self._wait(start_time)
+
+ # Return pins to base positions
+ self._mosi.value = 0
+ self._sclk.value = self._polarity
+
+ # pylint: disable=too-many-branches
  def readinto(self, buffer, start=0, end=None, write_value=0):
  """Read into the buffer specified by buf while writing zeroes. Requires the SPI being
  locked. If the number of bytes to read is 0, nothing happens.
@@ -372,43 +380,44 @@ def readinto(self, buffer, start=0, end=None, write_value=0):
  raise RuntimeError("Read attempted with no MISO pin specified.")
  if end is None:
  end = len(buffer)
- start_time = monotonic()
- for byte_position, _ in enumerate(buffer[start:end]):
- for bit_position in range(self._bits):
- bit_mask = 0x80 >> bit_position
- bit_value = write_value & 0x80 >> bit_position
- # Return clock to base
- self._sclk.value = self._polarity
- start_time = self._wait(start_time)
- # Handle read on leading edge of clock.
- if not self._phase: # Mode 0, 2
- if self._mosi is not None:
- self._mosi.value = bit_value
- if self._miso.value:
- # Set bit to 1 at appropriate location.
- buffer[byte_position] |= bit_mask
- else:
- # Set bit to 0 at appropriate location.
- buffer[byte_position] &= ~bit_mask
- # Flip clock off base
- self._sclk.value = not self._polarity
- start_time = self._wait(start_time)
- # Handle read on trailing edge of clock.
- if self._phase: # Mode 1, 3
- if self._mosi is not None:
- self._mosi.value = bit_value
- if self._miso.value:
- # Set bit to 1 at appropriate location.
- buffer[byte_position] |= bit_mask
- else:
- # Set bit to 0 at appropriate location.
- buffer[byte_position] &= ~bit_mask
 
- # Return pins to base positions
- self._mosi.value = 0
- self._sclk.value = self._polarity
+ if self._check_lock():
+ start_time = monotonic()
+ for byte_position, _ in enumerate(buffer[start:end]):
+ for bit_position in range(self._bits):
+ bit_mask = 0x80 >> bit_position
+ bit_value = write_value & 0x80 >> bit_position
+ # Return clock to base
+ self._sclk.value = self._polarity
+ start_time = self._wait(start_time)
+ # Handle read on leading edge of clock.
+ if not self._phase: # Mode 0, 2
+ if self._mosi is not None:
+ self._mosi.value = bit_value
+ if self._miso.value:
+ # Set bit to 1 at appropriate location.
+ buffer[byte_position] |= bit_mask
+ else:
+ # Set bit to 0 at appropriate location.
+ buffer[byte_position] &= ~bit_mask
+ # Flip clock off base
+ self._sclk.value = not self._polarity
+ start_time = self._wait(start_time)
+ # Handle read on trailing edge of clock.
+ if self._phase: # Mode 1, 3
+ if self._mosi is not None:
+ self._mosi.value = bit_value
+ if self._miso.value:
+ # Set bit to 1 at appropriate location.
+ buffer[byte_position] |= bit_mask
+ else:
+ # Set bit to 0 at appropriate location.
+ buffer[byte_position] &= ~bit_mask
+
+ # Return pins to base positions
+ self._mosi.value = 0
+ self._sclk.value = self._polarity
 
- # pylint: disable=too-many-branches
  def write_readinto(
  self,
  buffer_out,
@@ -435,40 +444,43 @@ def write_readinto(
  if len(buffer_out[out_start:out_end]) != len(buffer_in[in_start:in_end]):
  raise RuntimeError("Buffer slices must be equal length")
 
- start_time = monotonic()
- for byte_position, _ in enumerate(buffer_out[out_start:out_end]):
- for bit_position in range(self._bits):
- bit_mask = 0x80 >> bit_position
- bit_value = buffer_out[byte_position + out_start] & 0x80 >> bit_position
- in_byte_position = byte_position + in_start
- # Return clock to 0
- self._sclk.value = self._polarity
- start_time = self._wait(start_time)
- # Handle read on leading edge of clock.
- if not self._phase: # Mode 0, 2
- self._mosi.value = bit_value
- if self._miso.value:
- # Set bit to 1 at appropriate location.
- buffer_in[in_byte_position] |= bit_mask
- else:
- # Set bit to 0 at appropriate location.
- buffer_in[in_byte_position] &= ~bit_mask
- # Flip clock off base
- self._sclk.value = not self._polarity
- start_time = self._wait(start_time)
- # Handle read on trailing edge of clock.
- if self._phase: # Mode 1, 3
- self._mosi.value = bit_value
- if self._miso.value:
- # Set bit to 1 at appropriate location.
- buffer_in[in_byte_position] |= bit_mask
- else:
- # Set bit to 0 at appropriate location.
- buffer_in[in_byte_position] &= ~bit_mask
-
- # Return pins to base positions
- self._mosi.value = 0
- self._sclk.value = self._polarity
+ if self._check_lock():
+ start_time = monotonic()
+ for byte_position, _ in enumerate(buffer_out[out_start:out_end]):
+ for bit_position in range(self._bits):
+ bit_mask = 0x80 >> bit_position
+ bit_value = (
+ buffer_out[byte_position + out_start] & 0x80 >> bit_position
+ )
+ in_byte_position = byte_position + in_start
+ # Return clock to 0
+ self._sclk.value = self._polarity
+ start_time = self._wait(start_time)
+ # Handle read on leading edge of clock.
+ if not self._phase: # Mode 0, 2
+ self._mosi.value = bit_value
+ if self._miso.value:
+ # Set bit to 1 at appropriate location.
+ buffer_in[in_byte_position] |= bit_mask
+ else:
+ # Set bit to 0 at appropriate location.
+ buffer_in[in_byte_position] &= ~bit_mask
+ # Flip clock off base
+ self._sclk.value = not self._polarity
+ start_time = self._wait(start_time)
+ # Handle read on trailing edge of clock.
+ if self._phase: # Mode 1, 3
+ self._mosi.value = bit_value
+ if self._miso.value:
+ # Set bit to 1 at appropriate location.
+ buffer_in[in_byte_position] |= bit_mask
+ else:
+ # Set bit to 0 at appropriate location.
+ buffer_in[in_byte_position] &= ~bit_mask
+
+ # Return pins to base positions
+ self._mosi.value = 0
+ self._sclk.value = self._polarity
 
  # pylint: enable=too-many-branches