I work with a legacy project and on some entities one of the generics is named "DEFAULT". This gives the following error message:

Expected 'signal', 'constant', 'variable', '{identifier}', 'file', 'type', 'function', 'procedure', 'impure', 'pure' or 'package'vhdl ls

A minimal example to reproduce the behavior is the following:

library ieee; use ieee.std_logic_1164.all; entity test is generic ( g_this_is_fine : std_logic := '0'; default : std_logic := '0' -- this is bad ); port ( clk : in std_logic; reset : in std_logic ); end entity; architecture rtl of test is begin end architecture;

It does not matter if "default" is written in capital letters or not. As far as I know, there is no reserved keyword "default" in VHDL. Xilinx ISE also has no problem with it.
Could it be, that it is a keyword in Rust which leads to this error?

By the way: Kudos for creating and maintaining this project. I use it daily and it makes working with VHDL a charm!