BR instruction

Author: kddnewton

yjit/src/asm/arm64/inst/branch.rs

@@ -1,22 +1,39 @@
+/// Which operation to perform.
+enum Op {
+ /// Perform a BR instruction.
+ Br = 0b00,
+
+ /// Perform a RET instruction.
+ Ret = 0b10
+}
+
 /// The struct that represents an A64 branch instruction that can be encoded.
 ///
-/// RET
 /// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 /// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
-/// | 1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 |
-/// |   rn.............. rm.............. |
+/// | 1 1 0 1 0 1 1 0 0   1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 |
+/// | op... rn.............. rm.............. |
 /// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 ///
 pub struct Branch {
  /// The register holding the address to be branched to.
- rn: u8
+ rn: u8,
+
+ /// The operation to perform.
+ op: Op
 }
 
 impl Branch {
+ /// BR
+ /// https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/BR--Branch-to-Register-?lang=en
+ pub fn br(rn: u8) -> Self {
+ Self { rn, op: Op::Br }
+ }
+
  /// RET
  /// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/RET--Return-from-subroutine-?lang=en
  pub fn ret(rn: u8) -> Self {
- Self { rn }
+ Self { rn, op: Op::Ret }
  }
 }
 
@@ -29,7 +46,9 @@ impl From<Branch> for u32 {
  0
  | (0b11 << 30)
  | (FAMILY << 26)
- | (0b1001011111 << 16)
+ | (1 << 25)
+ | ((inst.op as u32) << 21)
+ | (0b11111 << 16)
  | ((inst.rn as u32) << 5)
  }
 }
@@ -46,17 +65,21 @@ impl From<Branch> for [u8; 4] {
 mod tests {
  use super::*;
 
+ #[test]
+ fn test_br() {
+ let result: u32 = Branch::br(0).into();
+ assert_eq!(0xd61f0000, result);
+ }
+
  #[test]
  fn test_ret() {
- let inst = Branch::ret(30);
- let result: u32 = inst.into();
+ let result: u32 = Branch::ret(30).into();
  assert_eq!(0xd65f03C0, result);
  }
 
  #[test]
  fn test_ret_rn() {
- let inst = Branch::ret(20);
- let result: u32 = inst.into();
+ let result: u32 = Branch::ret(20).into();
  assert_eq!(0xd65f0280, result);
  }
 }

yjit/src/asm/arm64/inst/mod.rs

@@ -14,7 +14,7 @@ use mov::Mov;
 use crate::asm::{CodeBlock, imm_num_bits};
 use super::opnd::*;
 
-/// ADD
+/// ADD - add rn and rm, put the result in rd, don't update flags
 pub fn add(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
  let bytes: [u8; 4] = match (rd, rn, rm) {
  (A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::Reg(rm)) => {
@@ -37,7 +37,7 @@ pub fn add(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
  cb.write_bytes(&bytes);
 }
 
-/// ADDS
+/// ADDS - add rn and rm, put the result in rd, update flags
 pub fn adds(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
  let bytes: [u8; 4] = match (rd, rn, rm) {
  (A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::Reg(rm)) => {
@@ -60,7 +60,17 @@ pub fn adds(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
  cb.write_bytes(&bytes);
 }
 
-/// LDUR
+/// BR - branch to a register
+pub fn br(cb: &mut CodeBlock, rn: A64Opnd) {
+ let bytes: [u8; 4] = match rn {
+ A64Opnd::Reg(rn) => Branch::br(rn.reg_no).into(),
+ _ => panic!("Invalid operand to br instruction."),
+ };
+
+ cb.write_bytes(&bytes);
+}
+
+/// LDUR - load a memory address into a register
 pub fn ldur(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) {
  let bytes: [u8; 4] = match (rt, rn) {
  (A64Opnd::Reg(rt), A64Opnd::Mem(rn)) => {
@@ -75,7 +85,7 @@ pub fn ldur(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) {
  cb.write_bytes(&bytes);
 }
 
-/// MOVK
+/// MOVK - move a 16 bit immediate into a register, keep the other bits in place
 pub fn movk(cb: &mut CodeBlock, rd: A64Opnd, imm16: A64Opnd, shift: u8) {
  let bytes: [u8; 4] = match (rd, imm16) {
  (A64Opnd::Reg(rd), A64Opnd::UImm(imm16)) => {
@@ -89,7 +99,7 @@ pub fn movk(cb: &mut CodeBlock, rd: A64Opnd, imm16: A64Opnd, shift: u8) {
  cb.write_bytes(&bytes);
 }
 
-/// MOVZ
+/// MOVZ - move a 16 bit immediate into a register, zero the other bits
 pub fn movz(cb: &mut CodeBlock, rd: A64Opnd, imm16: A64Opnd, shift: u8) {
  let bytes: [u8; 4] = match (rd, imm16) {
  (A64Opnd::Reg(rd), A64Opnd::UImm(imm16)) => {
@@ -103,7 +113,7 @@ pub fn movz(cb: &mut CodeBlock, rd: A64Opnd, imm16: A64Opnd, shift: u8) {
  cb.write_bytes(&bytes);
 }
 
-/// SUB
+/// SUB - subtract rm from rn, put the result in rd, don't update flags
 pub fn sub(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
  let bytes: [u8; 4] = match (rd, rn, rm) {
  (A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::Reg(rm)) => {
@@ -126,7 +136,7 @@ pub fn sub(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
  cb.write_bytes(&bytes);
 }
 
-/// SUBS
+/// SUBS - subtract rm from rn, put the result in rd, update flags
 pub fn subs(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
  let bytes: [u8; 4] = match (rd, rn, rm) {
  (A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::Reg(rm)) => {
@@ -149,12 +159,12 @@ pub fn subs(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
  cb.write_bytes(&bytes);
 }
 
-/// RET
+/// RET - unconditionally return to a location in a register, defaults to X30
 pub fn ret(cb: &mut CodeBlock, rn: A64Opnd) {
  let bytes: [u8; 4] = match rn {
  A64Opnd::None => Branch::ret(30).into(),
  A64Opnd::Reg(reg) => Branch::ret(reg.reg_no).into(),
- _ => panic!("Invalid operand for RET")
+ _ => panic!("Invalid operand to ret instruction.")
  };
 
  cb.write_bytes(&bytes);
@@ -191,6 +201,11 @@ mod tests {
  check_bytes("201c00b1", |cb| adds(cb, X0, X1, A64Opnd::new_uimm(7)));
  }
 
+ #[test]
+ fn test_br() {
+ check_bytes("80021fd6", |cb| br(cb, X20));
+ }
+
  #[test]
  fn test_ldur() {
  check_bytes("20b047f8", |cb| ldur(cb, X0, A64Opnd::new_mem(X1, 123)));