[PIR] Change log level of op verify (#73268)

Author: zyfncg

paddle/fluid/pir/dialect/distributed/ir/dist_op.cc

@@ -43,9 +43,9 @@ void VerifyOpArgNum(const pir::OpBase* op,
  size_t num_outputs,
  size_t op_dist_attr_ninputs,
  size_t op_dist_attr_noutputs) {
- VLOG(4) << "Start Verifying inputs, outputs and attributes for: "
+ VLOG(6) << "Start Verifying inputs, outputs and attributes for: "
  << T::name();
- VLOG(4) << "Verifying inputs num:";
+ VLOG(6) << "Verifying inputs num:";
  {
  auto input_size = op->num_operands();
  PADDLE_ENFORCE_EQ(input_size,
@@ -57,7 +57,7 @@ void VerifyOpArgNum(const pir::OpBase* op,
  input_size));
  }
 
- VLOG(4) << "Verifying outputs num:";
+ VLOG(6) << "Verifying outputs num:";
  {
  auto output_size = op->num_results();
  PADDLE_ENFORCE_EQ(output_size,
@@ -69,7 +69,7 @@ void VerifyOpArgNum(const pir::OpBase* op,
  output_size));
  }
 
- VLOG(4) << "Verifying attributes:";
+ VLOG(6) << "Verifying attributes:";
  {
  auto& attributes = op->attributes();
  PADDLE_ENFORCE_EQ(
@@ -87,7 +87,7 @@ void VerifyOpArgNum(const pir::OpBase* op,
  "Type of attribute: op_dist_attr is not right."));
  }
 
- VLOG(4) << "Verifying op dist attrs:";
+ VLOG(6) << "Verifying op dist attrs:";
  {
  auto op_dist_attr =
  op->attribute<paddle::dialect::OperationDistAttribute>("op_dist_attr");
@@ -103,7 +103,7 @@ void VerifyOpArgNum(const pir::OpBase* op,
  "The op_dist_attr output size must be equal to %u.",
  op_dist_attr_noutputs));
  }
- VLOG(4) << "End Verifying inputs, outputs and attributes num for: "
+ VLOG(6) << "End Verifying inputs, outputs and attributes num for: "
  << T::name();
 }
 
@@ -124,7 +124,7 @@ void ShardTensorOp::VerifySig() {
  "Mismatched output type. ShardTensorOp requires "
  "'DistDenseTensorType' for output."));
 
- VLOG(4) << "End Verifying for: ShardTensorOp.";
+ VLOG(6) << "End Verifying for: ShardTensorOp.";
 }
 
 void ShardTensorOp::Build(pir::Builder& builder,

paddle/fluid/pir/dialect/op_generator/op_verify_gen.py

@@ -15,23 +15,23 @@
 # verify
 OP_VERIFY_TEMPLATE = """
 void {op_name}::VerifySig() {{
- VLOG(4) << "Start Verifying inputs, outputs and attributes for: {op_name}.";
- VLOG(4) << "Verifying inputs:";
+ VLOG(8) << "Start Verifying inputs, outputs and attributes for: {op_name}.";
+ VLOG(8) << "Verifying inputs:";
  {{
  auto input_size = num_operands();
  PADDLE_ENFORCE_EQ(input_size , {inputs_size}, common::errors::InvalidArgument(
  "The size of inputs must be equal to {inputs_size}."));{inputs_type_check}
  }}
- VLOG(4) << "Verifying attributes:";
+ VLOG(8) << "Verifying attributes:";
  {{{attributes_check}
  }}
- VLOG(4) << "Verifying outputs:";
+ VLOG(8) << "Verifying outputs:";
  {{
  auto output_size = num_results();
  PADDLE_ENFORCE_EQ(output_size, {outputs_size}, common::errors::InvalidArgument(
  "The size of outputs must be equal to {outputs_size}."));{outputs_type_check}
  }}
- VLOG(4) << "End Verifying for: {op_name}.";
+ VLOG(8) << "End Verifying for: {op_name}.";
 }}
 """
 

paddle/fluid/pir/dialect/operator/ir/control_flow_op.cc

@@ -214,7 +214,7 @@ void IfOp::Print(pir::IrPrinter &printer) {
 }
 
 void IfOp::VerifySig() {
- VLOG(4) << "Start Verifying inputs, outputs and attributes for: IfOp.";
+ VLOG(6) << "Start Verifying inputs, outputs and attributes for: IfOp.";
  auto input_size = num_operands();
  PADDLE_ENFORCE_EQ(
  input_size,
@@ -243,8 +243,8 @@ void IfOp::VerifySig() {
 }
 
 void IfOp::VerifyRegion() {
- VLOG(4) << "Start Verifying sub regions for: IfOp.";
- VLOG(4) << "Start Verifying true branch.";
+ VLOG(6) << "Start Verifying sub regions for: IfOp.";
+ VLOG(6) << "Start Verifying true branch.";
  PADDLE_ENFORCE_EQ(
  (*this)->region(0).size(),
  1u,
@@ -267,7 +267,7 @@ void IfOp::VerifyRegion() {
  common::errors::PreconditionNotMet(
  "The size of last of true block op's input must be "
  "equal to IfOp's outputs num."));
- VLOG(4) << "Start Verifying false branch.";
+ VLOG(6) << "Start Verifying false branch.";
  PADDLE_ENFORCE_EQ((*this)->region(1).size(),
  1u,
  common::errors::PreconditionNotMet(
@@ -545,7 +545,7 @@ void WhileOp::Print(pir::IrPrinter &printer) {
 }
 
 void WhileOp::VerifySig() {
- VLOG(4) << "Start Verifying inputs, outputs and attributes for: WhileOp.";
+ VLOG(6) << "Start Verifying inputs, outputs and attributes for: WhileOp.";
  auto input_size = num_operands();
  PADDLE_ENFORCE_GE(
  input_size,
@@ -1153,8 +1153,8 @@ OpInfoTuple AssertOp::GetOpInfo() {
 }
 
 void AssertOp::VerifySig() {
- VLOG(4) << "Start Verifying inputs, outputs and attributes for: AssertOp.";
- VLOG(4) << "Verifying inputs:";
+ VLOG(6) << "Start Verifying inputs, outputs and attributes for: AssertOp.";
+ VLOG(6) << "Verifying inputs:";
  {
  auto input_size = num_operands();
  PADDLE_ENFORCE_EQ(
@@ -1199,7 +1199,7 @@ void AssertOp::VerifySig() {
  "Type validation failed for the 1th input."));
  }
  }
- VLOG(4) << "Verifying attributes:";
+ VLOG(6) << "Verifying attributes:";
  {
  auto &attributes = this->attributes();
  PADDLE_ENFORCE_GT(
@@ -1212,7 +1212,7 @@ void AssertOp::VerifySig() {
  common::errors::InvalidArgument(
  "Type of attribute: summarize is not pir::Int64Attribute."));
  }
- VLOG(4) << "Verifying outputs:";
+ VLOG(6) << "Verifying outputs:";
  {
  auto output_size = num_results();
  PADDLE_ENFORCE_EQ(
@@ -1222,7 +1222,7 @@ void AssertOp::VerifySig() {
  "The size %d of outputs must be equal to 0.", output_size));
  // Outputs num is 0, not need to check outputs type.
  }
- VLOG(4) << "End Verifying for: AssertOp.";
+ VLOG(6) << "End Verifying for: AssertOp.";
 }
 
 void SelectInputOp::VerifySig() {