update

Author: MaorAssayag

Hardware Design Lab for Computer Engineering/Pspice Design/PROJ.DSN

@@ -0,0 +1,23 @@
+.ALIASES
+R_R_var R_var(1=N15705 2=VCC_REF ) CN @PROJ.SCHEMATIC1(sch_1):INS14315@ANALOG.R_var.Normal(chips)
+X_U1B U1B(+=N19455 -=N15705 V+=VCC_REF V-=0 OUT=N28984 ) CN @PROJ.SCHEMATIC1(sch_1):INS14730@EVAL.LM324.Normal(chips)
+V_V1 V1(+=VCC_REF -=0 ) CN @PROJ.SCHEMATIC1(sch_1):INS14938@SOURCE.VDC.Normal(chips)
+R_R6 R6(1=0 2=N15705 ) CN @PROJ.SCHEMATIC1(sch_1):INS15115@ANALOG.R.Normal(chips)
+X_U2B U2B(+=N15797 -=N15705 V+=VCC_REF V-=0 OUT=N28868 ) CN @PROJ.SCHEMATIC1(sch_1):INS15565@EVAL.LM324.Normal(chips)
+R_LDR1 LDR1(1=N19455 2=0 ) CN @PROJ.SCHEMATIC1(sch_1):INS22502@ANALOG.R_var.Normal(chips)
+R_R7 R7(1=VCC_REF 2=N19455 ) CN @PROJ.SCHEMATIC1(sch_1):INS22563@ANALOG.R.Normal(chips)
+R_LDR2 LDR2(1=N15797 2=0 ) CN @PROJ.SCHEMATIC1(sch_1):INS22676@ANALOG.R_var.Normal(chips)
+R_R8 R8(1=VCC_REF 2=N15797 ) CN @PROJ.SCHEMATIC1(sch_1):INS22732@ANALOG.R.Normal(chips)
+X_U3A U3A(A=N28984 B=N28984 Y=N29410 VCC=$G_DPWR GND=$G_DGND ) CN
++@PROJ.SCHEMATIC1(sch_1):INS29013@7400.7432.Normal(chips)
+X_U3B U3B(A=N28868 B=N28868 Y=N29414 VCC=$G_DPWR GND=$G_DGND ) CN
++@PROJ.SCHEMATIC1(sch_1):INS29054@7400.7432.Normal(chips)
+X_Q1 Q1(C=N29671 B=N292801 E=0 ) CN @PROJ.SCHEMATIC1(sch_1):INS29268@BJN.2N2222A.Normal(chips)
+X_Q2 Q2(C=N29629 B=N293241 E=0 ) CN @PROJ.SCHEMATIC1(sch_1):INS29312@BJN.2N2222A.Normal(chips)
+R_R9 R9(1=N29410 2=N292801 ) CN @PROJ.SCHEMATIC1(sch_1):INS29352@ANALOG.R.Normal(chips)
+R_R10 R10(1=N29414 2=N293241 ) CN @PROJ.SCHEMATIC1(sch_1):INS29388@ANALOG.R.Normal(chips)
+R_R11 R11(1=N29671 2=VCC_REF ) CN @PROJ.SCHEMATIC1(sch_1):INS29561@ANALOG.R.Normal(chips)
+R_R12 R12(1=N29629 2=VCC_REF ) CN @PROJ.SCHEMATIC1(sch_1):INS29607@ANALOG.R.Normal(chips)
+R_R13 R13(1=N29629 2=N29671 ) CN @PROJ.SCHEMATIC1(sch_1):INS29715@ANALOG.R.Normal(chips)
+_ _(VCC_ref=VCC_REF)
+.ENDALIASES

Hardware Design Lab for Computer Engineering/Pspice Design/PROJ.DSNlck

@@ -0,0 +1,23 @@
+* source PROJ
+R_R_var N15705 VCC_REF {1.5k*0.5+.001}
+X_U1B N19455 N15705 VCC_REF 0 N28984 LM324
+V_V1 VCC_REF 0 5
+R_R6 0 N15705 0.5k TC=0,0 
+X_U2B N15797 N15705 VCC_REF 0 N28868 LM324
+R_LDR1 N19455 0 {2k*0.5+.001}
+R_R7 VCC_REF N19455 1k TC=0,0 
+R_LDR2 N15797 0 {200*0.5+.001}
+R_R8 VCC_REF N15797 1k TC=0,0 
+X_U3A N28984 N28984 N29410 $G_DPWR $G_DGND 7432 PARAMS:
++ IO_LEVEL=0 MNTYMXDLY=0
+X_U3B N28868 N28868 N29414 $G_DPWR $G_DGND 7432 PARAMS:
++ IO_LEVEL=0 MNTYMXDLY=0
+X_Q1 N29671 N292801 0 awb2n2222a PARAMS: 
++ 
+X_Q2 N29629 N293241 0 awb2n2222a PARAMS: 
++ 
+R_R9 N29410 N292801 1k TC=0,0 
+R_R10 N29414 N293241 1k TC=0,0 
+R_R11 N29671 VCC_REF 100 TC=0,0 
+R_R12 N29629 VCC_REF 100 TC=0,0 
+R_R13 N29629 N29671 100 TC=0,0