Revert "[SPIR-V] Implement SPV_KHR_float_controls2 (#146941)"

This reverts commit ebcf025.

Author: jsji

llvm/docs/SPIRVUsage.rst

@@ -232,7 +232,7 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
  * - ``SPV_INTEL_int4``
  - Adds support for 4-bit integer type, and allow this type to be used in cooperative matrices.
  * - ``SPV_KHR_float_controls2``
- - Adds execution modes and decorations to control floating-point computations in both kernels and shaders. It can be used on whole modules and individual instructions.
+ - Adds ability to specify the floating-point environment in shaders. It can be used on whole modules and individual instructions.
 
 SPIR-V representation in LLVM IR
 ================================
@@ -589,31 +589,3 @@ Group and Subgroup Operations
 For workgroup and subgroup operations, LLVM uses function calls to represent SPIR-V's
 group-based instructions. These builtins facilitate group synchronization, data sharing,
 and collective operations essential for efficient parallel computation.
-
-SPIR-V Instructions Mapped to LLVM Metadata
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-Some SPIR-V instructions don't have a direct equivalent in the LLVM IR language. To
-address this, the SPIR-V Target uses different specific LLVM named metadata to convey
-the necessary information. The SPIR-V specification allows multiple module-scope
-instructions, where as LLVM named metadata must be unique. Therefore, the encoding of
-such instructions has the following format:
-
-.. code-block:: llvm
-
- !spirv.<OpCodeName> = !{!<InstructionMetadata1>, !<InstructionMetadata2>, ..}
- !<InstructionMetadata1> = !{<Operand1>, <Operand2>, ..}
- !<InstructionMetadata2> = !{<Operand1>, <Operand2>, ..}
-
-Below, you will find the mappings between SPIR-V instruction and their corresponding
-LLVM IR representations.
-
-+--------------------+---------------------------------------------------------+
-| SPIR-V instruction | LLVM IR |
-+====================+=========================================================+
-| OpExecutionMode | .. code-block:: llvm |
-| | |
-| | !spirv.ExecutionMode = !{!0} |
-| | !0 = !{void @worker, i32 30, i32 262149} |
-| | ; Set execution mode with id 30 (VecTypeHint) and |
-| | ; literal `262149` operand. |
-+--------------------+---------------------------------------------------------+

llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp

@@ -81,7 +81,6 @@ class SPIRVAsmPrinter : public AsmPrinter {
  void outputExecutionMode(const Module &M);
  void outputAnnotations(const Module &M);
  void outputModuleSections();
- void outputFPFastMathDefaultInfo();
  bool isHidden() {
  return MF->getFunction()
  .getFnAttribute(SPIRV_BACKEND_SERVICE_FUN_NAME)
@@ -499,27 +498,11 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
  NamedMDNode *Node = M.getNamedMetadata("spirv.ExecutionMode");
  if (Node) {
  for (unsigned i = 0; i < Node->getNumOperands(); i++) {
- // If SPV_KHR_float_controls2 is enabled and we find any of
- // FPFastMathDefault, ContractionOff or SignedZeroInfNanPreserve execution
- // modes, skip it, it'll be done somewhere else.
- if (ST->canUseExtension(SPIRV::Extension::SPV_KHR_float_controls2)) {
- const auto EM =
- cast<ConstantInt>(
- cast<ConstantAsMetadata>((Node->getOperand(i))->getOperand(1))
- ->getValue())
- ->getZExtValue();
- if (EM == SPIRV::ExecutionMode::FPFastMathDefault ||
- EM == SPIRV::ExecutionMode::ContractionOff ||
- EM == SPIRV::ExecutionMode::SignedZeroInfNanPreserve)
- continue;
- }
-
  MCInst Inst;
  Inst.setOpcode(SPIRV::OpExecutionMode);
  addOpsFromMDNode(cast<MDNode>(Node->getOperand(i)), Inst, MAI);
  outputMCInst(Inst);
  }
- outputFPFastMathDefaultInfo();
  }
  for (auto FI = M.begin(), E = M.end(); FI != E; ++FI) {
  const Function &F = *FI;
@@ -569,84 +552,12 @@ void SPIRVAsmPrinter::outputExecutionMode(const Module &M) {
  }
  if (ST->isKernel() && !M.getNamedMetadata("spirv.ExecutionMode") &&
  !M.getNamedMetadata("opencl.enable.FP_CONTRACT")) {
- if (ST->canUseExtension(SPIRV::Extension::SPV_KHR_float_controls2)) {
- // When SPV_KHR_float_controls2 is enabled, ContractionOff is
- // deprecated. We need to use FPFastMathDefault with the appropriate
- // flags instead. Since FPFastMathDefault takes a target type, we need
- // to emit it for each floating-point type that exists in the module
- // to match the effect of ContractionOff. As of now, there are 3 FP
- // types: fp16, fp32 and fp64.
-
- // We only end up here because there is no "spirv.ExecutionMode"
- // metadata, so that means no FPFastMathDefault. Therefore, we only
- // need to make sure AllowContract is set to 0, as the rest of flags.
- // We still need to emit the OpExecutionMode instruction, otherwise
- // it's up to the client API to define the flags. Therefore, we need
- // to find the constant with 0 value.
-
- // Collect the SPIRVTypes for fp16, fp32, and fp64 and the constant of
- // type int32 with 0 value to represent the FP Fast Math Mode.
- std::vector<const MachineInstr *> SPIRVFloatTypes;
- const MachineInstr *ConstZero = nullptr;
- for (const MachineInstr *MI :
- MAI->getMSInstrs(SPIRV::MB_TypeConstVars)) {
- // Skip if the instruction is not OpTypeFloat or OpConstant.
- unsigned OpCode = MI->getOpcode();
- if (OpCode != SPIRV::OpTypeFloat && OpCode != SPIRV::OpConstantNull)
- continue;
-
- // Collect the SPIRV type if it's a float.
- if (OpCode == SPIRV::OpTypeFloat) {
- // Skip if the target type is not fp16, fp32, fp64.
- const unsigned OpTypeFloatSize = MI->getOperand(1).getImm();
- if (OpTypeFloatSize != 16 && OpTypeFloatSize != 32 &&
- OpTypeFloatSize != 64) {
- continue;
- }
- SPIRVFloatTypes.push_back(MI);
- } else {
- // Check if the constant is int32, if not skip it.
- const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
- MachineInstr *TypeMI = MRI.getVRegDef(MI->getOperand(1).getReg());
- if (!TypeMI || TypeMI->getOperand(1).getImm() != 32)
- continue;
-
- ConstZero = MI;
- }
- }
-
- // When SPV_KHR_float_controls2 is enabled, ContractionOff is
- // deprecated. We need to use FPFastMathDefault with the appropriate
- // flags instead. Since FPFastMathDefault takes a target type, we need
- // to emit it for each floating-point type that exists in the module
- // to match the effect of ContractionOff. As of now, there are 3 FP
- // types: fp16, fp32 and fp64.
- for (const MachineInstr *MI : SPIRVFloatTypes) {
- MCInst Inst;
- Inst.setOpcode(SPIRV::OpExecutionModeId);
- Inst.addOperand(MCOperand::createReg(FReg));
- unsigned EM =
- static_cast<unsigned>(SPIRV::ExecutionMode::FPFastMathDefault);
- Inst.addOperand(MCOperand::createImm(EM));
- const MachineFunction *MF = MI->getMF();
- MCRegister TypeReg =
- MAI->getRegisterAlias(MF, MI->getOperand(0).getReg());
- Inst.addOperand(MCOperand::createReg(TypeReg));
- assert(ConstZero && "There should be a constant zero.");
- MCRegister ConstReg = MAI->getRegisterAlias(
- ConstZero->getMF(), ConstZero->getOperand(0).getReg());
- Inst.addOperand(MCOperand::createReg(ConstReg));
- outputMCInst(Inst);
- }
- } else {
- MCInst Inst;
- Inst.setOpcode(SPIRV::OpExecutionMode);
- Inst.addOperand(MCOperand::createReg(FReg));
- unsigned EM =
- static_cast<unsigned>(SPIRV::ExecutionMode::ContractionOff);
- Inst.addOperand(MCOperand::createImm(EM));
- outputMCInst(Inst);
- }
+ MCInst Inst;
+ Inst.setOpcode(SPIRV::OpExecutionMode);
+ Inst.addOperand(MCOperand::createReg(FReg));
+ unsigned EM = static_cast<unsigned>(SPIRV::ExecutionMode::ContractionOff);
+ Inst.addOperand(MCOperand::createImm(EM));
+ outputMCInst(Inst);
  }
  }
 }
@@ -695,101 +606,6 @@ void SPIRVAsmPrinter::outputAnnotations(const Module &M) {
  }
 }
 
-void SPIRVAsmPrinter::outputFPFastMathDefaultInfo() {
- // Collect the SPIRVTypes that are OpTypeFloat and the constants of type
- // int32, that might be used as FP Fast Math Mode.
- std::vector<const MachineInstr *> SPIRVFloatTypes;
- // Hashtable to associate immediate values with the constant holding them.
- std::unordered_map<int, const MachineInstr *> ConstMap;
- for (const MachineInstr *MI : MAI->getMSInstrs(SPIRV::MB_TypeConstVars)) {
- // Skip if the instruction is not OpTypeFloat or OpConstant.
- unsigned OpCode = MI->getOpcode();
- if (OpCode != SPIRV::OpTypeFloat && OpCode != SPIRV::OpConstantI &&
- OpCode != SPIRV::OpConstantNull)
- continue;
-
- // Collect the SPIRV type if it's a float.
- if (OpCode == SPIRV::OpTypeFloat) {
- SPIRVFloatTypes.push_back(MI);
- } else {
- // Check if the constant is int32, if not skip it.
- const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
- MachineInstr *TypeMI = MRI.getVRegDef(MI->getOperand(1).getReg());
- if (!TypeMI || TypeMI->getOpcode() != SPIRV::OpTypeInt ||
- TypeMI->getOperand(1).getImm() != 32)
- continue;
-
- if (OpCode == SPIRV::OpConstantI)
- ConstMap[MI->getOperand(2).getImm()] = MI;
- else
- ConstMap[0] = MI;
- }
- }
-
- for (const auto &[Func, FPFastMathDefaultInfoVec] :
- MAI->FPFastMathDefaultInfoMap) {
- if (FPFastMathDefaultInfoVec.empty())
- continue;
-
- for (const MachineInstr *MI : SPIRVFloatTypes) {
- unsigned OpTypeFloatSize = MI->getOperand(1).getImm();
- unsigned Index = SPIRV::FPFastMathDefaultInfoVector::
- computeFPFastMathDefaultInfoVecIndex(OpTypeFloatSize);
- assert(Index < FPFastMathDefaultInfoVec.size() &&
- "Index out of bounds for FPFastMathDefaultInfoVec");
- const auto &FPFastMathDefaultInfo = FPFastMathDefaultInfoVec[Index];
- assert(FPFastMathDefaultInfo.Ty &&
- "Expected target type for FPFastMathDefaultInfo");
- assert(FPFastMathDefaultInfo.Ty->getScalarSizeInBits() ==
- OpTypeFloatSize &&
- "Mismatched float type size");
- MCInst Inst;
- Inst.setOpcode(SPIRV::OpExecutionModeId);
- MCRegister FuncReg = MAI->getFuncReg(Func);
- assert(FuncReg.isValid());
- Inst.addOperand(MCOperand::createReg(FuncReg));
- Inst.addOperand(
- MCOperand::createImm(SPIRV::ExecutionMode::FPFastMathDefault));
- MCRegister TypeReg =
- MAI->getRegisterAlias(MI->getMF(), MI->getOperand(0).getReg());
- Inst.addOperand(MCOperand::createReg(TypeReg));
- unsigned Flags = FPFastMathDefaultInfo.FastMathFlags;
- if (FPFastMathDefaultInfo.ContractionOff &&
- (Flags & SPIRV::FPFastMathMode::AllowContract))
- report_fatal_error(
- "Conflicting FPFastMathFlags: ContractionOff and AllowContract");
-
- if (FPFastMathDefaultInfo.SignedZeroInfNanPreserve &&
- !(Flags &
- (SPIRV::FPFastMathMode::NotNaN | SPIRV::FPFastMathMode::NotInf |
- SPIRV::FPFastMathMode::NSZ))) {
- if (FPFastMathDefaultInfo.FPFastMathDefault)
- report_fatal_error("Conflicting FPFastMathFlags: "
- "SignedZeroInfNanPreserve but at least one of "
- "NotNaN/NotInf/NSZ is enabled.");
- }
-
- // Don't emit if none of the execution modes was used.
- if (Flags == SPIRV::FPFastMathMode::None &&
- !FPFastMathDefaultInfo.ContractionOff &&
- !FPFastMathDefaultInfo.SignedZeroInfNanPreserve &&
- !FPFastMathDefaultInfo.FPFastMathDefault)
- continue;
-
- // Retrieve the constant instruction for the immediate value.
- auto It = ConstMap.find(Flags);
- if (It == ConstMap.end())
- report_fatal_error("Expected constant instruction for FP Fast Math "
- "Mode operand of FPFastMathDefault execution mode.");
- const MachineInstr *ConstMI = It->second;
- MCRegister ConstReg = MAI->getRegisterAlias(
- ConstMI->getMF(), ConstMI->getOperand(0).getReg());
- Inst.addOperand(MCOperand::createReg(ConstReg));
- outputMCInst(Inst);
- }
- }
-}
-
 void SPIRVAsmPrinter::outputModuleSections() {
  const Module *M = MMI->getModule();
  // Get the global subtarget to output module-level info.
@@ -798,17 +614,15 @@ void SPIRVAsmPrinter::outputModuleSections() {
  MAI = &SPIRVModuleAnalysis::MAI;
  assert(ST && TII && MAI && M && "Module analysis is required");
  // Output instructions according to the Logical Layout of a Module:
- // 1,2. All OpCapability instructions, then optional OpExtension
- // instructions.
+ // 1,2. All OpCapability instructions, then optional OpExtension instructions.
  outputGlobalRequirements();
  // 3. Optional OpExtInstImport instructions.
  outputOpExtInstImports(*M);
  // 4. The single required OpMemoryModel instruction.
  outputOpMemoryModel();
  // 5. All entry point declarations, using OpEntryPoint.
  outputEntryPoints();
- // 6. Execution-mode declarations, using OpExecutionMode or
- // OpExecutionModeId.
+ // 6. Execution-mode declarations, using OpExecutionMode or OpExecutionModeId.
  outputExecutionMode(*M);
  // 7a. Debug: all OpString, OpSourceExtension, OpSource, and
  // OpSourceContinued, without forward references.

llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp

@@ -1162,24 +1162,11 @@ static unsigned getNumSizeComponents(SPIRVType *imgType) {
 
 static bool generateExtInst(const SPIRV::IncomingCall *Call,
  MachineIRBuilder &MIRBuilder,
- SPIRVGlobalRegistry *GR, const CallBase &CB) {
+ SPIRVGlobalRegistry *GR) {
  // Lookup the extended instruction number in the TableGen records.
  const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
  uint32_t Number =
  SPIRV::lookupExtendedBuiltin(Builtin->Name, Builtin->Set)->Number;
- // fmin_common and fmax_common are now deprecated, and we should use fmin and
- // fmax with NotInf and NotNaN flags instead. Keep original number to add
- // later the NoNans and NoInfs flags.
- uint32_t OrigNumber = Number;
- const SPIRVSubtarget &ST =
- cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
- if (ST.canUseExtension(SPIRV::Extension::SPV_KHR_float_controls2) &&
- (Number == SPIRV::OpenCLExtInst::fmin_common ||
- Number == SPIRV::OpenCLExtInst::fmax_common)) {
- Number = (Number == SPIRV::OpenCLExtInst::fmin_common)
- ? SPIRV::OpenCLExtInst::fmin
- : SPIRV::OpenCLExtInst::fmax;
- }
 
  // Build extended instruction.
  auto MIB =
@@ -1191,13 +1178,6 @@ static bool generateExtInst(const SPIRV::IncomingCall *Call,
 
  for (auto Argument : Call->Arguments)
  MIB.addUse(Argument);
- MIB.getInstr()->copyIRFlags(CB);
- if (OrigNumber == SPIRV::OpenCLExtInst::fmin_common ||
- OrigNumber == SPIRV::OpenCLExtInst::fmax_common) {
- // Add NoNans and NoInfs flags to fmin/fmax instruction.
- MIB.getInstr()->setFlag(MachineInstr::MIFlag::FmNoNans);
- MIB.getInstr()->setFlag(MachineInstr::MIFlag::FmNoInfs);
- }
  return true;
 }
 
@@ -2909,7 +2889,7 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
  MachineIRBuilder &MIRBuilder,
  const Register OrigRet, const Type *OrigRetTy,
  const SmallVectorImpl<Register> &Args,
- SPIRVGlobalRegistry *GR, const CallBase &CB) {
+ SPIRVGlobalRegistry *GR) {
  LLVM_DEBUG(dbgs() << "Lowering builtin call: " << DemangledCall << "\n");
 
  // Lookup the builtin in the TableGen records.
@@ -2932,7 +2912,7 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
  // Match the builtin with implementation based on the grouping.
  switch (Call->Builtin->Group) {
  case SPIRV::Extended:
- return generateExtInst(Call.get(), MIRBuilder, GR, CB);
+ return generateExtInst(Call.get(), MIRBuilder, GR);
  case SPIRV::Relational:
  return generateRelationalInst(Call.get(), MIRBuilder, GR);
  case SPIRV::Group:

llvm/lib/Target/SPIRV/SPIRVBuiltins.h

@@ -39,7 +39,7 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
  MachineIRBuilder &MIRBuilder,
  const Register OrigRet, const Type *OrigRetTy,
  const SmallVectorImpl<Register> &Args,
- SPIRVGlobalRegistry *GR, const CallBase &CB);
+ SPIRVGlobalRegistry *GR);
 
 /// Helper function for finding a builtin function attributes
 /// by a demangled function name. Defined in SPIRVBuiltins.cpp.

llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp

@@ -641,9 +641,9 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
  GR->getPointerSize()));
  }
  }
- if (auto Res = SPIRV::lowerBuiltin(
- DemangledName, ST->getPreferredInstructionSet(), MIRBuilder,
- ResVReg, OrigRetTy, ArgVRegs, GR, *Info.CB))
+ if (auto Res =
+ SPIRV::lowerBuiltin(DemangledName, ST->getPreferredInstructionSet(),
+  MIRBuilder, ResVReg, OrigRetTy, ArgVRegs, GR))
  return *Res;
  }