diff options
| author | Ling Pei Lee <pei.lee.ling@intel.com> | 2021-11-11 17:53:18 +0800 |
|---|---|---|
| committer | Philip Cox <philip.cox@canonical.com> | 2022-11-14 14:16:06 -0500 |
| commit | dffd6860af48713545edcefb07f1e81f4d24b9a5 (patch) | |
| tree | dcf2c10cadfa364bd9b0aa10800ed7ff8ca234c1 | |
| parent | da0ba78be8c50b4f6a1c7986777183858d827d10 (diff) | |
stmmac: intel: Update PTP clock rate from 200MHz to 204.86MHz
BugLink: https://bugs.launchpad.net/bugs/1982282 Current Intel AlderLake-S and TigerLake platform has an output of ~976ms interval when probed on 1 Pulse-per-Second(PPS) hardware pin. After checking with hardware team, the correct PTP clock frequency should be 204.8MHz instead of 200MHz. Signed-off-by: Wong Vee Khee <vee.khee.wong@linux.intel.com> Signed-off-by: Ling Pei Lee <pei.lee.ling@intel.com> (picked from https://github.com/intel/linux-intel-quilt/tree/lts-v5.15.36-linux-220520T033542Z-1/patches/0031-stmmac-intel-Update-PTP-clock-rate-from-200MHz-to-20.patch) Signed-off-by: Philip Cox <philip.cox@canonical.com>
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index bed53d7dee2b..6c4bf980678f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -757,7 +757,7 @@ static int tgl_common_data(struct pci_dev *pdev, { plat->rx_queues_to_use = 6; plat->tx_queues_to_use = 4; - plat->clk_ptp_rate = 200000000; + plat->clk_ptp_rate = 204800000; plat->speed_mode_2500 = intel_speed_mode_2500; plat->safety_feat_cfg->tsoee = 1; |