By using this simulator for learning verilog hdl purpose, I found an problem in this simulator what make hdl code elements not portable, and I have to hardcode the verilog compile path:

Here is review:

1 Make an folder and file tree like this:

bug_review/ ├── main.dig ├── test.vh └── verilog_src └── test.v 

2 fill the files:
2.1 test.v:

module test ( input [1:0]	a, output [1:0]	b ); `include "../test.vh" assign b = header_param & a; endmodule

2.2 test.vh:

parameter header_param = 2'b01;

2.3 run the Digital and open the main.dig, and add the external verilog code file component like this :

When I check the code, it show the error:

[AWT-EventQueue-0] INFO de.neemann.gui.ErrorMessage - error message: Check Result: [AWT-EventQueue-0] INFO de.neemann.gui.ErrorMessage - throwable error cause java.io.IOException: Application exit status was not 0 but 2: test.v:7: Include file ../test.vh not found test.v:6: syntax error I give up. 

It seems the iverilog could not found the file what should be included. So I have to hardcode the include path in Iverilog Options : "-I/upper_folder/bug_review/".
And if I want to add verilog sub component, although they save in same folder, I have to hardcode the path options too: "-y/upper_folder/bug_review/verilog_src/". That's why I think project is not portable

So I read the source code, and I find the 2 same code in
ApplicationIVerilog.start(String label, String code, PortDefinition inputs, PortDefinition outputs, File root) and
ApplicationIVerilog.checkCode(String label, String code, PortDefinition inputs, PortDefinition outputs, File root)
in Digital/src/main/java/de/neemann/digital/core/extern/ApplicationIVerilog.java made the problem:

ProcessStarter.start(file.getParentFile(), new Options() .add(iverilog) .add("-tvvp") .add("-o") .add(testOutputName) .add(attr, Keys.IVERILOG_OPTIONS) .add(file.getName()) .getArray() )

By reading code, I know the working directory where build the Verilog source code is in /some_temp_path/ because we should proccess the code before Iverilog build(the createVerilogFile()) , instead of source path : /upper_path/bug_review/verilog_src
So that's why Iverilog compiler cannot found the "../test.vh": It work in /some_temp_path/ and only one source code file test.v copied there.That's why the problem I got.
I think the solution of this problem is inject the include and path before compile:

ProcessStarter.start(file.getParentFile(), new Options() .add(iverilog) .add("-tvvp") .add("-o") .add(testOutputName) //if the user provide header valid, use them first. .add(attr, Keys.IVERILOG_OPTIONS) //Before the iverilog options,we should inject the source path with "-I/path -y/path": //The `/path` is the relative path from working dig file.  //Such as from `main.dig` to `test.v` : `verilog_src/test.v`  .add("-I" + Paths.get(root).resolve(/*/path*/) .add("-y" +Paths.get(root).resolve(/*/path*/) .add(file.getName()) .getArray() )

If the component is External but not File, it should be still option enable. Because it could be also work as an "compiling work path":

That's all about hdl extern files not portable problem and my thinking of how to resolve it.
Digital is most portable and complete digital circuit simulator I seen, and it works so well that I never look the source code until this problem. So, anyone have the idea in resolve it, please share with us!