Building a RISC-V Processor with Chipyard: Debugging the Halt Failure
I thought building a RISC-V processor with Chipyard would be straightforward - clone, build, run. Instead, I spent days debugging a halt failure that took me...
I thought building a RISC-V processor with Chipyard would be straightforward - clone, build, run. Instead, I spent days debugging a halt failure that took me...
My notes from building a scalable and production-ready infrastructure in AWS. This post covers the basics of setting up a load-balanced infrastructure using ...
Explore advanced techniques for interfacing complex C data structures with Python using ctypes and SWIG. Learn how to seamlessly pass complex data structures...
In this post, we will explore how to setup a development environment for FreeRTOS on RISCV using QEMU. this includes setting up the RISCV toolchain, QEMU, an...
I recently had a discussion about the importance of writing about what you learn. This post delves into why this practice is essential and how it has persona...