| MIR verification rule banning unconnected components |   | 1 | 53 | March 30, 2025 |
| Can a normal compiler include a MachineFunctionPass? |    | 4 | 336 | March 29, 2025 |
| Why does IRTranslator align the size for dynamic alloca? |   | 4 | 136 | March 19, 2025 |
| [RFC][LLVM] Add Support for Target Specific Asm Streamer |  | 0 | 58 | March 10, 2025 |
| Any users of getLogicalOperandType GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP? |   | 4 | 51 | February 10, 2025 |
| PSA: API breaking changes for named operands in MIR | | 0 | 92 | February 6, 2025 |
| Question about RuntimeDyld::MemoryManager::allowStubAllocation |  | 0 | 31 | February 3, 2025 |
| SelectionDAG: Why there are no special cases handled in haveNoCommonBitsSet() implemented? |   | 2 | 80 | January 31, 2025 |
| Newbie how to prevent constant:i32<2> from becoming i8=constant<2> |   | 2 | 78 | January 29, 2025 |
| Using CodeGen information to modify IR |  | 2 | 77 | January 17, 2025 |
| Can't fold LOAD into user during ISel |    | 16 | 236 | January 10, 2025 |
| How do I get desired 'align' for byVal passes of struct vars to procedure calls in IR code? Where should I look to configure that? |  | 0 | 27 | January 7, 2025 |
| I want to default to ZEXT Loads instead of SEXT on my custom backend. Where should I look to change that? | | 5 | 142 | January 5, 2025 |
| Confusion about PostRAScheduler |  | 0 | 66 | December 6, 2024 |
| Why was post-misched originally designed with only a TopDown direction? |     | 7 | 205 | November 20, 2024 |
| How intelligent is LLVM backend? |   | 6 | 208 | November 7, 2024 |
| Debug information symbols of downstream target due to linker relaxation |     | 22 | 474 | November 7, 2024 |
| Non-standard integer size in SelectionDAG |  | 1 | 66 | November 4, 2024 |
| [MachinePipeliner] Replace `SwingSchedulerDAG` with directed graph that allows cycles |    | 11 | 565 | September 25, 2024 |
| About soften float rounding operation | | 0 | 28 | September 9, 2024 |
| PSA: Planned changes to TableGen `getAllDerivedDefinitions` API (potential downstream breakages) | | 0 | 252 | September 5, 2024 |
| [legacy PM] register dynamic MachineFunctionPass plugin |  | 1 | 61 | September 3, 2024 |
| Changing TableGen getAllDerivedDefinitions to return `ArrayRef<const Record *>`? | | 4 | 156 | September 2, 2024 |
| Beginner question: Criteria for Expand/Promote vs Custom, how to know what Expand/Promote will do? |   | 5 | 190 | August 7, 2024 |
| Intrinsic lowered to pseudo not preserving glue |  | 3 | 72 | July 26, 2024 |
| [RFC][GlobalISel] InstructionSelect: Allow arbitrary instruction erasure |   | 2 | 345 | July 23, 2024 |
| [DAGCombiner] Handling of volatile undef SelectionDAG stores |  | 3 | 100 | July 2, 2024 |
| Understanding Stack verses FixedStack PseudoSoruceValue's |  | 3 | 89 | July 1, 2024 |
| TableGen tied operand constraints |  | 5 | 158 | June 14, 2024 |
| Possible to force (redundant) use of rex.W in amd64 inline asm? |  | 2 | 72 | May 29, 2024 |