lp:~philcox/+git/lp1982282

Author: Christopher S Hall
Author Date: 2022-12-14 08:10:38 UTC

igc: Fix PPS delta between two synchronized end-points

BugLink: https://bugs.launchpad.net/bugs/2006706

[ Upstream commit 5e91c72e560cc85f7163bbe3d14197268de31383 ]

This patch fix the pulse per second output delta between
two synchronized end-points.

Based on Intel Discrete I225 Software User Manual Section
4.2.15 TimeSync Auxiliary Control Register, ST0[Bit 4] and
ST1[Bit 7] must be set to ensure that clock output will be
toggles based on frequency value defined. This is to ensure
that output of the PPS is aligned with the clock.

How to test:

1) Running time synchronization on both end points.
Ex: ptp4l --step_threshold=1 -m -f gPTP.cfg -i <interface name>

2) Configure PPS output using below command for both end-points
Ex: SDP0 on I225 REV4 SKU variant

./testptp -d /dev/ptp0 -L 0,2
./testptp -d /dev/ptp0 -p 1000000000

3) Measure the output using analyzer for both end-points

Fixes: 87938851b6ef ("igc: enable auxiliary PHC functions for the i225")
Signed-off-by: Christopher S Hall <christopher.s.hall@intel.com>
Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>
Acked-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Naama Meir <naamax.meir@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
(cherry picked from upstream stable commit cfd5978411edae852636f8a6cd53ea093f292e79)
Signed-off-by: Philip Cox <philip.cox@canonical.com>

Author: Michael Sit Wei Hong
Author Date: 2022-06-02 07:35:07 UTC

stmmac: intel: Add RPL-P PCI ID

BugLink: https://bugs.launchpad.net/bugs/1982282

Add PCI ID for Ethernet TSN Controller on RPL-P.

Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
Link: https://lore.kernel.org/r/20220602073507.3955721-1-michael.wei.hong.sit@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
(cherry picked from commit 83450bbafebdaf90818e77ee368202f03d056cd7)
Signed-off-by: Philip Cox <philip.cox@canonical.com>

Author: Michael Sit Wei Hong
Author Date: 2022-06-02 07:35:07 UTC

stmmac: intel: Add RPL-P PCI ID

BugLink: https://bugs.launchpad.net/bugs/1982282

Add PCI ID for Ethernet TSN Controller on RPL-P.

Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
Link: https://lore.kernel.org/r/20220602073507.3955721-1-michael.wei.hong.sit@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
(cherry picked from commit 83450bbafebdaf90818e77ee368202f03d056cd7)
Signed-off-by: Philip Cox <philip.cox@canonical.com>

Author: Michael Sit Wei Hong
Author Date: 2022-06-02 07:35:07 UTC

stmmac: intel: Add RPL-P PCI ID

Add PCI ID for Ethernet TSN Controller on RPL-P.

Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
Link: https://lore.kernel.org/r/20220602073507.3955721-1-michael.wei.hong.sit@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
(cherry picked from commit 83450bbafebdaf90818e77ee368202f03d056cd7)
Signed-off-by: Philip Cox <philip.cox@canonical.com>

Author: Philip Cox
Author Date: 2022-09-29 19:16:31 UTC

net: stmmac: enable Intel mGbE 1G/2.5G auto-negotiation support

BugLink: https://bugs.launchpad.net/bugs/1982282

Initially, Intel mGbE was only able to configure the overclocking of 2.5
times clock rate to enable 2.5Gbps in the BIOS during boot time. Kernel
driver had no access to modify the clock rate for 1G/2.5G mode at runtime.

Now, this patch enables the runtime 1G/2.5G auto-negotiation support to
gets rid of the dependency on BIOS to change the 1G/2.5G clock rate.

This patch adds several new functions below:-
- intel_check_TSN_interface(): This new function reads FIA lane ownership
  registers and common lane registers through IPC1 commands to know which
  lane the mGbE port is assigned to.
- stmmac_mac_prepare(): To obtain the latest PHY interface from phylink
  during initialization and call intel_config_serdes() to proceed with
  SERDES configuration.
- intel_config_serdes(): To configure the SERDES based on the assigned
  lane and latest PHY interface, it sends IPC1 command to the PMC through
  PMC driver/API. The PMC acts as a proxy for R/W on behalf of the driver.

Signed-off-by: Tan, Tee Min <tee.min.tan@intel.com>

(picked from https://github.com/intel/linux-intel-quilt/tree/lts-v5.15.36-linux-220520T033542Z-1/patches/0039-net-stmmac-enable-Intel-mGbE-1G-2.5G-auto-negotiatio.patch)
Signed-off-by: Philip Cox <philip.cox@canonical.com>