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When RISCV_ISA_EXT_A is enabled,
ATOMIC_OPERATIONS_BUILTIN automaticly enabled,
we don't need to do it at the soc level again.

Signed-off-by: Fin Maaß f.maass@vogl-electronic.com

When RISCV_ISA_EXT_A is enabled, ATOMIC_OPERATIONS_BUILTIN automaticly enabled, we don't need to do it at the soc level again. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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Right, this is already handled by config RISCV. Thanks!

@maass-hamburg maass-hamburg added the Trivial Changes that can be reviewed by anyone, i.e. doc changes, minor build system tweaks, etc. label Oct 22, 2025
@jhedberg jhedberg merged commit 45fc6fe into zephyrproject-rtos:main Oct 22, 2025
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@maass-hamburg maass-hamburg deleted the riscv_ATOMIC_OPERATIONS_BUILTIN branch October 23, 2025 07:07
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area: Boards/SoCs platform: Andes Technology Trivial Changes that can be reviewed by anyone, i.e. doc changes, minor build system tweaks, etc.

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