A High-performance Timing Analysis Tool for VLSI Systems
5 Day TCL begginer to advanced training workshop by VSD
TCL Script automating the frontend of ASIC design
UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:
CAD in NYCU
This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.
TCL Script to automate the generation of Pre-layout QoR results
Vending Machine Design using Verilog HDL built and tested in Vivado Design Suite
Microprocessor Design using Verilog HDL built and tested in Vivado Design Suite
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