ext: hal: mchp: Fix compilation for MEC1501 HAL macros

Correct HAL macros related to eSPI block Add GIRQ bit definitions for VWires and some peripherals Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>

Author: albertofloyd

mec/mec1501/component/ecia.h

@@ -122,14 +122,14 @@
 #define MCHP_GIRQ17_ZID9u
 #define MCHP_GIRQ18_ZID10u
 #define MCHP_GIRQ19_ZID11u
-#define MCHP_GIRQ20_ZID12u
+#define MCHP_GIRQ20_ZID12u /* Nothing in datasheet */
 #define MCHP_GIRQ21_ZID13u
-#define MCHP_GIRQ22_ZID14u
-#define MCHP_GIRQ23_ZID15u
-#define MCHP_GIRQ24_ZID16u
-#define MCHP_GIRQ25_ZID17u
-#define MCHP_GIRQ26_ZID18u
-#define MCHP_GIRQ_ZID_MAX19u
+
+#define MCHP_GIRQ23_ZID14u /* Adjust per datasheet */
+#define MCHP_GIRQ24_ZID15u
+#define MCHP_GIRQ25_ZID16u
+#define MCHP_GIRQ26_ZID17u
+#define MCHP_GIRQ_ZID_MAX18u
 
 #define MCHP_ECIA_BLK_ENSET_OFS0x200ul
 #define MCHP_ECIA_BLK_ENCLR_OFS0x204ul
@@ -321,14 +321,18 @@ enum MCHP_GIRQ_IDS {
 MCHP_GIRQ19_ID,
 MCHP_GIRQ20_ID,
 MCHP_GIRQ21_ID,
-MCHP_GIRQ22_ID,
+
 MCHP_GIRQ23_ID,
 MCHP_GIRQ24_ID,
 MCHP_GIRQ25_ID,
 MCHP_GIRQ26_ID,
 MCHP_GIRQ_ID_MAX,
 };
 
+/* GIRQ Source, Enable_Set/Clr, Result registers bit positions */
+#define MCHP_PORT80_DEBUG0_GIRQ_VAL(1ul << 22)
+#define MCHP_PORT80_DEBUG1_GIRQ_VAL(1ul << 23)
+
 /**
  * @brief EC Interrupt Aggregator (ECIA)
  */

mec/mec1501/component/espi_vw.h

@@ -198,6 +198,35 @@
 #define MEC_ESPI_MSVW06_SRC2_POS 26u
 #define MEC_ESPI_MSVW06_SRC3_POS 27u
 
+#define MEC_ESPI_MSVW00_SRC0_VAL (1 << MEC_ESPI_MSVW00_SRC0_POS)
+#define MEC_ESPI_MSVW00_SRC1_VAL (1 << MEC_ESPI_MSVW00_SRC1_POS)
+#define MEC_ESPI_MSVW00_SRC2_VAL (1 << MEC_ESPI_MSVW00_SRC2_POS)
+#define MEC_ESPI_MSVW00_SRC3_VAL (1 << MEC_ESPI_MSVW00_SRC3_POS)
+#define MEC_ESPI_MSVW01_SRC0_VAL (1 << MEC_ESPI_MSVW01_SRC0_POS)
+#define MEC_ESPI_MSVW01_SRC1_VAL (1 << MEC_ESPI_MSVW01_SRC1_POS)
+#define MEC_ESPI_MSVW01_SRC2_VAL (1 << MEC_ESPI_MSVW01_SRC2_POS)
+#define MEC_ESPI_MSVW01_SRC3_VAL (1 << MEC_ESPI_MSVW01_SRC3_POS)
+#define MEC_ESPI_MSVW02_SRC0_VAL (1 << MEC_ESPI_MSVW02_SRC0_POS)
+#define MEC_ESPI_MSVW02_SRC1_VAL (1 << MEC_ESPI_MSVW02_SRC1_POS)
+#define MEC_ESPI_MSVW02_SRC2_VAL (1 << MEC_ESPI_MSVW02_SRC2_POS)
+#define MEC_ESPI_MSVW02_SRC3_VAL (1 << MEC_ESPI_MSVW02_SRC3_POS)
+#define MEC_ESPI_MSVW03_SRC0_VAL (1 << MEC_ESPI_MSVW03_SRC0_POS)
+#define MEC_ESPI_MSVW03_SRC1_VAL (1 << MEC_ESPI_MSVW03_SRC1_POS)
+#define MEC_ESPI_MSVW03_SRC2_VAL (1 << MEC_ESPI_MSVW03_SRC2_POS)
+#define MEC_ESPI_MSVW03_SRC3_VAL (1 << MEC_ESPI_MSVW03_SRC3_POS)
+#define MEC_ESPI_MSVW04_SRC0_VAL (1 << MEC_ESPI_MSVW04_SRC0_POS)
+#define MEC_ESPI_MSVW04_SRC1_VAL (1 << MEC_ESPI_MSVW04_SRC1_POS)
+#define MEC_ESPI_MSVW04_SRC2_VAL (1 << MEC_ESPI_MSVW04_SRC2_POS)
+#define MEC_ESPI_MSVW04_SRC3_VAL (1 << MEC_ESPI_MSVW04_SRC3_POS)
+#define MEC_ESPI_MSVW05_SRC0_VAL (1 << MEC_ESPI_MSVW05_SRC0_POS)
+#define MEC_ESPI_MSVW05_SRC1_VAL (1 << MEC_ESPI_MSVW05_SRC1_POS)
+#define MEC_ESPI_MSVW05_SRC2_VAL (1 << MEC_ESPI_MSVW05_SRC2_POS)
+#define MEC_ESPI_MSVW05_SRC3_VAL (1 << MEC_ESPI_MSVW05_SRC3_POS)
+#define MEC_ESPI_MSVW06_SRC0_VAL (1 << MEC_ESPI_MSVW06_SRC0_POS)
+#define MEC_ESPI_MSVW06_SRC1_VAL (1 << MEC_ESPI_MSVW06_SRC1_POS)
+#define MEC_ESPI_MSVW06_SRC2_VAL (1 << MEC_ESPI_MSVW06_SRC2_POS)
+#define MEC_ESPI_MSVW06_SRC3_VAL (1 << MEC_ESPI_MSVW06_SRC3_POS)
+
 /*
  * 0 <= v <= 6
  * 0 <= s <= 3

mec/mec1501/component/vbat.h

@@ -121,7 +121,9 @@ typedef struct vbatr_regs
 __IOM uint32_t PFRS;/*! (@ 0x00000000) VBATR Power Fail Reset Status */
 uint8_t RSVD1[4];
 __IOM uint32_t CLK32_EN;/*! (@ 0x00000008) VBATR 32K clock enable */
-uint8_t RSVD2[20];
+__IOM uint32_t SHDN_EN;/*! (@ 0x0000000C) VBATR SHD pin enable */
+uint8_t RSVD2[12];
+__IOM uint32_t CKK32_TRIM;/*! (@ 0x0000001C) VBATR 32 clock override */
 __IOM uint32_t MCNT_LO;/*! (@ 0x00000020) VBATR monotonic count lo */
 __IOM uint32_t MCNT_HI;/*! (@ 0x00000024) VBATR monotonic count hi */
 } VBATR_Type;