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Commit 1c05507

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author
Andrew Haley
committed
8289743: AArch64: Clean up patching logic
Reviewed-by: adinn, ngasson
1 parent 011958d commit 1c05507

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6 files changed

+453
-183
lines changed

6 files changed

+453
-183
lines changed

src/hotspot/cpu/aarch64/assembler_aarch64.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -155,10 +155,6 @@ void Address::lea(MacroAssembler *as, Register r) const {
155155
}
156156
}
157157

158-
void Assembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
159-
ShouldNotReachHere();
160-
}
161-
162158
#undef __
163159

164160
#define starti Instruction_aarch64 current_insn(this);
@@ -189,7 +185,7 @@ void Assembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset)
189185
offset >>= 2;
190186
starti;
191187
f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
192-
rf(Rd, 0);
188+
zrf(Rd, 0);
193189
}
194190

195191
// An "all-purpose" add/subtract immediate, per ARM documentation:

src/hotspot/cpu/aarch64/assembler_aarch64.hpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -220,7 +220,7 @@ class Instruction_aarch64 {
220220
return extend(uval, msb - lsb);
221221
}
222222

223-
static void patch(address a, int msb, int lsb, uint64_t val) {
223+
static ALWAYSINLINE void patch(address a, int msb, int lsb, uint64_t val) {
224224
int nbits = msb - lsb + 1;
225225
guarantee(val < (1ULL << nbits), "Field too big for insn");
226226
assert_cond(msb >= lsb);
@@ -718,7 +718,7 @@ class Assembler : public AbstractAssembler {
718718
wrap_label(Rd, L, &Assembler::_adrp);
719719
}
720720

721-
void adrp(Register Rd, const Address &dest, uint64_t &offset);
721+
void adrp(Register Rd, const Address &dest, uint64_t &offset) = delete;
722722

723723
#undef INSN
724724

src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2690,7 +2690,7 @@ void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
26902690
assert_different_registers(val, crc, res);
26912691
uint64_t offset;
26922692
__ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2693-
if (offset) __ add(res, res, offset);
2693+
__ add(res, res, offset);
26942694

26952695
__ mvnw(crc, crc); // ~crc
26962696
__ update_byte_crc32(crc, val, res);

src/hotspot/cpu/aarch64/interp_masm_aarch64.cpp

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -170,7 +170,12 @@ void InterpreterMacroAssembler::get_unsigned_2_byte_index_at_bcp(
170170
void InterpreterMacroAssembler::get_dispatch() {
171171
uint64_t offset;
172172
adrp(rdispatch, ExternalAddress((address)Interpreter::dispatch_table()), offset);
173-
lea(rdispatch, Address(rdispatch, offset));
173+
// Use add() here after ARDP, rather than lea().
174+
// lea() does not generate anything if its offset is zero.
175+
// However, relocs expect to find either an ADD or a load/store
176+
// insn after an ADRP. add() always generates an ADD insn, even
177+
// for add(Rn, Rn, 0).
178+
add(rdispatch, rdispatch, offset);
174179
}
175180

176181
void InterpreterMacroAssembler::get_cache_index_at_bcp(Register index,

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