Merge tag 'omap-devel-a-for-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.10/crypto

For OMAP2+ SoCs, convert the SHA/MD5 and AES accelerator integration code and data to use hwmod and omap_device. This is a prerequisite for moving the hwmod code out of arch/arm. Basic test logs are available at: http://www.pwsan.com/omap/testlogs/sham_aes_integration_devel_3.10/20130330155313/

Author: tmlind

arch/arm/mach-omap2/cclock2430_data.c

@@ -1978,9 +1978,11 @@ static struct omap_clk omap2430_clks[] = {
 CLK(NULL,"sdrc_ick",&sdrc_ick),
 CLK(NULL,"des_ick",&des_ick),
 CLK("omap-sham","ick",&sha_ick),
-CLK("omap_rng","ick",&rng_ick),
+CLK(NULL,"sha_ick",&sha_ick),
+CLK("omap_rng", "ick",&rng_ick),
 CLK(NULL,"rng_ick",&rng_ick),
 CLK("omap-aes","ick",&aes_ick),
+CLK(NULL,"aes_ick",&aes_ick),
 CLK(NULL,"pka_ick",&pka_ick),
 CLK(NULL,"usb_fck",&usb_fck),
 CLK("musb-omap2430","ick",&usbhs_ick),

arch/arm/mach-omap2/cclock33xx_data.c

@@ -413,6 +413,14 @@ static struct clk smartreflex1_fck;
 DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
 DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
 
+static struct clk sha0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
+DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
+
+static struct clk aes0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
+DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
+
 /*
  * Modules clock nodes
  *
@@ -878,6 +886,8 @@ static struct omap_clk am33xx_clks[] = {
 CLK(NULL,"mmu_fck",&mmu_fck),
 CLK(NULL,"smartreflex0_fck",&smartreflex0_fck),
 CLK(NULL,"smartreflex1_fck",&smartreflex1_fck),
+CLK(NULL,"sha0_fck",&sha0_fck),
+CLK(NULL,"aes0_fck",&aes0_fck),
 CLK(NULL,"timer1_fck",&timer1_fck),
 CLK(NULL,"timer2_fck",&timer2_fck),
 CLK(NULL,"timer3_fck",&timer3_fck),

arch/arm/mach-omap2/cclock3xxx_data.c

@@ -3471,8 +3471,10 @@ static struct omap_clk omap3xxx_clks[] = {
 CLK("usbhs_tll","usb_tll_hs_usb_ch1_clk",&dummy_ck),
 CLK(NULL,"init_60m_fclk",&dummy_ck),
 CLK(NULL,"gpt1_fck",&gpt1_fck),
+CLK(NULL,"aes2_ick",&aes2_ick),
 CLK(NULL,"wkup_32k_fck",&wkup_32k_fck),
 CLK(NULL,"gpio1_dbck",&gpio1_dbck),
+CLK(NULL,"sha12_ick",&sha12_ick),
 CLK(NULL,"wdt2_fck",&wdt2_fck),
 CLK("omap_wdt","ick",&wdt2_ick),
 CLK(NULL,"wdt2_ick",&wdt2_ick),

arch/arm/mach-omap2/devices.c

@@ -504,140 +504,31 @@ static void omap_init_rng(void)
 WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
 }
 
-#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_sham_resources[] = {
-{
-.start= OMAP24XX_SEC_SHA1MD5_BASE,
-.end= OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
-.flags= IORESOURCE_MEM,
-},
-{
-.start= 51 + OMAP_INTC_START,
-.flags= IORESOURCE_IRQ,
-}
-};
-static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
-#else
-#define omap2_sham_resourcesNULL
-#define omap2_sham_resources_sz0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_sham_resources[] = {
-{
-.start= OMAP34XX_SEC_SHA1MD5_BASE,
-.end= OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
-.flags= IORESOURCE_MEM,
-},
-{
-.start= 49 + OMAP_INTC_START,
-.flags= IORESOURCE_IRQ,
-},
-{
-.start= OMAP34XX_DMA_SHA1MD5_RX,
-.flags= IORESOURCE_DMA,
-}
-};
-static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
-#else
-#define omap3_sham_resourcesNULL
-#define omap3_sham_resources_sz0
-#endif
-
-static struct platform_device sham_device = {
-.name= "omap-sham",
-.id= -1,
-};
-
-static void omap_init_sham(void)
+static void __init omap_init_sham(void)
 {
-if (cpu_is_omap24xx()) {
-sham_device.resource = omap2_sham_resources;
-sham_device.num_resources = omap2_sham_resources_sz;
-} else if (cpu_is_omap34xx()) {
-sham_device.resource = omap3_sham_resources;
-sham_device.num_resources = omap3_sham_resources_sz;
-} else {
-pr_err("%s: platform not supported\n", __func__);
-return;
-}
-platform_device_register(&sham_device);
-}
-#else
-static inline void omap_init_sham(void) { }
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_aes_resources[] = {
-{
-.start= OMAP24XX_SEC_AES_BASE,
-.end= OMAP24XX_SEC_AES_BASE + 0x4C,
-.flags= IORESOURCE_MEM,
-},
-{
-.start= OMAP24XX_DMA_AES_TX,
-.flags= IORESOURCE_DMA,
-},
-{
-.start= OMAP24XX_DMA_AES_RX,
-.flags= IORESOURCE_DMA,
-}
-};
-static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
-#else
-#define omap2_aes_resourcesNULL
-#define omap2_aes_resources_sz0
-#endif
+struct omap_hwmod *oh;
+struct platform_device *pdev;
 
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_aes_resources[] = {
-{
-.start= OMAP34XX_SEC_AES_BASE,
-.end= OMAP34XX_SEC_AES_BASE + 0x4C,
-.flags= IORESOURCE_MEM,
-},
-{
-.start= OMAP34XX_DMA_AES2_TX,
-.flags= IORESOURCE_DMA,
-},
-{
-.start= OMAP34XX_DMA_AES2_RX,
-.flags= IORESOURCE_DMA,
-}
-};
-static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
-#else
-#define omap3_aes_resourcesNULL
-#define omap3_aes_resources_sz0
-#endif
+oh = omap_hwmod_lookup("sham");
+if (!oh)
+return;
 
-static struct platform_device aes_device = {
-.name= "omap-aes",
-.id= -1,
-};
+pdev = omap_device_build("omap-sham", -1, oh, NULL, 0);
+WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
+}
 
-static void omap_init_aes(void)
+static void __init omap_init_aes(void)
 {
-if (cpu_is_omap24xx()) {
-aes_device.resource = omap2_aes_resources;
-aes_device.num_resources = omap2_aes_resources_sz;
-} else if (cpu_is_omap34xx()) {
-aes_device.resource = omap3_aes_resources;
-aes_device.num_resources = omap3_aes_resources_sz;
-} else {
-pr_err("%s: platform not supported\n", __func__);
+struct omap_hwmod *oh;
+struct platform_device *pdev;
+
+oh = omap_hwmod_lookup("aes");
+if (!oh)
 return;
-}
-platform_device_register(&aes_device);
-}
 
-#else
-static inline void omap_init_aes(void) { }
-#endif
+pdev = omap_device_build("omap-aes", -1, oh, NULL, 0);
+WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n");
+}
 
 /*-------------------------------------------------------------------------*/
 
@@ -764,11 +655,11 @@ static int __init omap2_init_devices(void)
 omap_init_dmic();
 omap_init_mcpdm();
 omap_init_mcspi();
+omap_init_sham();
+omap_init_aes();
 }
 omap_init_sti();
 omap_init_rng();
-omap_init_sham();
-omap_init_aes();
 omap_init_vout();
 omap_init_ocp2scp();
 

arch/arm/mach-omap2/omap_hwmod_2420_data.c

@@ -610,6 +610,8 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 &omap2420_l4_core__mcbsp2,
 &omap2420_l4_core__msdi1,
 &omap2xxx_l4_core__rng,
+&omap2xxx_l4_core__sham,
+&omap2xxx_l4_core__aes,
 &omap2420_l4_core__hdq1w,
 &omap2420_l4_wkup__counter_32k,
 &omap2420_l3__gpmc,

arch/arm/mach-omap2/omap_hwmod_2430_data.c

@@ -963,6 +963,8 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
 &omap2430_l4_core__mcbsp5,
 &omap2430_l4_core__hdq1w,
 &omap2xxx_l4_core__rng,
+&omap2xxx_l4_core__sham,
+&omap2xxx_l4_core__aes,
 &omap2430_l4_wkup__counter_32k,
 &omap2430_l3__gpmc,
 NULL,

arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c

@@ -138,6 +138,24 @@ static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
 { }
 };
 
+static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
+{
+.pa_start= 0x480a4000,
+.pa_end= 0x480a4000 + 0x64 - 1,
+.flags= ADDR_TYPE_RT
+},
+{ }
+};
+
+static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = {
+{
+.pa_start= 0x480a6000,
+.pa_end= 0x480a6000 + 0x50 - 1,
+.flags= ADDR_TYPE_RT
+},
+{ }
+};
+
 /*
  * Common interconnect data
  */
@@ -389,3 +407,21 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
 .addr= omap2_rng_addr_space,
 .user= OCP_USER_MPU | OCP_USER_SDMA,
 };
+
+/* l4 core -> sham interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
+.master= &omap2xxx_l4_core_hwmod,
+.slave= &omap2xxx_sham_hwmod,
+.clk= "sha_ick",
+.addr= omap2xxx_sham_addrs,
+.user= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> aes interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
+.master= &omap2xxx_l4_core_hwmod,
+.slave= &omap2xxx_aes_hwmod,
+.clk= "aes_ick",
+.addr= omap2xxx_aes_addrs,
+.user= OCP_USER_MPU | OCP_USER_SDMA,
+};

arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

@@ -864,3 +864,84 @@ struct omap_hwmod omap2xxx_rng_hwmod = {
 .flags= HWMOD_INIT_NO_RESET,
 .class= &omap2_rng_hwmod_class,
 };
+
+/* SHAM */
+
+static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
+.rev_offs= 0x5c,
+.sysc_offs= 0x60,
+.syss_offs= 0x64,
+.sysc_flags= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+.sysc_fields= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_sham_class = {
+.name= "sham",
+.sysc= &omap2_sham_sysc,
+};
+
+static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
+{ .irq = 51 + OMAP_INTC_START, },
+{ .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
+{ .name = "rx", .dma_req = 13 },
+{ .dma_req = -1 }
+};
+
+struct omap_hwmod omap2xxx_sham_hwmod = {
+.name= "sham",
+.mpu_irqs= omap2_sham_mpu_irqs,
+.sdma_reqs= omap2_sham_sdma_chs,
+.main_clk= "l4_ck",
+.prcm= {
+.omap2 = {
+.module_offs = CORE_MOD,
+.prcm_reg_id = 4,
+.module_bit = OMAP24XX_EN_SHA_SHIFT,
+.idlest_reg_id = 4,
+.idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
+},
+},
+.class= &omap2xxx_sham_class,
+};
+
+/* AES */
+
+static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
+.rev_offs= 0x44,
+.sysc_offs= 0x48,
+.syss_offs= 0x4c,
+.sysc_flags= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+.sysc_fields= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_aes_class = {
+.name= "aes",
+.sysc= &omap2_aes_sysc,
+};
+
+static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
+{ .name = "tx", .dma_req = 9 },
+{ .name = "rx", .dma_req = 10 },
+{ .dma_req = -1 }
+};
+
+struct omap_hwmod omap2xxx_aes_hwmod = {
+.name= "aes",
+.sdma_reqs= omap2_aes_sdma_chs,
+.main_clk= "l4_ck",
+.prcm= {
+.omap2 = {
+.module_offs = CORE_MOD,
+.prcm_reg_id = 4,
+.module_bit = OMAP24XX_EN_AES_SHIFT,
+.idlest_reg_id = 4,
+.idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
+},
+},
+.class= &omap2xxx_aes_class,
+};