Merge tag 'omap-fixes-a-for-3.9-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.9-rc3/fixes

Miscellaneous OMAP fixes for v3.9-rc. These primarily deal with OMAP2+ power management regressions. There's also a fix for the OMAP1 OHCI controller. Basic build, boot, and PM test logs are at: http://www.pwsan.com/omap/testlogs/fixes_a_3.9-rc/20130314101856/

Author: tmlind

arch/arm/mach-omap1/clock_data.c

@@ -538,15 +538,6 @@ static struct clk usb_hhc_ck16xx = {
 };
 
 static struct clk usb_dc_ck = {
-.name= "usb_dc_ck",
-.ops= &clkops_generic,
-/* Direct from ULPD, no parent */
-.rate= 48000000,
-.enable_reg= OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-.enable_bit= USB_REQ_EN_SHIFT,
-};
-
-static struct clk usb_dc_ck7xx = {
 .name= "usb_dc_ck",
 .ops= &clkops_generic,
 /* Direct from ULPD, no parent */
@@ -727,8 +718,7 @@ static struct omap_clk omap_clks[] = {
 CLK(NULL,"usb_clko",&usb_clko,CK_16XX | CK_1510 | CK_310),
 CLK(NULL,"usb_hhc_ck",&usb_hhc_ck1510, CK_1510 | CK_310),
 CLK(NULL,"usb_hhc_ck",&usb_hhc_ck16xx, CK_16XX),
-CLK(NULL,"usb_dc_ck",&usb_dc_ck,CK_16XX),
-CLK(NULL,"usb_dc_ck",&usb_dc_ck7xx,CK_7XX),
+CLK(NULL,"usb_dc_ck",&usb_dc_ck,CK_16XX | CK_7XX),
 CLK(NULL,"mclk",&mclk_1510,CK_1510 | CK_310),
 CLK(NULL,"mclk",&mclk_16xx,CK_16XX),
 CLK(NULL,"bclk",&bclk_1510,CK_1510 | CK_310),

arch/arm/mach-omap2/cclock44xx_data.c

@@ -52,6 +52,13 @@
  */
 #define OMAP4_DPLL_ABE_DEFFREQ98304000
 
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ960000000
+
 /* Root clocks */
 
 DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
@@ -1011,6 +1018,10 @@ DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
  OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
  hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
 
+DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
+OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
+
 DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
@@ -1538,6 +1549,7 @@ static struct omap_clk omap44xx_clks[] = {
 CLK(NULL,"per_mcbsp4_gfclk",&per_mcbsp4_gfclk,CK_443X),
 CLK(NULL,"hsmmc1_fclk",&hsmmc1_fclk,CK_443X),
 CLK(NULL,"hsmmc2_fclk",&hsmmc2_fclk,CK_443X),
+CLK(NULL,"ocp2scp_usb_phy_phy_48m",&ocp2scp_usb_phy_phy_48m,CK_443X),
 CLK(NULL,"sha2md5_fck",&sha2md5_fck,CK_443X),
 CLK(NULL,"slimbus1_fclk_1",&slimbus1_fclk_1,CK_443X),
 CLK(NULL,"slimbus1_fclk_0",&slimbus1_fclk_0,CK_443X),
@@ -1705,5 +1717,13 @@ int __init omap4xxx_clk_init(void)
 if (rc)
 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
+/*
+ * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+ * domain can transition to retention state when not in use.
+ */
+rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
+if (rc)
+pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
 return 0;
 }

arch/arm/mach-omap2/omap_hwmod.c

@@ -1368,7 +1368,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
 }
 
 if (sf & SYSC_HAS_MIDLEMODE) {
-if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+if (oh->flags & HWMOD_FORCE_MSTANDBY) {
+idlemode = HWMOD_IDLEMODE_FORCE;
+} else if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
 idlemode = HWMOD_IDLEMODE_NO;
 } else {
 if (sf & SYSC_HAS_ENAWAKEUP)
@@ -1440,7 +1442,8 @@ static void _idle_sysc(struct omap_hwmod *oh)
 }
 
 if (sf & SYSC_HAS_MIDLEMODE) {
-if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+if ((oh->flags & HWMOD_SWSUP_MSTANDBY) ||
+ (oh->flags & HWMOD_FORCE_MSTANDBY)) {
 idlemode = HWMOD_IDLEMODE_FORCE;
 } else {
 if (sf & SYSC_HAS_ENAWAKEUP)

arch/arm/mach-omap2/omap_hwmod.h

@@ -427,8 +427,8 @@ struct omap_hwmod_omap4_prcm {
  *
  * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
  * of idle, rather than relying on module smart-idle
- * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
- * of standby, rather than relying on module smart-standby
+ * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
+ * out of standby, rather than relying on module smart-standby
  * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
  * SDRAM controller, etc. XXX probably belongs outside the main hwmod file
  * XXX Should be HWMOD_SETUP_NO_RESET
@@ -459,6 +459,10 @@ struct omap_hwmod_omap4_prcm {
  * correctly, or this is being abused to deal with some PM latency
  * issues -- but we're currently suffering from a shortage of
  * folks who are able to track these issues down properly.
+ * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
+ * is kept in force-standby mode. Failing to do so causes PM problems
+ * with musb on OMAP3630 at least. Note that musb has a dedicated register
+ * to control MSTANDBY signal when MIDLEMODE is set to force-standby.
  */
 #define HWMOD_SWSUP_SIDLE(1 << 0)
 #define HWMOD_SWSUP_MSTANDBY(1 << 1)
@@ -471,6 +475,7 @@ struct omap_hwmod_omap4_prcm {
 #define HWMOD_16BIT_REG(1 << 8)
 #define HWMOD_EXT_OPT_MAIN_CLK(1 << 9)
 #define HWMOD_BLOCK_WFI(1 << 10)
+#define HWMOD_FORCE_MSTANDBY(1 << 11)
 
 /*
  * omap_hwmod._int_flags definitions

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

@@ -1707,9 +1707,14 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
  * Erratum ID: i479 idle_req / idle_ack mechanism potentially
  * broken when autoidle is enabled
  * workaround is to disable the autoidle bit at module level.
+ *
+ * Enabling the device in any other MIDLEMODE setting but force-idle
+ * causes core_pwrdm not enter idle states at least on OMAP3630.
+ * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
+ * signal when MIDLEMODE is set to force-idle.
  */
 .flags= HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
-| HWMOD_SWSUP_MSTANDBY,
+| HWMOD_FORCE_MSTANDBY,
 };
 
 /* usb_otg_hs */

arch/arm/mach-omap2/omap_hwmod_44xx_data.c

@@ -2714,6 +2714,10 @@ static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
 { }
 };
 
+static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
+{ .role = "48mhz", .clk = "ocp2scp_usb_phy_phy_48m" },
+};
+
 /* ocp2scp_usb_phy */
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
 .name= "ocp2scp_usb_phy",
@@ -2728,6 +2732,8 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
 },
 },
 .dev_attr= ocp2scp_dev_attr,
+.opt_clks= ocp2scp_usb_phy_opt_clks,
+.opt_clks_cnt= ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
 };
 
 /*