to_verilog("file.v") creates two empty lines at beginning of file #44
Description
Verilog output file has two empty lines before the module keyword
('\n' '\n' 'module blinkled #\n' '(\n' ' parameter WIDTH = 8\n' ')\n' '(\n' ' input CLK,\n' ' input RST,\n' ' output reg [WIDTH-1:0] LED\n' ');\n'