Initial Commit

Author: nxbyte

LICENSE

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+The MIT License (MIT)
+
+Copyright (c) 2016 
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

Project 1 – Introduction to Xilinx/Design Assignment 1.pdf

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+# Project 1 - Introduction to Xilinx
+
+## Objective
+
+The main goal of this lab is to create a verilog module, and through a test bench, analyze its waveform model once a schematic, and source code is created using the software, Xilinx ISE. Through this process, the team will be able to obtain a deeper understanding of how logic gates, or boolean logic, interacts with verilog code by analyzing certain scenarios that these two demonstrate. 
+
+## Waveforms
+
+Simulation results from the Verilog representation of this half-adder
+
+![Project 1 Waveform](/Project 1 – Introduction to Xilinx/Simulation Waveforms/project1_halfAdder.png)
+
+## Source Files
+- **Half-Adder Module** - half_adder.v
+- **Half-Adder Test Bench** - half_adder_test.v
+

Project 1 – Introduction to Xilinx/README.md

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+`timescale 1ns / 1ps
+
+/*
+Group Members: Luis Calderon and Warren Seto
+
+Lab Name: Introduction to Xilinx (Lab 1)
+Project Name: eng312_proj1
+Design Name: half_adder
+Design Description: Verilog Code for a half-adder
+*/
+
+// Input & Output components to use in the half-adder
+module half_adder
+(
+ input iA, input iB,
+ output oSUM, output oCARRY
+ );
+
+// This uses an exclusive OR gate to find the SUM of two inputs
+assign oSUM = iA ^ iB;
+
+// This uses an AND gate to find the CARRY of two inputs
+assign oCARRY = iA & iB;
+
+ endmodule

Project 1 – Introduction to Xilinx/Simulation Waveforms/project1_halfAdder.png

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+`timescale 1ns / 1ps
+
+/*
+Group Members: Luis Calderon and Warren Seto
+
+Lab Name: Introduction to Xilinx (Lab 1)
+Project Name: eng312_proj1
+Design Name: half_adder_test.v
+Design Description: Verilog Test Fixture created by ISE for module: half_adder
+*/
+
+module half_adder_test;
+
+// Input Registers:
+ reg iA;
+ reg iB;
+
+// Output Registers:
+ wire oSUM;
+ wire oCARRY;
+
+// Instantiate the Unit Under Test (UUT)
+half_adder uut 
+(
+.iA(iA), 
+.iB(iB), 
+.oSUM(oSUM), 
+.oCARRY(oCARRY)
+);
+
+// The code below tests the half-adder by manually changing the values of each input register
+initial begin
+
+// Set the both input registers as 0 as a default
+iA = 0;
+iB = 0;
+ 
+// For five seconds, set one register to 1 while leaving the other as its default 0
+#5 iA = 0; iB = 1;
+
+// For five seconds, set the other register to 1 while flipping the other to its default 0
+#5 iA = 1; iB = 0;
+ 
+// For five seconds, set both registers to 1
+#5 iA = 1; iB = 1;
+ 
+end 
+ 
+ // The test should run for a total of 25 nanoseconds
+initial #25 $finish;
+
+endmodule

Project 1 – Introduction to Xilinx/half_adder.v

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+# Project 2 - Combinational Logic
+
+## Objective
+
+The purpose of this design assignment was to create modules of combinational logic in the Verilog Hardware Description Language (HDL) format. While completing this task, students continued immersing themselves in the Xilinx platform and the Verilog HDL. Through this assignment the team: prepared truth tables, wrote Verilog code per module, and made test fixtures to test each module. The assignment tasked the group to create: a full adder, a 4-bit adder, a three bit comparator, a 4-16 decoder, a priority encoder, and a 4-1 multiplexer. 
+
+## Source Directories
+
+- **Four-Sixteen Decoder** - /dec_4_to_16
+- **Four-Bit Look Ahead Adder** - /four_bit_look_ahead_adder
+- **Four-Bit Ripple Adder**: - /four_bit_ripple_adder 
+- **Full Adder** - /full_adder
+- **Four-One Multiplexer** - /mux_four_to_one 
+- **Priority Encoder** - /priority_encoder
+- **Three-Bit Comparator** - /three_bit_comparator

Project 1 – Introduction to Xilinx/half_adder_test.v

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+# Four-Sixteen Decoder
+
+## Objective
+
+This 4-to-16 decoder takes one four bit input and outputs the sixteen bit representation of the input. This module uses the concept of one-hot decoding where each output would have one output that would correspond to the input. 
+
+An application for this decoder would be to convert a four bit binary to its hexadecimal representation. 
+
+To verify this module, the input’s binary bits were converted into their decimal representation and compared to the output’s decimal representation to see if they matched.
+
+## Waveforms
+
+Simulation results from the Verilog representation of this Four-Sixteen Decoder
+
+![Project 2 Waveform for Four-Sixteen Decoder](/Project 2 – Combinational Logic/dec_4_to_16/Simulation Waveforms/project2_416decode.png)
+
+## Source Files
+- **Four-Sixteen Decoder Module** - dec_4_to_16.v
+- **Four-Sixteen Decoder Test Bench** - dec_4_to_16_test.v