Updated Source Clarity

- Improved source code for clarity for various projects

Author: nxbyte

Project 1 – Introduction to Xilinx/half_adder.v

@@ -12,8 +12,8 @@
 // Input & Output components to use in the half-adder
 module half_adder
 (
- input iA, input iB,
- output oSUM, output oCARRY
+input iA, input iB,
+output oSUM, output oCARRY
  );
 
 // This uses an exclusive OR gate to find the SUM of two inputs

Project 2 – Combinational Logic/dec_4_to_16/README.md

@@ -2,11 +2,11 @@
 
 ## Objective
 
-This 4-to-16 decoder takes one four bit input and outputs the sixteen bit representation of the input. This module uses the concept of one-hot decoding where each output would have one output that would correspond to the input. 
+This 4-to-16 decoder takes one 4-bit input and outputs a 16-bit representation of the input. This module uses the concept of one-hot decoding where each output would have one output that would correspond to the input. 
 
-An application for this decoder would be to convert a four bit binary to its hexadecimal representation. 
+An application for this decoder would be to convert a 4-bit binary value to its hexadecimal representation. 
 
-To verify this module, the input’s binary bits were converted into their decimal representation and compared to the output’s decimal representation to see if they matched.
+To verify this module, the binary bits of the input is converted into their decimal representation and compared to the output’s decimal representation to see if they match.
 
 ## Waveforms
 

Project 2 – Combinational Logic/dec_4_to_16/dec_4_to_16_test.v

@@ -23,8 +23,8 @@ module dec_4_to_16_test;
 // Instantiate the Unit Under Test (UUT)
 dec_4_to_16 uut 
 (
- .ADDR(ADDR),
- .DEC(DEC)
+.ADDR(ADDR),
+.DEC(DEC)
 );
 
 initial begin
@@ -39,7 +39,6 @@ module dec_4_to_16_test;
  for (count = 1; count <= 16; count = count + 1) begin
 #5 ADDR = count;
 end
-
 end
 // The test will run for a total interval of 80ns
  initial #80 $finish;

Project 2 – Combinational Logic/four_bit_look_ahead_adder/README.md

@@ -2,7 +2,7 @@
 
 ## Objective
 
-This 4-bit look ahead adder is an improved implementation of a 4-bit ripple adder by eliminating the propagation delay found in the ripple 4-bit adder. For each output, this implementation computes each previous carry simultaneously instead of waiting for the previous adder block to yield a carry. In this adder, the first carry bit is set to zero and simplified the logic because there was no initial carry bit as the input. While this implementation uses more gates and more complex logic to accomplish the same task as the ripple adder, this implementation would add two 4-bit numbers faster than the ripple version.
+This 4-bit look ahead adder is an improved implementation of a 4-bit ripple adder by eliminating the propagation delay found in the 4-bit ripple adder. For each output, this implementation computes each previous carry simultaneously instead of waiting for the previous adder module to yield a carry. In this adder, the first carry bit is set to zero and simplifies the logic because there is no initial carry bit as the input. While this implementation uses more gates and more complex logic to accomplish the same task as the ripple adder, this implementation would add two 4-bit numbers much faster than the 4-bit ripple adder.
 
 ## Waveforms
 

Project 2 – Combinational Logic/four_bit_look_ahead_adder/four_bit_adder_EC_test.v

@@ -31,19 +31,19 @@ module four_bit_adder_EC_test;
 
  initial begin
 
-// Initialize Inputs
-A = 0;
-B = 0;
-count = 0;
+// Initialize Inputs
+A = 0;
+B = 0;
+count = 0;
+
 end
 
  //Whenever the value of either A or B changes, iterate the possible combinations 
  always @(A or B)
 begin
-
 // Loops over the possible combinations for A and B
 for (count = 0; count < 256; count = count + 1) 
- #1 {A, B} = count; 
+#1 {A, B} = count; 
 #2 $stop;
  end
 endmodule

Project 2 – Combinational Logic/four_bit_ripple_adder/README.md

@@ -2,7 +2,8 @@
 
 ## Objective
 
-This 4-bit adder takes advantage of the full adder module by taking four full adders and linking them together to add 2 four bit inputs. In the 4-bit adder, the first carry bit is set to zero because there was no initial carry bit as the input. 
+This 4-bit adder takes advantage of the full adder module by taking four full adders and linking them together to add 2 four bit inputs. In the 4-bit adder, the first carry bit is set to zero because there is no initial carry bit as an input. 
+
 
 ## Waveforms
 
@@ -12,4 +13,4 @@ Simulation results from the Verilog representation of this Four-Bit Ripple Adder
 
 ## Source Files
 - **Four-Bit Ripple Adder Module** - four_bit_adder.v
-- **Four-Bit Ripple Adder Test Bench** - four_bit_adder_test.v
+- **Four-Bit Ripple Adder Test Bench** - four_bit_adder_test.v

Project 2 – Combinational Logic/full_adder/README.md

@@ -2,7 +2,7 @@
 
 ## Objective
 
-This full adder takes 3-bits for the input as A, B and Carry In. It outputs 2-bits as Sum and Carry Out. The Sum will be the lowest value output and the Carry Out is the highest value output as well as where other full adders could be joined together.
+This full adder takes 3-bits for the input (A, B and carry in) and outputs a 2-bit Sum and its corresponding Carry Out. The Sum will be the lowest value output and the Carry Out is the highest value output as well as where other full adders could be joined together. 
 
 ## Waveforms
 
@@ -12,4 +12,4 @@ Simulation results from the Verilog representation of this Full Adder
 
 ## Source Files
 - **Full Adder Module** - full_adder.v
-- **Full Adder Test Bench** - full_adder_test.v
+- **Full Adder Test Bench** - full_adder_test.v

Project 2 – Combinational Logic/mux_four_to_one/README.md

@@ -2,7 +2,7 @@
 
 ## Objective
 
-This 4-1 multiplexer takes an input of four bits and another input of two bits and outputs the selected input. In this module, the two bits are the select bits that would select which one the inputs should be designated as the output. 
+This 4-1 multiplexer takes an input of four bits and another input of 2-bits and outputs the selected input. In this module, the two bits are the select bits that would select which one the inputs should be designated as the output. 
 
 ## Waveforms
 
@@ -12,4 +12,4 @@ Simulation results from the Verilog representation of this 4-1 Multiplexer
 
 ## Source Files
 - **4-1 Multiplexer Module** - mux_four_to_one.v
-- **4-1 Multiplexer Test Bench** - mux_four_to_one_test.v
+- **4-1 Multiplexer Test Bench** - mux_four_to_one_test.v

Project 2 – Combinational Logic/mux_four_to_one/mux_four_to_one_test.v

@@ -32,26 +32,27 @@ module mux_four_to_one_test;
 
 initial begin
 
-// Initialize Inputs
-DIN = 0;
-SEL = 0;
+// Initialize Inputs
+DIN = 0;
+SEL = 0;
 
-// Initialize counter variables
-count = 0;
-count2 = 0;
+// Initialize counter variables
+count = 0;
+count2 = 0;
 
 // Loops over the possible combinations for SEL and resets the value for DIN
  for (count = 0; count < 4; count = count + 1) begin
-SEL = count;
-DIN = 0;
+ SEL = count;
+ DIN = 0;
 
-// Loops over the possible combinations for DIN for each SEL value
-for (count2 = 0; count2 <= 16; count2 = count2 + 1) begin
-#5 DIN = count2;
+// Loops over the possible combinations for DIN for each SEL value
+for (count2 = 0; count2 <= 16; count2 = count2 + 1) begin
+#5 DIN = count2;
 end
 end
 
 end
-// The test will run for a total interval of 340ns
-initial #340 $finish;
+
+// The test will run for a total interval of 340ns
+initial #340 $finish;
 endmodule

Project 2 – Combinational Logic/priority_encoder/README.md

@@ -2,7 +2,7 @@
 
 ## Objective
 
-This priority encoder takes one four bit input and outputs the binary representation of the index of the active input bit with the highest priority. In addition, the module will indicate if the output generated is valid by toggling the valid bit, VLD. This solves the issue of having two inputs active at the same time by having the input of the highest priority take precedence.
+This priority encoder takes one 4-bit input and outputs the binary representation of the index of the active input bit with the highest priority. Also, the module will indicate if the output generated is valid by toggling the valid bit, VLD. This solves the issue of having two inputs active at the same time by having the input of the highest priority take precedence.
 
 ## Waveforms
 
@@ -12,4 +12,4 @@ Simulation results from the Verilog representation of this Priority Encoder
 
 ## Source Files
 - **Priority Encoder Module** - priority_encoder.v
-- **Priority Encoder Test Bench** - priority_encoder_test.v
+- **Priority Encoder Test Bench** - priority_encoder_test.v