verilog: Verilog parser and DSL.
A parser and DSL supporting a small subset of Verilog-95. Intended for machine generated, synthesizable code.
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- verilog-0.0.7.tar.gz [browse] (Cabal source package)
- Package description (as included in the package)
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| Versions [RSS] | 0.0.0, 0.0.1, 0.0.2, 0.0.4, 0.0.5, 0.0.6, 0.0.7, 0.0.8, 0.0.9, 0.0.10, 0.0.11 |
|---|---|
| Dependencies | array (>=0.4 && <5.0), base (>=4.0 && <5.0), monadLib (>=3.7 && <4.0) [details] |
| License | BSD-3-Clause |
| Author | Tom Hawkins <tomahawkins@gmail.com> |
| Maintainer | Tom Hawkins <tomahawkins@gmail.com> |
| Category | Language, Hardware, Embedded |
| Home page | http://github.com/tomahawkins/verilog |
| Source repo | head: git clone git://github.com/tomahawkins/verilog.git |
| Uploaded | by TomHawkins at 2014-07-18T22:10:30Z |
| Distributions | |
| Reverse Dependencies | 1 direct, 0 indirect [details] |
| Downloads | 7985 total (24 in the last 30 days) |
| Rating | (no votes yet) [estimated by Bayesian average] |
| Your Rating | |
| Status | Docs available [build log] Successful builds reported [all 1 reports] |