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arc64: Add initial floating-point instruction tests for hs5x.
Adds test coverage for the FCVT32, FLD32, FST32, and FSMUL instruction classes in the GNU Assembler (gas) for the hs5x target. These tests ensure correct assembly and encoding for a subset of floating-point operations supported by hs5x. This is not yet a complete testsuite for all floating-point instructions. Remaining instruction classes will be added in future commits. Signed-off-by: Luis Silva <luiss@synopsys.com>
1 parent 362f33d commit e75dcaa

32 files changed

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lines changed

‎gas/testsuite/gas/arc64/fh2s-32.d‎

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#as: -mcpu=hs5x
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#source: fh2s-32.s
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format elf32-.*arc64
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Disassembly of section .text:
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0x[0-9a-f]+ e060 0035[ ]+fh2s[ ]+f0,f0
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0x[0-9a-f]+ e160 0075[ ]+fh2s[ ]+f1,f1
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0x[0-9a-f]+ e260 00b5[ ]+fh2s[ ]+f2,f2
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0x[0-9a-f]+ e360 00f5[ ]+fh2s[ ]+f3,f3
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0x[0-9a-f]+ e460 0135[ ]+fh2s[ ]+f4,f4
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0x[0-9a-f]+ e560 0175[ ]+fh2s[ ]+f5,f5
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0x[0-9a-f]+ e660 01b5[ ]+fh2s[ ]+f6,f6
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0x[0-9a-f]+ e760 01f5[ ]+fh2s[ ]+f7,f7
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0x[0-9a-f]+ e060 1235[ ]+fh2s[ ]+f8,f8
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0x[0-9a-f]+ e160 1275[ ]+fh2s[ ]+f9,f9
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0x[0-9a-f]+ e260 12b5[ ]+fh2s[ ]+f10,f10
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0x[0-9a-f]+ e360 12f5[ ]+fh2s[ ]+f11,f11
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0x[0-9a-f]+ e460 1335[ ]+fh2s[ ]+f12,f12
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0x[0-9a-f]+ e560 1375[ ]+fh2s[ ]+f13,f13
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0x[0-9a-f]+ e660 13b5[ ]+fh2s[ ]+f14,f14
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0x[0-9a-f]+ e760 13f5[ ]+fh2s[ ]+f15,f15
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0x[0-9a-f]+ e060 2435[ ]+fh2s[ ]+f16,f16
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0x[0-9a-f]+ e160 2475[ ]+fh2s[ ]+f17,f17
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0x[0-9a-f]+ e260 24b5[ ]+fh2s[ ]+f18,f18
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0x[0-9a-f]+ e360 24f5[ ]+fh2s[ ]+f19,f19
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0x[0-9a-f]+ e460 2535[ ]+fh2s[ ]+f20,f20
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0x[0-9a-f]+ e560 2575[ ]+fh2s[ ]+f21,f21
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0x[0-9a-f]+ e660 25b5[ ]+fh2s[ ]+f22,f22
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0x[0-9a-f]+ e760 25f5[ ]+fh2s[ ]+f23,f23
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0x[0-9a-f]+ e060 3635[ ]+fh2s[ ]+f24,f24
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0x[0-9a-f]+ e160 3675[ ]+fh2s[ ]+f25,f25
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0x[0-9a-f]+ e260 36b5[ ]+fh2s[ ]+f26,f26
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0x[0-9a-f]+ e360 36f5[ ]+fh2s[ ]+f27,f27
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0x[0-9a-f]+ e460 3735[ ]+fh2s[ ]+f28,f28
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0x[0-9a-f]+ e560 3775[ ]+fh2s[ ]+f29,f29
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0x[0-9a-f]+ e660 37b5[ ]+fh2s[ ]+f30,f30
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0x[0-9a-f]+ e760 37f5[ ]+fh2s[ ]+f31,f31
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‎gas/testsuite/gas/arc64/fh2s-32.s‎

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; Validate fh2s: Convert half precision to single precision with no rounding.
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fh2s f0, f0
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fh2s f1, f1
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fh2s f2, f2
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fh2s f3, f3
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fh2s f4, f4
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fh2s f5, f5
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fh2s f6, f6
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fh2s f7, f7
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fh2s f8, f8
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fh2s f9, f9
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fh2s f10, f10
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fh2s f11, f11
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fh2s f12, f12
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fh2s f13, f13
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fh2s f14, f14
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fh2s f15, f15
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fh2s f16, f16
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fh2s f17, f17
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fh2s f18, f18
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fh2s f19, f19
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fh2s f20, f20
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fh2s f21, f21
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fh2s f22, f22
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fh2s f23, f23
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fh2s f24, f24
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fh2s f25, f25
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fh2s f26, f26
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fh2s f27, f27
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fh2s f28, f28
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fh2s f29, f29
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fh2s f30, f30
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fh2s f31, f31
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‎gas/testsuite/gas/arc64/fint2s-32.d‎

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#as: -mcpu=hs5x
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#source: fint2s-32.s
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format elf32-.*arc64
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Disassembly of section .text:
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0x[0-9a-f]+ e0e0 0022[ ]+fint2s[ ]+f0,r0
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0x[0-9a-f]+ e1e0 0062[ ]+fint2s[ ]+f1,r1
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0x[0-9a-f]+ e2e0 00a2[ ]+fint2s[ ]+f2,r2
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0x[0-9a-f]+ e3e0 00e2[ ]+fint2s[ ]+f3,r3
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0x[0-9a-f]+ e4e0 0122[ ]+fint2s[ ]+f4,r4
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0x[0-9a-f]+ e5e0 0162[ ]+fint2s[ ]+f5,r5
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0x[0-9a-f]+ e6e0 01a2[ ]+fint2s[ ]+f6,r6
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0x[0-9a-f]+ e7e0 01e2[ ]+fint2s[ ]+f7,r7
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0x[0-9a-f]+ e0e0 1222[ ]+fint2s[ ]+f8,r8
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0x[0-9a-f]+ e1e0 1262[ ]+fint2s[ ]+f9,r9
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0x[0-9a-f]+ e2e0 12a2[ ]+fint2s[ ]+f10,r10
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0x[0-9a-f]+ e3e0 12e2[ ]+fint2s[ ]+f11,r11
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0x[0-9a-f]+ e4e0 1322[ ]+fint2s[ ]+f12,r12
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0x[0-9a-f]+ e5e0 1362[ ]+fint2s[ ]+f13,r13
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0x[0-9a-f]+ e6e0 13a2[ ]+fint2s[ ]+f14,r14
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0x[0-9a-f]+ e7e0 13e2[ ]+fint2s[ ]+f15,r15
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0x[0-9a-f]+ e0e0 2422[ ]+fint2s[ ]+f16,r16
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0x[0-9a-f]+ e1e0 2462[ ]+fint2s[ ]+f17,r17
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0x[0-9a-f]+ e2e0 24a2[ ]+fint2s[ ]+f18,r18
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0x[0-9a-f]+ e3e0 24e2[ ]+fint2s[ ]+f19,r19
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0x[0-9a-f]+ e4e0 2522[ ]+fint2s[ ]+f20,r20
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0x[0-9a-f]+ e5e0 2562[ ]+fint2s[ ]+f21,r21
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0x[0-9a-f]+ e6e0 25a2[ ]+fint2s[ ]+f22,r22
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0x[0-9a-f]+ e7e0 25e2[ ]+fint2s[ ]+f23,r23
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0x[0-9a-f]+ e0e0 3622[ ]+fint2s[ ]+f24,r24
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0x[0-9a-f]+ e1e0 3662[ ]+fint2s[ ]+f25,r25
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0x[0-9a-f]+ e2e0 36a2[ ]+fint2s[ ]+f26,r26
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0x[0-9a-f]+ e3e0 36e2[ ]+fint2s[ ]+f27,fp
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0x[0-9a-f]+ e4e0 3722[ ]+fint2s[ ]+f28,sp
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0x[0-9a-f]+ e5e0 3762[ ]+fint2s[ ]+f29,ilink
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0x[0-9a-f]+ e6e0 37a2[ ]+fint2s[ ]+f30,r30
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0x[0-9a-f]+ e7e0 37e2[ ]+fint2s[ ]+f31,blink
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‎gas/testsuite/gas/arc64/fint2s-32.s‎

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; Validate fint2s: Convert single integer to single-precision float.
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fint2s f0, r0
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fint2s f1, r1
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fint2s f2, r2
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fint2s f3, r3
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fint2s f4, r4
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fint2s f5, r5
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fint2s f6, r6
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fint2s f7, r7
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fint2s f8, r8
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fint2s f9, r9
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fint2s f10, r10
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fint2s f11, r11
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fint2s f12, r12
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fint2s f13, r13
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fint2s f14, r14
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fint2s f15, r15
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fint2s f16, r16
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fint2s f17, r17
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fint2s f18, r18
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fint2s f19, r19
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fint2s f20, r20
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fint2s f21, r21
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fint2s f22, r22
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fint2s f23, r23
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fint2s f24, r24
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fint2s f25, r25
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fint2s f26, r26
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fint2s f27, r27
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fint2s f28, r28
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fint2s f29, r29
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fint2s f30, r30
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fint2s f31, r31
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‎gas/testsuite/gas/arc64/fld32-32.d‎

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#as: -mcpu=hs5x
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#source: fld32-32.s
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format elf32-.*arc64
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Disassembly of section .text:
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0x[0-9a-f]+ 6900 0100[ ]+fld32[ ]+f4,\[r1,0\]
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0x[0-9a-f]+ 6e00 7100 0000 1338[ ]+fld32[ ]+f4,\[0x1338\]
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0x[0-9a-f]+ 6e00 7180 7fff ffff[ ]+fld32[ ]+f6,\[0x7fffffff\]
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0x[0-9a-f]+ 6e00 7200 ffff fc00[ ]+fld32[ ]+f8,\[0xfffffc00\]
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0x[0-9a-f]+ 69ff 0000[ ]+fld32[ ]+f0,\[r1,255\]
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0x[0-9a-f]+ 6c00 8080[ ]+fld32[ ]+f2,\[r4,-256\]
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0x[0-9a-f]+ 6a14 8280[ ]+fld32[ ]+f10,\[r2,-236\]
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0x[0-9a-f]+ 697f 0300[ ]+fld32[ ]+f12,\[r1,127\]
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0x[0-9a-f]+ 6900 0008[ ]+fld32.aw[ ]+f0,\[r1,0\]
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0x[0-9a-f]+ 6bff 0088[ ]+fld32.aw[ ]+f2,\[r3,255\]
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0x[0-9a-f]+ 6d00 8108[ ]+fld32.aw[ ]+f4,\[r5,-256\]
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0x[0-9a-f]+ 6f00 0188[ ]+fld32.aw[ ]+f6,\[r7,0\]
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0x[0-9a-f]+ 6900 0008[ ]+fld32.aw[ ]+f0,\[r1,0\]
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0x[0-9a-f]+ 6bff 0088[ ]+fld32.aw[ ]+f2,\[r3,255\]
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0x[0-9a-f]+ 6d00 8108[ ]+fld32.aw[ ]+f4,\[r5,-256\]
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0x[0-9a-f]+ 6f00 0188[ ]+fld32.aw[ ]+f6,\[r7,0\]
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0x[0-9a-f]+ 6900 0010[ ]+fld32.ab[ ]+f0,\[r1,0\]
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0x[0-9a-f]+ 6b9c 8090[ ]+fld32.ab[ ]+f2,\[r3,-100\]
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0x[0-9a-f]+ 6dff 0110[ ]+fld32.ab[ ]+f4,\[r5,255\]
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0x[0-9a-f]+ 6900 0018[ ]+fld32.as[ ]+f0,\[r1,0\]
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0x[0-9a-f]+ 6bff 0098[ ]+fld32.as[ ]+f2,\[r3,255\]
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0x[0-9a-f]+ 6d00 8118[ ]+fld32.as[ ]+f4,\[r5,-256\]
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0x[0-9a-f]+ 6fff 0198[ ]+fld32.as[ ]+f6,\[r7,255\]
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‎gas/testsuite/gas/arc64/fld32-32.s‎

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; Validate fld32: Loads a 32-bit value from the memory address and
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; places it into the lower 32 bits of the destination floating-poing register.
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; basic variants
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fld32 f4, [r1] ; base register only
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fld32 f4, [0x1338] ; small limm, s9 = 0
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fld32 f6, [0x7fffffff] ; large limm, s9 = 0
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fld32 f8, [-1024] ; negative limm, s9 = 0
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fld32 f0, [r1,255] ; max positive s9
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fld32 f2, [r4,-256] ; min negative s9
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fld32 f10, [r2, -236] ; valid negative offset
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fld32 f12, [r1, 127] ; valid mid positive offset
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; .a/.aw - pre-increment with write-back
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fld32.a f0, [r1]
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fld32.a f2, [r3,255]
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fld32.a f4, [r5,-256]
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fld32.a f6, [r7, 0]
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fld32.aw f0, [r1]
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fld32.aw f2, [r3,255]
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fld32.aw f4, [r5,-256]
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fld32.aw f6, [r7,0]
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; .ab - post-increment with write-back
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fld32.ab f0, [r1]
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fld32.ab f2, [r3,-100]
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fld32.ab f4, [r5,255]
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; .as - scaled offset, no write-back
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fld32.as f0, [r1]
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fld32.as f2, [r3, 255]
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fld32.as f4, [r5, -256]
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fld32.as f6, [r7, 255]
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‎gas/testsuite/gas/arc64/fmvi2s-32.d‎

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#as: -mcpu=hs5x
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#source: fmvi2s-32.s
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format elf32-.*arc64
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Disassembly of section .text:
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0x[0-9a-f]+ e0e0 0030[ ]+fmvi2s[ ]+f0,r0
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0x[0-9a-f]+ e1e0 0070[ ]+fmvi2s[ ]+f1,r1
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0x[0-9a-f]+ e2e0 00b0[ ]+fmvi2s[ ]+f2,r2
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0x[0-9a-f]+ e3e0 00f0[ ]+fmvi2s[ ]+f3,r3
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0x[0-9a-f]+ e4e0 0130[ ]+fmvi2s[ ]+f4,r4
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0x[0-9a-f]+ e5e0 0170[ ]+fmvi2s[ ]+f5,r5
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0x[0-9a-f]+ e6e0 01b0[ ]+fmvi2s[ ]+f6,r6
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0x[0-9a-f]+ e7e0 01f0[ ]+fmvi2s[ ]+f7,r7
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0x[0-9a-f]+ e0e0 1230[ ]+fmvi2s[ ]+f8,r8
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0x[0-9a-f]+ e1e0 1270[ ]+fmvi2s[ ]+f9,r9
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0x[0-9a-f]+ e2e0 12b0[ ]+fmvi2s[ ]+f10,r10
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0x[0-9a-f]+ e3e0 12f0[ ]+fmvi2s[ ]+f11,r11
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0x[0-9a-f]+ e4e0 1330[ ]+fmvi2s[ ]+f12,r12
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0x[0-9a-f]+ e5e0 1370[ ]+fmvi2s[ ]+f13,r13
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0x[0-9a-f]+ e6e0 13b0[ ]+fmvi2s[ ]+f14,r14
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0x[0-9a-f]+ e7e0 13f0[ ]+fmvi2s[ ]+f15,r15
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0x[0-9a-f]+ e0e0 2430[ ]+fmvi2s[ ]+f16,r16
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0x[0-9a-f]+ e1e0 2470[ ]+fmvi2s[ ]+f17,r17
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0x[0-9a-f]+ e2e0 24b0[ ]+fmvi2s[ ]+f18,r18
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0x[0-9a-f]+ e3e0 24f0[ ]+fmvi2s[ ]+f19,r19
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0x[0-9a-f]+ e4e0 2530[ ]+fmvi2s[ ]+f20,r20
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0x[0-9a-f]+ e5e0 2570[ ]+fmvi2s[ ]+f21,r21
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0x[0-9a-f]+ e6e0 25b0[ ]+fmvi2s[ ]+f22,r22
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0x[0-9a-f]+ e7e0 25f0[ ]+fmvi2s[ ]+f23,r23
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0x[0-9a-f]+ e0e0 3630[ ]+fmvi2s[ ]+f24,r24
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0x[0-9a-f]+ e1e0 3670[ ]+fmvi2s[ ]+f25,r25
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0x[0-9a-f]+ e2e0 36b0[ ]+fmvi2s[ ]+f26,r26
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0x[0-9a-f]+ e3e0 36f0[ ]+fmvi2s[ ]+f27,fp
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0x[0-9a-f]+ e4e0 3730[ ]+fmvi2s[ ]+f28,sp
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0x[0-9a-f]+ e5e0 3770[ ]+fmvi2s[ ]+f29,ilink
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0x[0-9a-f]+ e6e0 37b0[ ]+fmvi2s[ ]+f30,r30
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0x[0-9a-f]+ e7e0 37f0[ ]+fmvi2s[ ]+f31,blink
40+

‎gas/testsuite/gas/arc64/fmvi2s-32.s‎

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; Validate fint2s: Convert single integer to single-precision float.
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fmvi2s f0, r0
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fmvi2s f1, r1
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fmvi2s f2, r2
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fmvi2s f3, r3
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fmvi2s f4, r4
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fmvi2s f5, r5
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fmvi2s f6, r6
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fmvi2s f7, r7
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fmvi2s f8, r8
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fmvi2s f9, r9
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fmvi2s f10, r10
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fmvi2s f11, r11
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fmvi2s f12, r12
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fmvi2s f13, r13
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fmvi2s f14, r14
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fmvi2s f15, r15
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fmvi2s f16, r16
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fmvi2s f17, r17
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fmvi2s f18, r18
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fmvi2s f19, r19
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fmvi2s f20, r20
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fmvi2s f21, r21
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fmvi2s f22, r22
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fmvi2s f23, r23
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fmvi2s f24, r24
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fmvi2s f25, r25
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fmvi2s f26, r26
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fmvi2s f27, r27
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fmvi2s f28, r28
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fmvi2s f29, r29
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fmvi2s f30, r30
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fmvi2s f31, r31
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‎gas/testsuite/gas/arc64/fmvs2i-32.d‎

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#as: -mcpu=hs5x
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#source: fmvs2i-32.s
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format elf32-.*arc64
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Disassembly of section .text:
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0x[0-9a-f]+ e060 0031[ ]+fmvs2i[ ]+r0,f0
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0x[0-9a-f]+ e160 0071[ ]+fmvs2i[ ]+r1,f1
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0x[0-9a-f]+ e260 00b1[ ]+fmvs2i[ ]+r2,f2
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0x[0-9a-f]+ e360 00f1[ ]+fmvs2i[ ]+r3,f3
12+
0x[0-9a-f]+ e460 0131[ ]+fmvs2i[ ]+r4,f4
13+
0x[0-9a-f]+ e560 0171[ ]+fmvs2i[ ]+r5,f5
14+
0x[0-9a-f]+ e660 01b1[ ]+fmvs2i[ ]+r6,f6
15+
0x[0-9a-f]+ e760 01f1[ ]+fmvs2i[ ]+r7,f7
16+
0x[0-9a-f]+ e060 1231[ ]+fmvs2i[ ]+r8,f8
17+
0x[0-9a-f]+ e160 1271[ ]+fmvs2i[ ]+r9,f9
18+
0x[0-9a-f]+ e260 12b1[ ]+fmvs2i[ ]+r10,f10
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0x[0-9a-f]+ e360 12f1[ ]+fmvs2i[ ]+r11,f11
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0x[0-9a-f]+ e460 1331[ ]+fmvs2i[ ]+r12,f12
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0x[0-9a-f]+ e560 1371[ ]+fmvs2i[ ]+r13,f13
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0x[0-9a-f]+ e660 13b1[ ]+fmvs2i[ ]+r14,f14
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0x[0-9a-f]+ e760 13f1[ ]+fmvs2i[ ]+r15,f15
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0x[0-9a-f]+ e060 2431[ ]+fmvs2i[ ]+r16,f16
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0x[0-9a-f]+ e160 2471[ ]+fmvs2i[ ]+r17,f17
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0x[0-9a-f]+ e260 24b1[ ]+fmvs2i[ ]+r18,f18
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0x[0-9a-f]+ e360 24f1[ ]+fmvs2i[ ]+r19,f19
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0x[0-9a-f]+ e460 2531[ ]+fmvs2i[ ]+r20,f20
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0x[0-9a-f]+ e560 2571[ ]+fmvs2i[ ]+r21,f21
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0x[0-9a-f]+ e660 25b1[ ]+fmvs2i[ ]+r22,f22
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0x[0-9a-f]+ e760 25f1[ ]+fmvs2i[ ]+r23,f23
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0x[0-9a-f]+ e060 3631[ ]+fmvs2i[ ]+r24,f24
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0x[0-9a-f]+ e160 3671[ ]+fmvs2i[ ]+r25,f25
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0x[0-9a-f]+ e260 36b1[ ]+fmvs2i[ ]+r26,f26
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0x[0-9a-f]+ e360 36f1[ ]+fmvs2i[ ]+fp,f27
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0x[0-9a-f]+ e460 3731[ ]+fmvs2i[ ]+sp,f28
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0x[0-9a-f]+ e560 3771[ ]+fmvs2i[ ]+ilink,f29
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0x[0-9a-f]+ e660 37b1[ ]+fmvs2i[ ]+r30,f30
39+
0x[0-9a-f]+ e760 37f1[ ]+fmvs2i[ ]+blink,f31

‎gas/testsuite/gas/arc64/fmvs2i-32.s‎

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; Validate fmvs2i: Move contens of a floating-point register
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; to a general-purpose regiter without type conversion.
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fmvs2i r0, f0
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fmvs2i r1, f1
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fmvs2i r2, f2
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fmvs2i r3, f3
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fmvs2i r4, f4
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fmvs2i r5, f5
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fmvs2i r6, f6
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fmvs2i r7, f7
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fmvs2i r8, f8
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fmvs2i r9, f9
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fmvs2i r10, f10
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fmvs2i r11, f11
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fmvs2i r12, f12
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fmvs2i r13, f13
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fmvs2i r14, f14
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fmvs2i r15, f15
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fmvs2i r16, f16
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fmvs2i r17, f17
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fmvs2i r18, f18
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fmvs2i r19, f19
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fmvs2i r20, f20
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fmvs2i r21, f21
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fmvs2i r22, f22
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fmvs2i r23, f23
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fmvs2i r24, f24
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fmvs2i r25, f25
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fmvs2i r26, f26
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fmvs2i r27, f27
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fmvs2i r28, f28
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fmvs2i r29, f29
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fmvs2i r30, f30
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fmvs2i r31, f31
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