arcv: dis: apex: Add APEX operand identifier support.

Introduce APEX-specific operand identifier masks and shift constants for RD, RS1, and RS2 fields (APEX_OP_MASK_RD/RS1/RS2 and APEX_OP_SH_RD/RS1/RS2) to allow easy extraction of operands from instruction words. Extend print_insn_args() to handle APEX operand specifier 'M', mapping 'd', 's', and 't' to RD, RS1, and RS2 respectively, using the new operand identifier macros. This enables proper disassembly of APEX instructions in the RISC-V disassembler. Signed-off-by: Alex Turjan <turjan@synopsys.com>

Author: luismgsilva

include/opcode/riscv.h

@@ -712,4 +712,11 @@ struct apex_insn
 #define ARCV_APEX_OFFSET_XI (ARCV_APEX_OFFSET_XS + 64) /* 256 + 64 = 320 */
 #define ARCV_APEX_OFFSET_XC (ARCV_APEX_OFFSET_XI + 32) /* 320 + 32 = 352 */
 
+#define APEX_OP_MASK_RS2 0x1f
+#define APEX_OP_SH_RS2 20
+#define APEX_OP_MASK_RS1 0x1f
+#define APEX_OP_SH_RS1 15
+#define APEX_OP_MASK_RD 0x1f
+#define APEX_OP_SH_RD 7
+
 #endif /* _RISCV_H_ */

opcodes/riscv-dis.c

@@ -416,6 +416,24 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
  }
  break;
 
+case 'M': /* APEX */
+ switch (*++oparg)
+ {
+ case 'd':
+ print (info->stream, dis_style_register, "%s",
+ riscv_gpr_names[(l >> APEX_OP_SH_RD) & APEX_OP_MASK_RD]);
+ break;
+ case 's':
+ print (info->stream, dis_style_register, "%s",
+ riscv_gpr_names[(l >> APEX_OP_SH_RS1) & APEX_OP_MASK_RS1]);
+ break;
+ case 't':
+ print (info->stream, dis_style_register, "%s",
+ riscv_gpr_names[(l >> APEX_OP_SH_RS2) & APEX_OP_MASK_RS2]);
+ break;
+ }
+ break;
+
 case 'V': /* RVV */
  switch (*++oparg)
  {