Commit 6bf02e6

authored

Multi Mode Display

This project demonstrates proper timing for VGA, SVGA, XGA, and VESA graphics modes, using the Vivado Clocking Wizard and Atrix 7 100T FPGA.

1 parent 1af65f0 commit 6bf02e6Copy full SHA for 6bf02e6

1 file changed

+1238

-88

lines changed

+1238

-88

lines changed

Comments

(0)