Pure and impure functions in VHDL

Author: Choaib-ELMADI

Docs/functions/.vhd

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+-> Functions in VHDL are subprograms that implement frequently used algorithms, take input values, and always return a value.
+-> Unlike procedures, functions cannot contain wait statements, meaning they consume zero simulation time.
+-> There are two types of functions in VHDL, pure and impure:
+ * A pure function doesn't modify or read external signals, always returning the same value with the same arguments.
+ * An impure function may interact with external signals and may have side effects.
+
+-> Syntax for a function:
+ [pure | impure] function <function_name> (
+ <parameter_name>: <parameter_type> := <default_value>;
+ ...
+ ) return <return_type> is
+ <constant_or_variable_declaration>
+ begin
+ <code_performed_by_the_function>
+ return <value>;
+ end function;
+
+-> Functions must always return a value and cannot modify parameters since all parameters are treated as constants.

Docs/functions/_tb.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity traffic_lights is
+ generic (CLOCK_FREQUENCY : integer);
+ port (
+ clk : in std_logic;
+ nRst : in std_logic;
+
+ NORTH_RED : out std_logic;
+ NORTH_YELLOW : out std_logic;
+ NORTH_GREEN : out std_logic;
+ WEST_RED : out std_logic;
+ WEST_YELLOW : out std_logic;
+ WEST_GREEN : out std_logic
+ );
+end entity;
+
+architecture rtl of traffic_lights is
+ type t_state is (NORTH_NEXT, NORTH_READY, NORTH, STOP_NORTH, WEST_NEXT, WEST_READY, WEST, STOP_WEST);
+ 
+ signal state : t_state;
+ signal counter : integer range 0 to CLOCK_FREQUENCY * 60;
+
+ function val_counter(minutes: integer := 0; seconds: integer := 0) return integer is
+ variable total_seconds: integer;
+ begin
+
+ total_seconds := seconds + minutes * 60;
+ return total_seconds * CLOCK_FREQUENCY - 1;
+
+ end function;
+begin
+
+ process(clk) is
+
+ impure function counter_expired(minutes: integer := 0; seconds: integer := 0) return boolean is
+ begin
+
+ if counter = val_counter(minutes, seconds) then
+ counter <= 0;
+ return true;
+ else
+ return false;
+ end if;
+
+ end function;
+
+ begin
+
+ if rising_edge(clk) then
+ if nRst = '0' then
+ state <= NORTH_NEXT;
+ counter <= 0;
+ NORTH_RED <= '1';
+ NORTH_YELLOW <= '0';
+ NORTH_GREEN <= '0';
+ WEST_RED <= '1';
+ WEST_YELLOW <= '0';
+ WEST_GREEN <= '0';
+ else
+ NORTH_RED <= '0';
+ NORTH_YELLOW <= '0';
+ NORTH_GREEN <= '0';
+ WEST_RED <= '0';
+ WEST_YELLOW <= '0';
+ WEST_GREEN <= '0';
+ counter <= counter + 1;
+
+ case state is
+ when NORTH_NEXT =>
+ NORTH_RED <= '1';
+ WEST_RED <= '1';
+ if counter_expired(seconds => 5) then
+ state <= NORTH_READY;
+ end if;
+
+ when NORTH_READY =>
+ NORTH_RED <= '1';
+ NORTH_YELLOW <= '1';
+ WEST_RED <= '1';
+ if counter_expired(seconds => 5) then
+ state <= NORTH;
+ end if;
+
+ when NORTH =>
+ NORTH_GREEN <= '1';
+ WEST_RED <= '1';
+ if counter_expired(minutes => 1) then
+ state <= STOP_NORTH;
+ end if;
+
+ when STOP_NORTH =>
+ NORTH_YELLOW <= '1';
+ WEST_RED <= '1';
+ if counter_expired(seconds => 5) then
+ state <= WEST_NEXT;
+ end if;
+
+ when WEST_NEXT =>
+ NORTH_RED <= '1';
+ WEST_RED <= '1';
+ if counter_expired(seconds => 5) then
+ state <= WEST_READY;
+ end if;
+
+ when WEST_READY =>
+ NORTH_RED <= '1';
+ WEST_YELLOW <= '1';
+ WEST_RED <= '1';
+ if counter_expired(seconds => 5) then
+ state <= WEST;
+ end if;
+
+ when WEST =>
+ NORTH_RED <= '1';
+ WEST_GREEN <= '1';
+ if counter_expired(minutes => 1) then
+ state <= STOP_WEST;
+ end if;
+
+ when STOP_WEST =>
+ NORTH_RED <= '1';
+ WEST_YELLOW <= '1';
+ if counter_expired(seconds => 5) then
+ state <= NORTH_NEXT;
+ end if;
+ end case;
+ end if;
+ end if;
+
+ end process;
+
+end architecture;

Docs/functions/main.txt

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity traffic_lights_tb is
+end entity;
+
+architecture sim of traffic_lights_tb is
+ constant CLOCK_FREQUENCY : integer := 100;
+ constant CLOCK_PERIOD : time := 1000 ms / CLOCK_FREQUENCY;
+
+ signal clk : std_logic := '1';
+ signal nRst : std_logic := '0';
+
+ signal NORTH_RED : std_logic;
+ signal NORTH_YELLOW : std_logic;
+ signal NORTH_GREEN : std_logic;
+ signal WEST_RED : std_logic;
+ signal WEST_YELLOW : std_logic;
+ signal WEST_GREEN : std_logic;
+begin
+
+ i_traffic_lights: entity work.traffic_lights(rtl)
+ generic map (CLOCK_FREQUENCY => CLOCK_FREQUENCY)
+ port map (
+ clk => clk,
+ nRst => nRst,
+
+ NORTH_RED => NORTH_RED,
+ NORTH_YELLOW => NORTH_YELLOW,
+ NORTH_GREEN => NORTH_GREEN,
+ WEST_RED => WEST_RED,
+ WEST_YELLOW => WEST_YELLOW,
+ WEST_GREEN => WEST_GREEN
+ );
+
+ clk <= not clk after CLOCK_PERIOD / 2;
+
+ process is
+ begin
+
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ nRst <= '1';
+ wait;
+
+ end process;
+
+end architecture;

Docs/functions/traffic_lights.vhd

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+vcom -work work -2002 -explicit -stats=none {C:/Users/Choaib ELMADI/Downloads/D.I.F.Y/7. Electronics/2. FPGA/Getting Started with VHDL/Docs/functions/traffic_lights.vhd}
+Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity traffic_lights
+-- Compiling architecture rtl of traffic_lights
+
+
+vcom -work work -2002 -explicit -stats=none {C:/Users/Choaib ELMADI/Downloads/D.I.F.Y/7. Electronics/2. FPGA/Getting Started with VHDL/Docs/functions/traffic_lights_tb.vhd}
+Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity traffic_lights_tb
+-- Compiling architecture sim of traffic_lights_tb
+-- Loading entity traffic_lights
+
+
+vsim -gui work.traffic_lights_tb
+vsim -gui work.traffic_lights_tb 
+Start time: 16:30:29 on Oct 05,2024
+Loading std.standard
+Loading std.textio(body)
+Loading ieee.std_logic_1164(body)
+Loading ieee.numeric_std(body)
+Loading work.traffic_lights_tb(sim)
+Loading work.traffic_lights(rtl)
+view -new wave
+-new not supported on PE
+add wave -position insertpoint \
+sim:/traffic_lights_tb/i_traffic_lights/clk \
+sim:/traffic_lights_tb/i_traffic_lights/nRst \
+sim:/traffic_lights_tb/i_traffic_lights/state \
+sim:/traffic_lights_tb/i_traffic_lights/counter
+run 5 min
+End time: 16:35:20 on Oct 05,2024, Elapsed time: 0:04:51
+Errors: 0, Warnings: 7