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Adder / subtractor module in ModelSim
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‎Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd‎

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library ieee;
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use ieee.std_logic_1164.all;
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entity four_bits_adder_subtractor is
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port (
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A, B : in std_logic_vector(3 downto 0);
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op : in std_logic;
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Res : out std_logic_vector(3 downto 0);
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ovf, cout : out std_logic
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);
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end entity;
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architecture arch of four_bits_adder_subtractor is
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component one_bit_adder is
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port (
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a, b : in std_logic;
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cin : in std_logic;
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s : out std_logic;
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cout : out std_logic
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);
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end component;
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signal c : std_logic_vector(3 downto 0);
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signal nB : std_logic_vector(3 downto 0);
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begin
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nB <= (op & op & op & op) xor B;
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r0: one_bit_adder port map (a => A(0), b => nB(0), cin => op, s => Res(0), cout => c(0));
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r1: one_bit_adder port map (a => A(1), b => nB(1), cin => c(0), s => Res(1), cout => c(1));
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r2: one_bit_adder port map (a => A(2), b => nB(2), cin => c(1), s => Res(2), cout => c(2));
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r3: one_bit_adder port map (a => A(3), b => nB(3), cin => c(2), s => Res(3), cout => c(3));
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ovf <= c(3) xor c(2);
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cout <= c(3);
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end architecture;

‎Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor_tb.vhd‎

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library ieee;
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use ieee.std_logic_1164.all;
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entity four_bits_adder_subtractor_tb is
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end entity;
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architecture sim of four_bits_adder_subtractor_tb is
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component four_bits_adder_subtractor is
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port (
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A, B : in std_logic_vector(3 downto 0);
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op : in std_logic;
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Res : out std_logic_vector(3 downto 0);
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ovf, cout : out std_logic
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);
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end component;
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signal A, B : std_logic_vector(3 downto 0);
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signal op : std_logic;
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signal Res : std_logic_vector(3 downto 0);
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signal ovf, cout : std_logic;
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begin
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DUT: four_bits_adder_subtractor port map (A, B, op, Res, ovf, cout);
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process is
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begin
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op <= '0'; --! ADDITION
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A <= "0000"; B <= "0000";
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wait for 10 ns;
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A <= "0100"; B <= "1001";
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wait for 10 ns;
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A <= "1010"; B <= "0100";
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wait for 10 ns;
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A <= "1111"; B <= "0001";
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wait for 10 ns;
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A <= "1010"; B <= "1001";
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wait for 10 ns;
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A <= "1000"; B <= "1001";
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wait for 10 ns;
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op <= '1'; --! SUBTRACTION
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A <= "0000"; B <= "0000";
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wait for 10 ns;
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A <= "0100"; B <= "1001";
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wait for 10 ns;
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A <= "1010"; B <= "0100";
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wait for 10 ns;
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A <= "1111"; B <= "0001";
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wait for 10 ns;
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A <= "1010"; B <= "1001";
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wait for 10 ns;
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A <= "1000"; B <= "1001";
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wait for 10 ns;
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wait;
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end process;
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end architecture;

‎Projects/ModelSim/FourBitsAdderSubtractor/one_bit_adder.vhd‎

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library ieee;
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use ieee.std_logic_1164.all;
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entity one_bit_adder is
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port (
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a, b : in std_logic;
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cin : in std_logic;
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s : out std_logic;
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cout : out std_logic
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);
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end entity;
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architecture arch of one_bit_adder is
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begin
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s <= a xor b xor cin;
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cout <= (a and b) or ((a xor b) and cin);
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end architecture;

‎Projects/ModelSim/FourBitsAdderSubtractor/transcript‎

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Compile of one_bit_adder.vhd was successful.
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vcom -work work -2002 -explicit -stats=none {C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd}
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Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity four_bits_adder_subtractor
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-- Compiling architecture arch of four_bits_adder_subtractor
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vcom -work work -2002 -explicit -stats=none {C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor_tb.vhd}
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Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity four_bits_adder_subtractor_tb
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-- Compiling architecture sim of four_bits_adder_subtractor_tb
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vsim -gui work.four_bits_adder_subtractor_tb
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vsim -gui work.four_bits_adder_subtractor_tb
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Start time: 08:48:27 on Nov 30,2024
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Loading std.standard
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Loading std.textio(body)
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Loading ieee.std_logic_1164(body)
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Loading work.four_bits_adder_subtractor_tb(sim)
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Loading work.four_bits_adder_subtractor(arch)
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Loading work.one_bit_adder(arch)
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add wave -position insertpoint \
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sim:/four_bits_adder_subtractor_tb/A \
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sim:/four_bits_adder_subtractor_tb/B \
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sim:/four_bits_adder_subtractor_tb/Sum \
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sim:/four_bits_adder_subtractor_tb/ovf \
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sim:/four_bits_adder_subtractor_tb/cout
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run
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vcom -work work -2002 -explicit -stats=none {C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd}
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Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity four_bits_adder_subtractor
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-- Compiling architecture arch of four_bits_adder_subtractor
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** Error: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(29): Illegal concurrent statement.
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** Error: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(35): (vcom-1136) Unknown identifier "Sum".
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** Error: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(35): (vcom-1454) Formal "s" of mode OUT cannot be associated with an expression.
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** Error: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(36): (vcom-1136) Unknown identifier "Sum".
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** Error: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(36): (vcom-1454) Formal "s" of mode OUT cannot be associated with an expression.
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** Error: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(37): (vcom-1136) Unknown identifier "Sum".
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** Error: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(37): (vcom-1454) Formal "s" of mode OUT cannot be associated with an expression.
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** Error: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(38): (vcom-1136) Unknown identifier "Sum".
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** Error: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(38): (vcom-1454) Formal "s" of mode OUT cannot be associated with an expression.
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** Note: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(43): VHDL Compiler exiting
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vcom -work work -2002 -explicit -stats=none {C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd}
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Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity four_bits_adder_subtractor
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-- Compiling architecture arch of four_bits_adder_subtractor
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** Error: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(29): Illegal concurrent statement.
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** Note: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(43): VHDL Compiler exiting
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vcom -work work -2002 -explicit -stats=none {C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd}
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Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity four_bits_adder_subtractor
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-- Compiling architecture arch of four_bits_adder_subtractor
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** Warning: C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd(43): (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
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vcom -work work -2002 -explicit -stats=none {C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor.vhd}
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Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity four_bits_adder_subtractor
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-- Compiling architecture arch of four_bits_adder_subtractor
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vcom -work work -2002 -explicit -stats=none {C:/Users/Choaib ELMADI/Documents/D.I.F.Y/2. Electronics/2. FPGA/Getting Started with VHDL/Projects/ModelSim/FourBitsAdderSubtractor/four_bits_adder_subtractor_tb.vhd}
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Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
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-- Loading package STANDARD
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-- Loading package TEXTIO
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-- Loading package std_logic_1164
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-- Compiling entity four_bits_adder_subtractor_tb
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-- Compiling architecture sim of four_bits_adder_subtractor_tb
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vsim -gui work.four_bits_adder_subtractor_tb
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End time: 09:11:41 on Nov 30,2024, Elapsed time: 0:23:14
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Errors: 0, Warnings: 15
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vsim -gui work.four_bits_adder_subtractor_tb
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Start time: 09:11:41 on Nov 30,2024
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Loading std.standard
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Loading std.textio(body)
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Loading ieee.std_logic_1164(body)
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Loading work.four_bits_adder_subtractor_tb(sim)
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Loading work.four_bits_adder_subtractor(arch)
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Loading work.one_bit_adder(arch)
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add wave -position insertpoint \
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sim:/four_bits_adder_subtractor_tb/A \
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sim:/four_bits_adder_subtractor_tb/B \
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sim:/four_bits_adder_subtractor_tb/op \
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sim:/four_bits_adder_subtractor_tb/Res \
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sim:/four_bits_adder_subtractor_tb/ovf \
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sim:/four_bits_adder_subtractor_tb/cout
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restart
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run
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GetModuleFileName: The specified module could not be found.
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quit -sim
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End time: 09:20:08 on Nov 30,2024, Elapsed time: 0:08:27
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Errors: 0, Warnings: 1

‎Projects/ModelSim/FourBitsAdderSubtractor/vsim.wlf‎

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